2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
52 /* Pre-declarations needed for WSI entrypoints */
55 typedef struct xcb_connection_t xcb_connection_t
;
56 typedef uint32_t xcb_visualid_t
;
57 typedef uint32_t xcb_window_t
;
61 #include <vulkan/vulkan.h>
62 #include <vulkan/vulkan_intel.h>
63 #include <vulkan/vk_icd.h>
65 #include "anv_entrypoints.h"
66 #include "brw_context.h"
69 #include "wsi_common.h"
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
83 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
85 #define anv_noreturn __attribute__((__noreturn__))
86 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
88 static inline uint32_t
89 align_down_npot_u32(uint32_t v
, uint32_t a
)
94 static inline uint32_t
95 align_u32(uint32_t v
, uint32_t a
)
97 assert(a
!= 0 && a
== (a
& -a
));
98 return (v
+ a
- 1) & ~(a
- 1);
101 static inline uint64_t
102 align_u64(uint64_t v
, uint64_t a
)
104 assert(a
!= 0 && a
== (a
& -a
));
105 return (v
+ a
- 1) & ~(a
- 1);
108 static inline int32_t
109 align_i32(int32_t v
, int32_t a
)
111 assert(a
!= 0 && a
== (a
& -a
));
112 return (v
+ a
- 1) & ~(a
- 1);
115 /** Alignment must be a power of 2. */
117 anv_is_aligned(uintmax_t n
, uintmax_t a
)
119 assert(a
== (a
& -a
));
120 return (n
& (a
- 1)) == 0;
123 static inline uint32_t
124 anv_minify(uint32_t n
, uint32_t levels
)
126 if (unlikely(n
== 0))
129 return MAX2(n
>> levels
, 1);
133 anv_clamp_f(float f
, float min
, float max
)
146 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
148 if (*inout_mask
& clear_mask
) {
149 *inout_mask
&= ~clear_mask
;
156 static inline union isl_color_value
157 vk_to_isl_color(VkClearColorValue color
)
159 return (union isl_color_value
) {
169 #define for_each_bit(b, dword) \
170 for (uint32_t __dword = (dword); \
171 (b) = __builtin_ffs(__dword) - 1, __dword; \
172 __dword &= ~(1 << (b)))
174 #define typed_memcpy(dest, src, count) ({ \
175 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
176 memcpy((dest), (src), (count) * sizeof(*(src))); \
179 /* Define no kernel as 1, since that's an illegal offset for a kernel */
183 VkStructureType sType
;
187 /* Whenever we generate an error, pass it through this function. Useful for
188 * debugging, where we can break on it. Only call at error site, not when
189 * propagating errors. Might be useful to plug in a stack trace here.
192 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
195 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
196 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
198 #define vk_error(error) error
199 #define vk_errorf(error, format, ...) error
202 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
203 anv_printflike(3, 4);
204 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
205 void anv_loge_v(const char *format
, va_list va
);
208 * Print a FINISHME message, including its source location.
210 #define anv_finishme(format, ...) \
212 static bool reported = false; \
214 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
219 /* A non-fatal assert. Useful for debugging. */
221 #define anv_assert(x) ({ \
222 if (unlikely(!(x))) \
223 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
226 #define anv_assert(x)
230 * If a block of code is annotated with anv_validate, then the block runs only
234 #define anv_validate if (1)
236 #define anv_validate if (0)
239 void anv_abortf(const char *format
, ...) anv_noreturn
anv_printflike(1, 2);
240 void anv_abortfv(const char *format
, va_list va
) anv_noreturn
;
242 #define stub_return(v) \
244 anv_finishme("stub %s", __func__); \
250 anv_finishme("stub %s", __func__); \
255 * A dynamically growable, circular buffer. Elements are added at head and
256 * removed from tail. head and tail are free-running uint32_t indices and we
257 * only compute the modulo with size when accessing the array. This way,
258 * number of bytes in the queue is always head - tail, even in case of
265 /* Index into the current validation list. This is used by the
266 * validation list building alrogithm to track which buffers are already
267 * in the validation list so that we can ensure uniqueness.
271 /* Last known offset. This value is provided by the kernel when we
272 * execbuf and is used as the presumed offset for the next bunch of
280 /* We need to set the WRITE flag on winsys bos so GEM will know we're
281 * writing to them and synchronize uses on other rings (eg if the display
282 * server uses the blitter ring).
288 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
290 bo
->gem_handle
= gem_handle
;
295 bo
->is_winsys_bo
= false;
298 /* Represents a lock-free linked list of "free" things. This is used by
299 * both the block pool and the state pools. Unfortunately, in order to
300 * solve the ABA problem, we can't use a single uint32_t head.
302 union anv_free_list
{
306 /* A simple count that is incremented every time the head changes. */
312 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
314 struct anv_block_state
{
324 struct anv_block_pool
{
325 struct anv_device
*device
;
329 /* The offset from the start of the bo to the "center" of the block
330 * pool. Pointers to allocated blocks are given by
331 * bo.map + center_bo_offset + offsets.
333 uint32_t center_bo_offset
;
335 /* Current memory map of the block pool. This pointer may or may not
336 * point to the actual beginning of the block pool memory. If
337 * anv_block_pool_alloc_back has ever been called, then this pointer
338 * will point to the "center" position of the buffer and all offsets
339 * (negative or positive) given out by the block pool alloc functions
340 * will be valid relative to this pointer.
342 * In particular, map == bo.map + center_offset
348 * Array of mmaps and gem handles owned by the block pool, reclaimed when
349 * the block pool is destroyed.
351 struct u_vector mmap_cleanups
;
355 union anv_free_list free_list
;
356 struct anv_block_state state
;
358 union anv_free_list back_free_list
;
359 struct anv_block_state back_state
;
362 /* Block pools are backed by a fixed-size 2GB memfd */
363 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
365 /* The center of the block pool is also the middle of the memfd. This may
366 * change in the future if we decide differently for some reason.
368 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
370 static inline uint32_t
371 anv_block_pool_size(struct anv_block_pool
*pool
)
373 return pool
->state
.end
+ pool
->back_state
.end
;
382 struct anv_fixed_size_state_pool
{
384 union anv_free_list free_list
;
385 struct anv_block_state block
;
388 #define ANV_MIN_STATE_SIZE_LOG2 6
389 #define ANV_MAX_STATE_SIZE_LOG2 17
391 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
393 struct anv_state_pool
{
394 struct anv_block_pool
*block_pool
;
395 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
398 struct anv_state_stream_block
;
400 struct anv_state_stream
{
401 struct anv_block_pool
*block_pool
;
403 /* The current working block */
404 struct anv_state_stream_block
*block
;
406 /* Offset at which the current block starts */
408 /* Offset at which to allocate the next state */
410 /* Offset at which the current block ends */
414 #define CACHELINE_SIZE 64
415 #define CACHELINE_MASK 63
418 anv_clflush_range(void *start
, size_t size
)
420 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
421 void *end
= start
+ size
;
423 __builtin_ia32_mfence();
425 __builtin_ia32_clflush(p
);
431 anv_state_clflush(struct anv_state state
)
433 anv_clflush_range(state
.map
, state
.alloc_size
);
436 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
437 struct anv_device
*device
, uint32_t block_size
);
438 void anv_block_pool_finish(struct anv_block_pool
*pool
);
439 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
);
440 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
);
441 void anv_block_pool_free(struct anv_block_pool
*pool
, int32_t offset
);
442 void anv_state_pool_init(struct anv_state_pool
*pool
,
443 struct anv_block_pool
*block_pool
);
444 void anv_state_pool_finish(struct anv_state_pool
*pool
);
445 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
446 size_t state_size
, size_t alignment
);
447 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
448 void anv_state_stream_init(struct anv_state_stream
*stream
,
449 struct anv_block_pool
*block_pool
);
450 void anv_state_stream_finish(struct anv_state_stream
*stream
);
451 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
452 uint32_t size
, uint32_t alignment
);
455 * Implements a pool of re-usable BOs. The interface is identical to that
456 * of block_pool except that each block is its own BO.
459 struct anv_device
*device
;
464 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
465 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
466 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
468 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
470 struct anv_scratch_bo
{
475 struct anv_scratch_pool
{
476 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
477 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
480 void anv_scratch_pool_init(struct anv_device
*device
,
481 struct anv_scratch_pool
*pool
);
482 void anv_scratch_pool_finish(struct anv_device
*device
,
483 struct anv_scratch_pool
*pool
);
484 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
485 struct anv_scratch_pool
*pool
,
486 gl_shader_stage stage
,
487 unsigned per_thread_scratch
);
489 extern struct anv_dispatch_table dtable
;
491 #define VK_ICD_WSI_PLATFORM_MAX 5
493 struct anv_physical_device
{
494 VK_LOADER_DATA _loader_data
;
496 struct anv_instance
* instance
;
500 struct gen_device_info info
;
501 uint64_t aperture_size
;
502 struct brw_compiler
* compiler
;
503 struct isl_device isl_dev
;
504 int cmd_parser_version
;
507 uint32_t subslice_total
;
509 uint8_t uuid
[VK_UUID_SIZE
];
511 struct wsi_device wsi_device
;
514 struct anv_instance
{
515 VK_LOADER_DATA _loader_data
;
517 VkAllocationCallbacks alloc
;
520 int physicalDeviceCount
;
521 struct anv_physical_device physicalDevice
;
524 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
525 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
528 VK_LOADER_DATA _loader_data
;
530 struct anv_device
* device
;
532 struct anv_state_pool
* pool
;
535 struct anv_pipeline_cache
{
536 struct anv_device
* device
;
537 pthread_mutex_t mutex
;
539 struct hash_table
* cache
;
542 struct anv_pipeline_bind_map
;
544 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
545 struct anv_device
*device
,
547 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
549 struct anv_shader_bin
*
550 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
551 const void *key
, uint32_t key_size
);
552 struct anv_shader_bin
*
553 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
554 const void *key_data
, uint32_t key_size
,
555 const void *kernel_data
, uint32_t kernel_size
,
556 const struct brw_stage_prog_data
*prog_data
,
557 uint32_t prog_data_size
,
558 const struct anv_pipeline_bind_map
*bind_map
);
561 VK_LOADER_DATA _loader_data
;
563 VkAllocationCallbacks alloc
;
565 struct anv_instance
* instance
;
567 struct gen_device_info info
;
568 struct isl_device isl_dev
;
571 bool can_chain_batches
;
572 bool robust_buffer_access
;
574 struct anv_bo_pool batch_bo_pool
;
576 struct anv_block_pool dynamic_state_block_pool
;
577 struct anv_state_pool dynamic_state_pool
;
579 struct anv_block_pool instruction_block_pool
;
580 struct anv_state_pool instruction_state_pool
;
582 struct anv_block_pool surface_state_block_pool
;
583 struct anv_state_pool surface_state_pool
;
585 struct anv_bo workaround_bo
;
587 struct anv_pipeline_cache blorp_shader_cache
;
588 struct blorp_context blorp
;
590 struct anv_state border_colors
;
592 struct anv_queue queue
;
594 struct anv_scratch_pool scratch_pool
;
596 uint32_t default_mocs
;
598 pthread_mutex_t mutex
;
599 pthread_cond_t queue_submit
;
602 void anv_device_init_blorp(struct anv_device
*device
);
603 void anv_device_finish_blorp(struct anv_device
*device
);
605 VkResult
anv_device_execbuf(struct anv_device
*device
,
606 struct drm_i915_gem_execbuffer2
*execbuf
,
607 struct anv_bo
**execbuf_bos
);
609 void* anv_gem_mmap(struct anv_device
*device
,
610 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
611 void anv_gem_munmap(void *p
, uint64_t size
);
612 uint32_t anv_gem_create(struct anv_device
*device
, size_t size
);
613 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
614 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
615 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
616 int anv_gem_execbuffer(struct anv_device
*device
,
617 struct drm_i915_gem_execbuffer2
*execbuf
);
618 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
619 uint32_t stride
, uint32_t tiling
);
620 int anv_gem_create_context(struct anv_device
*device
);
621 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
622 int anv_gem_get_param(int fd
, uint32_t param
);
623 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
624 int anv_gem_get_aperture(int fd
, uint64_t *size
);
625 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
626 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
627 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
628 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
629 uint32_t read_domains
, uint32_t write_domain
);
631 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
633 struct anv_reloc_list
{
636 struct drm_i915_gem_relocation_entry
* relocs
;
637 struct anv_bo
** reloc_bos
;
640 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
641 const VkAllocationCallbacks
*alloc
);
642 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
643 const VkAllocationCallbacks
*alloc
);
645 uint64_t anv_reloc_list_add(struct anv_reloc_list
*list
,
646 const VkAllocationCallbacks
*alloc
,
647 uint32_t offset
, struct anv_bo
*target_bo
,
650 struct anv_batch_bo
{
651 /* Link in the anv_cmd_buffer.owned_batch_bos list */
652 struct list_head link
;
656 /* Bytes actually consumed in this batch BO */
659 struct anv_reloc_list relocs
;
663 const VkAllocationCallbacks
* alloc
;
669 struct anv_reloc_list
* relocs
;
671 /* This callback is called (with the associated user data) in the event
672 * that the batch runs out of space.
674 VkResult (*extend_cb
)(struct anv_batch
*, void *);
678 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
679 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
680 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
681 void *location
, struct anv_bo
*bo
, uint32_t offset
);
682 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
683 struct anv_batch
*batch
);
690 static inline uint64_t
691 _anv_combine_address(struct anv_batch
*batch
, void *location
,
692 const struct anv_address address
, uint32_t delta
)
694 if (address
.bo
== NULL
) {
695 return address
.offset
+ delta
;
697 assert(batch
->start
<= location
&& location
< batch
->end
);
699 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
703 #define __gen_address_type struct anv_address
704 #define __gen_user_data struct anv_batch
705 #define __gen_combine_address _anv_combine_address
707 /* Wrapper macros needed to work around preprocessor argument issues. In
708 * particular, arguments don't get pre-evaluated if they are concatenated.
709 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
710 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
711 * We can work around this easily enough with these helpers.
713 #define __anv_cmd_length(cmd) cmd ## _length
714 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
715 #define __anv_cmd_header(cmd) cmd ## _header
716 #define __anv_cmd_pack(cmd) cmd ## _pack
717 #define __anv_reg_num(reg) reg ## _num
719 #define anv_pack_struct(dst, struc, ...) do { \
720 struct struc __template = { \
723 __anv_cmd_pack(struc)(NULL, dst, &__template); \
724 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
727 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
728 void *__dst = anv_batch_emit_dwords(batch, n); \
729 struct cmd __template = { \
730 __anv_cmd_header(cmd), \
731 .DWordLength = n - __anv_cmd_length_bias(cmd), \
734 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
738 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
742 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
743 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
744 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
745 dw[i] = (dwords0)[i] | (dwords1)[i]; \
746 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
749 #define anv_batch_emit(batch, cmd, name) \
750 for (struct cmd name = { __anv_cmd_header(cmd) }, \
751 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
752 __builtin_expect(_dst != NULL, 1); \
753 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
754 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
758 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
759 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
760 struct anv_state __state = \
761 anv_state_pool_alloc((pool), __size, align); \
762 struct cmd __template = { \
765 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
766 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
767 if (!(pool)->block_pool->device->info.has_llc) \
768 anv_state_clflush(__state); \
772 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
773 .GraphicsDataTypeGFDT = 0, \
774 .LLCCacheabilityControlLLCCC = 0, \
775 .L3CacheabilityControlL3CC = 1, \
778 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
779 .LLCeLLCCacheabilityControlLLCCC = 0, \
780 .L3CacheabilityControlL3CC = 1, \
783 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
784 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
785 .TargetCache = L3DefertoPATforLLCeLLCselection, \
789 /* Skylake: MOCS is now an index into an array of 62 different caching
790 * configurations programmed by the kernel.
793 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
794 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
795 .IndextoMOCSTables = 2 \
798 #define GEN9_MOCS_PTE { \
799 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
800 .IndextoMOCSTables = 1 \
803 struct anv_device_memory
{
806 VkDeviceSize map_size
;
811 * Header for Vertex URB Entry (VUE)
813 struct anv_vue_header
{
815 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
816 uint32_t ViewportIndex
;
820 struct anv_descriptor_set_binding_layout
{
822 /* The type of the descriptors in this binding */
823 VkDescriptorType type
;
826 /* Number of array elements in this binding */
829 /* Index into the flattend descriptor set */
830 uint16_t descriptor_index
;
832 /* Index into the dynamic state array for a dynamic buffer */
833 int16_t dynamic_offset_index
;
835 /* Index into the descriptor set buffer views */
836 int16_t buffer_index
;
839 /* Index into the binding table for the associated surface */
840 int16_t surface_index
;
842 /* Index into the sampler table for the associated sampler */
843 int16_t sampler_index
;
845 /* Index into the image table for the associated image */
847 } stage
[MESA_SHADER_STAGES
];
849 /* Immutable samplers (or NULL if no immutable samplers) */
850 struct anv_sampler
**immutable_samplers
;
853 struct anv_descriptor_set_layout
{
854 /* Number of bindings in this descriptor set */
855 uint16_t binding_count
;
857 /* Total size of the descriptor set with room for all array entries */
860 /* Shader stages affected by this descriptor set */
861 uint16_t shader_stages
;
863 /* Number of buffers in this descriptor set */
864 uint16_t buffer_count
;
866 /* Number of dynamic offsets used by this descriptor set */
867 uint16_t dynamic_offset_count
;
869 /* Bindings in this descriptor set */
870 struct anv_descriptor_set_binding_layout binding
[0];
873 struct anv_descriptor
{
874 VkDescriptorType type
;
878 struct anv_image_view
*image_view
;
879 struct anv_sampler
*sampler
;
882 struct anv_buffer_view
*buffer_view
;
886 struct anv_descriptor_set
{
887 const struct anv_descriptor_set_layout
*layout
;
889 uint32_t buffer_count
;
890 struct anv_buffer_view
*buffer_views
;
891 struct anv_descriptor descriptors
[0];
894 struct anv_descriptor_pool
{
899 struct anv_state_stream surface_state_stream
;
900 void *surface_state_free_list
;
906 anv_descriptor_set_create(struct anv_device
*device
,
907 struct anv_descriptor_pool
*pool
,
908 const struct anv_descriptor_set_layout
*layout
,
909 struct anv_descriptor_set
**out_set
);
912 anv_descriptor_set_destroy(struct anv_device
*device
,
913 struct anv_descriptor_pool
*pool
,
914 struct anv_descriptor_set
*set
);
916 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
918 struct anv_pipeline_binding
{
919 /* The descriptor set this surface corresponds to. The special value of
920 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
921 * to a color attachment and not a regular descriptor.
925 /* Binding in the descriptor set */
928 /* Index in the binding */
931 /* Input attachment index (relative to the subpass) */
932 uint8_t input_attachment_index
;
935 struct anv_pipeline_layout
{
937 struct anv_descriptor_set_layout
*layout
;
938 uint32_t dynamic_offset_start
;
944 bool has_dynamic_offsets
;
945 } stage
[MESA_SHADER_STAGES
];
947 unsigned char sha1
[20];
951 struct anv_device
* device
;
954 VkBufferUsageFlags usage
;
961 enum anv_cmd_dirty_bits
{
962 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
963 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
964 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
965 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
966 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
967 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
968 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
969 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
970 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
971 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
972 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
973 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
974 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
976 typedef uint32_t anv_cmd_dirty_mask_t
;
979 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
980 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
981 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
982 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
983 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
984 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
985 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
986 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
987 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
988 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
989 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
991 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
992 * a flush has happened but not a CS stall. The next time we do any sort
993 * of invalidation we need to insert a CS stall at that time. Otherwise,
994 * we would have to CS stall on every flush which could be bad.
996 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
999 #define ANV_PIPE_FLUSH_BITS ( \
1000 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1001 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1002 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1004 #define ANV_PIPE_STALL_BITS ( \
1005 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1006 ANV_PIPE_DEPTH_STALL_BIT | \
1007 ANV_PIPE_CS_STALL_BIT)
1009 #define ANV_PIPE_INVALIDATE_BITS ( \
1010 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1011 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1012 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1013 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1014 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1015 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1017 struct anv_vertex_binding
{
1018 struct anv_buffer
* buffer
;
1019 VkDeviceSize offset
;
1022 struct anv_push_constants
{
1023 /* Current allocated size of this push constants data structure.
1024 * Because a decent chunk of it may not be used (images on SKL, for
1025 * instance), we won't actually allocate the entire structure up-front.
1029 /* Push constant data provided by the client through vkPushConstants */
1030 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1032 /* Our hardware only provides zero-based vertex and instance id so, in
1033 * order to satisfy the vulkan requirements, we may have to push one or
1034 * both of these into the shader.
1036 uint32_t base_vertex
;
1037 uint32_t base_instance
;
1039 /* Offsets and ranges for dynamically bound buffers */
1043 } dynamic
[MAX_DYNAMIC_BUFFERS
];
1045 /* Image data for image_load_store on pre-SKL */
1046 struct brw_image_param images
[MAX_IMAGES
];
1049 struct anv_dynamic_state
{
1052 VkViewport viewports
[MAX_VIEWPORTS
];
1057 VkRect2D scissors
[MAX_SCISSORS
];
1068 float blend_constants
[4];
1078 } stencil_compare_mask
;
1083 } stencil_write_mask
;
1088 } stencil_reference
;
1091 extern const struct anv_dynamic_state default_dynamic_state
;
1093 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1094 const struct anv_dynamic_state
*src
,
1095 uint32_t copy_mask
);
1098 * Attachment state when recording a renderpass instance.
1100 * The clear value is valid only if there exists a pending clear.
1102 struct anv_attachment_state
{
1103 enum isl_aux_usage aux_usage
;
1104 enum isl_aux_usage input_aux_usage
;
1105 struct anv_state color_rt_state
;
1106 struct anv_state input_att_state
;
1108 VkImageAspectFlags pending_clear_aspects
;
1110 VkClearValue clear_value
;
1111 bool clear_color_is_zero_one
;
1114 /** State required while building cmd buffer */
1115 struct anv_cmd_state
{
1116 /* PIPELINE_SELECT.PipelineSelection */
1117 uint32_t current_pipeline
;
1118 const struct gen_l3_config
* current_l3_config
;
1120 anv_cmd_dirty_mask_t dirty
;
1121 anv_cmd_dirty_mask_t compute_dirty
;
1122 enum anv_pipe_bits pending_pipe_bits
;
1123 uint32_t num_workgroups_offset
;
1124 struct anv_bo
*num_workgroups_bo
;
1125 VkShaderStageFlags descriptors_dirty
;
1126 VkShaderStageFlags push_constants_dirty
;
1127 uint32_t scratch_size
;
1128 struct anv_pipeline
* pipeline
;
1129 struct anv_pipeline
* compute_pipeline
;
1130 struct anv_framebuffer
* framebuffer
;
1131 struct anv_render_pass
* pass
;
1132 struct anv_subpass
* subpass
;
1133 VkRect2D render_area
;
1134 uint32_t restart_index
;
1135 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1136 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1137 VkShaderStageFlags push_constant_stages
;
1138 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1139 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1140 struct anv_state samplers
[MESA_SHADER_STAGES
];
1141 struct anv_dynamic_state dynamic
;
1145 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1146 * valid only when recording a render pass instance.
1148 struct anv_attachment_state
* attachments
;
1151 * Surface states for color render targets. These are stored in a single
1152 * flat array. For depth-stencil attachments, the surface state is simply
1155 struct anv_state render_pass_states
;
1158 * A null surface state of the right size to match the framebuffer. This
1159 * is one of the states in render_pass_states.
1161 struct anv_state null_surface_state
;
1164 struct anv_buffer
* index_buffer
;
1165 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1166 uint32_t index_offset
;
1170 struct anv_cmd_pool
{
1171 VkAllocationCallbacks alloc
;
1172 struct list_head cmd_buffers
;
1175 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1177 enum anv_cmd_buffer_exec_mode
{
1178 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1179 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1180 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1181 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1182 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1185 struct anv_cmd_buffer
{
1186 VK_LOADER_DATA _loader_data
;
1188 struct anv_device
* device
;
1190 struct anv_cmd_pool
* pool
;
1191 struct list_head pool_link
;
1193 struct anv_batch batch
;
1195 /* Fields required for the actual chain of anv_batch_bo's.
1197 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1199 struct list_head batch_bos
;
1200 enum anv_cmd_buffer_exec_mode exec_mode
;
1202 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1203 * referenced by this command buffer
1205 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1207 struct u_vector seen_bbos
;
1209 /* A vector of int32_t's for every block of binding tables.
1211 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1213 struct u_vector bt_blocks
;
1216 struct anv_reloc_list surface_relocs
;
1217 /** Last seen surface state block pool center bo offset */
1218 uint32_t last_ss_pool_center
;
1220 /* Serial for tracking buffer completion */
1223 /* Stream objects for storing temporary data */
1224 struct anv_state_stream surface_state_stream
;
1225 struct anv_state_stream dynamic_state_stream
;
1227 VkCommandBufferUsageFlags usage_flags
;
1228 VkCommandBufferLevel level
;
1230 struct anv_cmd_state state
;
1233 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1234 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1235 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1236 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1237 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1238 struct anv_cmd_buffer
*secondary
);
1239 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1240 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1241 struct anv_cmd_buffer
*cmd_buffer
);
1243 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1246 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1247 gl_shader_stage stage
, uint32_t size
);
1248 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1249 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1250 (offsetof(struct anv_push_constants, field) + \
1251 sizeof(cmd_buffer->state.push_constants[0]->field)))
1253 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1254 const void *data
, uint32_t size
, uint32_t alignment
);
1255 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1256 uint32_t *a
, uint32_t *b
,
1257 uint32_t dwords
, uint32_t alignment
);
1260 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1262 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1263 uint32_t entries
, uint32_t *state_offset
);
1265 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1267 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1268 uint32_t size
, uint32_t alignment
);
1271 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1273 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1274 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1275 bool depth_clamp_enable
);
1276 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1278 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1279 struct anv_render_pass
*pass
,
1280 struct anv_framebuffer
*framebuffer
,
1281 const VkClearValue
*clear_values
);
1283 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1286 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1287 gl_shader_stage stage
);
1289 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1291 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1292 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1294 const struct anv_image_view
*
1295 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1298 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1299 uint32_t num_entries
,
1300 uint32_t *state_offset
);
1302 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1304 enum anv_fence_state
{
1305 /** Indicates that this is a new (or newly reset fence) */
1306 ANV_FENCE_STATE_RESET
,
1308 /** Indicates that this fence has been submitted to the GPU but is still
1309 * (as far as we know) in use by the GPU.
1311 ANV_FENCE_STATE_SUBMITTED
,
1313 ANV_FENCE_STATE_SIGNALED
,
1318 struct drm_i915_gem_execbuffer2 execbuf
;
1319 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1320 enum anv_fence_state state
;
1325 struct anv_state state
;
1328 struct anv_shader_module
{
1329 unsigned char sha1
[20];
1334 void anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
1335 struct anv_shader_module
*module
,
1336 const char *entrypoint
,
1337 const struct anv_pipeline_layout
*pipeline_layout
,
1338 const VkSpecializationInfo
*spec_info
);
1340 static inline gl_shader_stage
1341 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1343 assert(__builtin_popcount(vk_stage
) == 1);
1344 return ffs(vk_stage
) - 1;
1347 static inline VkShaderStageFlagBits
1348 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1350 return (1 << mesa_stage
);
1353 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1355 #define anv_foreach_stage(stage, stage_bits) \
1356 for (gl_shader_stage stage, \
1357 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1358 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1359 __tmp &= ~(1 << (stage)))
1361 struct anv_pipeline_bind_map
{
1362 uint32_t surface_count
;
1363 uint32_t sampler_count
;
1364 uint32_t image_count
;
1366 struct anv_pipeline_binding
* surface_to_descriptor
;
1367 struct anv_pipeline_binding
* sampler_to_descriptor
;
1370 struct anv_shader_bin_key
{
1375 struct anv_shader_bin
{
1378 const struct anv_shader_bin_key
*key
;
1380 struct anv_state kernel
;
1381 uint32_t kernel_size
;
1383 const struct brw_stage_prog_data
*prog_data
;
1384 uint32_t prog_data_size
;
1386 struct anv_pipeline_bind_map bind_map
;
1388 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1391 struct anv_shader_bin
*
1392 anv_shader_bin_create(struct anv_device
*device
,
1393 const void *key
, uint32_t key_size
,
1394 const void *kernel
, uint32_t kernel_size
,
1395 const struct brw_stage_prog_data
*prog_data
,
1396 uint32_t prog_data_size
, const void *prog_data_param
,
1397 const struct anv_pipeline_bind_map
*bind_map
);
1400 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1403 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1405 assert(shader
->ref_cnt
>= 1);
1406 __sync_fetch_and_add(&shader
->ref_cnt
, 1);
1410 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1412 assert(shader
->ref_cnt
>= 1);
1413 if (__sync_fetch_and_add(&shader
->ref_cnt
, -1) == 1)
1414 anv_shader_bin_destroy(device
, shader
);
1417 struct anv_pipeline
{
1418 struct anv_device
* device
;
1419 struct anv_batch batch
;
1420 uint32_t batch_data
[512];
1421 struct anv_reloc_list batch_relocs
;
1422 uint32_t dynamic_state_mask
;
1423 struct anv_dynamic_state dynamic_state
;
1425 struct anv_pipeline_layout
* layout
;
1427 bool needs_data_cache
;
1429 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1432 const struct gen_l3_config
* l3_config
;
1433 uint32_t total_size
;
1436 VkShaderStageFlags active_stages
;
1437 struct anv_state blend_state
;
1440 uint32_t binding_stride
[MAX_VBS
];
1441 bool instancing_enable
[MAX_VBS
];
1442 bool primitive_restart
;
1445 uint32_t cs_right_mask
;
1447 bool depth_clamp_enable
;
1451 uint32_t depth_stencil_state
[3];
1457 uint32_t wm_depth_stencil
[3];
1461 uint32_t wm_depth_stencil
[4];
1464 uint32_t interface_descriptor_data
[8];
1468 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1469 gl_shader_stage stage
)
1471 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1474 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1475 static inline const struct brw_##prefix##_prog_data * \
1476 get_##prefix##_prog_data(struct anv_pipeline *pipeline) \
1478 if (anv_pipeline_has_stage(pipeline, stage)) { \
1479 return (const struct brw_##prefix##_prog_data *) \
1480 pipeline->shaders[stage]->prog_data; \
1486 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1487 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1488 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1489 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1492 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1493 struct anv_pipeline_cache
*cache
,
1494 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1495 const VkAllocationCallbacks
*alloc
);
1498 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1499 struct anv_pipeline_cache
*cache
,
1500 const VkComputePipelineCreateInfo
*info
,
1501 struct anv_shader_module
*module
,
1502 const char *entrypoint
,
1503 const VkSpecializationInfo
*spec_info
);
1506 enum isl_format isl_format
:16;
1507 struct isl_swizzle swizzle
;
1511 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1512 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1514 static inline enum isl_format
1515 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1516 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1518 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1522 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
1525 * Subsurface of an anv_image.
1527 struct anv_surface
{
1528 /** Valid only if isl_surf::size > 0. */
1529 struct isl_surf isl
;
1532 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1539 /* The original VkFormat provided by the client. This may not match any
1540 * of the actual surface formats.
1543 VkImageAspectFlags aspects
;
1546 uint32_t array_size
;
1547 uint32_t samples
; /**< VkImageCreateInfo::samples */
1548 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1549 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1554 /* Set when bound */
1556 VkDeviceSize offset
;
1561 * For each foo, anv_image::foo_surface is valid if and only if
1562 * anv_image::aspects has a foo aspect.
1564 * The hardware requires that the depth buffer and stencil buffer be
1565 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1566 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1567 * allocate the depth and stencil buffers as separate surfaces in the same
1571 struct anv_surface color_surface
;
1574 struct anv_surface depth_surface
;
1575 struct anv_surface stencil_surface
;
1579 /** The aux usage for this surface when outside a render pass */
1580 enum isl_aux_usage aux_usage
;
1582 struct anv_surface aux_surface
;
1585 static inline uint32_t
1586 anv_get_layerCount(const struct anv_image
*image
,
1587 const VkImageSubresourceRange
*range
)
1589 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1590 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1593 static inline uint32_t
1594 anv_get_levelCount(const struct anv_image
*image
,
1595 const VkImageSubresourceRange
*range
)
1597 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1598 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1602 struct anv_image_view
{
1603 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
1605 uint32_t offset
; /**< Offset into bo. */
1607 struct isl_view isl
;
1609 VkImageAspectFlags aspect_mask
;
1611 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1613 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1614 struct anv_state sampler_surface_state
;
1616 /** RENDER_SURFACE_STATE when using image as a storage image. */
1617 struct anv_state storage_surface_state
;
1619 struct brw_image_param storage_image_param
;
1622 struct anv_image_create_info
{
1623 const VkImageCreateInfo
*vk_info
;
1625 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1626 isl_tiling_flags_t isl_tiling_flags
;
1631 VkResult
anv_image_create(VkDevice _device
,
1632 const struct anv_image_create_info
*info
,
1633 const VkAllocationCallbacks
* alloc
,
1636 const struct anv_surface
*
1637 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1638 VkImageAspectFlags aspect_mask
);
1641 anv_image_has_hiz(const struct anv_image
*image
)
1643 /* We must check the aspect because anv_image::aux_surface may be used for
1644 * any type of auxiliary surface, not just HiZ.
1646 return (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1647 image
->aux_surface
.isl
.size
> 0;
1650 struct anv_buffer_view
{
1651 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1653 uint32_t offset
; /**< Offset into bo. */
1654 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1656 struct anv_state surface_state
;
1657 struct anv_state storage_surface_state
;
1659 struct brw_image_param storage_image_param
;
1663 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
1665 static inline struct VkExtent3D
1666 anv_sanitize_image_extent(const VkImageType imageType
,
1667 const struct VkExtent3D imageExtent
)
1669 switch (imageType
) {
1670 case VK_IMAGE_TYPE_1D
:
1671 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1672 case VK_IMAGE_TYPE_2D
:
1673 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1674 case VK_IMAGE_TYPE_3D
:
1677 unreachable("invalid image type");
1681 static inline struct VkOffset3D
1682 anv_sanitize_image_offset(const VkImageType imageType
,
1683 const struct VkOffset3D imageOffset
)
1685 switch (imageType
) {
1686 case VK_IMAGE_TYPE_1D
:
1687 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1688 case VK_IMAGE_TYPE_2D
:
1689 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1690 case VK_IMAGE_TYPE_3D
:
1693 unreachable("invalid image type");
1698 void anv_fill_buffer_surface_state(struct anv_device
*device
,
1699 struct anv_state state
,
1700 enum isl_format format
,
1701 uint32_t offset
, uint32_t range
,
1704 void anv_image_view_fill_image_param(struct anv_device
*device
,
1705 struct anv_image_view
*view
,
1706 struct brw_image_param
*param
);
1707 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
1708 struct anv_buffer_view
*view
,
1709 struct brw_image_param
*param
);
1711 struct anv_sampler
{
1715 struct anv_framebuffer
{
1720 uint32_t attachment_count
;
1721 struct anv_image_view
* attachments
[0];
1724 struct anv_subpass
{
1725 uint32_t input_count
;
1726 uint32_t * input_attachments
;
1727 uint32_t color_count
;
1728 uint32_t * color_attachments
;
1729 uint32_t * resolve_attachments
;
1730 uint32_t depth_stencil_attachment
;
1732 /** Subpass has a depth/stencil self-dependency */
1733 bool has_ds_self_dep
;
1735 /** Subpass has at least one resolve attachment */
1739 enum anv_subpass_usage
{
1740 ANV_SUBPASS_USAGE_DRAW
= (1 << 0),
1741 ANV_SUBPASS_USAGE_INPUT
= (1 << 1),
1742 ANV_SUBPASS_USAGE_RESOLVE_SRC
= (1 << 2),
1743 ANV_SUBPASS_USAGE_RESOLVE_DST
= (1 << 3),
1746 struct anv_render_pass_attachment
{
1749 VkImageUsageFlags usage
;
1750 VkAttachmentLoadOp load_op
;
1751 VkAttachmentStoreOp store_op
;
1752 VkAttachmentLoadOp stencil_load_op
;
1754 /* An array, indexed by subpass id, of how the attachment will be used. */
1755 enum anv_subpass_usage
* subpass_usage
;
1758 struct anv_render_pass
{
1759 uint32_t attachment_count
;
1760 uint32_t subpass_count
;
1761 uint32_t * subpass_attachments
;
1762 enum anv_subpass_usage
* subpass_usages
;
1763 struct anv_render_pass_attachment
* attachments
;
1764 struct anv_subpass subpasses
[0];
1767 struct anv_query_pool_slot
{
1773 struct anv_query_pool
{
1779 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
1782 void anv_dump_image_to_ppm(struct anv_device
*device
,
1783 struct anv_image
*image
, unsigned miplevel
,
1784 unsigned array_layer
, VkImageAspectFlagBits aspect
,
1785 const char *filename
);
1787 enum anv_dump_action
{
1788 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
1791 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
1792 void anv_dump_finish(void);
1794 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
1795 struct anv_framebuffer
*fb
);
1797 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1799 static inline struct __anv_type * \
1800 __anv_type ## _from_handle(__VkType _handle) \
1802 return (struct __anv_type *) _handle; \
1805 static inline __VkType \
1806 __anv_type ## _to_handle(struct __anv_type *_obj) \
1808 return (__VkType) _obj; \
1811 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1813 static inline struct __anv_type * \
1814 __anv_type ## _from_handle(__VkType _handle) \
1816 return (struct __anv_type *)(uintptr_t) _handle; \
1819 static inline __VkType \
1820 __anv_type ## _to_handle(struct __anv_type *_obj) \
1822 return (__VkType)(uintptr_t) _obj; \
1825 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1826 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1828 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
1829 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
1830 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
1831 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
1832 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
1834 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
1835 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
1836 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
1837 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
1838 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
1839 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
1840 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
1841 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
1842 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
1843 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
1844 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
1845 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
1846 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
1847 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
1848 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
1849 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
1850 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
1851 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
1852 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
1854 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1856 static inline const __VkType * \
1857 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1859 return (const __VkType *) __anv_obj; \
1862 #define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1863 const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name)
1865 ANV_DEFINE_STRUCT_CASTS(anv_common
, VkMemoryBarrier
)
1866 ANV_DEFINE_STRUCT_CASTS(anv_common
, VkBufferMemoryBarrier
)
1867 ANV_DEFINE_STRUCT_CASTS(anv_common
, VkImageMemoryBarrier
)
1869 /* Gen-specific function declarations */
1871 # include "anv_genX.h"
1873 # define genX(x) gen7_##x
1874 # include "anv_genX.h"
1876 # define genX(x) gen75_##x
1877 # include "anv_genX.h"
1879 # define genX(x) gen8_##x
1880 # include "anv_genX.h"
1882 # define genX(x) gen9_##x
1883 # include "anv_genX.h"
1891 #endif /* ANV_PRIVATE_H */