2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "compiler/brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
52 /* Pre-declarations needed for WSI entrypoints */
55 typedef struct xcb_connection_t xcb_connection_t
;
56 typedef uint32_t xcb_visualid_t
;
57 typedef uint32_t xcb_window_t
;
60 struct anv_buffer_view
;
61 struct anv_image_view
;
65 #include <vulkan/vulkan.h>
66 #include <vulkan/vulkan_intel.h>
67 #include <vulkan/vk_icd.h>
69 #include "anv_entrypoints.h"
72 #include "common/gen_debug.h"
73 #include "wsi_common.h"
75 /* Allowing different clear colors requires us to perform a depth resolve at
76 * the end of certain render passes. This is because while slow clears store
77 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
78 * See the PRMs for examples describing when additional resolves would be
79 * necessary. To enable fast clears without requiring extra resolves, we set
80 * the clear value to a globally-defined one. We could allow different values
81 * if the user doesn't expect coherent data during or after a render passes
82 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
83 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
84 * 1.0f seems to be the only value used. The only application that doesn't set
85 * this value does so through the usage of an seemingly uninitialized clear
88 #define ANV_HZ_FC_VAL 1.0f
93 #define MAX_VIEWPORTS 16
94 #define MAX_SCISSORS 16
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_DYNAMIC_BUFFERS 16
98 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
100 #define ANV_SVGS_VB_INDEX MAX_VBS
101 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
103 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
105 static inline uint32_t
106 align_down_npot_u32(uint32_t v
, uint32_t a
)
111 static inline uint32_t
112 align_u32(uint32_t v
, uint32_t a
)
114 assert(a
!= 0 && a
== (a
& -a
));
115 return (v
+ a
- 1) & ~(a
- 1);
118 static inline uint64_t
119 align_u64(uint64_t v
, uint64_t a
)
121 assert(a
!= 0 && a
== (a
& -a
));
122 return (v
+ a
- 1) & ~(a
- 1);
125 static inline int32_t
126 align_i32(int32_t v
, int32_t a
)
128 assert(a
!= 0 && a
== (a
& -a
));
129 return (v
+ a
- 1) & ~(a
- 1);
132 /** Alignment must be a power of 2. */
134 anv_is_aligned(uintmax_t n
, uintmax_t a
)
136 assert(a
== (a
& -a
));
137 return (n
& (a
- 1)) == 0;
140 static inline uint32_t
141 anv_minify(uint32_t n
, uint32_t levels
)
143 if (unlikely(n
== 0))
146 return MAX2(n
>> levels
, 1);
150 anv_clamp_f(float f
, float min
, float max
)
163 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
165 if (*inout_mask
& clear_mask
) {
166 *inout_mask
&= ~clear_mask
;
173 static inline union isl_color_value
174 vk_to_isl_color(VkClearColorValue color
)
176 return (union isl_color_value
) {
186 #define for_each_bit(b, dword) \
187 for (uint32_t __dword = (dword); \
188 (b) = __builtin_ffs(__dword) - 1, __dword; \
189 __dword &= ~(1 << (b)))
191 #define typed_memcpy(dest, src, count) ({ \
192 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
193 memcpy((dest), (src), (count) * sizeof(*(src))); \
196 /* Whenever we generate an error, pass it through this function. Useful for
197 * debugging, where we can break on it. Only call at error site, not when
198 * propagating errors. Might be useful to plug in a stack trace here.
201 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
204 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
205 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
206 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
208 #define vk_error(error) error
209 #define vk_errorf(error, format, ...) error
210 #define anv_debug(format, ...)
214 * Warn on ignored extension structs.
216 * The Vulkan spec requires us to ignore unsupported or unknown structs in
217 * a pNext chain. In debug mode, emitting warnings for ignored structs may
218 * help us discover structs that we should not have ignored.
221 * From the Vulkan 1.0.38 spec:
223 * Any component of the implementation (the loader, any enabled layers,
224 * and drivers) must skip over, without processing (other than reading the
225 * sType and pNext members) any chained structures with sType values not
226 * defined by extensions supported by that component.
228 #define anv_debug_ignored_stype(sType) \
229 anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType))
231 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
232 anv_printflike(3, 4);
233 void __anv_perf_warn(const char *file
, int line
, const char *format
, ...)
234 anv_printflike(3, 4);
235 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
236 void anv_loge_v(const char *format
, va_list va
);
239 * Print a FINISHME message, including its source location.
241 #define anv_finishme(format, ...) \
243 static bool reported = false; \
245 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
251 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
253 #define anv_perf_warn(format, ...) \
255 static bool reported = false; \
256 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
257 __anv_perf_warn(__FILE__, __LINE__, format, ##__VA_ARGS__); \
262 /* A non-fatal assert. Useful for debugging. */
264 #define anv_assert(x) ({ \
265 if (unlikely(!(x))) \
266 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
269 #define anv_assert(x)
272 /* A multi-pointer allocator
274 * When copying data structures from the user (such as a render pass), it's
275 * common to need to allocate data for a bunch of different things. Instead
276 * of doing several allocations and having to handle all of the error checking
277 * that entails, it can be easier to do a single allocation. This struct
278 * helps facilitate that. The intended usage looks like this:
281 * anv_multialloc_add(&ma, &main_ptr, 1);
282 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
283 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
285 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
286 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
288 struct anv_multialloc
{
296 #define ANV_MULTIALLOC_INIT \
297 ((struct anv_multialloc) { 0, })
299 #define ANV_MULTIALLOC(_name) \
300 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
302 __attribute__((always_inline
))
304 _anv_multialloc_add(struct anv_multialloc
*ma
,
305 void **ptr
, size_t size
, size_t align
)
307 size_t offset
= align_u64(ma
->size
, align
);
308 ma
->size
= offset
+ size
;
309 ma
->align
= MAX2(ma
->align
, align
);
311 /* Store the offset in the pointer. */
312 *ptr
= (void *)(uintptr_t)offset
;
314 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
315 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
318 #define anv_multialloc_add(_ma, _ptr, _count) \
319 _anv_multialloc_add((_ma), (void **)(_ptr), \
320 (_count) * sizeof(**(_ptr)), __alignof__(**(_ptr)))
322 __attribute__((always_inline
))
324 anv_multialloc_alloc(struct anv_multialloc
*ma
,
325 const VkAllocationCallbacks
*alloc
,
326 VkSystemAllocationScope scope
)
328 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
332 /* Fill out each of the pointers with their final value.
334 * for (uint32_t i = 0; i < ma->ptr_count; i++)
335 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
337 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
338 * constant, GCC is incapable of figuring this out and unrolling the loop
339 * so we have to give it a little help.
341 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
342 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
343 if ((_i) < ma->ptr_count) \
344 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
345 _ANV_MULTIALLOC_UPDATE_POINTER(0);
346 _ANV_MULTIALLOC_UPDATE_POINTER(1);
347 _ANV_MULTIALLOC_UPDATE_POINTER(2);
348 _ANV_MULTIALLOC_UPDATE_POINTER(3);
349 _ANV_MULTIALLOC_UPDATE_POINTER(4);
350 _ANV_MULTIALLOC_UPDATE_POINTER(5);
351 _ANV_MULTIALLOC_UPDATE_POINTER(6);
352 _ANV_MULTIALLOC_UPDATE_POINTER(7);
353 #undef _ANV_MULTIALLOC_UPDATE_POINTER
358 __attribute__((always_inline
))
360 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
361 const VkAllocationCallbacks
*parent_alloc
,
362 const VkAllocationCallbacks
*alloc
,
363 VkSystemAllocationScope scope
)
365 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
369 * A dynamically growable, circular buffer. Elements are added at head and
370 * removed from tail. head and tail are free-running uint32_t indices and we
371 * only compute the modulo with size when accessing the array. This way,
372 * number of bytes in the queue is always head - tail, even in case of
379 /* Index into the current validation list. This is used by the
380 * validation list building alrogithm to track which buffers are already
381 * in the validation list so that we can ensure uniqueness.
385 /* Last known offset. This value is provided by the kernel when we
386 * execbuf and is used as the presumed offset for the next bunch of
394 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
399 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
401 bo
->gem_handle
= gem_handle
;
409 /* Represents a lock-free linked list of "free" things. This is used by
410 * both the block pool and the state pools. Unfortunately, in order to
411 * solve the ABA problem, we can't use a single uint32_t head.
413 union anv_free_list
{
417 /* A simple count that is incremented every time the head changes. */
423 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
425 struct anv_block_state
{
435 struct anv_block_pool
{
436 struct anv_device
*device
;
440 /* The offset from the start of the bo to the "center" of the block
441 * pool. Pointers to allocated blocks are given by
442 * bo.map + center_bo_offset + offsets.
444 uint32_t center_bo_offset
;
446 /* Current memory map of the block pool. This pointer may or may not
447 * point to the actual beginning of the block pool memory. If
448 * anv_block_pool_alloc_back has ever been called, then this pointer
449 * will point to the "center" position of the buffer and all offsets
450 * (negative or positive) given out by the block pool alloc functions
451 * will be valid relative to this pointer.
453 * In particular, map == bo.map + center_offset
459 * Array of mmaps and gem handles owned by the block pool, reclaimed when
460 * the block pool is destroyed.
462 struct u_vector mmap_cleanups
;
466 union anv_free_list free_list
;
467 struct anv_block_state state
;
469 union anv_free_list back_free_list
;
470 struct anv_block_state back_state
;
473 /* Block pools are backed by a fixed-size 1GB memfd */
474 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
476 /* The center of the block pool is also the middle of the memfd. This may
477 * change in the future if we decide differently for some reason.
479 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
481 static inline uint32_t
482 anv_block_pool_size(struct anv_block_pool
*pool
)
484 return pool
->state
.end
+ pool
->back_state
.end
;
493 struct anv_fixed_size_state_pool
{
495 union anv_free_list free_list
;
496 struct anv_block_state block
;
499 #define ANV_MIN_STATE_SIZE_LOG2 6
500 #define ANV_MAX_STATE_SIZE_LOG2 20
502 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
504 struct anv_state_pool
{
505 struct anv_block_pool
*block_pool
;
506 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
509 struct anv_state_stream_block
;
511 struct anv_state_stream
{
512 struct anv_block_pool
*block_pool
;
514 /* The current working block */
515 struct anv_state_stream_block
*block
;
517 /* Offset at which the current block starts */
519 /* Offset at which to allocate the next state */
521 /* Offset at which the current block ends */
525 #define CACHELINE_SIZE 64
526 #define CACHELINE_MASK 63
529 anv_clflush_range(void *start
, size_t size
)
531 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
532 void *end
= start
+ size
;
535 __builtin_ia32_clflush(p
);
541 anv_flush_range(void *start
, size_t size
)
543 __builtin_ia32_mfence();
544 anv_clflush_range(start
, size
);
548 anv_invalidate_range(void *start
, size_t size
)
550 anv_clflush_range(start
, size
);
551 __builtin_ia32_mfence();
554 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
555 struct anv_device
*device
, uint32_t block_size
);
556 void anv_block_pool_finish(struct anv_block_pool
*pool
);
557 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
);
558 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
);
559 void anv_block_pool_free(struct anv_block_pool
*pool
, int32_t offset
);
560 void anv_state_pool_init(struct anv_state_pool
*pool
,
561 struct anv_block_pool
*block_pool
);
562 void anv_state_pool_finish(struct anv_state_pool
*pool
);
563 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
564 size_t state_size
, size_t alignment
);
565 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
566 void anv_state_stream_init(struct anv_state_stream
*stream
,
567 struct anv_block_pool
*block_pool
);
568 void anv_state_stream_finish(struct anv_state_stream
*stream
);
569 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
570 uint32_t size
, uint32_t alignment
);
573 * Implements a pool of re-usable BOs. The interface is identical to that
574 * of block_pool except that each block is its own BO.
577 struct anv_device
*device
;
582 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
583 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
584 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
586 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
588 struct anv_scratch_bo
{
593 struct anv_scratch_pool
{
594 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
595 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
598 void anv_scratch_pool_init(struct anv_device
*device
,
599 struct anv_scratch_pool
*pool
);
600 void anv_scratch_pool_finish(struct anv_device
*device
,
601 struct anv_scratch_pool
*pool
);
602 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
603 struct anv_scratch_pool
*pool
,
604 gl_shader_stage stage
,
605 unsigned per_thread_scratch
);
607 struct anv_physical_device
{
608 VK_LOADER_DATA _loader_data
;
610 struct anv_instance
* instance
;
614 struct gen_device_info info
;
615 /** Amount of "GPU memory" we want to advertise
617 * Clearly, this value is bogus since Intel is a UMA architecture. On
618 * gen7 platforms, we are limited by GTT size unless we want to implement
619 * fine-grained tracking and GTT splitting. On Broadwell and above we are
620 * practically unlimited. However, we will never report more than 3/4 of
621 * the total system ram to try and avoid running out of RAM.
624 bool supports_48bit_addresses
;
625 struct brw_compiler
* compiler
;
626 struct isl_device isl_dev
;
627 int cmd_parser_version
;
630 uint32_t subslice_total
;
632 uint8_t uuid
[VK_UUID_SIZE
];
634 struct wsi_device wsi_device
;
638 struct anv_instance
{
639 VK_LOADER_DATA _loader_data
;
641 VkAllocationCallbacks alloc
;
644 int physicalDeviceCount
;
645 struct anv_physical_device physicalDevice
;
648 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
649 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
652 VK_LOADER_DATA _loader_data
;
654 struct anv_device
* device
;
656 struct anv_state_pool
* pool
;
659 struct anv_pipeline_cache
{
660 struct anv_device
* device
;
661 pthread_mutex_t mutex
;
663 struct hash_table
* cache
;
666 struct anv_pipeline_bind_map
;
668 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
669 struct anv_device
*device
,
671 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
673 struct anv_shader_bin
*
674 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
675 const void *key
, uint32_t key_size
);
676 struct anv_shader_bin
*
677 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
678 const void *key_data
, uint32_t key_size
,
679 const void *kernel_data
, uint32_t kernel_size
,
680 const struct brw_stage_prog_data
*prog_data
,
681 uint32_t prog_data_size
,
682 const struct anv_pipeline_bind_map
*bind_map
);
685 VK_LOADER_DATA _loader_data
;
687 VkAllocationCallbacks alloc
;
689 struct anv_instance
* instance
;
691 struct gen_device_info info
;
692 struct isl_device isl_dev
;
695 bool can_chain_batches
;
696 bool robust_buffer_access
;
698 struct anv_bo_pool batch_bo_pool
;
700 struct anv_block_pool dynamic_state_block_pool
;
701 struct anv_state_pool dynamic_state_pool
;
703 struct anv_block_pool instruction_block_pool
;
704 struct anv_state_pool instruction_state_pool
;
706 struct anv_block_pool surface_state_block_pool
;
707 struct anv_state_pool surface_state_pool
;
709 struct anv_bo workaround_bo
;
711 struct anv_pipeline_cache blorp_shader_cache
;
712 struct blorp_context blorp
;
714 struct anv_state border_colors
;
716 struct anv_queue queue
;
718 struct anv_scratch_pool scratch_pool
;
720 uint32_t default_mocs
;
722 pthread_mutex_t mutex
;
723 pthread_cond_t queue_submit
;
728 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
730 if (device
->info
.has_llc
)
733 anv_flush_range(state
.map
, state
.alloc_size
);
736 void anv_device_init_blorp(struct anv_device
*device
);
737 void anv_device_finish_blorp(struct anv_device
*device
);
739 VkResult
anv_device_execbuf(struct anv_device
*device
,
740 struct drm_i915_gem_execbuffer2
*execbuf
,
741 struct anv_bo
**execbuf_bos
);
742 VkResult
anv_device_query_status(struct anv_device
*device
);
743 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
744 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
747 void* anv_gem_mmap(struct anv_device
*device
,
748 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
749 void anv_gem_munmap(void *p
, uint64_t size
);
750 uint32_t anv_gem_create(struct anv_device
*device
, size_t size
);
751 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
752 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
753 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
754 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
755 int anv_gem_execbuffer(struct anv_device
*device
,
756 struct drm_i915_gem_execbuffer2
*execbuf
);
757 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
758 uint32_t stride
, uint32_t tiling
);
759 int anv_gem_create_context(struct anv_device
*device
);
760 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
761 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
763 int anv_gem_get_param(int fd
, uint32_t param
);
764 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
765 int anv_gem_get_aperture(int fd
, uint64_t *size
);
766 bool anv_gem_supports_48b_addresses(int fd
);
767 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
768 uint32_t *active
, uint32_t *pending
);
769 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
770 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
771 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
772 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
773 uint32_t read_domains
, uint32_t write_domain
);
775 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
777 struct anv_reloc_list
{
780 struct drm_i915_gem_relocation_entry
* relocs
;
781 struct anv_bo
** reloc_bos
;
784 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
785 const VkAllocationCallbacks
*alloc
);
786 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
787 const VkAllocationCallbacks
*alloc
);
789 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
790 const VkAllocationCallbacks
*alloc
,
791 uint32_t offset
, struct anv_bo
*target_bo
,
794 struct anv_batch_bo
{
795 /* Link in the anv_cmd_buffer.owned_batch_bos list */
796 struct list_head link
;
800 /* Bytes actually consumed in this batch BO */
803 struct anv_reloc_list relocs
;
807 const VkAllocationCallbacks
* alloc
;
813 struct anv_reloc_list
* relocs
;
815 /* This callback is called (with the associated user data) in the event
816 * that the batch runs out of space.
818 VkResult (*extend_cb
)(struct anv_batch
*, void *);
822 * Current error status of the command buffer. Used to track inconsistent
823 * or incomplete command buffer states that are the consequence of run-time
824 * errors such as out of memory scenarios. We want to track this in the
825 * batch because the command buffer object is not visible to some parts
831 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
832 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
833 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
834 void *location
, struct anv_bo
*bo
, uint32_t offset
);
835 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
836 struct anv_batch
*batch
);
838 static inline VkResult
839 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
841 assert(error
!= VK_SUCCESS
);
842 if (batch
->status
== VK_SUCCESS
)
843 batch
->status
= error
;
844 return batch
->status
;
848 anv_batch_has_error(struct anv_batch
*batch
)
850 return batch
->status
!= VK_SUCCESS
;
858 static inline uint64_t
859 _anv_combine_address(struct anv_batch
*batch
, void *location
,
860 const struct anv_address address
, uint32_t delta
)
862 if (address
.bo
== NULL
) {
863 return address
.offset
+ delta
;
865 assert(batch
->start
<= location
&& location
< batch
->end
);
867 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
871 #define __gen_address_type struct anv_address
872 #define __gen_user_data struct anv_batch
873 #define __gen_combine_address _anv_combine_address
875 /* Wrapper macros needed to work around preprocessor argument issues. In
876 * particular, arguments don't get pre-evaluated if they are concatenated.
877 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
878 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
879 * We can work around this easily enough with these helpers.
881 #define __anv_cmd_length(cmd) cmd ## _length
882 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
883 #define __anv_cmd_header(cmd) cmd ## _header
884 #define __anv_cmd_pack(cmd) cmd ## _pack
885 #define __anv_reg_num(reg) reg ## _num
887 #define anv_pack_struct(dst, struc, ...) do { \
888 struct struc __template = { \
891 __anv_cmd_pack(struc)(NULL, dst, &__template); \
892 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
895 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
896 void *__dst = anv_batch_emit_dwords(batch, n); \
898 struct cmd __template = { \
899 __anv_cmd_header(cmd), \
900 .DWordLength = n - __anv_cmd_length_bias(cmd), \
903 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
908 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
912 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
913 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
916 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
917 dw[i] = (dwords0)[i] | (dwords1)[i]; \
918 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
921 #define anv_batch_emit(batch, cmd, name) \
922 for (struct cmd name = { __anv_cmd_header(cmd) }, \
923 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
924 __builtin_expect(_dst != NULL, 1); \
925 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
926 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
930 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
931 .GraphicsDataTypeGFDT = 0, \
932 .LLCCacheabilityControlLLCCC = 0, \
933 .L3CacheabilityControlL3CC = 1, \
936 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
937 .LLCeLLCCacheabilityControlLLCCC = 0, \
938 .L3CacheabilityControlL3CC = 1, \
941 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
942 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
943 .TargetCache = L3DefertoPATforLLCeLLCselection, \
947 /* Skylake: MOCS is now an index into an array of 62 different caching
948 * configurations programmed by the kernel.
951 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
952 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
953 .IndextoMOCSTables = 2 \
956 #define GEN9_MOCS_PTE { \
957 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
958 .IndextoMOCSTables = 1 \
961 struct anv_device_memory
{
964 VkDeviceSize map_size
;
969 * Header for Vertex URB Entry (VUE)
971 struct anv_vue_header
{
973 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
974 uint32_t ViewportIndex
;
978 struct anv_descriptor_set_binding_layout
{
980 /* The type of the descriptors in this binding */
981 VkDescriptorType type
;
984 /* Number of array elements in this binding */
987 /* Index into the flattend descriptor set */
988 uint16_t descriptor_index
;
990 /* Index into the dynamic state array for a dynamic buffer */
991 int16_t dynamic_offset_index
;
993 /* Index into the descriptor set buffer views */
994 int16_t buffer_index
;
997 /* Index into the binding table for the associated surface */
998 int16_t surface_index
;
1000 /* Index into the sampler table for the associated sampler */
1001 int16_t sampler_index
;
1003 /* Index into the image table for the associated image */
1004 int16_t image_index
;
1005 } stage
[MESA_SHADER_STAGES
];
1007 /* Immutable samplers (or NULL if no immutable samplers) */
1008 struct anv_sampler
**immutable_samplers
;
1011 struct anv_descriptor_set_layout
{
1012 /* Number of bindings in this descriptor set */
1013 uint16_t binding_count
;
1015 /* Total size of the descriptor set with room for all array entries */
1018 /* Shader stages affected by this descriptor set */
1019 uint16_t shader_stages
;
1021 /* Number of buffers in this descriptor set */
1022 uint16_t buffer_count
;
1024 /* Number of dynamic offsets used by this descriptor set */
1025 uint16_t dynamic_offset_count
;
1027 /* Bindings in this descriptor set */
1028 struct anv_descriptor_set_binding_layout binding
[0];
1031 struct anv_descriptor
{
1032 VkDescriptorType type
;
1036 struct anv_image_view
*image_view
;
1037 struct anv_sampler
*sampler
;
1039 /* Used to determine whether or not we need the surface state to have
1040 * the auxiliary buffer enabled.
1042 enum isl_aux_usage aux_usage
;
1046 struct anv_buffer
*buffer
;
1051 struct anv_buffer_view
*buffer_view
;
1055 struct anv_descriptor_set
{
1056 const struct anv_descriptor_set_layout
*layout
;
1058 uint32_t buffer_count
;
1059 struct anv_buffer_view
*buffer_views
;
1060 struct anv_descriptor descriptors
[0];
1063 struct anv_buffer_view
{
1064 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1066 uint32_t offset
; /**< Offset into bo. */
1067 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1069 struct anv_state surface_state
;
1070 struct anv_state storage_surface_state
;
1071 struct anv_state writeonly_storage_surface_state
;
1073 struct brw_image_param storage_image_param
;
1076 struct anv_push_descriptor_set
{
1077 struct anv_descriptor_set set
;
1079 /* Put this field right behind anv_descriptor_set so it fills up the
1080 * descriptors[0] field. */
1081 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1083 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1086 struct anv_descriptor_pool
{
1091 struct anv_state_stream surface_state_stream
;
1092 void *surface_state_free_list
;
1097 enum anv_descriptor_template_entry_type
{
1098 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1099 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1100 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1103 struct anv_descriptor_template_entry
{
1104 /* The type of descriptor in this entry */
1105 VkDescriptorType type
;
1107 /* Binding in the descriptor set */
1110 /* Offset at which to write into the descriptor set binding */
1111 uint32_t array_element
;
1113 /* Number of elements to write into the descriptor set binding */
1114 uint32_t array_count
;
1116 /* Offset into the user provided data */
1119 /* Stride between elements into the user provided data */
1123 struct anv_descriptor_update_template
{
1124 /* The descriptor set this template corresponds to. This value is only
1125 * valid if the template was created with the templateType
1126 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1130 /* Number of entries in this template */
1131 uint32_t entry_count
;
1133 /* Entries of the template */
1134 struct anv_descriptor_template_entry entries
[0];
1138 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1141 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1142 const struct gen_device_info
* const devinfo
,
1143 const VkDescriptorImageInfo
* const info
,
1144 VkDescriptorType type
,
1149 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1150 VkDescriptorType type
,
1151 struct anv_buffer_view
*buffer_view
,
1156 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1157 struct anv_device
*device
,
1158 struct anv_state_stream
*alloc_stream
,
1159 VkDescriptorType type
,
1160 struct anv_buffer
*buffer
,
1163 VkDeviceSize offset
,
1164 VkDeviceSize range
);
1167 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1168 struct anv_device
*device
,
1169 struct anv_state_stream
*alloc_stream
,
1170 const struct anv_descriptor_update_template
*template,
1174 anv_descriptor_set_create(struct anv_device
*device
,
1175 struct anv_descriptor_pool
*pool
,
1176 const struct anv_descriptor_set_layout
*layout
,
1177 struct anv_descriptor_set
**out_set
);
1180 anv_descriptor_set_destroy(struct anv_device
*device
,
1181 struct anv_descriptor_pool
*pool
,
1182 struct anv_descriptor_set
*set
);
1184 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1186 struct anv_pipeline_binding
{
1187 /* The descriptor set this surface corresponds to. The special value of
1188 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1189 * to a color attachment and not a regular descriptor.
1193 /* Binding in the descriptor set */
1196 /* Index in the binding */
1199 /* Input attachment index (relative to the subpass) */
1200 uint8_t input_attachment_index
;
1202 /* For a storage image, whether it is write-only */
1206 struct anv_pipeline_layout
{
1208 struct anv_descriptor_set_layout
*layout
;
1209 uint32_t dynamic_offset_start
;
1215 bool has_dynamic_offsets
;
1216 } stage
[MESA_SHADER_STAGES
];
1218 unsigned char sha1
[20];
1222 struct anv_device
* device
;
1225 VkBufferUsageFlags usage
;
1227 /* Set when bound */
1229 VkDeviceSize offset
;
1232 static inline uint64_t
1233 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1235 assert(offset
<= buffer
->size
);
1236 if (range
== VK_WHOLE_SIZE
) {
1237 return buffer
->size
- offset
;
1239 assert(range
<= buffer
->size
);
1244 enum anv_cmd_dirty_bits
{
1245 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1246 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1247 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1248 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1249 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1250 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1251 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1252 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1253 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1254 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1255 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1256 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1257 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1259 typedef uint32_t anv_cmd_dirty_mask_t
;
1261 enum anv_pipe_bits
{
1262 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1263 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1264 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1265 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1266 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1267 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1268 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1269 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1270 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1271 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1272 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1274 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1275 * a flush has happened but not a CS stall. The next time we do any sort
1276 * of invalidation we need to insert a CS stall at that time. Otherwise,
1277 * we would have to CS stall on every flush which could be bad.
1279 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1282 #define ANV_PIPE_FLUSH_BITS ( \
1283 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1284 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1285 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1287 #define ANV_PIPE_STALL_BITS ( \
1288 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1289 ANV_PIPE_DEPTH_STALL_BIT | \
1290 ANV_PIPE_CS_STALL_BIT)
1292 #define ANV_PIPE_INVALIDATE_BITS ( \
1293 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1294 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1295 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1296 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1297 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1298 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1300 static inline enum anv_pipe_bits
1301 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1303 enum anv_pipe_bits pipe_bits
= 0;
1306 for_each_bit(b
, flags
) {
1307 switch ((VkAccessFlagBits
)(1 << b
)) {
1308 case VK_ACCESS_SHADER_WRITE_BIT
:
1309 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1311 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1312 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1314 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1315 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1317 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1318 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1319 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1322 break; /* Nothing to do */
1329 static inline enum anv_pipe_bits
1330 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1332 enum anv_pipe_bits pipe_bits
= 0;
1335 for_each_bit(b
, flags
) {
1336 switch ((VkAccessFlagBits
)(1 << b
)) {
1337 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1338 case VK_ACCESS_INDEX_READ_BIT
:
1339 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1340 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1342 case VK_ACCESS_UNIFORM_READ_BIT
:
1343 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1344 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1346 case VK_ACCESS_SHADER_READ_BIT
:
1347 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1348 case VK_ACCESS_TRANSFER_READ_BIT
:
1349 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1352 break; /* Nothing to do */
1359 struct anv_vertex_binding
{
1360 struct anv_buffer
* buffer
;
1361 VkDeviceSize offset
;
1364 struct anv_push_constants
{
1365 /* Current allocated size of this push constants data structure.
1366 * Because a decent chunk of it may not be used (images on SKL, for
1367 * instance), we won't actually allocate the entire structure up-front.
1371 /* Push constant data provided by the client through vkPushConstants */
1372 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1374 /* Our hardware only provides zero-based vertex and instance id so, in
1375 * order to satisfy the vulkan requirements, we may have to push one or
1376 * both of these into the shader.
1378 uint32_t base_vertex
;
1379 uint32_t base_instance
;
1381 /* Image data for image_load_store on pre-SKL */
1382 struct brw_image_param images
[MAX_IMAGES
];
1385 struct anv_dynamic_state
{
1388 VkViewport viewports
[MAX_VIEWPORTS
];
1393 VkRect2D scissors
[MAX_SCISSORS
];
1404 float blend_constants
[4];
1414 } stencil_compare_mask
;
1419 } stencil_write_mask
;
1424 } stencil_reference
;
1427 extern const struct anv_dynamic_state default_dynamic_state
;
1429 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1430 const struct anv_dynamic_state
*src
,
1431 uint32_t copy_mask
);
1434 * Attachment state when recording a renderpass instance.
1436 * The clear value is valid only if there exists a pending clear.
1438 struct anv_attachment_state
{
1439 enum isl_aux_usage aux_usage
;
1440 enum isl_aux_usage input_aux_usage
;
1441 struct anv_state color_rt_state
;
1442 struct anv_state input_att_state
;
1444 VkImageLayout current_layout
;
1445 VkImageAspectFlags pending_clear_aspects
;
1447 VkClearValue clear_value
;
1448 bool clear_color_is_zero_one
;
1451 /** State required while building cmd buffer */
1452 struct anv_cmd_state
{
1453 /* PIPELINE_SELECT.PipelineSelection */
1454 uint32_t current_pipeline
;
1455 const struct gen_l3_config
* current_l3_config
;
1457 anv_cmd_dirty_mask_t dirty
;
1458 anv_cmd_dirty_mask_t compute_dirty
;
1459 enum anv_pipe_bits pending_pipe_bits
;
1460 uint32_t num_workgroups_offset
;
1461 struct anv_bo
*num_workgroups_bo
;
1462 VkShaderStageFlags descriptors_dirty
;
1463 VkShaderStageFlags push_constants_dirty
;
1464 uint32_t scratch_size
;
1465 struct anv_pipeline
* pipeline
;
1466 struct anv_pipeline
* compute_pipeline
;
1467 struct anv_framebuffer
* framebuffer
;
1468 struct anv_render_pass
* pass
;
1469 struct anv_subpass
* subpass
;
1470 VkRect2D render_area
;
1471 uint32_t restart_index
;
1472 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1473 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1474 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
1475 VkShaderStageFlags push_constant_stages
;
1476 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1477 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1478 struct anv_state samplers
[MESA_SHADER_STAGES
];
1479 struct anv_dynamic_state dynamic
;
1482 struct anv_push_descriptor_set push_descriptor
;
1485 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1486 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1487 * and before invoking the secondary in ExecuteCommands.
1489 bool pma_fix_enabled
;
1492 * Whether or not we know for certain that HiZ is enabled for the current
1493 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1494 * enabled or not, this will be false.
1499 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1500 * valid only when recording a render pass instance.
1502 struct anv_attachment_state
* attachments
;
1505 * Surface states for color render targets. These are stored in a single
1506 * flat array. For depth-stencil attachments, the surface state is simply
1509 struct anv_state render_pass_states
;
1512 * A null surface state of the right size to match the framebuffer. This
1513 * is one of the states in render_pass_states.
1515 struct anv_state null_surface_state
;
1518 struct anv_buffer
* index_buffer
;
1519 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1520 uint32_t index_offset
;
1524 struct anv_cmd_pool
{
1525 VkAllocationCallbacks alloc
;
1526 struct list_head cmd_buffers
;
1529 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1531 enum anv_cmd_buffer_exec_mode
{
1532 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1533 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1534 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1535 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1536 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1539 struct anv_cmd_buffer
{
1540 VK_LOADER_DATA _loader_data
;
1542 struct anv_device
* device
;
1544 struct anv_cmd_pool
* pool
;
1545 struct list_head pool_link
;
1547 struct anv_batch batch
;
1549 /* Fields required for the actual chain of anv_batch_bo's.
1551 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1553 struct list_head batch_bos
;
1554 enum anv_cmd_buffer_exec_mode exec_mode
;
1556 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1557 * referenced by this command buffer
1559 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1561 struct u_vector seen_bbos
;
1563 /* A vector of int32_t's for every block of binding tables.
1565 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1567 struct u_vector bt_blocks
;
1570 struct anv_reloc_list surface_relocs
;
1571 /** Last seen surface state block pool center bo offset */
1572 uint32_t last_ss_pool_center
;
1574 /* Serial for tracking buffer completion */
1577 /* Stream objects for storing temporary data */
1578 struct anv_state_stream surface_state_stream
;
1579 struct anv_state_stream dynamic_state_stream
;
1581 VkCommandBufferUsageFlags usage_flags
;
1582 VkCommandBufferLevel level
;
1584 struct anv_cmd_state state
;
1587 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1588 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1589 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1590 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1591 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1592 struct anv_cmd_buffer
*secondary
);
1593 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1594 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1595 struct anv_cmd_buffer
*cmd_buffer
);
1597 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1600 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1601 gl_shader_stage stage
, uint32_t size
);
1602 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1603 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1604 (offsetof(struct anv_push_constants, field) + \
1605 sizeof(cmd_buffer->state.push_constants[0]->field)))
1607 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1608 const void *data
, uint32_t size
, uint32_t alignment
);
1609 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1610 uint32_t *a
, uint32_t *b
,
1611 uint32_t dwords
, uint32_t alignment
);
1614 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1616 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1617 uint32_t entries
, uint32_t *state_offset
);
1619 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1621 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1622 uint32_t size
, uint32_t alignment
);
1625 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1627 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1628 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1629 bool depth_clamp_enable
);
1630 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1632 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1633 struct anv_render_pass
*pass
,
1634 struct anv_framebuffer
*framebuffer
,
1635 const VkClearValue
*clear_values
);
1637 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1640 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1641 gl_shader_stage stage
);
1643 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1645 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1646 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1648 const struct anv_image_view
*
1649 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1652 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1653 uint32_t num_entries
,
1654 uint32_t *state_offset
,
1655 struct anv_state
*bt_state
);
1657 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1659 enum anv_fence_state
{
1660 /** Indicates that this is a new (or newly reset fence) */
1661 ANV_FENCE_STATE_RESET
,
1663 /** Indicates that this fence has been submitted to the GPU but is still
1664 * (as far as we know) in use by the GPU.
1666 ANV_FENCE_STATE_SUBMITTED
,
1668 ANV_FENCE_STATE_SIGNALED
,
1673 struct drm_i915_gem_execbuffer2 execbuf
;
1674 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1675 enum anv_fence_state state
;
1680 struct anv_state state
;
1683 struct anv_shader_module
{
1684 unsigned char sha1
[20];
1689 void anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
1690 struct anv_shader_module
*module
,
1691 const char *entrypoint
,
1692 const struct anv_pipeline_layout
*pipeline_layout
,
1693 const VkSpecializationInfo
*spec_info
);
1695 static inline gl_shader_stage
1696 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1698 assert(__builtin_popcount(vk_stage
) == 1);
1699 return ffs(vk_stage
) - 1;
1702 static inline VkShaderStageFlagBits
1703 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1705 return (1 << mesa_stage
);
1708 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1710 #define anv_foreach_stage(stage, stage_bits) \
1711 for (gl_shader_stage stage, \
1712 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1713 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1714 __tmp &= ~(1 << (stage)))
1716 struct anv_pipeline_bind_map
{
1717 uint32_t surface_count
;
1718 uint32_t sampler_count
;
1719 uint32_t image_count
;
1721 struct anv_pipeline_binding
* surface_to_descriptor
;
1722 struct anv_pipeline_binding
* sampler_to_descriptor
;
1725 struct anv_shader_bin_key
{
1730 struct anv_shader_bin
{
1733 const struct anv_shader_bin_key
*key
;
1735 struct anv_state kernel
;
1736 uint32_t kernel_size
;
1738 const struct brw_stage_prog_data
*prog_data
;
1739 uint32_t prog_data_size
;
1741 struct anv_pipeline_bind_map bind_map
;
1743 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1746 struct anv_shader_bin
*
1747 anv_shader_bin_create(struct anv_device
*device
,
1748 const void *key
, uint32_t key_size
,
1749 const void *kernel
, uint32_t kernel_size
,
1750 const struct brw_stage_prog_data
*prog_data
,
1751 uint32_t prog_data_size
, const void *prog_data_param
,
1752 const struct anv_pipeline_bind_map
*bind_map
);
1755 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1758 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1760 assert(shader
&& shader
->ref_cnt
>= 1);
1761 __sync_fetch_and_add(&shader
->ref_cnt
, 1);
1765 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1767 assert(shader
&& shader
->ref_cnt
>= 1);
1768 if (__sync_fetch_and_add(&shader
->ref_cnt
, -1) == 1)
1769 anv_shader_bin_destroy(device
, shader
);
1772 struct anv_pipeline
{
1773 struct anv_device
* device
;
1774 struct anv_batch batch
;
1775 uint32_t batch_data
[512];
1776 struct anv_reloc_list batch_relocs
;
1777 uint32_t dynamic_state_mask
;
1778 struct anv_dynamic_state dynamic_state
;
1780 struct anv_pipeline_layout
* layout
;
1782 bool needs_data_cache
;
1784 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1787 const struct gen_l3_config
* l3_config
;
1788 uint32_t total_size
;
1791 VkShaderStageFlags active_stages
;
1792 struct anv_state blend_state
;
1795 uint32_t binding_stride
[MAX_VBS
];
1796 bool instancing_enable
[MAX_VBS
];
1797 bool primitive_restart
;
1800 uint32_t cs_right_mask
;
1803 bool depth_test_enable
;
1804 bool writes_stencil
;
1805 bool stencil_test_enable
;
1806 bool depth_clamp_enable
;
1807 bool sample_shading_enable
;
1812 uint32_t depth_stencil_state
[3];
1818 uint32_t wm_depth_stencil
[3];
1822 uint32_t wm_depth_stencil
[4];
1825 uint32_t interface_descriptor_data
[8];
1829 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1830 gl_shader_stage stage
)
1832 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1835 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1836 static inline const struct brw_##prefix##_prog_data * \
1837 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1839 if (anv_pipeline_has_stage(pipeline, stage)) { \
1840 return (const struct brw_##prefix##_prog_data *) \
1841 pipeline->shaders[stage]->prog_data; \
1847 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1848 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
1849 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
1850 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1851 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1852 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1854 static inline const struct brw_vue_prog_data
*
1855 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
1857 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1858 return &get_gs_prog_data(pipeline
)->base
;
1859 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1860 return &get_tes_prog_data(pipeline
)->base
;
1862 return &get_vs_prog_data(pipeline
)->base
;
1866 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1867 struct anv_pipeline_cache
*cache
,
1868 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1869 const VkAllocationCallbacks
*alloc
);
1872 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1873 struct anv_pipeline_cache
*cache
,
1874 const VkComputePipelineCreateInfo
*info
,
1875 struct anv_shader_module
*module
,
1876 const char *entrypoint
,
1877 const VkSpecializationInfo
*spec_info
);
1880 enum isl_format isl_format
:16;
1881 struct isl_swizzle swizzle
;
1885 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1886 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1888 static inline enum isl_format
1889 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1890 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1892 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1895 static inline struct isl_swizzle
1896 anv_swizzle_for_render(struct isl_swizzle swizzle
)
1898 /* Sometimes the swizzle will have alpha map to one. We do this to fake
1899 * RGB as RGBA for texturing
1901 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
1902 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
1904 /* But it doesn't matter what we render to that channel */
1905 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
1911 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
1914 * Subsurface of an anv_image.
1916 struct anv_surface
{
1917 /** Valid only if isl_surf::size > 0. */
1918 struct isl_surf isl
;
1921 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1928 /* The original VkFormat provided by the client. This may not match any
1929 * of the actual surface formats.
1932 VkImageAspectFlags aspects
;
1935 uint32_t array_size
;
1936 uint32_t samples
; /**< VkImageCreateInfo::samples */
1937 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1938 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1943 /* Set when bound */
1945 VkDeviceSize offset
;
1950 * For each foo, anv_image::foo_surface is valid if and only if
1951 * anv_image::aspects has a foo aspect.
1953 * The hardware requires that the depth buffer and stencil buffer be
1954 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1955 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1956 * allocate the depth and stencil buffers as separate surfaces in the same
1960 struct anv_surface color_surface
;
1963 struct anv_surface depth_surface
;
1964 struct anv_surface stencil_surface
;
1969 * For color images, this is the aux usage for this image when not used as a
1972 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
1975 enum isl_aux_usage aux_usage
;
1977 struct anv_surface aux_surface
;
1980 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
1982 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
1983 const VkImageAspectFlags aspect_mask
,
1984 const uint32_t samples
)
1986 /* Validate the inputs. */
1987 assert(devinfo
&& aspect_mask
&& samples
);
1988 return devinfo
->gen
>= 8 && (aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1993 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
1994 const struct anv_image
*image
,
1995 enum blorp_hiz_op op
);
1998 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
1999 const struct anv_image
*image
,
2000 const VkImageAspectFlags aspects
,
2001 const VkImageLayout layout
);
2003 /* This is defined as a macro so that it works for both
2004 * VkImageSubresourceRange and VkImageSubresourceLayers
2006 #define anv_get_layerCount(_image, _range) \
2007 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2008 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2010 static inline uint32_t
2011 anv_get_levelCount(const struct anv_image
*image
,
2012 const VkImageSubresourceRange
*range
)
2014 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
2015 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
2019 struct anv_image_view
{
2020 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
2022 uint32_t offset
; /**< Offset into bo. */
2024 struct isl_view isl
;
2026 VkImageAspectFlags aspect_mask
;
2028 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2030 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
2031 struct anv_state sampler_surface_state
;
2034 * RENDER_SURFACE_STATE when using image as a sampler surface with the
2035 * auxiliary buffer disabled.
2037 struct anv_state no_aux_sampler_surface_state
;
2040 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
2041 * for write-only and readable, using the real format for write-only and the
2042 * lowered format for readable.
2044 struct anv_state storage_surface_state
;
2045 struct anv_state writeonly_storage_surface_state
;
2047 struct brw_image_param storage_image_param
;
2050 struct anv_image_create_info
{
2051 const VkImageCreateInfo
*vk_info
;
2053 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2054 isl_tiling_flags_t isl_tiling_flags
;
2059 VkResult
anv_image_create(VkDevice _device
,
2060 const struct anv_image_create_info
*info
,
2061 const VkAllocationCallbacks
* alloc
,
2064 const struct anv_surface
*
2065 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
2066 VkImageAspectFlags aspect_mask
);
2069 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
2071 static inline struct VkExtent3D
2072 anv_sanitize_image_extent(const VkImageType imageType
,
2073 const struct VkExtent3D imageExtent
)
2075 switch (imageType
) {
2076 case VK_IMAGE_TYPE_1D
:
2077 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2078 case VK_IMAGE_TYPE_2D
:
2079 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2080 case VK_IMAGE_TYPE_3D
:
2083 unreachable("invalid image type");
2087 static inline struct VkOffset3D
2088 anv_sanitize_image_offset(const VkImageType imageType
,
2089 const struct VkOffset3D imageOffset
)
2091 switch (imageType
) {
2092 case VK_IMAGE_TYPE_1D
:
2093 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2094 case VK_IMAGE_TYPE_2D
:
2095 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2096 case VK_IMAGE_TYPE_3D
:
2099 unreachable("invalid image type");
2104 void anv_fill_buffer_surface_state(struct anv_device
*device
,
2105 struct anv_state state
,
2106 enum isl_format format
,
2107 uint32_t offset
, uint32_t range
,
2110 void anv_image_view_fill_image_param(struct anv_device
*device
,
2111 struct anv_image_view
*view
,
2112 struct brw_image_param
*param
);
2113 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
2114 struct anv_buffer_view
*view
,
2115 struct brw_image_param
*param
);
2117 struct anv_sampler
{
2121 struct anv_framebuffer
{
2126 uint32_t attachment_count
;
2127 struct anv_image_view
* attachments
[0];
2130 struct anv_subpass
{
2131 uint32_t attachment_count
;
2134 * A pointer to all attachment references used in this subpass.
2135 * Only valid if ::attachment_count > 0.
2137 VkAttachmentReference
* attachments
;
2138 uint32_t input_count
;
2139 VkAttachmentReference
* input_attachments
;
2140 uint32_t color_count
;
2141 VkAttachmentReference
* color_attachments
;
2142 VkAttachmentReference
* resolve_attachments
;
2144 VkAttachmentReference depth_stencil_attachment
;
2146 /** Subpass has a depth/stencil self-dependency */
2147 bool has_ds_self_dep
;
2149 /** Subpass has at least one resolve attachment */
2153 enum anv_subpass_usage
{
2154 ANV_SUBPASS_USAGE_DRAW
= (1 << 0),
2155 ANV_SUBPASS_USAGE_INPUT
= (1 << 1),
2156 ANV_SUBPASS_USAGE_RESOLVE_SRC
= (1 << 2),
2157 ANV_SUBPASS_USAGE_RESOLVE_DST
= (1 << 3),
2160 struct anv_render_pass_attachment
{
2161 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2162 * its members individually.
2166 VkImageUsageFlags usage
;
2167 VkAttachmentLoadOp load_op
;
2168 VkAttachmentStoreOp store_op
;
2169 VkAttachmentLoadOp stencil_load_op
;
2170 VkImageLayout initial_layout
;
2171 VkImageLayout final_layout
;
2173 /* An array, indexed by subpass id, of how the attachment will be used. */
2174 enum anv_subpass_usage
* subpass_usage
;
2176 /* The subpass id in which the attachment will be used last. */
2177 uint32_t last_subpass_idx
;
2180 struct anv_render_pass
{
2181 uint32_t attachment_count
;
2182 uint32_t subpass_count
;
2183 VkAttachmentReference
* subpass_attachments
;
2184 struct anv_render_pass_attachment
* attachments
;
2185 struct anv_subpass subpasses
[0];
2188 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2190 struct anv_query_pool
{
2192 VkQueryPipelineStatisticFlags pipeline_statistics
;
2193 /** Stride between slots, in bytes */
2195 /** Number of slots in this query pool */
2200 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
2203 void anv_dump_image_to_ppm(struct anv_device
*device
,
2204 struct anv_image
*image
, unsigned miplevel
,
2205 unsigned array_layer
, VkImageAspectFlagBits aspect
,
2206 const char *filename
);
2208 enum anv_dump_action
{
2209 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
2212 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
2213 void anv_dump_finish(void);
2215 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
2216 struct anv_framebuffer
*fb
);
2218 static inline uint32_t
2219 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
2221 /* This function must be called from within a subpass. */
2222 assert(cmd_state
->pass
&& cmd_state
->subpass
);
2224 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
2226 /* The id of this subpass shouldn't exceed the number of subpasses in this
2227 * render pass minus 1.
2229 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
2233 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2235 static inline struct __anv_type * \
2236 __anv_type ## _from_handle(__VkType _handle) \
2238 return (struct __anv_type *) _handle; \
2241 static inline __VkType \
2242 __anv_type ## _to_handle(struct __anv_type *_obj) \
2244 return (__VkType) _obj; \
2247 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2249 static inline struct __anv_type * \
2250 __anv_type ## _from_handle(__VkType _handle) \
2252 return (struct __anv_type *)(uintptr_t) _handle; \
2255 static inline __VkType \
2256 __anv_type ## _to_handle(struct __anv_type *_obj) \
2258 return (__VkType)(uintptr_t) _obj; \
2261 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2262 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2264 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
2265 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
2266 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
2267 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
2268 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
2270 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
2271 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
2272 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
2273 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
2274 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
2275 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
2276 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
2277 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
2278 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
2279 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
2280 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
2281 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
2282 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
2283 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
2284 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
2285 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
2286 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
2287 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
2288 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
2289 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
2291 /* Gen-specific function declarations */
2293 # include "anv_genX.h"
2295 # define genX(x) gen7_##x
2296 # include "anv_genX.h"
2298 # define genX(x) gen75_##x
2299 # include "anv_genX.h"
2301 # define genX(x) gen8_##x
2302 # include "anv_genX.h"
2304 # define genX(x) gen9_##x
2305 # include "anv_genX.h"
2309 #endif /* ANV_PRIVATE_H */