2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
62 #include "util/xmlconfig.h"
64 #include "vk_debug_report.h"
65 #include "vk_object.h"
67 /* Pre-declarations needed for WSI entrypoints */
70 typedef struct xcb_connection_t xcb_connection_t
;
71 typedef uint32_t xcb_visualid_t
;
72 typedef uint32_t xcb_window_t
;
76 struct anv_buffer_view
;
77 struct anv_image_view
;
80 struct gen_aux_map_context
;
81 struct gen_perf_config
;
83 #include <vulkan/vulkan.h>
84 #include <vulkan/vulkan_intel.h>
85 #include <vulkan/vk_icd.h>
87 #include "anv_android.h"
88 #include "anv_entrypoints.h"
89 #include "anv_extensions.h"
92 #include "dev/gen_debug.h"
93 #include "common/intel_log.h"
94 #include "wsi_common.h"
96 #define NSEC_PER_SEC 1000000000ull
98 /* anv Virtual Memory Layout
99 * =========================
101 * When the anv driver is determining the virtual graphics addresses of memory
102 * objects itself using the softpin mechanism, the following memory ranges
105 * Three special considerations to notice:
107 * (1) the dynamic state pool is located within the same 4 GiB as the low
108 * heap. This is to work around a VF cache issue described in a comment in
109 * anv_physical_device_init_heaps.
111 * (2) the binding table pool is located at lower addresses than the surface
112 * state pool, within a 4 GiB range. This allows surface state base addresses
113 * to cover both binding tables (16 bit offsets) and surface states (32 bit
116 * (3) the last 4 GiB of the address space is withheld from the high
117 * heap. Various hardware units will read past the end of an object for
118 * various reasons. This healthy margin prevents reads from wrapping around
121 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
122 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
123 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
124 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
125 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
126 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
127 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
128 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
129 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
130 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
131 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
132 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
133 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
135 #define LOW_HEAP_SIZE \
136 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
137 #define DYNAMIC_STATE_POOL_SIZE \
138 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
139 #define BINDING_TABLE_POOL_SIZE \
140 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
141 #define SURFACE_STATE_POOL_SIZE \
142 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
143 #define INSTRUCTION_STATE_POOL_SIZE \
144 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
145 #define CLIENT_VISIBLE_HEAP_SIZE \
146 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
148 /* Allowing different clear colors requires us to perform a depth resolve at
149 * the end of certain render passes. This is because while slow clears store
150 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
151 * See the PRMs for examples describing when additional resolves would be
152 * necessary. To enable fast clears without requiring extra resolves, we set
153 * the clear value to a globally-defined one. We could allow different values
154 * if the user doesn't expect coherent data during or after a render passes
155 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
156 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
157 * 1.0f seems to be the only value used. The only application that doesn't set
158 * this value does so through the usage of an seemingly uninitialized clear
161 #define ANV_HZ_FC_VAL 1.0f
164 #define MAX_XFB_BUFFERS 4
165 #define MAX_XFB_STREAMS 4
168 #define MAX_VIEWPORTS 16
169 #define MAX_SCISSORS 16
170 #define MAX_PUSH_CONSTANTS_SIZE 128
171 #define MAX_DYNAMIC_BUFFERS 16
172 #define MAX_IMAGES 64
173 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
174 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
175 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
176 /* We need 16 for UBO block reads to work and 32 for push UBOs. However, we
177 * use 64 here to avoid cache issues. This could most likely bring it back to
178 * 32 if we had different virtual addresses for the different views on a given
181 #define ANV_UBO_ALIGNMENT 64
182 #define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
183 #define MAX_VIEWS_FOR_PRIMITIVE_REPLICATION 16
185 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
187 * "The surface state model is used when a Binding Table Index (specified
188 * in the message descriptor) of less than 240 is specified. In this model,
189 * the Binding Table Index is used to index into the binding table, and the
190 * binding table entry contains a pointer to the SURFACE_STATE."
192 * Binding table values above 240 are used for various things in the hardware
193 * such as stateless, stateless with incoherent cache, SLM, and bindless.
195 #define MAX_BINDING_TABLE_SIZE 240
197 /* The kernel relocation API has a limitation of a 32-bit delta value
198 * applied to the address before it is written which, in spite of it being
199 * unsigned, is treated as signed . Because of the way that this maps to
200 * the Vulkan API, we cannot handle an offset into a buffer that does not
201 * fit into a signed 32 bits. The only mechanism we have for dealing with
202 * this at the moment is to limit all VkDeviceMemory objects to a maximum
203 * of 2GB each. The Vulkan spec allows us to do this:
205 * "Some platforms may have a limit on the maximum size of a single
206 * allocation. For example, certain systems may fail to create
207 * allocations with a size greater than or equal to 4GB. Such a limit is
208 * implementation-dependent, and if such a failure occurs then the error
209 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
211 * We don't use vk_error here because it's not an error so much as an
212 * indication to the application that the allocation is too large.
214 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
216 #define ANV_SVGS_VB_INDEX MAX_VBS
217 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
219 /* We reserve this MI ALU register for the purpose of handling predication.
220 * Other code which uses the MI ALU should leave it alone.
222 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
224 /* For gen12 we set the streamout buffers using 4 separate commands
225 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
226 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
227 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
228 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
229 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
230 * 3DSTATE_SO_BUFFER_INDEX_0.
232 #define SO_BUFFER_INDEX_0_CMD 0x60
233 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
235 static inline uint32_t
236 align_down_npot_u32(uint32_t v
, uint32_t a
)
241 static inline uint32_t
242 align_down_u32(uint32_t v
, uint32_t a
)
244 assert(a
!= 0 && a
== (a
& -a
));
248 static inline uint32_t
249 align_u32(uint32_t v
, uint32_t a
)
251 assert(a
!= 0 && a
== (a
& -a
));
252 return align_down_u32(v
+ a
- 1, a
);
255 static inline uint64_t
256 align_down_u64(uint64_t v
, uint64_t a
)
258 assert(a
!= 0 && a
== (a
& -a
));
262 static inline uint64_t
263 align_u64(uint64_t v
, uint64_t a
)
265 return align_down_u64(v
+ a
- 1, a
);
268 static inline int32_t
269 align_i32(int32_t v
, int32_t a
)
271 assert(a
!= 0 && a
== (a
& -a
));
272 return (v
+ a
- 1) & ~(a
- 1);
275 /** Alignment must be a power of 2. */
277 anv_is_aligned(uintmax_t n
, uintmax_t a
)
279 assert(a
== (a
& -a
));
280 return (n
& (a
- 1)) == 0;
283 static inline uint32_t
284 anv_minify(uint32_t n
, uint32_t levels
)
286 if (unlikely(n
== 0))
289 return MAX2(n
>> levels
, 1);
293 anv_clamp_f(float f
, float min
, float max
)
306 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
308 if (*inout_mask
& clear_mask
) {
309 *inout_mask
&= ~clear_mask
;
316 static inline union isl_color_value
317 vk_to_isl_color(VkClearColorValue color
)
319 return (union isl_color_value
) {
329 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
331 uintptr_t mask
= (1ull << bits
) - 1;
333 return (void *) (ptr
& ~mask
);
336 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
338 uintptr_t value
= (uintptr_t) ptr
;
339 uintptr_t mask
= (1ull << bits
) - 1;
340 return value
| (mask
& flags
);
343 #define for_each_bit(b, dword) \
344 for (uint32_t __dword = (dword); \
345 (b) = __builtin_ffs(__dword) - 1, __dword; \
346 __dword &= ~(1 << (b)))
348 #define typed_memcpy(dest, src, count) ({ \
349 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
350 memcpy((dest), (src), (count) * sizeof(*(src))); \
353 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
354 * to be added here in order to utilize mapping in debug/error/perf macros.
356 #define REPORT_OBJECT_TYPE(o) \
357 __builtin_choose_expr ( \
358 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
359 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
360 __builtin_choose_expr ( \
361 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
362 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
363 __builtin_choose_expr ( \
364 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
365 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
366 __builtin_choose_expr ( \
367 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
368 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
369 __builtin_choose_expr ( \
370 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
371 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
372 __builtin_choose_expr ( \
373 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
374 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
375 __builtin_choose_expr ( \
376 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
377 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
378 __builtin_choose_expr ( \
379 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
380 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
381 __builtin_choose_expr ( \
382 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
383 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
384 __builtin_choose_expr ( \
385 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
386 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
387 __builtin_choose_expr ( \
388 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
389 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
390 __builtin_choose_expr ( \
391 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
392 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
393 __builtin_choose_expr ( \
394 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
395 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
396 __builtin_choose_expr ( \
397 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
398 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
399 __builtin_choose_expr ( \
400 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
401 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
402 __builtin_choose_expr ( \
403 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
404 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
405 __builtin_choose_expr ( \
406 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
407 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
408 __builtin_choose_expr ( \
409 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
410 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
411 __builtin_choose_expr ( \
412 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
413 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
414 __builtin_choose_expr ( \
415 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
416 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
417 __builtin_choose_expr ( \
418 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
419 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
420 __builtin_choose_expr ( \
421 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
422 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
423 __builtin_choose_expr ( \
424 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
425 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
426 __builtin_choose_expr ( \
427 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
428 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
429 __builtin_choose_expr ( \
430 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
431 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
432 __builtin_choose_expr ( \
433 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
434 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
435 __builtin_choose_expr ( \
436 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
437 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
438 __builtin_choose_expr ( \
439 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
440 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
441 __builtin_choose_expr ( \
442 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
443 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
444 __builtin_choose_expr ( \
445 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
446 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
447 __builtin_choose_expr ( \
448 __builtin_types_compatible_p (__typeof (o), void*), \
449 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
450 /* The void expression results in a compile-time error \
451 when assigning the result to something. */ \
452 (void)0)))))))))))))))))))))))))))))))
454 /* Whenever we generate an error, pass it through this function. Useful for
455 * debugging, where we can break on it. Only call at error site, not when
456 * propagating errors. Might be useful to plug in a stack trace here.
459 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
460 VkDebugReportObjectTypeEXT type
, VkResult error
,
461 const char *file
, int line
, const char *format
,
464 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
465 VkDebugReportObjectTypeEXT type
, VkResult error
,
466 const char *file
, int line
, const char *format
, ...)
467 anv_printflike(7, 8);
470 #define vk_error(error) __vk_errorf(NULL, NULL,\
471 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
472 error, __FILE__, __LINE__, NULL)
473 #define vk_errorfi(instance, obj, error, format, ...)\
474 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
475 __FILE__, __LINE__, format, ## __VA_ARGS__)
476 #define vk_errorf(device, obj, error, format, ...)\
477 vk_errorfi(anv_device_instance_or_null(device),\
478 obj, error, format, ## __VA_ARGS__)
480 #define vk_error(error) error
481 #define vk_errorfi(instance, obj, error, format, ...) error
482 #define vk_errorf(device, obj, error, format, ...) error
486 * Warn on ignored extension structs.
488 * The Vulkan spec requires us to ignore unsupported or unknown structs in
489 * a pNext chain. In debug mode, emitting warnings for ignored structs may
490 * help us discover structs that we should not have ignored.
493 * From the Vulkan 1.0.38 spec:
495 * Any component of the implementation (the loader, any enabled layers,
496 * and drivers) must skip over, without processing (other than reading the
497 * sType and pNext members) any chained structures with sType values not
498 * defined by extensions supported by that component.
500 #define anv_debug_ignored_stype(sType) \
501 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
503 void __anv_perf_warn(struct anv_device
*device
, const void *object
,
504 VkDebugReportObjectTypeEXT type
, const char *file
,
505 int line
, const char *format
, ...)
506 anv_printflike(6, 7);
507 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
508 void anv_loge_v(const char *format
, va_list va
);
511 * Print a FINISHME message, including its source location.
513 #define anv_finishme(format, ...) \
515 static bool reported = false; \
517 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
524 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
526 #define anv_perf_warn(instance, obj, format, ...) \
528 static bool reported = false; \
529 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
530 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
531 format, ##__VA_ARGS__); \
536 /* A non-fatal assert. Useful for debugging. */
538 #define anv_assert(x) ({ \
539 if (unlikely(!(x))) \
540 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
543 #define anv_assert(x)
546 /* A multi-pointer allocator
548 * When copying data structures from the user (such as a render pass), it's
549 * common to need to allocate data for a bunch of different things. Instead
550 * of doing several allocations and having to handle all of the error checking
551 * that entails, it can be easier to do a single allocation. This struct
552 * helps facilitate that. The intended usage looks like this:
555 * anv_multialloc_add(&ma, &main_ptr, 1);
556 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
557 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
559 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
560 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
562 struct anv_multialloc
{
570 #define ANV_MULTIALLOC_INIT \
571 ((struct anv_multialloc) { 0, })
573 #define ANV_MULTIALLOC(_name) \
574 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
576 __attribute__((always_inline
))
578 _anv_multialloc_add(struct anv_multialloc
*ma
,
579 void **ptr
, size_t size
, size_t align
)
581 size_t offset
= align_u64(ma
->size
, align
);
582 ma
->size
= offset
+ size
;
583 ma
->align
= MAX2(ma
->align
, align
);
585 /* Store the offset in the pointer. */
586 *ptr
= (void *)(uintptr_t)offset
;
588 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
589 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
592 #define anv_multialloc_add_size(_ma, _ptr, _size) \
593 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
595 #define anv_multialloc_add(_ma, _ptr, _count) \
596 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
598 __attribute__((always_inline
))
600 anv_multialloc_alloc(struct anv_multialloc
*ma
,
601 const VkAllocationCallbacks
*alloc
,
602 VkSystemAllocationScope scope
)
604 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
608 /* Fill out each of the pointers with their final value.
610 * for (uint32_t i = 0; i < ma->ptr_count; i++)
611 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
613 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
614 * constant, GCC is incapable of figuring this out and unrolling the loop
615 * so we have to give it a little help.
617 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
618 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
619 if ((_i) < ma->ptr_count) \
620 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
621 _ANV_MULTIALLOC_UPDATE_POINTER(0);
622 _ANV_MULTIALLOC_UPDATE_POINTER(1);
623 _ANV_MULTIALLOC_UPDATE_POINTER(2);
624 _ANV_MULTIALLOC_UPDATE_POINTER(3);
625 _ANV_MULTIALLOC_UPDATE_POINTER(4);
626 _ANV_MULTIALLOC_UPDATE_POINTER(5);
627 _ANV_MULTIALLOC_UPDATE_POINTER(6);
628 _ANV_MULTIALLOC_UPDATE_POINTER(7);
629 #undef _ANV_MULTIALLOC_UPDATE_POINTER
634 __attribute__((always_inline
))
636 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
637 const VkAllocationCallbacks
*parent_alloc
,
638 const VkAllocationCallbacks
*alloc
,
639 VkSystemAllocationScope scope
)
641 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
649 /* Index into the current validation list. This is used by the
650 * validation list building alrogithm to track which buffers are already
651 * in the validation list so that we can ensure uniqueness.
655 /* Index for use with util_sparse_array_free_list */
658 /* Last known offset. This value is provided by the kernel when we
659 * execbuf and is used as the presumed offset for the next bunch of
664 /** Size of the buffer not including implicit aux */
667 /* Map for internally mapped BOs.
669 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
673 /** Size of the implicit CCS range at the end of the buffer
675 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
676 * page of main surface data maps to a 256B chunk of CCS data and that
677 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
678 * addresses in the main surface to virtual memory addresses for CCS data.
680 * Because we can't change these maps around easily and because Vulkan
681 * allows two VkImages to be bound to overlapping memory regions (as long
682 * as the app is careful), it's not feasible to make this mapping part of
683 * the image. (On Gen11 and earlier, the mapping was provided via
684 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
685 * Instead, we attach the CCS data directly to the buffer object and setup
686 * the AUX table mapping at BO creation time.
688 * This field is for internal tracking use by the BO allocator only and
689 * should not be touched by other parts of the code. If something wants to
690 * know if a BO has implicit CCS data, it should instead look at the
691 * has_implicit_ccs boolean below.
693 * This data is not included in maps of this buffer.
697 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
700 /** True if this BO may be shared with other processes */
703 /** True if this BO is a wrapper
705 * When set to true, none of the fields in this BO are meaningful except
706 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
707 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
708 * is set in the physical device.
712 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
713 bool has_fixed_address
:1;
715 /** True if this BO wraps a host pointer */
716 bool from_host_ptr
:1;
718 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
719 bool has_client_visible_address
:1;
721 /** True if this BO has implicit CCS data attached to it */
722 bool has_implicit_ccs
:1;
725 static inline struct anv_bo
*
726 anv_bo_ref(struct anv_bo
*bo
)
728 p_atomic_inc(&bo
->refcount
);
732 static inline struct anv_bo
*
733 anv_bo_unwrap(struct anv_bo
*bo
)
735 while (bo
->is_wrapper
)
740 /* Represents a lock-free linked list of "free" things. This is used by
741 * both the block pool and the state pools. Unfortunately, in order to
742 * solve the ABA problem, we can't use a single uint32_t head.
744 union anv_free_list
{
748 /* A simple count that is incremented every time the head changes. */
751 /* Make sure it's aligned to 64 bits. This will make atomic operations
752 * faster on 32 bit platforms.
754 uint64_t u64
__attribute__ ((aligned (8)));
757 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
759 struct anv_block_state
{
765 /* Make sure it's aligned to 64 bits. This will make atomic operations
766 * faster on 32 bit platforms.
768 uint64_t u64
__attribute__ ((aligned (8)));
772 #define anv_block_pool_foreach_bo(bo, pool) \
773 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
774 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
777 #define ANV_MAX_BLOCK_POOL_BOS 20
779 struct anv_block_pool
{
780 struct anv_device
*device
;
783 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
784 * around the actual BO so that we grow the pool after the wrapper BO has
785 * been put in a relocation list. This is only used in the non-softpin
788 struct anv_bo wrapper_bo
;
790 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
796 /* The address where the start of the pool is pinned. The various bos that
797 * are created as the pool grows will have addresses in the range
798 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
800 uint64_t start_address
;
802 /* The offset from the start of the bo to the "center" of the block
803 * pool. Pointers to allocated blocks are given by
804 * bo.map + center_bo_offset + offsets.
806 uint32_t center_bo_offset
;
808 /* Current memory map of the block pool. This pointer may or may not
809 * point to the actual beginning of the block pool memory. If
810 * anv_block_pool_alloc_back has ever been called, then this pointer
811 * will point to the "center" position of the buffer and all offsets
812 * (negative or positive) given out by the block pool alloc functions
813 * will be valid relative to this pointer.
815 * In particular, map == bo.map + center_offset
817 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
818 * since it will handle the softpin case as well, where this points to NULL.
824 * Array of mmaps and gem handles owned by the block pool, reclaimed when
825 * the block pool is destroyed.
827 struct u_vector mmap_cleanups
;
829 struct anv_block_state state
;
831 struct anv_block_state back_state
;
834 /* Block pools are backed by a fixed-size 1GB memfd */
835 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
837 /* The center of the block pool is also the middle of the memfd. This may
838 * change in the future if we decide differently for some reason.
840 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
842 static inline uint32_t
843 anv_block_pool_size(struct anv_block_pool
*pool
)
845 return pool
->state
.end
+ pool
->back_state
.end
;
855 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
857 struct anv_fixed_size_state_pool
{
858 union anv_free_list free_list
;
859 struct anv_block_state block
;
862 #define ANV_MIN_STATE_SIZE_LOG2 6
863 #define ANV_MAX_STATE_SIZE_LOG2 21
865 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
867 struct anv_free_entry
{
869 struct anv_state state
;
872 struct anv_state_table
{
873 struct anv_device
*device
;
875 struct anv_free_entry
*map
;
877 struct anv_block_state state
;
878 struct u_vector cleanups
;
881 struct anv_state_pool
{
882 struct anv_block_pool block_pool
;
884 /* Offset into the relevant state base address where the state pool starts
887 int32_t start_offset
;
889 struct anv_state_table table
;
891 /* The size of blocks which will be allocated from the block pool */
894 /** Free list for "back" allocations */
895 union anv_free_list back_alloc_free_list
;
897 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
900 struct anv_state_reserved_pool
{
901 struct anv_state_pool
*pool
;
902 union anv_free_list reserved_blocks
;
906 struct anv_state_stream
{
907 struct anv_state_pool
*state_pool
;
909 /* The size of blocks to allocate from the state pool */
912 /* Current block we're allocating from */
913 struct anv_state block
;
915 /* Offset into the current block at which to allocate the next state */
918 /* List of all blocks allocated from this pool */
919 struct util_dynarray all_blocks
;
922 /* The block_pool functions exported for testing only. The block pool should
923 * only be used via a state pool (see below).
925 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
926 struct anv_device
*device
,
927 uint64_t start_address
,
928 uint32_t initial_size
);
929 void anv_block_pool_finish(struct anv_block_pool
*pool
);
930 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
931 uint32_t block_size
, uint32_t *padding
);
932 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
933 uint32_t block_size
);
934 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
, uint32_t
937 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
938 struct anv_device
*device
,
939 uint64_t base_address
,
940 int32_t start_offset
,
941 uint32_t block_size
);
942 void anv_state_pool_finish(struct anv_state_pool
*pool
);
943 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
944 uint32_t state_size
, uint32_t alignment
);
945 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
946 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
947 void anv_state_stream_init(struct anv_state_stream
*stream
,
948 struct anv_state_pool
*state_pool
,
949 uint32_t block_size
);
950 void anv_state_stream_finish(struct anv_state_stream
*stream
);
951 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
952 uint32_t size
, uint32_t alignment
);
954 void anv_state_reserved_pool_init(struct anv_state_reserved_pool
*pool
,
955 struct anv_state_pool
*parent
,
956 uint32_t count
, uint32_t size
,
958 void anv_state_reserved_pool_finish(struct anv_state_reserved_pool
*pool
);
959 struct anv_state
anv_state_reserved_pool_alloc(struct anv_state_reserved_pool
*pool
);
960 void anv_state_reserved_pool_free(struct anv_state_reserved_pool
*pool
,
961 struct anv_state state
);
963 VkResult
anv_state_table_init(struct anv_state_table
*table
,
964 struct anv_device
*device
,
965 uint32_t initial_entries
);
966 void anv_state_table_finish(struct anv_state_table
*table
);
967 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
969 void anv_free_list_push(union anv_free_list
*list
,
970 struct anv_state_table
*table
,
971 uint32_t idx
, uint32_t count
);
972 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
973 struct anv_state_table
*table
);
976 static inline struct anv_state
*
977 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
979 return &table
->map
[idx
].state
;
982 * Implements a pool of re-usable BOs. The interface is identical to that
983 * of block_pool except that each block is its own BO.
986 struct anv_device
*device
;
988 struct util_sparse_array_free_list free_list
[16];
991 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
992 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
993 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
994 struct anv_bo
**bo_out
);
995 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
997 struct anv_scratch_pool
{
998 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
999 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
1002 void anv_scratch_pool_init(struct anv_device
*device
,
1003 struct anv_scratch_pool
*pool
);
1004 void anv_scratch_pool_finish(struct anv_device
*device
,
1005 struct anv_scratch_pool
*pool
);
1006 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
1007 struct anv_scratch_pool
*pool
,
1008 gl_shader_stage stage
,
1009 unsigned per_thread_scratch
);
1011 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
1012 struct anv_bo_cache
{
1013 struct util_sparse_array bo_map
;
1014 pthread_mutex_t mutex
;
1017 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
1018 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
1020 struct anv_memory_type
{
1021 /* Standard bits passed on to the client */
1022 VkMemoryPropertyFlags propertyFlags
;
1026 struct anv_memory_heap
{
1027 /* Standard bits passed on to the client */
1029 VkMemoryHeapFlags flags
;
1031 /* Driver-internal book-keeping */
1035 struct anv_physical_device
{
1036 struct vk_object_base base
;
1038 /* Link in anv_instance::physical_devices */
1039 struct list_head link
;
1041 struct anv_instance
* instance
;
1051 struct gen_device_info info
;
1052 /** Amount of "GPU memory" we want to advertise
1054 * Clearly, this value is bogus since Intel is a UMA architecture. On
1055 * gen7 platforms, we are limited by GTT size unless we want to implement
1056 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1057 * practically unlimited. However, we will never report more than 3/4 of
1058 * the total system ram to try and avoid running out of RAM.
1060 bool supports_48bit_addresses
;
1061 struct brw_compiler
* compiler
;
1062 struct isl_device isl_dev
;
1063 struct gen_perf_config
* perf
;
1064 int cmd_parser_version
;
1066 bool has_exec_async
;
1067 bool has_exec_capture
;
1068 bool has_exec_fence
;
1070 bool has_syncobj_wait
;
1071 bool has_context_priority
;
1072 bool has_context_isolation
;
1073 bool has_mem_available
;
1074 bool has_mmap_offset
;
1078 bool always_use_bindless
;
1080 /** True if we can access buffers using A64 messages */
1081 bool has_a64_buffer_access
;
1082 /** True if we can use bindless access for images */
1083 bool has_bindless_images
;
1084 /** True if we can use bindless access for samplers */
1085 bool has_bindless_samplers
;
1087 /** True if this device has implicit AUX
1089 * If true, CCS is handled as an implicit attachment to the BO rather than
1090 * as an explicitly bound surface.
1092 bool has_implicit_ccs
;
1094 bool always_flush_cache
;
1096 struct anv_device_extension_table supported_extensions
;
1099 uint32_t subslice_total
;
1102 uint32_t type_count
;
1103 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1104 uint32_t heap_count
;
1105 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1108 uint8_t driver_build_sha1
[20];
1109 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1110 uint8_t driver_uuid
[VK_UUID_SIZE
];
1111 uint8_t device_uuid
[VK_UUID_SIZE
];
1113 struct disk_cache
* disk_cache
;
1115 struct wsi_device wsi_device
;
1120 struct anv_app_info
{
1121 const char* app_name
;
1122 uint32_t app_version
;
1123 const char* engine_name
;
1124 uint32_t engine_version
;
1125 uint32_t api_version
;
1128 struct anv_instance
{
1129 struct vk_object_base base
;
1131 VkAllocationCallbacks alloc
;
1133 struct anv_app_info app_info
;
1135 struct anv_instance_extension_table enabled_extensions
;
1136 struct anv_instance_dispatch_table dispatch
;
1137 struct anv_physical_device_dispatch_table physical_device_dispatch
;
1138 struct anv_device_dispatch_table device_dispatch
;
1140 bool physical_devices_enumerated
;
1141 struct list_head physical_devices
;
1143 bool pipeline_cache_enabled
;
1145 struct vk_debug_report_instance debug_report_callbacks
;
1147 struct driOptionCache dri_options
;
1148 struct driOptionCache available_dri_options
;
1151 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1152 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1154 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1155 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1158 struct anv_queue_submit
{
1159 struct anv_cmd_buffer
* cmd_buffer
;
1161 uint32_t fence_count
;
1162 uint32_t fence_array_length
;
1163 struct drm_i915_gem_exec_fence
* fences
;
1165 uint32_t temporary_semaphore_count
;
1166 uint32_t temporary_semaphore_array_length
;
1167 struct anv_semaphore_impl
* temporary_semaphores
;
1169 /* Semaphores to be signaled with a SYNC_FD. */
1170 struct anv_semaphore
** sync_fd_semaphores
;
1171 uint32_t sync_fd_semaphore_count
;
1172 uint32_t sync_fd_semaphore_array_length
;
1174 /* Allocated only with non shareable timelines. */
1175 struct anv_timeline
** wait_timelines
;
1176 uint32_t wait_timeline_count
;
1177 uint32_t wait_timeline_array_length
;
1178 uint64_t * wait_timeline_values
;
1180 struct anv_timeline
** signal_timelines
;
1181 uint32_t signal_timeline_count
;
1182 uint32_t signal_timeline_array_length
;
1183 uint64_t * signal_timeline_values
;
1186 bool need_out_fence
;
1189 uint32_t fence_bo_count
;
1190 uint32_t fence_bo_array_length
;
1191 /* An array of struct anv_bo pointers with lower bit used as a flag to
1192 * signal we will wait on that BO (see anv_(un)pack_ptr).
1194 uintptr_t * fence_bos
;
1196 const VkAllocationCallbacks
* alloc
;
1197 VkSystemAllocationScope alloc_scope
;
1199 struct anv_bo
* simple_bo
;
1200 uint32_t simple_bo_size
;
1202 struct list_head link
;
1206 struct vk_object_base base
;
1208 struct anv_device
* device
;
1211 * A list of struct anv_queue_submit to be submitted to i915.
1213 struct list_head queued_submits
;
1215 VkDeviceQueueCreateFlags flags
;
1218 struct anv_pipeline_cache
{
1219 struct vk_object_base base
;
1220 struct anv_device
* device
;
1221 pthread_mutex_t mutex
;
1223 struct hash_table
* nir_cache
;
1225 struct hash_table
* cache
;
1228 struct nir_xfb_info
;
1229 struct anv_pipeline_bind_map
;
1231 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1232 struct anv_device
*device
,
1233 bool cache_enabled
);
1234 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1236 struct anv_shader_bin
*
1237 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1238 const void *key
, uint32_t key_size
);
1239 struct anv_shader_bin
*
1240 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1241 gl_shader_stage stage
,
1242 const void *key_data
, uint32_t key_size
,
1243 const void *kernel_data
, uint32_t kernel_size
,
1244 const void *constant_data
,
1245 uint32_t constant_data_size
,
1246 const struct brw_stage_prog_data
*prog_data
,
1247 uint32_t prog_data_size
,
1248 const struct brw_compile_stats
*stats
,
1250 const struct nir_xfb_info
*xfb_info
,
1251 const struct anv_pipeline_bind_map
*bind_map
);
1253 struct anv_shader_bin
*
1254 anv_device_search_for_kernel(struct anv_device
*device
,
1255 struct anv_pipeline_cache
*cache
,
1256 const void *key_data
, uint32_t key_size
,
1257 bool *user_cache_bit
);
1259 struct anv_shader_bin
*
1260 anv_device_upload_kernel(struct anv_device
*device
,
1261 struct anv_pipeline_cache
*cache
,
1262 gl_shader_stage stage
,
1263 const void *key_data
, uint32_t key_size
,
1264 const void *kernel_data
, uint32_t kernel_size
,
1265 const void *constant_data
,
1266 uint32_t constant_data_size
,
1267 const struct brw_stage_prog_data
*prog_data
,
1268 uint32_t prog_data_size
,
1269 const struct brw_compile_stats
*stats
,
1271 const struct nir_xfb_info
*xfb_info
,
1272 const struct anv_pipeline_bind_map
*bind_map
);
1275 struct nir_shader_compiler_options
;
1278 anv_device_search_for_nir(struct anv_device
*device
,
1279 struct anv_pipeline_cache
*cache
,
1280 const struct nir_shader_compiler_options
*nir_options
,
1281 unsigned char sha1_key
[20],
1285 anv_device_upload_nir(struct anv_device
*device
,
1286 struct anv_pipeline_cache
*cache
,
1287 const struct nir_shader
*nir
,
1288 unsigned char sha1_key
[20]);
1291 struct vk_device vk
;
1293 struct anv_physical_device
* physical
;
1295 struct gen_device_info info
;
1296 struct isl_device isl_dev
;
1299 bool can_chain_batches
;
1300 bool robust_buffer_access
;
1301 struct anv_device_extension_table enabled_extensions
;
1302 struct anv_device_dispatch_table dispatch
;
1304 pthread_mutex_t vma_mutex
;
1305 struct util_vma_heap vma_lo
;
1306 struct util_vma_heap vma_cva
;
1307 struct util_vma_heap vma_hi
;
1309 /** List of all anv_device_memory objects */
1310 struct list_head memory_objects
;
1312 struct anv_bo_pool batch_bo_pool
;
1314 struct anv_bo_cache bo_cache
;
1316 struct anv_state_pool dynamic_state_pool
;
1317 struct anv_state_pool instruction_state_pool
;
1318 struct anv_state_pool binding_table_pool
;
1319 struct anv_state_pool surface_state_pool
;
1321 struct anv_state_reserved_pool custom_border_colors
;
1323 /** BO used for various workarounds
1325 * There are a number of workarounds on our hardware which require writing
1326 * data somewhere and it doesn't really matter where. For that, we use
1327 * this BO and just write to the first dword or so.
1329 * We also need to be able to handle NULL buffers bound as pushed UBOs.
1330 * For that, we use the high bytes (>= 1024) of the workaround BO.
1332 struct anv_bo
* workaround_bo
;
1333 struct anv_bo
* trivial_batch_bo
;
1334 struct anv_bo
* hiz_clear_bo
;
1335 struct anv_state null_surface_state
;
1337 struct anv_pipeline_cache default_pipeline_cache
;
1338 struct blorp_context blorp
;
1340 struct anv_state border_colors
;
1342 struct anv_state slice_hash
;
1344 struct anv_queue queue
;
1346 struct anv_scratch_pool scratch_pool
;
1348 pthread_mutex_t mutex
;
1349 pthread_cond_t queue_submit
;
1352 struct gen_batch_decode_ctx decoder_ctx
;
1354 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1355 * the cmd_buffer's list.
1357 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1359 int perf_fd
; /* -1 if no opened */
1360 uint64_t perf_metric
; /* 0 if unset */
1362 struct gen_aux_map_context
*aux_map_ctx
;
1365 static inline struct anv_instance
*
1366 anv_device_instance_or_null(const struct anv_device
*device
)
1368 return device
? device
->physical
->instance
: NULL
;
1371 static inline struct anv_state_pool
*
1372 anv_binding_table_pool(struct anv_device
*device
)
1374 if (device
->physical
->use_softpin
)
1375 return &device
->binding_table_pool
;
1377 return &device
->surface_state_pool
;
1380 static inline struct anv_state
1381 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1382 if (device
->physical
->use_softpin
)
1383 return anv_state_pool_alloc(&device
->binding_table_pool
,
1384 device
->binding_table_pool
.block_size
, 0);
1386 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1390 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1391 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1394 static inline uint32_t
1395 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1397 if (bo
->is_external
)
1398 return device
->isl_dev
.mocs
.external
;
1400 return device
->isl_dev
.mocs
.internal
;
1403 void anv_device_init_blorp(struct anv_device
*device
);
1404 void anv_device_finish_blorp(struct anv_device
*device
);
1406 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1407 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1408 const char *file
, int line
,
1409 const char *msg
, ...)
1410 anv_printflike(4, 5);
1411 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1412 const char *file
, int line
,
1413 const char *msg
, ...)
1414 anv_printflike(4, 5);
1415 #define anv_device_set_lost(dev, ...) \
1416 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1417 #define anv_queue_set_lost(queue, ...) \
1418 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1421 anv_device_is_lost(struct anv_device
*device
)
1423 return unlikely(p_atomic_read(&device
->_lost
));
1426 VkResult
anv_device_query_status(struct anv_device
*device
);
1429 enum anv_bo_alloc_flags
{
1430 /** Specifies that the BO must have a 32-bit address
1432 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1434 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1436 /** Specifies that the BO may be shared externally */
1437 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1439 /** Specifies that the BO should be mapped */
1440 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1442 /** Specifies that the BO should be snooped so we get coherency */
1443 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1445 /** Specifies that the BO should be captured in error states */
1446 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1448 /** Specifies that the BO will have an address assigned by the caller
1450 * Such BOs do not exist in any VMA heap.
1452 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1454 /** Enables implicit synchronization on the BO
1456 * This is the opposite of EXEC_OBJECT_ASYNC.
1458 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1460 /** Enables implicit synchronization on the BO
1462 * This is equivalent to EXEC_OBJECT_WRITE.
1464 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1466 /** Has an address which is visible to the client */
1467 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS
= (1 << 8),
1469 /** This buffer has implicit CCS data attached to it */
1470 ANV_BO_ALLOC_IMPLICIT_CCS
= (1 << 9),
1473 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1474 enum anv_bo_alloc_flags alloc_flags
,
1475 uint64_t explicit_address
,
1476 struct anv_bo
**bo
);
1477 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1478 void *host_ptr
, uint32_t size
,
1479 enum anv_bo_alloc_flags alloc_flags
,
1480 uint64_t client_address
,
1481 struct anv_bo
**bo_out
);
1482 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1483 enum anv_bo_alloc_flags alloc_flags
,
1484 uint64_t client_address
,
1485 struct anv_bo
**bo
);
1486 VkResult
anv_device_export_bo(struct anv_device
*device
,
1487 struct anv_bo
*bo
, int *fd_out
);
1488 void anv_device_release_bo(struct anv_device
*device
,
1491 static inline struct anv_bo
*
1492 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1494 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1497 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1498 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1501 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1502 void anv_queue_finish(struct anv_queue
*queue
);
1504 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1505 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1506 struct anv_batch
*batch
);
1508 uint64_t anv_gettime_ns(void);
1509 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1511 void* anv_gem_mmap(struct anv_device
*device
,
1512 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1513 void anv_gem_munmap(struct anv_device
*device
, void *p
, uint64_t size
);
1514 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1515 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1516 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1517 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1518 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1519 int anv_gem_execbuffer(struct anv_device
*device
,
1520 struct drm_i915_gem_execbuffer2
*execbuf
);
1521 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1522 uint32_t stride
, uint32_t tiling
);
1523 int anv_gem_create_context(struct anv_device
*device
);
1524 bool anv_gem_has_context_priority(int fd
);
1525 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1526 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1528 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1530 int anv_gem_get_param(int fd
, uint32_t param
);
1531 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1532 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1533 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1534 uint32_t *active
, uint32_t *pending
);
1535 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1536 int anv_gem_reg_read(struct anv_device
*device
,
1537 uint32_t offset
, uint64_t *result
);
1538 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1539 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1540 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1541 uint32_t read_domains
, uint32_t write_domain
);
1542 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1543 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1544 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1545 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1546 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1547 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1549 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1550 uint32_t handle
, int fd
);
1551 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1552 bool anv_gem_supports_syncobj_wait(int fd
);
1553 int anv_gem_syncobj_wait(struct anv_device
*device
,
1554 uint32_t *handles
, uint32_t num_handles
,
1555 int64_t abs_timeout_ns
, bool wait_all
);
1557 uint64_t anv_vma_alloc(struct anv_device
*device
,
1558 uint64_t size
, uint64_t align
,
1559 enum anv_bo_alloc_flags alloc_flags
,
1560 uint64_t client_address
);
1561 void anv_vma_free(struct anv_device
*device
,
1562 uint64_t address
, uint64_t size
);
1564 struct anv_reloc_list
{
1565 uint32_t num_relocs
;
1566 uint32_t array_length
;
1567 struct drm_i915_gem_relocation_entry
* relocs
;
1568 struct anv_bo
** reloc_bos
;
1573 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1574 const VkAllocationCallbacks
*alloc
);
1575 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1576 const VkAllocationCallbacks
*alloc
);
1578 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1579 const VkAllocationCallbacks
*alloc
,
1580 uint32_t offset
, struct anv_bo
*target_bo
,
1581 uint32_t delta
, uint64_t *address_u64_out
);
1583 struct anv_batch_bo
{
1584 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1585 struct list_head link
;
1589 /* Bytes actually consumed in this batch BO */
1592 struct anv_reloc_list relocs
;
1595 struct anv_address
{
1601 const VkAllocationCallbacks
* alloc
;
1603 struct anv_address start_addr
;
1609 struct anv_reloc_list
* relocs
;
1611 /* This callback is called (with the associated user data) in the event
1612 * that the batch runs out of space.
1614 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1618 * Current error status of the command buffer. Used to track inconsistent
1619 * or incomplete command buffer states that are the consequence of run-time
1620 * errors such as out of memory scenarios. We want to track this in the
1621 * batch because the command buffer object is not visible to some parts
1627 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1628 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1629 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1630 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1631 struct anv_address
anv_batch_address(struct anv_batch
*batch
, void *batch_location
);
1633 static inline VkResult
1634 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1636 assert(error
!= VK_SUCCESS
);
1637 if (batch
->status
== VK_SUCCESS
)
1638 batch
->status
= error
;
1639 return batch
->status
;
1643 anv_batch_has_error(struct anv_batch
*batch
)
1645 return batch
->status
!= VK_SUCCESS
;
1648 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1651 anv_address_is_null(struct anv_address addr
)
1653 return addr
.bo
== NULL
&& addr
.offset
== 0;
1656 static inline uint64_t
1657 anv_address_physical(struct anv_address addr
)
1659 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1660 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1662 return gen_canonical_address(addr
.offset
);
1665 static inline struct anv_address
1666 anv_address_add(struct anv_address addr
, uint64_t offset
)
1668 addr
.offset
+= offset
;
1673 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1675 unsigned reloc_size
= 0;
1676 if (device
->info
.gen
>= 8) {
1677 reloc_size
= sizeof(uint64_t);
1678 *(uint64_t *)p
= gen_canonical_address(v
);
1680 reloc_size
= sizeof(uint32_t);
1684 if (flush
&& !device
->info
.has_llc
)
1685 gen_flush_range(p
, reloc_size
);
1688 static inline uint64_t
1689 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1690 const struct anv_address address
, uint32_t delta
)
1692 if (address
.bo
== NULL
) {
1693 return address
.offset
+ delta
;
1695 assert(batch
->start
<= location
&& location
< batch
->end
);
1697 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1701 #define __gen_address_type struct anv_address
1702 #define __gen_user_data struct anv_batch
1703 #define __gen_combine_address _anv_combine_address
1705 /* Wrapper macros needed to work around preprocessor argument issues. In
1706 * particular, arguments don't get pre-evaluated if they are concatenated.
1707 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1708 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1709 * We can work around this easily enough with these helpers.
1711 #define __anv_cmd_length(cmd) cmd ## _length
1712 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1713 #define __anv_cmd_header(cmd) cmd ## _header
1714 #define __anv_cmd_pack(cmd) cmd ## _pack
1715 #define __anv_reg_num(reg) reg ## _num
1717 #define anv_pack_struct(dst, struc, ...) do { \
1718 struct struc __template = { \
1721 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1722 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1725 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1726 void *__dst = anv_batch_emit_dwords(batch, n); \
1728 struct cmd __template = { \
1729 __anv_cmd_header(cmd), \
1730 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1733 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1738 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1742 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1743 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1746 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1747 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1748 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1751 #define anv_batch_emit(batch, cmd, name) \
1752 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1753 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1754 __builtin_expect(_dst != NULL, 1); \
1755 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1756 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1760 struct anv_device_memory
{
1761 struct vk_object_base base
;
1763 struct list_head link
;
1766 struct anv_memory_type
* type
;
1767 VkDeviceSize map_size
;
1770 /* If set, we are holding reference to AHardwareBuffer
1771 * which we must release when memory is freed.
1773 struct AHardwareBuffer
* ahw
;
1775 /* If set, this memory comes from a host pointer. */
1780 * Header for Vertex URB Entry (VUE)
1782 struct anv_vue_header
{
1784 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1785 uint32_t ViewportIndex
;
1789 /** Struct representing a sampled image descriptor
1791 * This descriptor layout is used for sampled images, bare sampler, and
1792 * combined image/sampler descriptors.
1794 struct anv_sampled_image_descriptor
{
1795 /** Bindless image handle
1797 * This is expected to already be shifted such that the 20-bit
1798 * SURFACE_STATE table index is in the top 20 bits.
1802 /** Bindless sampler handle
1804 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1805 * to the dynamic state base address.
1810 struct anv_texture_swizzle_descriptor
{
1813 * See also nir_intrinsic_channel_select_intel
1817 /** Unused padding to ensure the struct is a multiple of 64 bits */
1821 /** Struct representing a storage image descriptor */
1822 struct anv_storage_image_descriptor
{
1823 /** Bindless image handles
1825 * These are expected to already be shifted such that the 20-bit
1826 * SURFACE_STATE table index is in the top 20 bits.
1828 uint32_t read_write
;
1829 uint32_t write_only
;
1832 /** Struct representing a address/range descriptor
1834 * The fields of this struct correspond directly to the data layout of
1835 * nir_address_format_64bit_bounded_global addresses. The last field is the
1836 * offset in the NIR address so it must be zero so that when you load the
1837 * descriptor you get a pointer to the start of the range.
1839 struct anv_address_range_descriptor
{
1845 enum anv_descriptor_data
{
1846 /** The descriptor contains a BTI reference to a surface state */
1847 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1848 /** The descriptor contains a BTI reference to a sampler state */
1849 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1850 /** The descriptor contains an actual buffer view */
1851 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1852 /** The descriptor contains auxiliary image layout data */
1853 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1854 /** The descriptor contains auxiliary image layout data */
1855 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1856 /** anv_address_range_descriptor with a buffer address and range */
1857 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1858 /** Bindless surface handle */
1859 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1860 /** Storage image handles */
1861 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1862 /** Storage image handles */
1863 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1866 struct anv_descriptor_set_binding_layout
{
1868 /* The type of the descriptors in this binding */
1869 VkDescriptorType type
;
1872 /* Flags provided when this binding was created */
1873 VkDescriptorBindingFlagsEXT flags
;
1875 /* Bitfield representing the type of data this descriptor contains */
1876 enum anv_descriptor_data data
;
1878 /* Maximum number of YCbCr texture/sampler planes */
1879 uint8_t max_plane_count
;
1881 /* Number of array elements in this binding (or size in bytes for inline
1884 uint16_t array_size
;
1886 /* Index into the flattend descriptor set */
1887 uint16_t descriptor_index
;
1889 /* Index into the dynamic state array for a dynamic buffer */
1890 int16_t dynamic_offset_index
;
1892 /* Index into the descriptor set buffer views */
1893 int16_t buffer_view_index
;
1895 /* Offset into the descriptor buffer where this descriptor lives */
1896 uint32_t descriptor_offset
;
1898 /* Immutable samplers (or NULL if no immutable samplers) */
1899 struct anv_sampler
**immutable_samplers
;
1902 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1904 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1905 VkDescriptorType type
);
1907 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1908 const struct anv_descriptor_set_binding_layout
*binding
,
1911 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1912 const struct anv_descriptor_set_binding_layout
*binding
,
1915 struct anv_descriptor_set_layout
{
1916 struct vk_object_base base
;
1918 /* Descriptor set layouts can be destroyed at almost any time */
1921 /* Number of bindings in this descriptor set */
1922 uint16_t binding_count
;
1924 /* Total size of the descriptor set with room for all array entries */
1927 /* Shader stages affected by this descriptor set */
1928 uint16_t shader_stages
;
1930 /* Number of buffer views in this descriptor set */
1931 uint16_t buffer_view_count
;
1933 /* Number of dynamic offsets used by this descriptor set */
1934 uint16_t dynamic_offset_count
;
1936 /* For each shader stage, which offsets apply to that stage */
1937 uint16_t stage_dynamic_offsets
[MESA_SHADER_STAGES
];
1939 /* Size of the descriptor buffer for this descriptor set */
1940 uint32_t descriptor_buffer_size
;
1942 /* Bindings in this descriptor set */
1943 struct anv_descriptor_set_binding_layout binding
[0];
1946 void anv_descriptor_set_layout_destroy(struct anv_device
*device
,
1947 struct anv_descriptor_set_layout
*layout
);
1950 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1952 assert(layout
&& layout
->ref_cnt
>= 1);
1953 p_atomic_inc(&layout
->ref_cnt
);
1957 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1958 struct anv_descriptor_set_layout
*layout
)
1960 assert(layout
&& layout
->ref_cnt
>= 1);
1961 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1962 anv_descriptor_set_layout_destroy(device
, layout
);
1965 struct anv_descriptor
{
1966 VkDescriptorType type
;
1970 VkImageLayout layout
;
1971 struct anv_image_view
*image_view
;
1972 struct anv_sampler
*sampler
;
1976 struct anv_buffer
*buffer
;
1981 struct anv_buffer_view
*buffer_view
;
1985 struct anv_descriptor_set
{
1986 struct vk_object_base base
;
1988 struct anv_descriptor_pool
*pool
;
1989 struct anv_descriptor_set_layout
*layout
;
1992 /* State relative to anv_descriptor_pool::bo */
1993 struct anv_state desc_mem
;
1994 /* Surface state for the descriptor buffer */
1995 struct anv_state desc_surface_state
;
1997 uint32_t buffer_view_count
;
1998 struct anv_buffer_view
*buffer_views
;
2000 /* Link to descriptor pool's desc_sets list . */
2001 struct list_head pool_link
;
2003 struct anv_descriptor descriptors
[0];
2006 struct anv_buffer_view
{
2007 struct vk_object_base base
;
2009 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
2010 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2012 struct anv_address address
;
2014 struct anv_state surface_state
;
2015 struct anv_state storage_surface_state
;
2016 struct anv_state writeonly_storage_surface_state
;
2018 struct brw_image_param storage_image_param
;
2021 struct anv_push_descriptor_set
{
2022 struct anv_descriptor_set set
;
2024 /* Put this field right behind anv_descriptor_set so it fills up the
2025 * descriptors[0] field. */
2026 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
2028 /** True if the descriptor set buffer has been referenced by a draw or
2031 bool set_used_on_gpu
;
2033 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
2036 struct anv_descriptor_pool
{
2037 struct vk_object_base base
;
2044 struct util_vma_heap bo_heap
;
2046 struct anv_state_stream surface_state_stream
;
2047 void *surface_state_free_list
;
2049 struct list_head desc_sets
;
2054 enum anv_descriptor_template_entry_type
{
2055 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
2056 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
2057 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
2060 struct anv_descriptor_template_entry
{
2061 /* The type of descriptor in this entry */
2062 VkDescriptorType type
;
2064 /* Binding in the descriptor set */
2067 /* Offset at which to write into the descriptor set binding */
2068 uint32_t array_element
;
2070 /* Number of elements to write into the descriptor set binding */
2071 uint32_t array_count
;
2073 /* Offset into the user provided data */
2076 /* Stride between elements into the user provided data */
2080 struct anv_descriptor_update_template
{
2081 struct vk_object_base base
;
2083 VkPipelineBindPoint bind_point
;
2085 /* The descriptor set this template corresponds to. This value is only
2086 * valid if the template was created with the templateType
2087 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2091 /* Number of entries in this template */
2092 uint32_t entry_count
;
2094 /* Entries of the template */
2095 struct anv_descriptor_template_entry entries
[0];
2099 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
2102 anv_descriptor_set_write_image_view(struct anv_device
*device
,
2103 struct anv_descriptor_set
*set
,
2104 const VkDescriptorImageInfo
* const info
,
2105 VkDescriptorType type
,
2110 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
2111 struct anv_descriptor_set
*set
,
2112 VkDescriptorType type
,
2113 struct anv_buffer_view
*buffer_view
,
2118 anv_descriptor_set_write_buffer(struct anv_device
*device
,
2119 struct anv_descriptor_set
*set
,
2120 struct anv_state_stream
*alloc_stream
,
2121 VkDescriptorType type
,
2122 struct anv_buffer
*buffer
,
2125 VkDeviceSize offset
,
2126 VkDeviceSize range
);
2128 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
2129 struct anv_descriptor_set
*set
,
2136 anv_descriptor_set_write_template(struct anv_device
*device
,
2137 struct anv_descriptor_set
*set
,
2138 struct anv_state_stream
*alloc_stream
,
2139 const struct anv_descriptor_update_template
*template,
2143 anv_descriptor_set_create(struct anv_device
*device
,
2144 struct anv_descriptor_pool
*pool
,
2145 struct anv_descriptor_set_layout
*layout
,
2146 struct anv_descriptor_set
**out_set
);
2149 anv_descriptor_set_destroy(struct anv_device
*device
,
2150 struct anv_descriptor_pool
*pool
,
2151 struct anv_descriptor_set
*set
);
2153 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2154 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2155 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2156 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2157 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2158 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2160 struct anv_pipeline_binding
{
2161 /** Index in the descriptor set
2163 * This is a flattened index; the descriptor set layout is already taken
2168 /** The descriptor set this surface corresponds to.
2170 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2171 * binding is not a normal descriptor set but something else.
2176 /** Plane in the binding index for images */
2179 /** Input attachment index (relative to the subpass) */
2180 uint8_t input_attachment_index
;
2182 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2183 uint8_t dynamic_offset_index
;
2186 /** For a storage image, whether it is write-only */
2189 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2190 * assuming POD zero-initialization.
2195 struct anv_push_range
{
2196 /** Index in the descriptor set */
2199 /** Descriptor set index */
2202 /** Dynamic offset index (for dynamic UBOs) */
2203 uint8_t dynamic_offset_index
;
2205 /** Start offset in units of 32B */
2208 /** Range in units of 32B */
2212 struct anv_pipeline_layout
{
2213 struct vk_object_base base
;
2216 struct anv_descriptor_set_layout
*layout
;
2217 uint32_t dynamic_offset_start
;
2222 unsigned char sha1
[20];
2226 struct vk_object_base base
;
2228 struct anv_device
* device
;
2231 VkBufferUsageFlags usage
;
2233 /* Set when bound */
2234 struct anv_address address
;
2237 static inline uint64_t
2238 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2240 assert(offset
<= buffer
->size
);
2241 if (range
== VK_WHOLE_SIZE
) {
2242 return buffer
->size
- offset
;
2244 assert(range
+ offset
>= range
);
2245 assert(range
+ offset
<= buffer
->size
);
2250 enum anv_cmd_dirty_bits
{
2251 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2252 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2253 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2254 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2255 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2256 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2257 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2258 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2259 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2260 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2261 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2262 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2263 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2264 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2266 typedef uint32_t anv_cmd_dirty_mask_t
;
2268 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2269 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2270 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2271 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2272 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2273 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2274 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2275 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2276 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2277 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2278 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2280 static inline enum anv_cmd_dirty_bits
2281 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2284 case VK_DYNAMIC_STATE_VIEWPORT
:
2285 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2286 case VK_DYNAMIC_STATE_SCISSOR
:
2287 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2288 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2289 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2290 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2291 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2292 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2293 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2294 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2295 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2296 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2297 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2298 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2299 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2300 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2301 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2302 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2303 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2305 assert(!"Unsupported dynamic state");
2311 enum anv_pipe_bits
{
2312 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2313 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2314 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2315 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2316 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2317 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2318 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2319 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2320 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2321 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2322 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2323 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2324 ANV_PIPE_END_OF_PIPE_SYNC_BIT
= (1 << 21),
2326 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2327 * a flush has happened but not a CS stall. The next time we do any sort
2328 * of invalidation we need to insert a CS stall at that time. Otherwise,
2329 * we would have to CS stall on every flush which could be bad.
2331 ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
= (1 << 22),
2333 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2334 * target operations related to transfer commands with VkBuffer as
2335 * destination are ongoing. Some operations like copies on the command
2336 * streamer might need to be aware of this to trigger the appropriate stall
2337 * before they can proceed with the copy.
2339 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 23),
2341 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2342 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2343 * done by writing the AUX-TT register.
2345 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
= (1 << 24),
2347 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2348 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2349 * implement a workaround for Gen9.
2351 ANV_PIPE_POST_SYNC_BIT
= (1 << 25),
2354 #define ANV_PIPE_FLUSH_BITS ( \
2355 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2356 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2357 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2358 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2360 #define ANV_PIPE_STALL_BITS ( \
2361 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2362 ANV_PIPE_DEPTH_STALL_BIT | \
2363 ANV_PIPE_CS_STALL_BIT)
2365 #define ANV_PIPE_INVALIDATE_BITS ( \
2366 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2367 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2368 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2369 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2370 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2371 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2372 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2374 static inline enum anv_pipe_bits
2375 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2377 enum anv_pipe_bits pipe_bits
= 0;
2380 for_each_bit(b
, flags
) {
2381 switch ((VkAccessFlagBits
)(1 << b
)) {
2382 case VK_ACCESS_SHADER_WRITE_BIT
:
2383 /* We're transitioning a buffer that was previously used as write
2384 * destination through the data port. To make its content available
2385 * to future operations, flush the data cache.
2387 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2389 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2390 /* We're transitioning a buffer that was previously used as render
2391 * target. To make its content available to future operations, flush
2392 * the render target cache.
2394 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2396 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2397 /* We're transitioning a buffer that was previously used as depth
2398 * buffer. To make its content available to future operations, flush
2401 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2403 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2404 /* We're transitioning a buffer that was previously used as a
2405 * transfer write destination. Generic write operations include color
2406 * & depth operations as well as buffer operations like :
2407 * - vkCmdClearColorImage()
2408 * - vkCmdClearDepthStencilImage()
2409 * - vkCmdBlitImage()
2410 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2412 * Most of these operations are implemented using Blorp which writes
2413 * through the render target, so flush that cache to make it visible
2414 * to future operations. And for depth related operations we also
2415 * need to flush the depth cache.
2417 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2418 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2420 case VK_ACCESS_MEMORY_WRITE_BIT
:
2421 /* We're transitioning a buffer for generic write operations. Flush
2424 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2427 break; /* Nothing to do */
2434 static inline enum anv_pipe_bits
2435 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2437 enum anv_pipe_bits pipe_bits
= 0;
2440 for_each_bit(b
, flags
) {
2441 switch ((VkAccessFlagBits
)(1 << b
)) {
2442 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2443 /* Indirect draw commands take a buffer as input that we're going to
2444 * read from the command streamer to load some of the HW registers
2445 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2446 * command streamer stall so that all the cache flushes have
2447 * completed before the command streamer loads from memory.
2449 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2450 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2451 * through a vertex buffer, so invalidate that cache.
2453 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2454 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2455 * UBO from the buffer, so we need to invalidate constant cache.
2457 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2459 case VK_ACCESS_INDEX_READ_BIT
:
2460 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2461 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2462 * commands, so we invalidate the VF cache to make sure there is no
2463 * stale data when we start rendering.
2465 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2467 case VK_ACCESS_UNIFORM_READ_BIT
:
2468 /* We transitioning a buffer to be used as uniform data. Because
2469 * uniform is accessed through the data port & sampler, we need to
2470 * invalidate the texture cache (sampler) & constant cache (data
2471 * port) to avoid stale data.
2473 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2474 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2476 case VK_ACCESS_SHADER_READ_BIT
:
2477 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2478 case VK_ACCESS_TRANSFER_READ_BIT
:
2479 /* Transitioning a buffer to be read through the sampler, so
2480 * invalidate the texture cache, we don't want any stale data.
2482 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2484 case VK_ACCESS_MEMORY_READ_BIT
:
2485 /* Transitioning a buffer for generic read, invalidate all the
2488 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2490 case VK_ACCESS_MEMORY_WRITE_BIT
:
2491 /* Generic write, make sure all previously written things land in
2494 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2496 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2497 /* Transitioning a buffer for conditional rendering. We'll load the
2498 * content of this buffer into HW registers using the command
2499 * streamer, so we need to stall the command streamer to make sure
2500 * any in-flight flush operations have completed.
2502 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2505 break; /* Nothing to do */
2512 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2513 VK_IMAGE_ASPECT_COLOR_BIT | \
2514 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2515 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2516 VK_IMAGE_ASPECT_PLANE_2_BIT)
2517 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2518 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2519 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2520 VK_IMAGE_ASPECT_PLANE_2_BIT)
2522 struct anv_vertex_binding
{
2523 struct anv_buffer
* buffer
;
2524 VkDeviceSize offset
;
2527 struct anv_xfb_binding
{
2528 struct anv_buffer
* buffer
;
2529 VkDeviceSize offset
;
2533 struct anv_push_constants
{
2534 /** Push constant data provided by the client through vkPushConstants */
2535 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2537 /** Dynamic offsets for dynamic UBOs and SSBOs */
2538 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2540 uint64_t push_reg_mask
;
2542 /** Pad out to a multiple of 32 bytes */
2546 /** Base workgroup ID
2548 * Used for vkCmdDispatchBase.
2550 uint32_t base_work_group_id
[3];
2554 * This is never set by software but is implicitly filled out when
2555 * uploading the push constants for compute shaders.
2557 uint32_t subgroup_id
;
2561 struct anv_dynamic_state
{
2564 VkViewport viewports
[MAX_VIEWPORTS
];
2569 VkRect2D scissors
[MAX_SCISSORS
];
2580 float blend_constants
[4];
2590 } stencil_compare_mask
;
2595 } stencil_write_mask
;
2600 } stencil_reference
;
2608 extern const struct anv_dynamic_state default_dynamic_state
;
2610 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2611 const struct anv_dynamic_state
*src
,
2612 uint32_t copy_mask
);
2614 struct anv_surface_state
{
2615 struct anv_state state
;
2616 /** Address of the surface referred to by this state
2618 * This address is relative to the start of the BO.
2620 struct anv_address address
;
2621 /* Address of the aux surface, if any
2623 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2625 * With the exception of gen8, the bottom 12 bits of this address' offset
2626 * include extra aux information.
2628 struct anv_address aux_address
;
2629 /* Address of the clear color, if any
2631 * This address is relative to the start of the BO.
2633 struct anv_address clear_address
;
2637 * Attachment state when recording a renderpass instance.
2639 * The clear value is valid only if there exists a pending clear.
2641 struct anv_attachment_state
{
2642 enum isl_aux_usage aux_usage
;
2643 struct anv_surface_state color
;
2644 struct anv_surface_state input
;
2646 VkImageLayout current_layout
;
2647 VkImageLayout current_stencil_layout
;
2648 VkImageAspectFlags pending_clear_aspects
;
2649 VkImageAspectFlags pending_load_aspects
;
2651 VkClearValue clear_value
;
2653 /* When multiview is active, attachments with a renderpass clear
2654 * operation have their respective layers cleared on the first
2655 * subpass that uses them, and only in that subpass. We keep track
2656 * of this using a bitfield to indicate which layers of an attachment
2657 * have not been cleared yet when multiview is active.
2659 uint32_t pending_clear_views
;
2660 struct anv_image_view
* image_view
;
2663 /** State tracking for vertex buffer flushes
2665 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2666 * addresses. If you happen to have two vertex buffers which get placed
2667 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2668 * collisions. In order to solve this problem, we track vertex address ranges
2669 * which are live in the cache and invalidate the cache if one ever exceeds 32
2672 struct anv_vb_cache_range
{
2673 /* Virtual address at which the live vertex buffer cache range starts for
2674 * this vertex buffer index.
2678 /* Virtual address of the byte after where vertex buffer cache range ends.
2679 * This is exclusive such that end - start is the size of the range.
2684 /** State tracking for particular pipeline bind point
2686 * This struct is the base struct for anv_cmd_graphics_state and
2687 * anv_cmd_compute_state. These are used to track state which is bound to a
2688 * particular type of pipeline. Generic state that applies per-stage such as
2689 * binding table offsets and push constants is tracked generically with a
2690 * per-stage array in anv_cmd_state.
2692 struct anv_cmd_pipeline_state
{
2693 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2694 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2697 /** State tracking for graphics pipeline
2699 * This has anv_cmd_pipeline_state as a base struct to track things which get
2700 * bound to a graphics pipeline. Along with general pipeline bind point state
2701 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2702 * state which is graphics-specific.
2704 struct anv_cmd_graphics_state
{
2705 struct anv_cmd_pipeline_state base
;
2707 struct anv_graphics_pipeline
*pipeline
;
2709 anv_cmd_dirty_mask_t dirty
;
2712 struct anv_vb_cache_range ib_bound_range
;
2713 struct anv_vb_cache_range ib_dirty_range
;
2714 struct anv_vb_cache_range vb_bound_ranges
[33];
2715 struct anv_vb_cache_range vb_dirty_ranges
[33];
2717 struct anv_dynamic_state dynamic
;
2720 struct anv_buffer
*index_buffer
;
2721 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2722 uint32_t index_offset
;
2726 /** State tracking for compute pipeline
2728 * This has anv_cmd_pipeline_state as a base struct to track things which get
2729 * bound to a compute pipeline. Along with general pipeline bind point state
2730 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2731 * state which is compute-specific.
2733 struct anv_cmd_compute_state
{
2734 struct anv_cmd_pipeline_state base
;
2736 struct anv_compute_pipeline
*pipeline
;
2738 bool pipeline_dirty
;
2740 struct anv_address num_workgroups
;
2743 /** State required while building cmd buffer */
2744 struct anv_cmd_state
{
2745 /* PIPELINE_SELECT.PipelineSelection */
2746 uint32_t current_pipeline
;
2747 const struct gen_l3_config
* current_l3_config
;
2748 uint32_t last_aux_map_state
;
2750 struct anv_cmd_graphics_state gfx
;
2751 struct anv_cmd_compute_state compute
;
2753 enum anv_pipe_bits pending_pipe_bits
;
2754 VkShaderStageFlags descriptors_dirty
;
2755 VkShaderStageFlags push_constants_dirty
;
2757 struct anv_framebuffer
* framebuffer
;
2758 struct anv_render_pass
* pass
;
2759 struct anv_subpass
* subpass
;
2760 VkRect2D render_area
;
2761 uint32_t restart_index
;
2762 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2764 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2765 VkShaderStageFlags push_constant_stages
;
2766 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2767 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2768 struct anv_state samplers
[MESA_SHADER_STAGES
];
2770 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2771 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2772 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2775 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2776 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2777 * and before invoking the secondary in ExecuteCommands.
2779 bool pma_fix_enabled
;
2782 * Whether or not we know for certain that HiZ is enabled for the current
2783 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2784 * enabled or not, this will be false.
2788 bool conditional_render_enabled
;
2791 * Last rendering scale argument provided to
2792 * genX(cmd_buffer_emit_hashing_mode)().
2794 unsigned current_hash_scale
;
2797 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2798 * valid only when recording a render pass instance.
2800 struct anv_attachment_state
* attachments
;
2803 * Surface states for color render targets. These are stored in a single
2804 * flat array. For depth-stencil attachments, the surface state is simply
2807 struct anv_state attachment_states
;
2810 * A null surface state of the right size to match the framebuffer. This
2811 * is one of the states in attachment_states.
2813 struct anv_state null_surface_state
;
2816 struct anv_cmd_pool
{
2817 struct vk_object_base base
;
2818 VkAllocationCallbacks alloc
;
2819 struct list_head cmd_buffers
;
2822 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2824 enum anv_cmd_buffer_exec_mode
{
2825 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2826 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2827 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2828 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2829 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2830 ANV_CMD_BUFFER_EXEC_MODE_CALL_AND_RETURN
,
2833 struct anv_cmd_buffer
{
2834 struct vk_object_base base
;
2836 struct anv_device
* device
;
2838 struct anv_cmd_pool
* pool
;
2839 struct list_head pool_link
;
2841 struct anv_batch batch
;
2843 /* Fields required for the actual chain of anv_batch_bo's.
2845 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2847 struct list_head batch_bos
;
2848 enum anv_cmd_buffer_exec_mode exec_mode
;
2850 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2851 * referenced by this command buffer
2853 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2855 struct u_vector seen_bbos
;
2857 /* A vector of int32_t's for every block of binding tables.
2859 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2861 struct u_vector bt_block_states
;
2862 struct anv_state bt_next
;
2864 struct anv_reloc_list surface_relocs
;
2865 /** Last seen surface state block pool center bo offset */
2866 uint32_t last_ss_pool_center
;
2868 /* Serial for tracking buffer completion */
2871 /* Stream objects for storing temporary data */
2872 struct anv_state_stream surface_state_stream
;
2873 struct anv_state_stream dynamic_state_stream
;
2875 VkCommandBufferUsageFlags usage_flags
;
2876 VkCommandBufferLevel level
;
2878 struct anv_cmd_state state
;
2880 struct anv_address return_addr
;
2882 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2883 uint64_t intel_perf_marker
;
2886 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2887 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2888 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2889 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2890 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2891 struct anv_cmd_buffer
*secondary
);
2892 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2893 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
2894 struct anv_cmd_buffer
*cmd_buffer
,
2895 const VkSemaphore
*in_semaphores
,
2896 const uint64_t *in_wait_values
,
2897 uint32_t num_in_semaphores
,
2898 const VkSemaphore
*out_semaphores
,
2899 const uint64_t *out_signal_values
,
2900 uint32_t num_out_semaphores
,
2903 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2905 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2906 const void *data
, uint32_t size
, uint32_t alignment
);
2907 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2908 uint32_t *a
, uint32_t *b
,
2909 uint32_t dwords
, uint32_t alignment
);
2912 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2914 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2915 uint32_t entries
, uint32_t *state_offset
);
2917 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2919 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2920 uint32_t size
, uint32_t alignment
);
2923 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2925 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2926 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2927 bool depth_clamp_enable
);
2928 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2930 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2931 struct anv_render_pass
*pass
,
2932 struct anv_framebuffer
*framebuffer
,
2933 const VkClearValue
*clear_values
);
2935 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2938 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2939 gl_shader_stage stage
);
2941 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2943 const struct anv_image_view
*
2944 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2947 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2948 uint32_t num_entries
,
2949 uint32_t *state_offset
,
2950 struct anv_state
*bt_state
);
2952 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2954 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2956 enum anv_fence_type
{
2957 ANV_FENCE_TYPE_NONE
= 0,
2959 ANV_FENCE_TYPE_WSI_BO
,
2960 ANV_FENCE_TYPE_SYNCOBJ
,
2964 enum anv_bo_fence_state
{
2965 /** Indicates that this is a new (or newly reset fence) */
2966 ANV_BO_FENCE_STATE_RESET
,
2968 /** Indicates that this fence has been submitted to the GPU but is still
2969 * (as far as we know) in use by the GPU.
2971 ANV_BO_FENCE_STATE_SUBMITTED
,
2973 ANV_BO_FENCE_STATE_SIGNALED
,
2976 struct anv_fence_impl
{
2977 enum anv_fence_type type
;
2980 /** Fence implementation for BO fences
2982 * These fences use a BO and a set of CPU-tracked state flags. The BO
2983 * is added to the object list of the last execbuf call in a QueueSubmit
2984 * and is marked EXEC_WRITE. The state flags track when the BO has been
2985 * submitted to the kernel. We need to do this because Vulkan lets you
2986 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2987 * will say it's idle in this case.
2991 enum anv_bo_fence_state state
;
2994 /** DRM syncobj handle for syncobj-based fences */
2998 struct wsi_fence
*fence_wsi
;
3003 struct vk_object_base base
;
3005 /* Permanent fence state. Every fence has some form of permanent state
3006 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
3007 * cross-process fences) or it could just be a dummy for use internally.
3009 struct anv_fence_impl permanent
;
3011 /* Temporary fence state. A fence *may* have temporary state. That state
3012 * is added to the fence by an import operation and is reset back to
3013 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
3014 * state cannot be signaled because the fence must already be signaled
3015 * before the temporary state can be exported from the fence in the other
3016 * process and imported here.
3018 struct anv_fence_impl temporary
;
3021 void anv_fence_reset_temporary(struct anv_device
*device
,
3022 struct anv_fence
*fence
);
3025 struct vk_object_base base
;
3027 struct anv_state state
;
3030 enum anv_semaphore_type
{
3031 ANV_SEMAPHORE_TYPE_NONE
= 0,
3032 ANV_SEMAPHORE_TYPE_DUMMY
,
3033 ANV_SEMAPHORE_TYPE_BO
,
3034 ANV_SEMAPHORE_TYPE_WSI_BO
,
3035 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
3036 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
3037 ANV_SEMAPHORE_TYPE_TIMELINE
,
3040 struct anv_timeline_point
{
3041 struct list_head link
;
3045 /* Number of waiter on this point, when > 0 the point should not be garbage
3050 /* BO used for synchronization. */
3054 struct anv_timeline
{
3055 pthread_mutex_t mutex
;
3056 pthread_cond_t cond
;
3058 uint64_t highest_past
;
3059 uint64_t highest_pending
;
3061 struct list_head points
;
3062 struct list_head free_points
;
3065 struct anv_semaphore_impl
{
3066 enum anv_semaphore_type type
;
3069 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
3070 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
3071 * object list on any execbuf2 calls for which this semaphore is used as
3072 * a wait or signal fence. When used as a signal fence or when type ==
3073 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
3077 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
3078 * If the semaphore is in the unsignaled state due to either just being
3079 * created or because it has been used for a wait, fd will be -1.
3083 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3084 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3085 * import so we don't need to bother with a userspace cache.
3089 /* Non shareable timeline semaphore
3091 * Used when kernel don't have support for timeline semaphores.
3093 struct anv_timeline timeline
;
3097 struct anv_semaphore
{
3098 struct vk_object_base base
;
3102 /* Permanent semaphore state. Every semaphore has some form of permanent
3103 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3104 * (for cross-process semaphores0 or it could just be a dummy for use
3107 struct anv_semaphore_impl permanent
;
3109 /* Temporary semaphore state. A semaphore *may* have temporary state.
3110 * That state is added to the semaphore by an import operation and is reset
3111 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3112 * semaphore with temporary state cannot be signaled because the semaphore
3113 * must already be signaled before the temporary state can be exported from
3114 * the semaphore in the other process and imported here.
3116 struct anv_semaphore_impl temporary
;
3119 void anv_semaphore_reset_temporary(struct anv_device
*device
,
3120 struct anv_semaphore
*semaphore
);
3122 struct anv_shader_module
{
3123 struct vk_object_base base
;
3125 unsigned char sha1
[20];
3130 static inline gl_shader_stage
3131 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
3133 assert(__builtin_popcount(vk_stage
) == 1);
3134 return ffs(vk_stage
) - 1;
3137 static inline VkShaderStageFlagBits
3138 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
3140 return (1 << mesa_stage
);
3143 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3145 #define anv_foreach_stage(stage, stage_bits) \
3146 for (gl_shader_stage stage, \
3147 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3148 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3149 __tmp &= ~(1 << (stage)))
3151 struct anv_pipeline_bind_map
{
3152 unsigned char surface_sha1
[20];
3153 unsigned char sampler_sha1
[20];
3154 unsigned char push_sha1
[20];
3156 uint32_t surface_count
;
3157 uint32_t sampler_count
;
3159 struct anv_pipeline_binding
* surface_to_descriptor
;
3160 struct anv_pipeline_binding
* sampler_to_descriptor
;
3162 struct anv_push_range push_ranges
[4];
3165 struct anv_shader_bin_key
{
3170 struct anv_shader_bin
{
3173 gl_shader_stage stage
;
3175 const struct anv_shader_bin_key
*key
;
3177 struct anv_state kernel
;
3178 uint32_t kernel_size
;
3180 struct anv_state constant_data
;
3181 uint32_t constant_data_size
;
3183 const struct brw_stage_prog_data
*prog_data
;
3184 uint32_t prog_data_size
;
3186 struct brw_compile_stats stats
[3];
3189 struct nir_xfb_info
*xfb_info
;
3191 struct anv_pipeline_bind_map bind_map
;
3194 struct anv_shader_bin
*
3195 anv_shader_bin_create(struct anv_device
*device
,
3196 gl_shader_stage stage
,
3197 const void *key
, uint32_t key_size
,
3198 const void *kernel
, uint32_t kernel_size
,
3199 const void *constant_data
, uint32_t constant_data_size
,
3200 const struct brw_stage_prog_data
*prog_data
,
3201 uint32_t prog_data_size
,
3202 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
3203 const struct nir_xfb_info
*xfb_info
,
3204 const struct anv_pipeline_bind_map
*bind_map
);
3207 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3210 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3212 assert(shader
&& shader
->ref_cnt
>= 1);
3213 p_atomic_inc(&shader
->ref_cnt
);
3217 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3219 assert(shader
&& shader
->ref_cnt
>= 1);
3220 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3221 anv_shader_bin_destroy(device
, shader
);
3224 struct anv_pipeline_executable
{
3225 gl_shader_stage stage
;
3227 struct brw_compile_stats stats
;
3233 enum anv_pipeline_type
{
3234 ANV_PIPELINE_GRAPHICS
,
3235 ANV_PIPELINE_COMPUTE
,
3238 struct anv_pipeline
{
3239 struct vk_object_base base
;
3241 struct anv_device
* device
;
3243 struct anv_batch batch
;
3244 struct anv_reloc_list batch_relocs
;
3248 enum anv_pipeline_type type
;
3249 VkPipelineCreateFlags flags
;
3251 struct util_dynarray executables
;
3253 const struct gen_l3_config
* l3_config
;
3256 struct anv_graphics_pipeline
{
3257 struct anv_pipeline base
;
3259 uint32_t batch_data
[512];
3261 anv_cmd_dirty_mask_t dynamic_state_mask
;
3262 struct anv_dynamic_state dynamic_state
;
3266 struct anv_subpass
* subpass
;
3268 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3270 VkShaderStageFlags active_stages
;
3272 bool primitive_restart
;
3274 bool depth_test_enable
;
3275 bool writes_stencil
;
3276 bool stencil_test_enable
;
3277 bool depth_clamp_enable
;
3278 bool depth_clip_enable
;
3279 bool sample_shading_enable
;
3281 bool depth_bounds_test_enable
;
3283 /* When primitive replication is used, subpass->view_mask will describe what
3284 * views to replicate.
3286 bool use_primitive_replication
;
3288 struct anv_state blend_state
;
3291 struct anv_pipeline_vertex_binding
{
3294 uint32_t instance_divisor
;
3299 uint32_t depth_stencil_state
[3];
3305 uint32_t wm_depth_stencil
[3];
3309 uint32_t wm_depth_stencil
[4];
3313 struct anv_compute_pipeline
{
3314 struct anv_pipeline base
;
3316 struct anv_shader_bin
* cs
;
3317 uint32_t cs_right_mask
;
3318 uint32_t batch_data
[9];
3319 uint32_t interface_descriptor_data
[8];
3322 #define ANV_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
3323 static inline struct anv_##pipe_type##_pipeline * \
3324 anv_pipeline_to_##pipe_type(struct anv_pipeline *pipeline) \
3326 assert(pipeline->type == pipe_enum); \
3327 return (struct anv_##pipe_type##_pipeline *) pipeline; \
3330 ANV_DECL_PIPELINE_DOWNCAST(graphics
, ANV_PIPELINE_GRAPHICS
)
3331 ANV_DECL_PIPELINE_DOWNCAST(compute
, ANV_PIPELINE_COMPUTE
)
3334 anv_pipeline_has_stage(const struct anv_graphics_pipeline
*pipeline
,
3335 gl_shader_stage stage
)
3337 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3340 #define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \
3341 static inline const struct brw_##prefix##_prog_data * \
3342 get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \
3344 if (anv_pipeline_has_stage(pipeline, stage)) { \
3345 return (const struct brw_##prefix##_prog_data *) \
3346 pipeline->shaders[stage]->prog_data; \
3352 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3353 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3354 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3355 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3356 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3358 static inline const struct brw_cs_prog_data
*
3359 get_cs_prog_data(const struct anv_compute_pipeline
*pipeline
)
3361 assert(pipeline
->cs
);
3362 return (const struct brw_cs_prog_data
*) pipeline
->cs
->prog_data
;
3365 static inline const struct brw_vue_prog_data
*
3366 anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline
*pipeline
)
3368 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3369 return &get_gs_prog_data(pipeline
)->base
;
3370 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3371 return &get_tes_prog_data(pipeline
)->base
;
3373 return &get_vs_prog_data(pipeline
)->base
;
3377 anv_pipeline_init(struct anv_graphics_pipeline
*pipeline
, struct anv_device
*device
,
3378 struct anv_pipeline_cache
*cache
,
3379 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3380 const VkAllocationCallbacks
*alloc
);
3383 anv_pipeline_compile_cs(struct anv_compute_pipeline
*pipeline
,
3384 struct anv_pipeline_cache
*cache
,
3385 const VkComputePipelineCreateInfo
*info
,
3386 const struct anv_shader_module
*module
,
3387 const char *entrypoint
,
3388 const VkSpecializationInfo
*spec_info
);
3391 anv_cs_workgroup_size(const struct anv_compute_pipeline
*pipeline
);
3394 anv_cs_threads(const struct anv_compute_pipeline
*pipeline
);
3396 struct anv_format_plane
{
3397 enum isl_format isl_format
:16;
3398 struct isl_swizzle swizzle
;
3400 /* Whether this plane contains chroma channels */
3403 /* For downscaling of YUV planes */
3404 uint8_t denominator_scales
[2];
3406 /* How to map sampled ycbcr planes to a single 4 component element. */
3407 struct isl_swizzle ycbcr_swizzle
;
3409 /* What aspect is associated to this plane */
3410 VkImageAspectFlags aspect
;
3415 struct anv_format_plane planes
[3];
3422 * Return the aspect's _format_ plane, not its _memory_ plane (using the
3423 * vocabulary of VK_EXT_image_drm_format_modifier). As a consequence, \a
3424 * aspect_mask may contain VK_IMAGE_ASPECT_PLANE_*, but must not contain
3425 * VK_IMAGE_ASPECT_MEMORY_PLANE_* .
3427 static inline uint32_t
3428 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3429 VkImageAspectFlags aspect_mask
)
3431 switch (aspect_mask
) {
3432 case VK_IMAGE_ASPECT_COLOR_BIT
:
3433 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3434 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3436 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3437 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3440 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3442 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3445 /* Purposefully assert with depth/stencil aspects. */
3446 unreachable("invalid image aspect");
3450 static inline VkImageAspectFlags
3451 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3454 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3455 if (util_bitcount(image_aspects
) > 1)
3456 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3457 return VK_IMAGE_ASPECT_COLOR_BIT
;
3459 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3460 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3461 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3462 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3465 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3466 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3468 const struct anv_format
*
3469 anv_get_format(VkFormat format
);
3471 static inline uint32_t
3472 anv_get_format_planes(VkFormat vk_format
)
3474 const struct anv_format
*format
= anv_get_format(vk_format
);
3476 return format
!= NULL
? format
->n_planes
: 0;
3479 struct anv_format_plane
3480 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3481 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3483 static inline enum isl_format
3484 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3485 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3487 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3490 bool anv_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
3491 VkImageCreateFlags create_flags
,
3493 VkImageTiling vk_tiling
,
3494 const VkImageFormatListCreateInfoKHR
*fmt_list
);
3496 static inline struct isl_swizzle
3497 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3499 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3500 * RGB as RGBA for texturing
3502 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3503 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3505 /* But it doesn't matter what we render to that channel */
3506 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3512 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3515 * Subsurface of an anv_image.
3517 struct anv_surface
{
3518 /** Valid only if isl_surf::size_B > 0. */
3519 struct isl_surf isl
;
3522 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3528 struct vk_object_base base
;
3530 VkImageType type
; /**< VkImageCreateInfo::imageType */
3531 /* The original VkFormat provided by the client. This may not match any
3532 * of the actual surface formats.
3535 const struct anv_format
*format
;
3537 VkImageAspectFlags aspects
;
3540 uint32_t array_size
;
3541 uint32_t samples
; /**< VkImageCreateInfo::samples */
3543 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3544 VkImageUsageFlags stencil_usage
;
3545 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3546 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3548 /** True if this is needs to be bound to an appropriately tiled BO.
3550 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3551 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3552 * we require a dedicated allocation so that we can know to allocate a
3555 bool needs_set_tiling
;
3558 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3559 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3561 uint64_t drm_format_mod
;
3566 /* Whether the image is made of several underlying buffer objects rather a
3567 * single one with different offsets.
3571 /* Image was created with external format. */
3572 bool external_format
;
3577 * For each foo, anv_image::planes[x].surface is valid if and only if
3578 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3579 * to figure the number associated with a given aspect.
3581 * The hardware requires that the depth buffer and stencil buffer be
3582 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3583 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3584 * allocate the depth and stencil buffers as separate surfaces in the same
3589 * -----------------------
3591 * ----------------------- |
3592 * | shadow surface0 | |
3593 * ----------------------- | Plane 0
3594 * | aux surface0 | |
3595 * ----------------------- |
3596 * | fast clear colors0 | \|/
3597 * -----------------------
3599 * ----------------------- |
3600 * | shadow surface1 | |
3601 * ----------------------- | Plane 1
3602 * | aux surface1 | |
3603 * ----------------------- |
3604 * | fast clear colors1 | \|/
3605 * -----------------------
3608 * -----------------------
3612 * Offset of the entire plane (whenever the image is disjoint this is
3620 struct anv_surface surface
;
3623 * A surface which shadows the main surface and may have different
3624 * tiling. This is used for sampling using a tiling that isn't supported
3625 * for other operations.
3627 struct anv_surface shadow_surface
;
3630 * The base aux usage for this image. For color images, this can be
3631 * either CCS_E or CCS_D depending on whether or not we can reliably
3632 * leave CCS on all the time.
3634 enum isl_aux_usage aux_usage
;
3636 struct anv_surface aux_surface
;
3639 * Offset of the fast clear state (used to compute the
3640 * fast_clear_state_offset of the following planes).
3642 uint32_t fast_clear_state_offset
;
3645 * BO associated with this plane, set when bound.
3647 struct anv_address address
;
3650 * When destroying the image, also free the bo.
3656 /* The ordering of this enum is important */
3657 enum anv_fast_clear_type
{
3658 /** Image does not have/support any fast-clear blocks */
3659 ANV_FAST_CLEAR_NONE
= 0,
3660 /** Image has/supports fast-clear but only to the default value */
3661 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3662 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3663 ANV_FAST_CLEAR_ANY
= 2,
3666 /* Returns the number of auxiliary buffer levels attached to an image. */
3667 static inline uint8_t
3668 anv_image_aux_levels(const struct anv_image
* const image
,
3669 VkImageAspectFlagBits aspect
)
3671 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3672 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
3675 /* The Gen12 CCS aux surface is represented with only one level. */
3676 return image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3677 image
->planes
[plane
].surface
.isl
.levels
:
3678 image
->planes
[plane
].aux_surface
.isl
.levels
;
3681 /* Returns the number of auxiliary buffer layers attached to an image. */
3682 static inline uint32_t
3683 anv_image_aux_layers(const struct anv_image
* const image
,
3684 VkImageAspectFlagBits aspect
,
3685 const uint8_t miplevel
)
3689 /* The miplevel must exist in the main buffer. */
3690 assert(miplevel
< image
->levels
);
3692 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3693 /* There are no layers with auxiliary data because the miplevel has no
3698 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3700 /* The Gen12 CCS aux surface is represented with only one layer. */
3701 const struct isl_extent4d
*aux_logical_level0_px
=
3702 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3703 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3704 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3706 return MAX2(aux_logical_level0_px
->array_len
,
3707 aux_logical_level0_px
->depth
>> miplevel
);
3711 static inline struct anv_address
3712 anv_image_get_clear_color_addr(UNUSED
const struct anv_device
*device
,
3713 const struct anv_image
*image
,
3714 VkImageAspectFlagBits aspect
)
3716 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3718 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3719 return anv_address_add(image
->planes
[plane
].address
,
3720 image
->planes
[plane
].fast_clear_state_offset
);
3723 static inline struct anv_address
3724 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3725 const struct anv_image
*image
,
3726 VkImageAspectFlagBits aspect
)
3728 struct anv_address addr
=
3729 anv_image_get_clear_color_addr(device
, image
, aspect
);
3731 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3732 device
->isl_dev
.ss
.clear_color_state_size
:
3733 device
->isl_dev
.ss
.clear_value_size
;
3734 return anv_address_add(addr
, clear_color_state_size
);
3737 static inline struct anv_address
3738 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3739 const struct anv_image
*image
,
3740 VkImageAspectFlagBits aspect
,
3741 uint32_t level
, uint32_t array_layer
)
3743 assert(level
< anv_image_aux_levels(image
, aspect
));
3744 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3745 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3746 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3748 struct anv_address addr
=
3749 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3750 addr
.offset
+= 4; /* Go past the fast clear type */
3752 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3753 for (uint32_t l
= 0; l
< level
; l
++)
3754 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3756 addr
.offset
+= level
* image
->array_size
* 4;
3758 addr
.offset
+= array_layer
* 4;
3760 assert(addr
.offset
<
3761 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3765 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3767 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3768 const struct anv_image
*image
)
3770 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3773 /* For Gen8-11, there are some restrictions around sampling from HiZ.
3774 * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
3777 * "If this field is set to AUX_HIZ, Number of Multisamples must
3778 * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
3780 if (image
->type
== VK_IMAGE_TYPE_3D
)
3783 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3784 * struct. There's documentation which suggests that this feature actually
3785 * reduces performance on BDW, but it has only been observed to help so
3786 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3787 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3789 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3792 return image
->samples
== 1;
3796 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3797 const struct anv_image
*image
,
3800 return device
->info
.has_aux_map
&&
3801 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3805 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3806 const struct anv_image
*image
,
3807 VkImageAspectFlagBits aspect
,
3808 enum isl_aux_usage aux_usage
,
3810 uint32_t base_layer
,
3811 uint32_t layer_count
);
3814 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3815 const struct anv_image
*image
,
3816 VkImageAspectFlagBits aspect
,
3817 enum isl_aux_usage aux_usage
,
3818 enum isl_format format
, struct isl_swizzle swizzle
,
3819 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3820 VkRect2D area
, union isl_color_value clear_color
);
3822 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3823 const struct anv_image
*image
,
3824 VkImageAspectFlags aspects
,
3825 enum isl_aux_usage depth_aux_usage
,
3827 uint32_t base_layer
, uint32_t layer_count
,
3829 float depth_value
, uint8_t stencil_value
);
3831 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3832 const struct anv_image
*src_image
,
3833 enum isl_aux_usage src_aux_usage
,
3834 uint32_t src_level
, uint32_t src_base_layer
,
3835 const struct anv_image
*dst_image
,
3836 enum isl_aux_usage dst_aux_usage
,
3837 uint32_t dst_level
, uint32_t dst_base_layer
,
3838 VkImageAspectFlagBits aspect
,
3839 uint32_t src_x
, uint32_t src_y
,
3840 uint32_t dst_x
, uint32_t dst_y
,
3841 uint32_t width
, uint32_t height
,
3842 uint32_t layer_count
,
3843 enum blorp_filter filter
);
3845 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3846 const struct anv_image
*image
,
3847 VkImageAspectFlagBits aspect
, uint32_t level
,
3848 uint32_t base_layer
, uint32_t layer_count
,
3849 enum isl_aux_op hiz_op
);
3851 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3852 const struct anv_image
*image
,
3853 VkImageAspectFlags aspects
,
3855 uint32_t base_layer
, uint32_t layer_count
,
3856 VkRect2D area
, uint8_t stencil_value
);
3858 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3859 const struct anv_image
*image
,
3860 enum isl_format format
, struct isl_swizzle swizzle
,
3861 VkImageAspectFlagBits aspect
,
3862 uint32_t base_layer
, uint32_t layer_count
,
3863 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3866 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3867 const struct anv_image
*image
,
3868 enum isl_format format
, struct isl_swizzle swizzle
,
3869 VkImageAspectFlagBits aspect
, uint32_t level
,
3870 uint32_t base_layer
, uint32_t layer_count
,
3871 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3875 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3876 const struct anv_image
*image
,
3877 VkImageAspectFlagBits aspect
,
3878 uint32_t base_level
, uint32_t level_count
,
3879 uint32_t base_layer
, uint32_t layer_count
);
3882 anv_layout_to_aux_state(const struct gen_device_info
* const devinfo
,
3883 const struct anv_image
*image
,
3884 const VkImageAspectFlagBits aspect
,
3885 const VkImageLayout layout
);
3888 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3889 const struct anv_image
*image
,
3890 const VkImageAspectFlagBits aspect
,
3891 const VkImageUsageFlagBits usage
,
3892 const VkImageLayout layout
);
3894 enum anv_fast_clear_type
3895 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3896 const struct anv_image
* const image
,
3897 const VkImageAspectFlagBits aspect
,
3898 const VkImageLayout layout
);
3900 /* This is defined as a macro so that it works for both
3901 * VkImageSubresourceRange and VkImageSubresourceLayers
3903 #define anv_get_layerCount(_image, _range) \
3904 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3905 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3907 static inline uint32_t
3908 anv_get_levelCount(const struct anv_image
*image
,
3909 const VkImageSubresourceRange
*range
)
3911 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3912 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3915 static inline VkImageAspectFlags
3916 anv_image_expand_aspects(const struct anv_image
*image
,
3917 VkImageAspectFlags aspects
)
3919 /* If the underlying image has color plane aspects and
3920 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3921 * the underlying image. */
3922 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3923 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3924 return image
->aspects
;
3930 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3931 VkImageAspectFlags aspects2
)
3933 if (aspects1
== aspects2
)
3936 /* Only 1 color aspects are compatibles. */
3937 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3938 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3939 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3945 struct anv_image_view
{
3946 struct vk_object_base base
;
3948 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3950 VkImageAspectFlags aspect_mask
;
3952 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3956 uint32_t image_plane
;
3958 struct isl_view isl
;
3961 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3962 * image layout of SHADER_READ_ONLY_OPTIMAL or
3963 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3965 struct anv_surface_state optimal_sampler_surface_state
;
3968 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3969 * image layout of GENERAL.
3971 struct anv_surface_state general_sampler_surface_state
;
3974 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3975 * states for write-only and readable, using the real format for
3976 * write-only and the lowered format for readable.
3978 struct anv_surface_state storage_surface_state
;
3979 struct anv_surface_state writeonly_storage_surface_state
;
3981 struct brw_image_param storage_image_param
;
3985 enum anv_image_view_state_flags
{
3986 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3987 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3990 void anv_image_fill_surface_state(struct anv_device
*device
,
3991 const struct anv_image
*image
,
3992 VkImageAspectFlagBits aspect
,
3993 const struct isl_view
*view
,
3994 isl_surf_usage_flags_t view_usage
,
3995 enum isl_aux_usage aux_usage
,
3996 const union isl_color_value
*clear_color
,
3997 enum anv_image_view_state_flags flags
,
3998 struct anv_surface_state
*state_inout
,
3999 struct brw_image_param
*image_param_out
);
4001 struct anv_image_create_info
{
4002 const VkImageCreateInfo
*vk_info
;
4004 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
4005 isl_tiling_flags_t isl_tiling_flags
;
4007 /** These flags will be added to any derived from VkImageCreateInfo. */
4008 isl_surf_usage_flags_t isl_extra_usage_flags
;
4011 bool external_format
;
4014 VkResult
anv_image_create(VkDevice _device
,
4015 const struct anv_image_create_info
*info
,
4016 const VkAllocationCallbacks
* alloc
,
4020 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
4022 static inline VkExtent3D
4023 anv_sanitize_image_extent(const VkImageType imageType
,
4024 const VkExtent3D imageExtent
)
4026 switch (imageType
) {
4027 case VK_IMAGE_TYPE_1D
:
4028 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
4029 case VK_IMAGE_TYPE_2D
:
4030 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
4031 case VK_IMAGE_TYPE_3D
:
4034 unreachable("invalid image type");
4038 static inline VkOffset3D
4039 anv_sanitize_image_offset(const VkImageType imageType
,
4040 const VkOffset3D imageOffset
)
4042 switch (imageType
) {
4043 case VK_IMAGE_TYPE_1D
:
4044 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
4045 case VK_IMAGE_TYPE_2D
:
4046 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
4047 case VK_IMAGE_TYPE_3D
:
4050 unreachable("invalid image type");
4054 VkFormatFeatureFlags
4055 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
4057 const struct anv_format
*anv_format
,
4058 VkImageTiling vk_tiling
);
4060 void anv_fill_buffer_surface_state(struct anv_device
*device
,
4061 struct anv_state state
,
4062 enum isl_format format
,
4063 struct anv_address address
,
4064 uint32_t range
, uint32_t stride
);
4067 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
4068 const struct anv_attachment_state
*att_state
,
4069 const struct anv_image_view
*iview
)
4071 const struct isl_format_layout
*view_fmtl
=
4072 isl_format_get_layout(iview
->planes
[0].isl
.format
);
4074 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
4075 if (view_fmtl->channels.c.bits) \
4076 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
4078 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
4079 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
4080 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
4081 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
4083 #undef COPY_CLEAR_COLOR_CHANNEL
4087 /* Haswell border color is a bit of a disaster. Float and unorm formats use a
4088 * straightforward 32-bit float color in the first 64 bytes. Instead of using
4089 * a nice float/integer union like Gen8+, Haswell specifies the integer border
4090 * color as a separate entry /after/ the float color. The layout of this entry
4091 * also depends on the format's bpp (with extra hacks for RG32), and overlaps.
4093 * Since we don't know the format/bpp, we can't make any of the border colors
4094 * containing '1' work for all formats, as it would be in the wrong place for
4095 * some of them. We opt to make 32-bit integers work as this seems like the
4096 * most common option. Fortunately, transparent black works regardless, as
4097 * all zeroes is the same in every bit-size.
4099 struct hsw_border_color
{
4103 uint32_t _pad1
[108];
4106 struct gen8_border_color
{
4111 /* Pad out to 64 bytes */
4115 struct anv_ycbcr_conversion
{
4116 struct vk_object_base base
;
4118 const struct anv_format
* format
;
4119 VkSamplerYcbcrModelConversion ycbcr_model
;
4120 VkSamplerYcbcrRange ycbcr_range
;
4121 VkComponentSwizzle mapping
[4];
4122 VkChromaLocation chroma_offsets
[2];
4123 VkFilter chroma_filter
;
4124 bool chroma_reconstruction
;
4127 struct anv_sampler
{
4128 struct vk_object_base base
;
4130 uint32_t state
[3][4];
4132 struct anv_ycbcr_conversion
*conversion
;
4134 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
4135 * and with a 32-byte stride for use as bindless samplers.
4137 struct anv_state bindless_state
;
4139 struct anv_state custom_border_color
;
4142 struct anv_framebuffer
{
4143 struct vk_object_base base
;
4149 uint32_t attachment_count
;
4150 struct anv_image_view
* attachments
[0];
4153 struct anv_subpass_attachment
{
4154 VkImageUsageFlagBits usage
;
4155 uint32_t attachment
;
4156 VkImageLayout layout
;
4158 /* Used only with attachment containing stencil data. */
4159 VkImageLayout stencil_layout
;
4162 struct anv_subpass
{
4163 uint32_t attachment_count
;
4166 * A pointer to all attachment references used in this subpass.
4167 * Only valid if ::attachment_count > 0.
4169 struct anv_subpass_attachment
* attachments
;
4170 uint32_t input_count
;
4171 struct anv_subpass_attachment
* input_attachments
;
4172 uint32_t color_count
;
4173 struct anv_subpass_attachment
* color_attachments
;
4174 struct anv_subpass_attachment
* resolve_attachments
;
4176 struct anv_subpass_attachment
* depth_stencil_attachment
;
4177 struct anv_subpass_attachment
* ds_resolve_attachment
;
4178 VkResolveModeFlagBitsKHR depth_resolve_mode
;
4179 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
4183 /** Subpass has a depth/stencil self-dependency */
4184 bool has_ds_self_dep
;
4186 /** Subpass has at least one color resolve attachment */
4187 bool has_color_resolve
;
4190 static inline unsigned
4191 anv_subpass_view_count(const struct anv_subpass
*subpass
)
4193 return MAX2(1, util_bitcount(subpass
->view_mask
));
4196 struct anv_render_pass_attachment
{
4197 /* TODO: Consider using VkAttachmentDescription instead of storing each of
4198 * its members individually.
4202 VkImageUsageFlags usage
;
4203 VkAttachmentLoadOp load_op
;
4204 VkAttachmentStoreOp store_op
;
4205 VkAttachmentLoadOp stencil_load_op
;
4206 VkImageLayout initial_layout
;
4207 VkImageLayout final_layout
;
4208 VkImageLayout first_subpass_layout
;
4210 VkImageLayout stencil_initial_layout
;
4211 VkImageLayout stencil_final_layout
;
4213 /* The subpass id in which the attachment will be used last. */
4214 uint32_t last_subpass_idx
;
4217 struct anv_render_pass
{
4218 struct vk_object_base base
;
4220 uint32_t attachment_count
;
4221 uint32_t subpass_count
;
4222 /* An array of subpass_count+1 flushes, one per subpass boundary */
4223 enum anv_pipe_bits
* subpass_flushes
;
4224 struct anv_render_pass_attachment
* attachments
;
4225 struct anv_subpass subpasses
[0];
4228 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
4230 struct anv_query_pool
{
4231 struct vk_object_base base
;
4234 VkQueryPipelineStatisticFlags pipeline_statistics
;
4235 /** Stride between slots, in bytes */
4237 /** Number of slots in this query pool */
4242 int anv_get_instance_entrypoint_index(const char *name
);
4243 int anv_get_device_entrypoint_index(const char *name
);
4244 int anv_get_physical_device_entrypoint_index(const char *name
);
4246 const char *anv_get_instance_entry_name(int index
);
4247 const char *anv_get_physical_device_entry_name(int index
);
4248 const char *anv_get_device_entry_name(int index
);
4251 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
4252 const struct anv_instance_extension_table
*instance
);
4254 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4255 const struct anv_instance_extension_table
*instance
);
4257 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4258 const struct anv_instance_extension_table
*instance
,
4259 const struct anv_device_extension_table
*device
);
4261 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
4264 void anv_dump_image_to_ppm(struct anv_device
*device
,
4265 struct anv_image
*image
, unsigned miplevel
,
4266 unsigned array_layer
, VkImageAspectFlagBits aspect
,
4267 const char *filename
);
4269 enum anv_dump_action
{
4270 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
4273 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
4274 void anv_dump_finish(void);
4276 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
4278 static inline uint32_t
4279 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
4281 /* This function must be called from within a subpass. */
4282 assert(cmd_state
->pass
&& cmd_state
->subpass
);
4284 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
4286 /* The id of this subpass shouldn't exceed the number of subpasses in this
4287 * render pass minus 1.
4289 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
4293 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
4294 void anv_device_perf_init(struct anv_device
*device
);
4296 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4297 VK_FROM_HANDLE(__anv_type, __name, __handle)
4299 VK_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, base
, VkCommandBuffer
,
4300 VK_OBJECT_TYPE_COMMAND_BUFFER
)
4301 VK_DEFINE_HANDLE_CASTS(anv_device
, vk
.base
, VkDevice
, VK_OBJECT_TYPE_DEVICE
)
4302 VK_DEFINE_HANDLE_CASTS(anv_instance
, base
, VkInstance
, VK_OBJECT_TYPE_INSTANCE
)
4303 VK_DEFINE_HANDLE_CASTS(anv_physical_device
, base
, VkPhysicalDevice
,
4304 VK_OBJECT_TYPE_PHYSICAL_DEVICE
)
4305 VK_DEFINE_HANDLE_CASTS(anv_queue
, base
, VkQueue
, VK_OBJECT_TYPE_QUEUE
)
4307 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, base
, VkCommandPool
,
4308 VK_OBJECT_TYPE_COMMAND_POOL
)
4309 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, base
, VkBuffer
,
4310 VK_OBJECT_TYPE_BUFFER
)
4311 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, base
, VkBufferView
,
4312 VK_OBJECT_TYPE_BUFFER_VIEW
)
4313 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, base
, VkDescriptorPool
,
4314 VK_OBJECT_TYPE_DESCRIPTOR_POOL
)
4315 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, base
, VkDescriptorSet
,
4316 VK_OBJECT_TYPE_DESCRIPTOR_SET
)
4317 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, base
,
4318 VkDescriptorSetLayout
,
4319 VK_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT
)
4320 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, base
,
4321 VkDescriptorUpdateTemplate
,
4322 VK_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE
)
4323 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, base
, VkDeviceMemory
,
4324 VK_OBJECT_TYPE_DEVICE_MEMORY
)
4325 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, base
, VkFence
, VK_OBJECT_TYPE_FENCE
)
4326 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, base
, VkEvent
, VK_OBJECT_TYPE_EVENT
)
4327 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, base
, VkFramebuffer
,
4328 VK_OBJECT_TYPE_FRAMEBUFFER
)
4329 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, base
, VkImage
, VK_OBJECT_TYPE_IMAGE
)
4330 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, base
, VkImageView
,
4331 VK_OBJECT_TYPE_IMAGE_VIEW
);
4332 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, base
, VkPipelineCache
,
4333 VK_OBJECT_TYPE_PIPELINE_CACHE
)
4334 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, base
, VkPipeline
,
4335 VK_OBJECT_TYPE_PIPELINE
)
4336 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, base
, VkPipelineLayout
,
4337 VK_OBJECT_TYPE_PIPELINE_LAYOUT
)
4338 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, base
, VkQueryPool
,
4339 VK_OBJECT_TYPE_QUERY_POOL
)
4340 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, base
, VkRenderPass
,
4341 VK_OBJECT_TYPE_RENDER_PASS
)
4342 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, base
, VkSampler
,
4343 VK_OBJECT_TYPE_SAMPLER
)
4344 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, base
, VkSemaphore
,
4345 VK_OBJECT_TYPE_SEMAPHORE
)
4346 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, base
, VkShaderModule
,
4347 VK_OBJECT_TYPE_SHADER_MODULE
)
4348 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, base
,
4349 VkSamplerYcbcrConversion
,
4350 VK_OBJECT_TYPE_SAMPLER_YCBCR_CONVERSION
)
4352 /* Gen-specific function declarations */
4354 # include "anv_genX.h"
4356 # define genX(x) gen7_##x
4357 # include "anv_genX.h"
4359 # define genX(x) gen75_##x
4360 # include "anv_genX.h"
4362 # define genX(x) gen8_##x
4363 # include "anv_genX.h"
4365 # define genX(x) gen9_##x
4366 # include "anv_genX.h"
4368 # define genX(x) gen10_##x
4369 # include "anv_genX.h"
4371 # define genX(x) gen11_##x
4372 # include "anv_genX.h"
4374 # define genX(x) gen12_##x
4375 # include "anv_genX.h"
4379 #endif /* ANV_PRIVATE_H */