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[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 /* Pre-declarations needed for WSI entrypoints */
56 struct wl_surface;
57 struct wl_display;
58 typedef struct xcb_connection_t xcb_connection_t;
59 typedef uint32_t xcb_visualid_t;
60 typedef uint32_t xcb_window_t;
61
62 struct anv_buffer;
63 struct anv_buffer_view;
64 struct anv_image_view;
65 struct anv_instance;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72 #include <vulkan/vk_android_native_buffer.h>
73
74 #include "anv_entrypoints.h"
75 #include "anv_extensions.h"
76 #include "isl/isl.h"
77
78 #include "common/gen_debug.h"
79 #include "common/intel_log.h"
80 #include "wsi_common.h"
81
82 /* Allowing different clear colors requires us to perform a depth resolve at
83 * the end of certain render passes. This is because while slow clears store
84 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
85 * See the PRMs for examples describing when additional resolves would be
86 * necessary. To enable fast clears without requiring extra resolves, we set
87 * the clear value to a globally-defined one. We could allow different values
88 * if the user doesn't expect coherent data during or after a render passes
89 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
90 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
91 * 1.0f seems to be the only value used. The only application that doesn't set
92 * this value does so through the usage of an seemingly uninitialized clear
93 * value.
94 */
95 #define ANV_HZ_FC_VAL 1.0f
96
97 #define MAX_VBS 28
98 #define MAX_SETS 8
99 #define MAX_RTS 8
100 #define MAX_VIEWPORTS 16
101 #define MAX_SCISSORS 16
102 #define MAX_PUSH_CONSTANTS_SIZE 128
103 #define MAX_DYNAMIC_BUFFERS 16
104 #define MAX_IMAGES 8
105 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
106
107 #define ANV_SVGS_VB_INDEX MAX_VBS
108 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
109
110 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
111
112 static inline uint32_t
113 align_down_npot_u32(uint32_t v, uint32_t a)
114 {
115 return v - (v % a);
116 }
117
118 static inline uint32_t
119 align_u32(uint32_t v, uint32_t a)
120 {
121 assert(a != 0 && a == (a & -a));
122 return (v + a - 1) & ~(a - 1);
123 }
124
125 static inline uint64_t
126 align_u64(uint64_t v, uint64_t a)
127 {
128 assert(a != 0 && a == (a & -a));
129 return (v + a - 1) & ~(a - 1);
130 }
131
132 static inline int32_t
133 align_i32(int32_t v, int32_t a)
134 {
135 assert(a != 0 && a == (a & -a));
136 return (v + a - 1) & ~(a - 1);
137 }
138
139 /** Alignment must be a power of 2. */
140 static inline bool
141 anv_is_aligned(uintmax_t n, uintmax_t a)
142 {
143 assert(a == (a & -a));
144 return (n & (a - 1)) == 0;
145 }
146
147 static inline uint32_t
148 anv_minify(uint32_t n, uint32_t levels)
149 {
150 if (unlikely(n == 0))
151 return 0;
152 else
153 return MAX2(n >> levels, 1);
154 }
155
156 static inline float
157 anv_clamp_f(float f, float min, float max)
158 {
159 assert(min < max);
160
161 if (f > max)
162 return max;
163 else if (f < min)
164 return min;
165 else
166 return f;
167 }
168
169 static inline bool
170 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
171 {
172 if (*inout_mask & clear_mask) {
173 *inout_mask &= ~clear_mask;
174 return true;
175 } else {
176 return false;
177 }
178 }
179
180 static inline union isl_color_value
181 vk_to_isl_color(VkClearColorValue color)
182 {
183 return (union isl_color_value) {
184 .u32 = {
185 color.uint32[0],
186 color.uint32[1],
187 color.uint32[2],
188 color.uint32[3],
189 },
190 };
191 }
192
193 #define for_each_bit(b, dword) \
194 for (uint32_t __dword = (dword); \
195 (b) = __builtin_ffs(__dword) - 1, __dword; \
196 __dword &= ~(1 << (b)))
197
198 #define typed_memcpy(dest, src, count) ({ \
199 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
200 memcpy((dest), (src), (count) * sizeof(*(src))); \
201 })
202
203 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
204 * to be added here in order to utilize mapping in debug/error/perf macros.
205 */
206 #define REPORT_OBJECT_TYPE(o) \
207 __builtin_choose_expr ( \
208 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
209 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
210 __builtin_choose_expr ( \
211 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
212 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
213 __builtin_choose_expr ( \
214 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
215 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
216 __builtin_choose_expr ( \
217 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
218 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
219 __builtin_choose_expr ( \
220 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
221 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
222 __builtin_choose_expr ( \
223 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
224 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
225 __builtin_choose_expr ( \
226 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
227 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
228 __builtin_choose_expr ( \
229 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
230 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
231 __builtin_choose_expr ( \
232 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
233 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
234 __builtin_choose_expr ( \
235 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
236 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
237 __builtin_choose_expr ( \
238 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
239 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
240 __builtin_choose_expr ( \
241 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
242 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
243 __builtin_choose_expr ( \
244 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
245 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
246 __builtin_choose_expr ( \
247 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
248 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
249 __builtin_choose_expr ( \
250 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
251 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
252 __builtin_choose_expr ( \
253 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
254 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
255 __builtin_choose_expr ( \
256 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
257 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
258 __builtin_choose_expr ( \
259 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
260 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
261 __builtin_choose_expr ( \
262 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
263 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
264 __builtin_choose_expr ( \
265 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
266 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
267 __builtin_choose_expr ( \
268 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
269 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
270 __builtin_choose_expr ( \
271 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
272 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
273 __builtin_choose_expr ( \
274 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
275 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
276 __builtin_choose_expr ( \
277 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
278 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
279 __builtin_choose_expr ( \
280 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
281 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
282 __builtin_choose_expr ( \
283 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
284 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
285 __builtin_choose_expr ( \
286 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
287 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
288 __builtin_choose_expr ( \
289 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
290 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
291 __builtin_choose_expr ( \
292 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
293 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
294 __builtin_choose_expr ( \
295 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
296 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
297 __builtin_choose_expr ( \
298 __builtin_types_compatible_p (__typeof (o), void*), \
299 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
300 /* The void expression results in a compile-time error \
301 when assigning the result to something. */ \
302 (void)0)))))))))))))))))))))))))))))))
303
304 /* Whenever we generate an error, pass it through this function. Useful for
305 * debugging, where we can break on it. Only call at error site, not when
306 * propagating errors. Might be useful to plug in a stack trace here.
307 */
308
309 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
310 VkDebugReportObjectTypeEXT type, VkResult error,
311 const char *file, int line, const char *format, ...);
312
313 #ifdef DEBUG
314 #define vk_error(error) __vk_errorf(NULL, NULL,\
315 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
316 error, __FILE__, __LINE__, NULL)
317 #define vk_errorf(instance, obj, error, format, ...)\
318 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
319 __FILE__, __LINE__, format, ## __VA_ARGS__)
320 #else
321 #define vk_error(error) error
322 #define vk_errorf(instance, obj, error, format, ...) error
323 #endif
324
325 /**
326 * Warn on ignored extension structs.
327 *
328 * The Vulkan spec requires us to ignore unsupported or unknown structs in
329 * a pNext chain. In debug mode, emitting warnings for ignored structs may
330 * help us discover structs that we should not have ignored.
331 *
332 *
333 * From the Vulkan 1.0.38 spec:
334 *
335 * Any component of the implementation (the loader, any enabled layers,
336 * and drivers) must skip over, without processing (other than reading the
337 * sType and pNext members) any chained structures with sType values not
338 * defined by extensions supported by that component.
339 */
340 #define anv_debug_ignored_stype(sType) \
341 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
342
343 void __anv_perf_warn(struct anv_instance *instance, const void *object,
344 VkDebugReportObjectTypeEXT type, const char *file,
345 int line, const char *format, ...)
346 anv_printflike(6, 7);
347 void anv_loge(const char *format, ...) anv_printflike(1, 2);
348 void anv_loge_v(const char *format, va_list va);
349
350 /**
351 * Print a FINISHME message, including its source location.
352 */
353 #define anv_finishme(format, ...) \
354 do { \
355 static bool reported = false; \
356 if (!reported) { \
357 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
358 ##__VA_ARGS__); \
359 reported = true; \
360 } \
361 } while (0)
362
363 /**
364 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
365 */
366 #define anv_perf_warn(instance, obj, format, ...) \
367 do { \
368 static bool reported = false; \
369 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
370 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
371 format, ##__VA_ARGS__); \
372 reported = true; \
373 } \
374 } while (0)
375
376 /* A non-fatal assert. Useful for debugging. */
377 #ifdef DEBUG
378 #define anv_assert(x) ({ \
379 if (unlikely(!(x))) \
380 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
381 })
382 #else
383 #define anv_assert(x)
384 #endif
385
386 /* A multi-pointer allocator
387 *
388 * When copying data structures from the user (such as a render pass), it's
389 * common to need to allocate data for a bunch of different things. Instead
390 * of doing several allocations and having to handle all of the error checking
391 * that entails, it can be easier to do a single allocation. This struct
392 * helps facilitate that. The intended usage looks like this:
393 *
394 * ANV_MULTIALLOC(ma)
395 * anv_multialloc_add(&ma, &main_ptr, 1);
396 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
397 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
398 *
399 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
400 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
401 */
402 struct anv_multialloc {
403 size_t size;
404 size_t align;
405
406 uint32_t ptr_count;
407 void **ptrs[8];
408 };
409
410 #define ANV_MULTIALLOC_INIT \
411 ((struct anv_multialloc) { 0, })
412
413 #define ANV_MULTIALLOC(_name) \
414 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
415
416 __attribute__((always_inline))
417 static inline void
418 _anv_multialloc_add(struct anv_multialloc *ma,
419 void **ptr, size_t size, size_t align)
420 {
421 size_t offset = align_u64(ma->size, align);
422 ma->size = offset + size;
423 ma->align = MAX2(ma->align, align);
424
425 /* Store the offset in the pointer. */
426 *ptr = (void *)(uintptr_t)offset;
427
428 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
429 ma->ptrs[ma->ptr_count++] = ptr;
430 }
431
432 #define anv_multialloc_add_size(_ma, _ptr, _size) \
433 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
434
435 #define anv_multialloc_add(_ma, _ptr, _count) \
436 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
437
438 __attribute__((always_inline))
439 static inline void *
440 anv_multialloc_alloc(struct anv_multialloc *ma,
441 const VkAllocationCallbacks *alloc,
442 VkSystemAllocationScope scope)
443 {
444 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
445 if (!ptr)
446 return NULL;
447
448 /* Fill out each of the pointers with their final value.
449 *
450 * for (uint32_t i = 0; i < ma->ptr_count; i++)
451 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
452 *
453 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
454 * constant, GCC is incapable of figuring this out and unrolling the loop
455 * so we have to give it a little help.
456 */
457 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
458 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
459 if ((_i) < ma->ptr_count) \
460 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
461 _ANV_MULTIALLOC_UPDATE_POINTER(0);
462 _ANV_MULTIALLOC_UPDATE_POINTER(1);
463 _ANV_MULTIALLOC_UPDATE_POINTER(2);
464 _ANV_MULTIALLOC_UPDATE_POINTER(3);
465 _ANV_MULTIALLOC_UPDATE_POINTER(4);
466 _ANV_MULTIALLOC_UPDATE_POINTER(5);
467 _ANV_MULTIALLOC_UPDATE_POINTER(6);
468 _ANV_MULTIALLOC_UPDATE_POINTER(7);
469 #undef _ANV_MULTIALLOC_UPDATE_POINTER
470
471 return ptr;
472 }
473
474 __attribute__((always_inline))
475 static inline void *
476 anv_multialloc_alloc2(struct anv_multialloc *ma,
477 const VkAllocationCallbacks *parent_alloc,
478 const VkAllocationCallbacks *alloc,
479 VkSystemAllocationScope scope)
480 {
481 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
482 }
483
484 struct anv_bo {
485 uint32_t gem_handle;
486
487 /* Index into the current validation list. This is used by the
488 * validation list building alrogithm to track which buffers are already
489 * in the validation list so that we can ensure uniqueness.
490 */
491 uint32_t index;
492
493 /* Last known offset. This value is provided by the kernel when we
494 * execbuf and is used as the presumed offset for the next bunch of
495 * relocations.
496 */
497 uint64_t offset;
498
499 uint64_t size;
500 void *map;
501
502 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
503 uint32_t flags;
504 };
505
506 static inline void
507 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
508 {
509 bo->gem_handle = gem_handle;
510 bo->index = 0;
511 bo->offset = -1;
512 bo->size = size;
513 bo->map = NULL;
514 bo->flags = 0;
515 }
516
517 /* Represents a lock-free linked list of "free" things. This is used by
518 * both the block pool and the state pools. Unfortunately, in order to
519 * solve the ABA problem, we can't use a single uint32_t head.
520 */
521 union anv_free_list {
522 struct {
523 int32_t offset;
524
525 /* A simple count that is incremented every time the head changes. */
526 uint32_t count;
527 };
528 uint64_t u64;
529 };
530
531 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
532
533 struct anv_block_state {
534 union {
535 struct {
536 uint32_t next;
537 uint32_t end;
538 };
539 uint64_t u64;
540 };
541 };
542
543 struct anv_block_pool {
544 struct anv_device *device;
545
546 uint64_t bo_flags;
547
548 struct anv_bo bo;
549
550 /* The offset from the start of the bo to the "center" of the block
551 * pool. Pointers to allocated blocks are given by
552 * bo.map + center_bo_offset + offsets.
553 */
554 uint32_t center_bo_offset;
555
556 /* Current memory map of the block pool. This pointer may or may not
557 * point to the actual beginning of the block pool memory. If
558 * anv_block_pool_alloc_back has ever been called, then this pointer
559 * will point to the "center" position of the buffer and all offsets
560 * (negative or positive) given out by the block pool alloc functions
561 * will be valid relative to this pointer.
562 *
563 * In particular, map == bo.map + center_offset
564 */
565 void *map;
566 int fd;
567
568 /**
569 * Array of mmaps and gem handles owned by the block pool, reclaimed when
570 * the block pool is destroyed.
571 */
572 struct u_vector mmap_cleanups;
573
574 struct anv_block_state state;
575
576 struct anv_block_state back_state;
577 };
578
579 /* Block pools are backed by a fixed-size 1GB memfd */
580 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
581
582 /* The center of the block pool is also the middle of the memfd. This may
583 * change in the future if we decide differently for some reason.
584 */
585 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
586
587 static inline uint32_t
588 anv_block_pool_size(struct anv_block_pool *pool)
589 {
590 return pool->state.end + pool->back_state.end;
591 }
592
593 struct anv_state {
594 int32_t offset;
595 uint32_t alloc_size;
596 void *map;
597 };
598
599 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
600
601 struct anv_fixed_size_state_pool {
602 union anv_free_list free_list;
603 struct anv_block_state block;
604 };
605
606 #define ANV_MIN_STATE_SIZE_LOG2 6
607 #define ANV_MAX_STATE_SIZE_LOG2 20
608
609 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
610
611 struct anv_state_pool {
612 struct anv_block_pool block_pool;
613
614 /* The size of blocks which will be allocated from the block pool */
615 uint32_t block_size;
616
617 /** Free list for "back" allocations */
618 union anv_free_list back_alloc_free_list;
619
620 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
621 };
622
623 struct anv_state_stream_block;
624
625 struct anv_state_stream {
626 struct anv_state_pool *state_pool;
627
628 /* The size of blocks to allocate from the state pool */
629 uint32_t block_size;
630
631 /* Current block we're allocating from */
632 struct anv_state block;
633
634 /* Offset into the current block at which to allocate the next state */
635 uint32_t next;
636
637 /* List of all blocks allocated from this pool */
638 struct anv_state_stream_block *block_list;
639 };
640
641 /* The block_pool functions exported for testing only. The block pool should
642 * only be used via a state pool (see below).
643 */
644 VkResult anv_block_pool_init(struct anv_block_pool *pool,
645 struct anv_device *device,
646 uint32_t initial_size,
647 uint64_t bo_flags);
648 void anv_block_pool_finish(struct anv_block_pool *pool);
649 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
650 uint32_t block_size);
651 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
652 uint32_t block_size);
653
654 VkResult anv_state_pool_init(struct anv_state_pool *pool,
655 struct anv_device *device,
656 uint32_t block_size,
657 uint64_t bo_flags);
658 void anv_state_pool_finish(struct anv_state_pool *pool);
659 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
660 uint32_t state_size, uint32_t alignment);
661 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
662 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
663 void anv_state_stream_init(struct anv_state_stream *stream,
664 struct anv_state_pool *state_pool,
665 uint32_t block_size);
666 void anv_state_stream_finish(struct anv_state_stream *stream);
667 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
668 uint32_t size, uint32_t alignment);
669
670 /**
671 * Implements a pool of re-usable BOs. The interface is identical to that
672 * of block_pool except that each block is its own BO.
673 */
674 struct anv_bo_pool {
675 struct anv_device *device;
676
677 uint64_t bo_flags;
678
679 void *free_list[16];
680 };
681
682 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
683 uint64_t bo_flags);
684 void anv_bo_pool_finish(struct anv_bo_pool *pool);
685 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
686 uint32_t size);
687 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
688
689 struct anv_scratch_bo {
690 bool exists;
691 struct anv_bo bo;
692 };
693
694 struct anv_scratch_pool {
695 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
696 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
697 };
698
699 void anv_scratch_pool_init(struct anv_device *device,
700 struct anv_scratch_pool *pool);
701 void anv_scratch_pool_finish(struct anv_device *device,
702 struct anv_scratch_pool *pool);
703 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
704 struct anv_scratch_pool *pool,
705 gl_shader_stage stage,
706 unsigned per_thread_scratch);
707
708 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
709 struct anv_bo_cache {
710 struct hash_table *bo_map;
711 pthread_mutex_t mutex;
712 };
713
714 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
715 void anv_bo_cache_finish(struct anv_bo_cache *cache);
716 VkResult anv_bo_cache_alloc(struct anv_device *device,
717 struct anv_bo_cache *cache,
718 uint64_t size, struct anv_bo **bo);
719 VkResult anv_bo_cache_import(struct anv_device *device,
720 struct anv_bo_cache *cache,
721 int fd, struct anv_bo **bo);
722 VkResult anv_bo_cache_export(struct anv_device *device,
723 struct anv_bo_cache *cache,
724 struct anv_bo *bo_in, int *fd_out);
725 void anv_bo_cache_release(struct anv_device *device,
726 struct anv_bo_cache *cache,
727 struct anv_bo *bo);
728
729 struct anv_memory_type {
730 /* Standard bits passed on to the client */
731 VkMemoryPropertyFlags propertyFlags;
732 uint32_t heapIndex;
733
734 /* Driver-internal book-keeping */
735 VkBufferUsageFlags valid_buffer_usage;
736 };
737
738 struct anv_memory_heap {
739 /* Standard bits passed on to the client */
740 VkDeviceSize size;
741 VkMemoryHeapFlags flags;
742
743 /* Driver-internal book-keeping */
744 bool supports_48bit_addresses;
745 };
746
747 struct anv_physical_device {
748 VK_LOADER_DATA _loader_data;
749
750 struct anv_instance * instance;
751 uint32_t chipset_id;
752 bool no_hw;
753 char path[20];
754 const char * name;
755 struct gen_device_info info;
756 /** Amount of "GPU memory" we want to advertise
757 *
758 * Clearly, this value is bogus since Intel is a UMA architecture. On
759 * gen7 platforms, we are limited by GTT size unless we want to implement
760 * fine-grained tracking and GTT splitting. On Broadwell and above we are
761 * practically unlimited. However, we will never report more than 3/4 of
762 * the total system ram to try and avoid running out of RAM.
763 */
764 bool supports_48bit_addresses;
765 struct brw_compiler * compiler;
766 struct isl_device isl_dev;
767 int cmd_parser_version;
768 bool has_exec_async;
769 bool has_exec_capture;
770 bool has_exec_fence;
771 bool has_syncobj;
772 bool has_syncobj_wait;
773 bool has_context_priority;
774
775 struct anv_device_extension_table supported_extensions;
776
777 uint32_t eu_total;
778 uint32_t subslice_total;
779
780 struct {
781 uint32_t type_count;
782 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
783 uint32_t heap_count;
784 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
785 } memory;
786
787 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
788 uint8_t driver_uuid[VK_UUID_SIZE];
789 uint8_t device_uuid[VK_UUID_SIZE];
790
791 struct wsi_device wsi_device;
792 int local_fd;
793 };
794
795 struct anv_instance {
796 VK_LOADER_DATA _loader_data;
797
798 VkAllocationCallbacks alloc;
799
800 uint32_t apiVersion;
801 struct anv_instance_extension_table enabled_extensions;
802 struct anv_dispatch_table dispatch;
803
804 int physicalDeviceCount;
805 struct anv_physical_device physicalDevice;
806
807 struct vk_debug_report_instance debug_report_callbacks;
808 };
809
810 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
811 void anv_finish_wsi(struct anv_physical_device *physical_device);
812
813 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
814 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
815 const char *name);
816
817 struct anv_queue {
818 VK_LOADER_DATA _loader_data;
819
820 struct anv_device * device;
821
822 struct anv_state_pool * pool;
823 };
824
825 struct anv_pipeline_cache {
826 struct anv_device * device;
827 pthread_mutex_t mutex;
828
829 struct hash_table * cache;
830 };
831
832 struct anv_pipeline_bind_map;
833
834 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
835 struct anv_device *device,
836 bool cache_enabled);
837 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
838
839 struct anv_shader_bin *
840 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
841 const void *key, uint32_t key_size);
842 struct anv_shader_bin *
843 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
844 const void *key_data, uint32_t key_size,
845 const void *kernel_data, uint32_t kernel_size,
846 const struct brw_stage_prog_data *prog_data,
847 uint32_t prog_data_size,
848 const struct anv_pipeline_bind_map *bind_map);
849
850 struct anv_device {
851 VK_LOADER_DATA _loader_data;
852
853 VkAllocationCallbacks alloc;
854
855 struct anv_instance * instance;
856 uint32_t chipset_id;
857 bool no_hw;
858 struct gen_device_info info;
859 struct isl_device isl_dev;
860 int context_id;
861 int fd;
862 bool can_chain_batches;
863 bool robust_buffer_access;
864 struct anv_device_extension_table enabled_extensions;
865 struct anv_dispatch_table dispatch;
866
867 struct anv_bo_pool batch_bo_pool;
868
869 struct anv_bo_cache bo_cache;
870
871 struct anv_state_pool dynamic_state_pool;
872 struct anv_state_pool instruction_state_pool;
873 struct anv_state_pool surface_state_pool;
874
875 struct anv_bo workaround_bo;
876 struct anv_bo trivial_batch_bo;
877
878 struct anv_pipeline_cache blorp_shader_cache;
879 struct blorp_context blorp;
880
881 struct anv_state border_colors;
882
883 struct anv_queue queue;
884
885 struct anv_scratch_pool scratch_pool;
886
887 uint32_t default_mocs;
888
889 pthread_mutex_t mutex;
890 pthread_cond_t queue_submit;
891 bool lost;
892 };
893
894 static void inline
895 anv_state_flush(struct anv_device *device, struct anv_state state)
896 {
897 if (device->info.has_llc)
898 return;
899
900 gen_flush_range(state.map, state.alloc_size);
901 }
902
903 void anv_device_init_blorp(struct anv_device *device);
904 void anv_device_finish_blorp(struct anv_device *device);
905
906 VkResult anv_device_execbuf(struct anv_device *device,
907 struct drm_i915_gem_execbuffer2 *execbuf,
908 struct anv_bo **execbuf_bos);
909 VkResult anv_device_query_status(struct anv_device *device);
910 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
911 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
912 int64_t timeout);
913
914 void* anv_gem_mmap(struct anv_device *device,
915 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
916 void anv_gem_munmap(void *p, uint64_t size);
917 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
918 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
919 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
920 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
921 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
922 int anv_gem_execbuffer(struct anv_device *device,
923 struct drm_i915_gem_execbuffer2 *execbuf);
924 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
925 uint32_t stride, uint32_t tiling);
926 int anv_gem_create_context(struct anv_device *device);
927 bool anv_gem_has_context_priority(int fd);
928 int anv_gem_set_context_priority(struct anv_device *device, int priority);
929 int anv_gem_destroy_context(struct anv_device *device, int context);
930 int anv_gem_set_context_param(int fd, int context, uint32_t param,
931 uint64_t value);
932 int anv_gem_get_context_param(int fd, int context, uint32_t param,
933 uint64_t *value);
934 int anv_gem_get_param(int fd, uint32_t param);
935 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
936 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
937 int anv_gem_get_aperture(int fd, uint64_t *size);
938 bool anv_gem_supports_48b_addresses(int fd);
939 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
940 uint32_t *active, uint32_t *pending);
941 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
942 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
943 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
944 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
945 uint32_t read_domains, uint32_t write_domain);
946 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
947 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
948 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
949 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
950 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
951 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
952 uint32_t handle);
953 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
954 uint32_t handle, int fd);
955 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
956 bool anv_gem_supports_syncobj_wait(int fd);
957 int anv_gem_syncobj_wait(struct anv_device *device,
958 uint32_t *handles, uint32_t num_handles,
959 int64_t abs_timeout_ns, bool wait_all);
960
961 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
962
963 struct anv_reloc_list {
964 uint32_t num_relocs;
965 uint32_t array_length;
966 struct drm_i915_gem_relocation_entry * relocs;
967 struct anv_bo ** reloc_bos;
968 };
969
970 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
971 const VkAllocationCallbacks *alloc);
972 void anv_reloc_list_finish(struct anv_reloc_list *list,
973 const VkAllocationCallbacks *alloc);
974
975 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
976 const VkAllocationCallbacks *alloc,
977 uint32_t offset, struct anv_bo *target_bo,
978 uint32_t delta);
979
980 struct anv_batch_bo {
981 /* Link in the anv_cmd_buffer.owned_batch_bos list */
982 struct list_head link;
983
984 struct anv_bo bo;
985
986 /* Bytes actually consumed in this batch BO */
987 uint32_t length;
988
989 struct anv_reloc_list relocs;
990 };
991
992 struct anv_batch {
993 const VkAllocationCallbacks * alloc;
994
995 void * start;
996 void * end;
997 void * next;
998
999 struct anv_reloc_list * relocs;
1000
1001 /* This callback is called (with the associated user data) in the event
1002 * that the batch runs out of space.
1003 */
1004 VkResult (*extend_cb)(struct anv_batch *, void *);
1005 void * user_data;
1006
1007 /**
1008 * Current error status of the command buffer. Used to track inconsistent
1009 * or incomplete command buffer states that are the consequence of run-time
1010 * errors such as out of memory scenarios. We want to track this in the
1011 * batch because the command buffer object is not visible to some parts
1012 * of the driver.
1013 */
1014 VkResult status;
1015 };
1016
1017 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1018 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1019 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1020 void *location, struct anv_bo *bo, uint32_t offset);
1021 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1022 struct anv_batch *batch);
1023
1024 static inline VkResult
1025 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1026 {
1027 assert(error != VK_SUCCESS);
1028 if (batch->status == VK_SUCCESS)
1029 batch->status = error;
1030 return batch->status;
1031 }
1032
1033 static inline bool
1034 anv_batch_has_error(struct anv_batch *batch)
1035 {
1036 return batch->status != VK_SUCCESS;
1037 }
1038
1039 struct anv_address {
1040 struct anv_bo *bo;
1041 uint32_t offset;
1042 };
1043
1044 static inline uint64_t
1045 _anv_combine_address(struct anv_batch *batch, void *location,
1046 const struct anv_address address, uint32_t delta)
1047 {
1048 if (address.bo == NULL) {
1049 return address.offset + delta;
1050 } else {
1051 assert(batch->start <= location && location < batch->end);
1052
1053 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1054 }
1055 }
1056
1057 #define __gen_address_type struct anv_address
1058 #define __gen_user_data struct anv_batch
1059 #define __gen_combine_address _anv_combine_address
1060
1061 /* Wrapper macros needed to work around preprocessor argument issues. In
1062 * particular, arguments don't get pre-evaluated if they are concatenated.
1063 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1064 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1065 * We can work around this easily enough with these helpers.
1066 */
1067 #define __anv_cmd_length(cmd) cmd ## _length
1068 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1069 #define __anv_cmd_header(cmd) cmd ## _header
1070 #define __anv_cmd_pack(cmd) cmd ## _pack
1071 #define __anv_reg_num(reg) reg ## _num
1072
1073 #define anv_pack_struct(dst, struc, ...) do { \
1074 struct struc __template = { \
1075 __VA_ARGS__ \
1076 }; \
1077 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1078 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1079 } while (0)
1080
1081 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1082 void *__dst = anv_batch_emit_dwords(batch, n); \
1083 if (__dst) { \
1084 struct cmd __template = { \
1085 __anv_cmd_header(cmd), \
1086 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1087 __VA_ARGS__ \
1088 }; \
1089 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1090 } \
1091 __dst; \
1092 })
1093
1094 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1095 do { \
1096 uint32_t *dw; \
1097 \
1098 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1099 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1100 if (!dw) \
1101 break; \
1102 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1103 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1104 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1105 } while (0)
1106
1107 #define anv_batch_emit(batch, cmd, name) \
1108 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1109 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1110 __builtin_expect(_dst != NULL, 1); \
1111 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1112 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1113 _dst = NULL; \
1114 }))
1115
1116 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1117 .GraphicsDataTypeGFDT = 0, \
1118 .LLCCacheabilityControlLLCCC = 0, \
1119 .L3CacheabilityControlL3CC = 1, \
1120 }
1121
1122 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1123 .LLCeLLCCacheabilityControlLLCCC = 0, \
1124 .L3CacheabilityControlL3CC = 1, \
1125 }
1126
1127 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1128 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1129 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1130 .AgeforQUADLRU = 0 \
1131 }
1132
1133 /* Skylake: MOCS is now an index into an array of 62 different caching
1134 * configurations programmed by the kernel.
1135 */
1136
1137 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1138 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1139 .IndextoMOCSTables = 2 \
1140 }
1141
1142 #define GEN9_MOCS_PTE { \
1143 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1144 .IndextoMOCSTables = 1 \
1145 }
1146
1147 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1148 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1149 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1150 .IndextoMOCSTables = 2 \
1151 }
1152
1153 #define GEN10_MOCS_PTE { \
1154 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1155 .IndextoMOCSTables = 1 \
1156 }
1157
1158 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1159 #define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1160 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1161 .IndextoMOCSTables = 2 \
1162 }
1163
1164 #define GEN11_MOCS_PTE { \
1165 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1166 .IndextoMOCSTables = 1 \
1167 }
1168
1169 struct anv_device_memory {
1170 struct anv_bo * bo;
1171 struct anv_memory_type * type;
1172 VkDeviceSize map_size;
1173 void * map;
1174 };
1175
1176 /**
1177 * Header for Vertex URB Entry (VUE)
1178 */
1179 struct anv_vue_header {
1180 uint32_t Reserved;
1181 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1182 uint32_t ViewportIndex;
1183 float PointWidth;
1184 };
1185
1186 struct anv_descriptor_set_binding_layout {
1187 #ifndef NDEBUG
1188 /* The type of the descriptors in this binding */
1189 VkDescriptorType type;
1190 #endif
1191
1192 /* Number of array elements in this binding */
1193 uint16_t array_size;
1194
1195 /* Index into the flattend descriptor set */
1196 uint16_t descriptor_index;
1197
1198 /* Index into the dynamic state array for a dynamic buffer */
1199 int16_t dynamic_offset_index;
1200
1201 /* Index into the descriptor set buffer views */
1202 int16_t buffer_index;
1203
1204 struct {
1205 /* Index into the binding table for the associated surface */
1206 int16_t surface_index;
1207
1208 /* Index into the sampler table for the associated sampler */
1209 int16_t sampler_index;
1210
1211 /* Index into the image table for the associated image */
1212 int16_t image_index;
1213 } stage[MESA_SHADER_STAGES];
1214
1215 /* Immutable samplers (or NULL if no immutable samplers) */
1216 struct anv_sampler **immutable_samplers;
1217 };
1218
1219 struct anv_descriptor_set_layout {
1220 /* Descriptor set layouts can be destroyed at almost any time */
1221 uint32_t ref_cnt;
1222
1223 /* Number of bindings in this descriptor set */
1224 uint16_t binding_count;
1225
1226 /* Total size of the descriptor set with room for all array entries */
1227 uint16_t size;
1228
1229 /* Shader stages affected by this descriptor set */
1230 uint16_t shader_stages;
1231
1232 /* Number of buffers in this descriptor set */
1233 uint16_t buffer_count;
1234
1235 /* Number of dynamic offsets used by this descriptor set */
1236 uint16_t dynamic_offset_count;
1237
1238 /* Bindings in this descriptor set */
1239 struct anv_descriptor_set_binding_layout binding[0];
1240 };
1241
1242 static inline void
1243 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
1244 {
1245 assert(layout && layout->ref_cnt >= 1);
1246 p_atomic_inc(&layout->ref_cnt);
1247 }
1248
1249 static inline void
1250 anv_descriptor_set_layout_unref(struct anv_device *device,
1251 struct anv_descriptor_set_layout *layout)
1252 {
1253 assert(layout && layout->ref_cnt >= 1);
1254 if (p_atomic_dec_zero(&layout->ref_cnt))
1255 vk_free(&device->alloc, layout);
1256 }
1257
1258 struct anv_descriptor {
1259 VkDescriptorType type;
1260
1261 union {
1262 struct {
1263 VkImageLayout layout;
1264 struct anv_image_view *image_view;
1265 struct anv_sampler *sampler;
1266 };
1267
1268 struct {
1269 struct anv_buffer *buffer;
1270 uint64_t offset;
1271 uint64_t range;
1272 };
1273
1274 struct anv_buffer_view *buffer_view;
1275 };
1276 };
1277
1278 struct anv_descriptor_set {
1279 struct anv_descriptor_set_layout *layout;
1280 uint32_t size;
1281 uint32_t buffer_count;
1282 struct anv_buffer_view *buffer_views;
1283 struct anv_descriptor descriptors[0];
1284 };
1285
1286 struct anv_buffer_view {
1287 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1288 struct anv_bo *bo;
1289 uint32_t offset; /**< Offset into bo. */
1290 uint64_t range; /**< VkBufferViewCreateInfo::range */
1291
1292 struct anv_state surface_state;
1293 struct anv_state storage_surface_state;
1294 struct anv_state writeonly_storage_surface_state;
1295
1296 struct brw_image_param storage_image_param;
1297 };
1298
1299 struct anv_push_descriptor_set {
1300 struct anv_descriptor_set set;
1301
1302 /* Put this field right behind anv_descriptor_set so it fills up the
1303 * descriptors[0] field. */
1304 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1305 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1306 };
1307
1308 struct anv_descriptor_pool {
1309 uint32_t size;
1310 uint32_t next;
1311 uint32_t free_list;
1312
1313 struct anv_state_stream surface_state_stream;
1314 void *surface_state_free_list;
1315
1316 char data[0];
1317 };
1318
1319 enum anv_descriptor_template_entry_type {
1320 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1321 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1322 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1323 };
1324
1325 struct anv_descriptor_template_entry {
1326 /* The type of descriptor in this entry */
1327 VkDescriptorType type;
1328
1329 /* Binding in the descriptor set */
1330 uint32_t binding;
1331
1332 /* Offset at which to write into the descriptor set binding */
1333 uint32_t array_element;
1334
1335 /* Number of elements to write into the descriptor set binding */
1336 uint32_t array_count;
1337
1338 /* Offset into the user provided data */
1339 size_t offset;
1340
1341 /* Stride between elements into the user provided data */
1342 size_t stride;
1343 };
1344
1345 struct anv_descriptor_update_template {
1346 VkPipelineBindPoint bind_point;
1347
1348 /* The descriptor set this template corresponds to. This value is only
1349 * valid if the template was created with the templateType
1350 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1351 */
1352 uint8_t set;
1353
1354 /* Number of entries in this template */
1355 uint32_t entry_count;
1356
1357 /* Entries of the template */
1358 struct anv_descriptor_template_entry entries[0];
1359 };
1360
1361 size_t
1362 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1363
1364 size_t
1365 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1366
1367 void
1368 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1369 const struct gen_device_info * const devinfo,
1370 const VkDescriptorImageInfo * const info,
1371 VkDescriptorType type,
1372 uint32_t binding,
1373 uint32_t element);
1374
1375 void
1376 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1377 VkDescriptorType type,
1378 struct anv_buffer_view *buffer_view,
1379 uint32_t binding,
1380 uint32_t element);
1381
1382 void
1383 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1384 struct anv_device *device,
1385 struct anv_state_stream *alloc_stream,
1386 VkDescriptorType type,
1387 struct anv_buffer *buffer,
1388 uint32_t binding,
1389 uint32_t element,
1390 VkDeviceSize offset,
1391 VkDeviceSize range);
1392
1393 void
1394 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1395 struct anv_device *device,
1396 struct anv_state_stream *alloc_stream,
1397 const struct anv_descriptor_update_template *template,
1398 const void *data);
1399
1400 VkResult
1401 anv_descriptor_set_create(struct anv_device *device,
1402 struct anv_descriptor_pool *pool,
1403 struct anv_descriptor_set_layout *layout,
1404 struct anv_descriptor_set **out_set);
1405
1406 void
1407 anv_descriptor_set_destroy(struct anv_device *device,
1408 struct anv_descriptor_pool *pool,
1409 struct anv_descriptor_set *set);
1410
1411 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1412
1413 struct anv_pipeline_binding {
1414 /* The descriptor set this surface corresponds to. The special value of
1415 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1416 * to a color attachment and not a regular descriptor.
1417 */
1418 uint8_t set;
1419
1420 /* Binding in the descriptor set */
1421 uint32_t binding;
1422
1423 /* Index in the binding */
1424 uint32_t index;
1425
1426 /* Plane in the binding index */
1427 uint8_t plane;
1428
1429 /* Input attachment index (relative to the subpass) */
1430 uint8_t input_attachment_index;
1431
1432 /* For a storage image, whether it is write-only */
1433 bool write_only;
1434 };
1435
1436 struct anv_pipeline_layout {
1437 struct {
1438 struct anv_descriptor_set_layout *layout;
1439 uint32_t dynamic_offset_start;
1440 } set[MAX_SETS];
1441
1442 uint32_t num_sets;
1443
1444 struct {
1445 bool has_dynamic_offsets;
1446 } stage[MESA_SHADER_STAGES];
1447
1448 unsigned char sha1[20];
1449 };
1450
1451 struct anv_buffer {
1452 struct anv_device * device;
1453 VkDeviceSize size;
1454
1455 VkBufferUsageFlags usage;
1456
1457 /* Set when bound */
1458 struct anv_bo * bo;
1459 VkDeviceSize offset;
1460 };
1461
1462 static inline uint64_t
1463 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1464 {
1465 assert(offset <= buffer->size);
1466 if (range == VK_WHOLE_SIZE) {
1467 return buffer->size - offset;
1468 } else {
1469 assert(range <= buffer->size);
1470 return range;
1471 }
1472 }
1473
1474 enum anv_cmd_dirty_bits {
1475 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1476 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1477 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1478 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1479 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1480 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1481 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1482 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1483 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1484 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1485 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1486 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1487 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1488 };
1489 typedef uint32_t anv_cmd_dirty_mask_t;
1490
1491 enum anv_pipe_bits {
1492 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1493 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1494 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1495 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1496 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1497 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1498 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1499 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1500 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1501 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1502 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1503
1504 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1505 * a flush has happened but not a CS stall. The next time we do any sort
1506 * of invalidation we need to insert a CS stall at that time. Otherwise,
1507 * we would have to CS stall on every flush which could be bad.
1508 */
1509 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1510 };
1511
1512 #define ANV_PIPE_FLUSH_BITS ( \
1513 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1514 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1515 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1516
1517 #define ANV_PIPE_STALL_BITS ( \
1518 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1519 ANV_PIPE_DEPTH_STALL_BIT | \
1520 ANV_PIPE_CS_STALL_BIT)
1521
1522 #define ANV_PIPE_INVALIDATE_BITS ( \
1523 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1524 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1525 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1526 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1527 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1528 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1529
1530 static inline enum anv_pipe_bits
1531 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1532 {
1533 enum anv_pipe_bits pipe_bits = 0;
1534
1535 unsigned b;
1536 for_each_bit(b, flags) {
1537 switch ((VkAccessFlagBits)(1 << b)) {
1538 case VK_ACCESS_SHADER_WRITE_BIT:
1539 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1540 break;
1541 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1542 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1543 break;
1544 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1545 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1546 break;
1547 case VK_ACCESS_TRANSFER_WRITE_BIT:
1548 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1549 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1550 break;
1551 default:
1552 break; /* Nothing to do */
1553 }
1554 }
1555
1556 return pipe_bits;
1557 }
1558
1559 static inline enum anv_pipe_bits
1560 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1561 {
1562 enum anv_pipe_bits pipe_bits = 0;
1563
1564 unsigned b;
1565 for_each_bit(b, flags) {
1566 switch ((VkAccessFlagBits)(1 << b)) {
1567 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1568 case VK_ACCESS_INDEX_READ_BIT:
1569 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1570 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1571 break;
1572 case VK_ACCESS_UNIFORM_READ_BIT:
1573 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1574 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1575 break;
1576 case VK_ACCESS_SHADER_READ_BIT:
1577 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1578 case VK_ACCESS_TRANSFER_READ_BIT:
1579 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1580 break;
1581 default:
1582 break; /* Nothing to do */
1583 }
1584 }
1585
1586 return pipe_bits;
1587 }
1588
1589 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1590 VK_IMAGE_ASPECT_COLOR_BIT | \
1591 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1592 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1593 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1594 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1595 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1596 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1597 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1598
1599 struct anv_vertex_binding {
1600 struct anv_buffer * buffer;
1601 VkDeviceSize offset;
1602 };
1603
1604 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1605 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1606
1607 struct anv_push_constants {
1608 /* Current allocated size of this push constants data structure.
1609 * Because a decent chunk of it may not be used (images on SKL, for
1610 * instance), we won't actually allocate the entire structure up-front.
1611 */
1612 uint32_t size;
1613
1614 /* Push constant data provided by the client through vkPushConstants */
1615 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1616
1617 /* Image data for image_load_store on pre-SKL */
1618 struct brw_image_param images[MAX_IMAGES];
1619 };
1620
1621 struct anv_dynamic_state {
1622 struct {
1623 uint32_t count;
1624 VkViewport viewports[MAX_VIEWPORTS];
1625 } viewport;
1626
1627 struct {
1628 uint32_t count;
1629 VkRect2D scissors[MAX_SCISSORS];
1630 } scissor;
1631
1632 float line_width;
1633
1634 struct {
1635 float bias;
1636 float clamp;
1637 float slope;
1638 } depth_bias;
1639
1640 float blend_constants[4];
1641
1642 struct {
1643 float min;
1644 float max;
1645 } depth_bounds;
1646
1647 struct {
1648 uint32_t front;
1649 uint32_t back;
1650 } stencil_compare_mask;
1651
1652 struct {
1653 uint32_t front;
1654 uint32_t back;
1655 } stencil_write_mask;
1656
1657 struct {
1658 uint32_t front;
1659 uint32_t back;
1660 } stencil_reference;
1661 };
1662
1663 extern const struct anv_dynamic_state default_dynamic_state;
1664
1665 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1666 const struct anv_dynamic_state *src,
1667 uint32_t copy_mask);
1668
1669 struct anv_surface_state {
1670 struct anv_state state;
1671 /** Address of the surface referred to by this state
1672 *
1673 * This address is relative to the start of the BO.
1674 */
1675 uint64_t address;
1676 /* Address of the aux surface, if any
1677 *
1678 * This field is 0 if and only if no aux surface exists.
1679 *
1680 * This address is relative to the start of the BO. On gen7, the bottom 12
1681 * bits of this address include extra aux information.
1682 */
1683 uint64_t aux_address;
1684 };
1685
1686 /**
1687 * Attachment state when recording a renderpass instance.
1688 *
1689 * The clear value is valid only if there exists a pending clear.
1690 */
1691 struct anv_attachment_state {
1692 enum isl_aux_usage aux_usage;
1693 enum isl_aux_usage input_aux_usage;
1694 struct anv_surface_state color;
1695 struct anv_surface_state input;
1696
1697 VkImageLayout current_layout;
1698 VkImageAspectFlags pending_clear_aspects;
1699 VkImageAspectFlags pending_load_aspects;
1700 bool fast_clear;
1701 VkClearValue clear_value;
1702 bool clear_color_is_zero_one;
1703 bool clear_color_is_zero;
1704 };
1705
1706 /** State tracking for particular pipeline bind point
1707 *
1708 * This struct is the base struct for anv_cmd_graphics_state and
1709 * anv_cmd_compute_state. These are used to track state which is bound to a
1710 * particular type of pipeline. Generic state that applies per-stage such as
1711 * binding table offsets and push constants is tracked generically with a
1712 * per-stage array in anv_cmd_state.
1713 */
1714 struct anv_cmd_pipeline_state {
1715 struct anv_pipeline *pipeline;
1716 struct anv_pipeline_layout *layout;
1717
1718 struct anv_descriptor_set *descriptors[MAX_SETS];
1719 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1720
1721 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
1722 };
1723
1724 /** State tracking for graphics pipeline
1725 *
1726 * This has anv_cmd_pipeline_state as a base struct to track things which get
1727 * bound to a graphics pipeline. Along with general pipeline bind point state
1728 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1729 * state which is graphics-specific.
1730 */
1731 struct anv_cmd_graphics_state {
1732 struct anv_cmd_pipeline_state base;
1733
1734 anv_cmd_dirty_mask_t dirty;
1735 uint32_t vb_dirty;
1736
1737 struct anv_dynamic_state dynamic;
1738
1739 struct {
1740 struct anv_buffer *index_buffer;
1741 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1742 uint32_t index_offset;
1743 } gen7;
1744 };
1745
1746 /** State tracking for compute pipeline
1747 *
1748 * This has anv_cmd_pipeline_state as a base struct to track things which get
1749 * bound to a compute pipeline. Along with general pipeline bind point state
1750 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1751 * state which is compute-specific.
1752 */
1753 struct anv_cmd_compute_state {
1754 struct anv_cmd_pipeline_state base;
1755
1756 bool pipeline_dirty;
1757
1758 struct anv_address num_workgroups;
1759 };
1760
1761 /** State required while building cmd buffer */
1762 struct anv_cmd_state {
1763 /* PIPELINE_SELECT.PipelineSelection */
1764 uint32_t current_pipeline;
1765 const struct gen_l3_config * current_l3_config;
1766
1767 struct anv_cmd_graphics_state gfx;
1768 struct anv_cmd_compute_state compute;
1769
1770 enum anv_pipe_bits pending_pipe_bits;
1771 VkShaderStageFlags descriptors_dirty;
1772 VkShaderStageFlags push_constants_dirty;
1773
1774 struct anv_framebuffer * framebuffer;
1775 struct anv_render_pass * pass;
1776 struct anv_subpass * subpass;
1777 VkRect2D render_area;
1778 uint32_t restart_index;
1779 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1780 VkShaderStageFlags push_constant_stages;
1781 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1782 struct anv_state binding_tables[MESA_SHADER_STAGES];
1783 struct anv_state samplers[MESA_SHADER_STAGES];
1784
1785 /**
1786 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1787 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1788 * and before invoking the secondary in ExecuteCommands.
1789 */
1790 bool pma_fix_enabled;
1791
1792 /**
1793 * Whether or not we know for certain that HiZ is enabled for the current
1794 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1795 * enabled or not, this will be false.
1796 */
1797 bool hiz_enabled;
1798
1799 /**
1800 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1801 * valid only when recording a render pass instance.
1802 */
1803 struct anv_attachment_state * attachments;
1804
1805 /**
1806 * Surface states for color render targets. These are stored in a single
1807 * flat array. For depth-stencil attachments, the surface state is simply
1808 * left blank.
1809 */
1810 struct anv_state render_pass_states;
1811
1812 /**
1813 * A null surface state of the right size to match the framebuffer. This
1814 * is one of the states in render_pass_states.
1815 */
1816 struct anv_state null_surface_state;
1817 };
1818
1819 struct anv_cmd_pool {
1820 VkAllocationCallbacks alloc;
1821 struct list_head cmd_buffers;
1822 };
1823
1824 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1825
1826 enum anv_cmd_buffer_exec_mode {
1827 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1828 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1829 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1830 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1831 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1832 };
1833
1834 struct anv_cmd_buffer {
1835 VK_LOADER_DATA _loader_data;
1836
1837 struct anv_device * device;
1838
1839 struct anv_cmd_pool * pool;
1840 struct list_head pool_link;
1841
1842 struct anv_batch batch;
1843
1844 /* Fields required for the actual chain of anv_batch_bo's.
1845 *
1846 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1847 */
1848 struct list_head batch_bos;
1849 enum anv_cmd_buffer_exec_mode exec_mode;
1850
1851 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1852 * referenced by this command buffer
1853 *
1854 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1855 */
1856 struct u_vector seen_bbos;
1857
1858 /* A vector of int32_t's for every block of binding tables.
1859 *
1860 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1861 */
1862 struct u_vector bt_block_states;
1863 uint32_t bt_next;
1864
1865 struct anv_reloc_list surface_relocs;
1866 /** Last seen surface state block pool center bo offset */
1867 uint32_t last_ss_pool_center;
1868
1869 /* Serial for tracking buffer completion */
1870 uint32_t serial;
1871
1872 /* Stream objects for storing temporary data */
1873 struct anv_state_stream surface_state_stream;
1874 struct anv_state_stream dynamic_state_stream;
1875
1876 VkCommandBufferUsageFlags usage_flags;
1877 VkCommandBufferLevel level;
1878
1879 struct anv_cmd_state state;
1880 };
1881
1882 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1883 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1884 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1885 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1886 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1887 struct anv_cmd_buffer *secondary);
1888 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1889 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1890 struct anv_cmd_buffer *cmd_buffer,
1891 const VkSemaphore *in_semaphores,
1892 uint32_t num_in_semaphores,
1893 const VkSemaphore *out_semaphores,
1894 uint32_t num_out_semaphores,
1895 VkFence fence);
1896
1897 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1898
1899 VkResult
1900 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1901 gl_shader_stage stage, uint32_t size);
1902 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1903 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1904 (offsetof(struct anv_push_constants, field) + \
1905 sizeof(cmd_buffer->state.push_constants[0]->field)))
1906
1907 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1908 const void *data, uint32_t size, uint32_t alignment);
1909 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1910 uint32_t *a, uint32_t *b,
1911 uint32_t dwords, uint32_t alignment);
1912
1913 struct anv_address
1914 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1915 struct anv_state
1916 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1917 uint32_t entries, uint32_t *state_offset);
1918 struct anv_state
1919 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1920 struct anv_state
1921 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1922 uint32_t size, uint32_t alignment);
1923
1924 VkResult
1925 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1926
1927 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1928 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1929 bool depth_clamp_enable);
1930 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1931
1932 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1933 struct anv_render_pass *pass,
1934 struct anv_framebuffer *framebuffer,
1935 const VkClearValue *clear_values);
1936
1937 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1938
1939 struct anv_state
1940 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1941 gl_shader_stage stage);
1942 struct anv_state
1943 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1944
1945 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1946
1947 const struct anv_image_view *
1948 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1949
1950 VkResult
1951 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1952 uint32_t num_entries,
1953 uint32_t *state_offset,
1954 struct anv_state *bt_state);
1955
1956 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1957
1958 enum anv_fence_type {
1959 ANV_FENCE_TYPE_NONE = 0,
1960 ANV_FENCE_TYPE_BO,
1961 ANV_FENCE_TYPE_SYNCOBJ,
1962 };
1963
1964 enum anv_bo_fence_state {
1965 /** Indicates that this is a new (or newly reset fence) */
1966 ANV_BO_FENCE_STATE_RESET,
1967
1968 /** Indicates that this fence has been submitted to the GPU but is still
1969 * (as far as we know) in use by the GPU.
1970 */
1971 ANV_BO_FENCE_STATE_SUBMITTED,
1972
1973 ANV_BO_FENCE_STATE_SIGNALED,
1974 };
1975
1976 struct anv_fence_impl {
1977 enum anv_fence_type type;
1978
1979 union {
1980 /** Fence implementation for BO fences
1981 *
1982 * These fences use a BO and a set of CPU-tracked state flags. The BO
1983 * is added to the object list of the last execbuf call in a QueueSubmit
1984 * and is marked EXEC_WRITE. The state flags track when the BO has been
1985 * submitted to the kernel. We need to do this because Vulkan lets you
1986 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1987 * will say it's idle in this case.
1988 */
1989 struct {
1990 struct anv_bo bo;
1991 enum anv_bo_fence_state state;
1992 } bo;
1993
1994 /** DRM syncobj handle for syncobj-based fences */
1995 uint32_t syncobj;
1996 };
1997 };
1998
1999 struct anv_fence {
2000 /* Permanent fence state. Every fence has some form of permanent state
2001 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2002 * cross-process fences) or it could just be a dummy for use internally.
2003 */
2004 struct anv_fence_impl permanent;
2005
2006 /* Temporary fence state. A fence *may* have temporary state. That state
2007 * is added to the fence by an import operation and is reset back to
2008 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2009 * state cannot be signaled because the fence must already be signaled
2010 * before the temporary state can be exported from the fence in the other
2011 * process and imported here.
2012 */
2013 struct anv_fence_impl temporary;
2014 };
2015
2016 struct anv_event {
2017 uint64_t semaphore;
2018 struct anv_state state;
2019 };
2020
2021 enum anv_semaphore_type {
2022 ANV_SEMAPHORE_TYPE_NONE = 0,
2023 ANV_SEMAPHORE_TYPE_DUMMY,
2024 ANV_SEMAPHORE_TYPE_BO,
2025 ANV_SEMAPHORE_TYPE_SYNC_FILE,
2026 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
2027 };
2028
2029 struct anv_semaphore_impl {
2030 enum anv_semaphore_type type;
2031
2032 union {
2033 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2034 * This BO will be added to the object list on any execbuf2 calls for
2035 * which this semaphore is used as a wait or signal fence. When used as
2036 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2037 */
2038 struct anv_bo *bo;
2039
2040 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2041 * If the semaphore is in the unsignaled state due to either just being
2042 * created or because it has been used for a wait, fd will be -1.
2043 */
2044 int fd;
2045
2046 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2047 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2048 * import so we don't need to bother with a userspace cache.
2049 */
2050 uint32_t syncobj;
2051 };
2052 };
2053
2054 struct anv_semaphore {
2055 /* Permanent semaphore state. Every semaphore has some form of permanent
2056 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2057 * (for cross-process semaphores0 or it could just be a dummy for use
2058 * internally.
2059 */
2060 struct anv_semaphore_impl permanent;
2061
2062 /* Temporary semaphore state. A semaphore *may* have temporary state.
2063 * That state is added to the semaphore by an import operation and is reset
2064 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2065 * semaphore with temporary state cannot be signaled because the semaphore
2066 * must already be signaled before the temporary state can be exported from
2067 * the semaphore in the other process and imported here.
2068 */
2069 struct anv_semaphore_impl temporary;
2070 };
2071
2072 void anv_semaphore_reset_temporary(struct anv_device *device,
2073 struct anv_semaphore *semaphore);
2074
2075 struct anv_shader_module {
2076 unsigned char sha1[20];
2077 uint32_t size;
2078 char data[0];
2079 };
2080
2081 static inline gl_shader_stage
2082 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2083 {
2084 assert(__builtin_popcount(vk_stage) == 1);
2085 return ffs(vk_stage) - 1;
2086 }
2087
2088 static inline VkShaderStageFlagBits
2089 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2090 {
2091 return (1 << mesa_stage);
2092 }
2093
2094 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2095
2096 #define anv_foreach_stage(stage, stage_bits) \
2097 for (gl_shader_stage stage, \
2098 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2099 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2100 __tmp &= ~(1 << (stage)))
2101
2102 struct anv_pipeline_bind_map {
2103 uint32_t surface_count;
2104 uint32_t sampler_count;
2105 uint32_t image_count;
2106
2107 struct anv_pipeline_binding * surface_to_descriptor;
2108 struct anv_pipeline_binding * sampler_to_descriptor;
2109 };
2110
2111 struct anv_shader_bin_key {
2112 uint32_t size;
2113 uint8_t data[0];
2114 };
2115
2116 struct anv_shader_bin {
2117 uint32_t ref_cnt;
2118
2119 const struct anv_shader_bin_key *key;
2120
2121 struct anv_state kernel;
2122 uint32_t kernel_size;
2123
2124 const struct brw_stage_prog_data *prog_data;
2125 uint32_t prog_data_size;
2126
2127 struct anv_pipeline_bind_map bind_map;
2128 };
2129
2130 struct anv_shader_bin *
2131 anv_shader_bin_create(struct anv_device *device,
2132 const void *key, uint32_t key_size,
2133 const void *kernel, uint32_t kernel_size,
2134 const struct brw_stage_prog_data *prog_data,
2135 uint32_t prog_data_size, const void *prog_data_param,
2136 const struct anv_pipeline_bind_map *bind_map);
2137
2138 void
2139 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2140
2141 static inline void
2142 anv_shader_bin_ref(struct anv_shader_bin *shader)
2143 {
2144 assert(shader && shader->ref_cnt >= 1);
2145 p_atomic_inc(&shader->ref_cnt);
2146 }
2147
2148 static inline void
2149 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2150 {
2151 assert(shader && shader->ref_cnt >= 1);
2152 if (p_atomic_dec_zero(&shader->ref_cnt))
2153 anv_shader_bin_destroy(device, shader);
2154 }
2155
2156 struct anv_pipeline {
2157 struct anv_device * device;
2158 struct anv_batch batch;
2159 uint32_t batch_data[512];
2160 struct anv_reloc_list batch_relocs;
2161 uint32_t dynamic_state_mask;
2162 struct anv_dynamic_state dynamic_state;
2163
2164 struct anv_subpass * subpass;
2165
2166 bool needs_data_cache;
2167
2168 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2169
2170 struct {
2171 const struct gen_l3_config * l3_config;
2172 uint32_t total_size;
2173 } urb;
2174
2175 VkShaderStageFlags active_stages;
2176 struct anv_state blend_state;
2177
2178 uint32_t vb_used;
2179 uint32_t binding_stride[MAX_VBS];
2180 bool instancing_enable[MAX_VBS];
2181 bool primitive_restart;
2182 uint32_t topology;
2183
2184 uint32_t cs_right_mask;
2185
2186 bool writes_depth;
2187 bool depth_test_enable;
2188 bool writes_stencil;
2189 bool stencil_test_enable;
2190 bool depth_clamp_enable;
2191 bool sample_shading_enable;
2192 bool kill_pixel;
2193
2194 struct {
2195 uint32_t sf[7];
2196 uint32_t depth_stencil_state[3];
2197 } gen7;
2198
2199 struct {
2200 uint32_t sf[4];
2201 uint32_t raster[5];
2202 uint32_t wm_depth_stencil[3];
2203 } gen8;
2204
2205 struct {
2206 uint32_t wm_depth_stencil[4];
2207 } gen9;
2208
2209 uint32_t interface_descriptor_data[8];
2210 };
2211
2212 static inline bool
2213 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2214 gl_shader_stage stage)
2215 {
2216 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2217 }
2218
2219 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2220 static inline const struct brw_##prefix##_prog_data * \
2221 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2222 { \
2223 if (anv_pipeline_has_stage(pipeline, stage)) { \
2224 return (const struct brw_##prefix##_prog_data *) \
2225 pipeline->shaders[stage]->prog_data; \
2226 } else { \
2227 return NULL; \
2228 } \
2229 }
2230
2231 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2232 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2233 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2234 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2235 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2236 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2237
2238 static inline const struct brw_vue_prog_data *
2239 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2240 {
2241 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2242 return &get_gs_prog_data(pipeline)->base;
2243 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2244 return &get_tes_prog_data(pipeline)->base;
2245 else
2246 return &get_vs_prog_data(pipeline)->base;
2247 }
2248
2249 VkResult
2250 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2251 struct anv_pipeline_cache *cache,
2252 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2253 const VkAllocationCallbacks *alloc);
2254
2255 VkResult
2256 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2257 struct anv_pipeline_cache *cache,
2258 const VkComputePipelineCreateInfo *info,
2259 struct anv_shader_module *module,
2260 const char *entrypoint,
2261 const VkSpecializationInfo *spec_info);
2262
2263 struct anv_format_plane {
2264 enum isl_format isl_format:16;
2265 struct isl_swizzle swizzle;
2266
2267 /* Whether this plane contains chroma channels */
2268 bool has_chroma;
2269
2270 /* For downscaling of YUV planes */
2271 uint8_t denominator_scales[2];
2272
2273 /* How to map sampled ycbcr planes to a single 4 component element. */
2274 struct isl_swizzle ycbcr_swizzle;
2275 };
2276
2277
2278 struct anv_format {
2279 struct anv_format_plane planes[3];
2280 uint8_t n_planes;
2281 bool can_ycbcr;
2282 };
2283
2284 static inline uint32_t
2285 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2286 VkImageAspectFlags aspect_mask)
2287 {
2288 switch (aspect_mask) {
2289 case VK_IMAGE_ASPECT_COLOR_BIT:
2290 case VK_IMAGE_ASPECT_DEPTH_BIT:
2291 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
2292 return 0;
2293 case VK_IMAGE_ASPECT_STENCIL_BIT:
2294 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2295 return 0;
2296 /* Fall-through */
2297 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
2298 return 1;
2299 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
2300 return 2;
2301 default:
2302 /* Purposefully assert with depth/stencil aspects. */
2303 unreachable("invalid image aspect");
2304 }
2305 }
2306
2307 static inline uint32_t
2308 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2309 {
2310 uint32_t planes = 0;
2311
2312 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2313 VK_IMAGE_ASPECT_DEPTH_BIT |
2314 VK_IMAGE_ASPECT_STENCIL_BIT |
2315 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR))
2316 planes++;
2317 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT_KHR)
2318 planes++;
2319 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
2320 planes++;
2321
2322 return planes;
2323 }
2324
2325 static inline VkImageAspectFlags
2326 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2327 uint32_t plane)
2328 {
2329 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2330 if (_mesa_bitcount(image_aspects) > 1)
2331 return VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << plane;
2332 return VK_IMAGE_ASPECT_COLOR_BIT;
2333 }
2334 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2335 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2336 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2337 return VK_IMAGE_ASPECT_STENCIL_BIT;
2338 }
2339
2340 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2341 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2342
2343 const struct anv_format *
2344 anv_get_format(VkFormat format);
2345
2346 static inline uint32_t
2347 anv_get_format_planes(VkFormat vk_format)
2348 {
2349 const struct anv_format *format = anv_get_format(vk_format);
2350
2351 return format != NULL ? format->n_planes : 0;
2352 }
2353
2354 struct anv_format_plane
2355 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2356 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2357
2358 static inline enum isl_format
2359 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2360 VkImageAspectFlags aspect, VkImageTiling tiling)
2361 {
2362 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2363 }
2364
2365 static inline struct isl_swizzle
2366 anv_swizzle_for_render(struct isl_swizzle swizzle)
2367 {
2368 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2369 * RGB as RGBA for texturing
2370 */
2371 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2372 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2373
2374 /* But it doesn't matter what we render to that channel */
2375 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2376
2377 return swizzle;
2378 }
2379
2380 void
2381 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2382
2383 /**
2384 * Subsurface of an anv_image.
2385 */
2386 struct anv_surface {
2387 /** Valid only if isl_surf::size > 0. */
2388 struct isl_surf isl;
2389
2390 /**
2391 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2392 */
2393 uint32_t offset;
2394 };
2395
2396 struct anv_image {
2397 VkImageType type;
2398 /* The original VkFormat provided by the client. This may not match any
2399 * of the actual surface formats.
2400 */
2401 VkFormat vk_format;
2402 const struct anv_format *format;
2403
2404 VkImageAspectFlags aspects;
2405 VkExtent3D extent;
2406 uint32_t levels;
2407 uint32_t array_size;
2408 uint32_t samples; /**< VkImageCreateInfo::samples */
2409 uint32_t n_planes;
2410 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2411 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2412
2413 /** True if this is needs to be bound to an appropriately tiled BO.
2414 *
2415 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2416 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2417 * we require a dedicated allocation so that we can know to allocate a
2418 * tiled buffer.
2419 */
2420 bool needs_set_tiling;
2421
2422 /**
2423 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2424 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2425 */
2426 uint64_t drm_format_mod;
2427
2428 VkDeviceSize size;
2429 uint32_t alignment;
2430
2431 /* Whether the image is made of several underlying buffer objects rather a
2432 * single one with different offsets.
2433 */
2434 bool disjoint;
2435
2436 /**
2437 * Image subsurfaces
2438 *
2439 * For each foo, anv_image::planes[x].surface is valid if and only if
2440 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2441 * to figure the number associated with a given aspect.
2442 *
2443 * The hardware requires that the depth buffer and stencil buffer be
2444 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2445 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2446 * allocate the depth and stencil buffers as separate surfaces in the same
2447 * bo.
2448 *
2449 * Memory layout :
2450 *
2451 * -----------------------
2452 * | surface0 | /|\
2453 * ----------------------- |
2454 * | shadow surface0 | |
2455 * ----------------------- | Plane 0
2456 * | aux surface0 | |
2457 * ----------------------- |
2458 * | fast clear colors0 | \|/
2459 * -----------------------
2460 * | surface1 | /|\
2461 * ----------------------- |
2462 * | shadow surface1 | |
2463 * ----------------------- | Plane 1
2464 * | aux surface1 | |
2465 * ----------------------- |
2466 * | fast clear colors1 | \|/
2467 * -----------------------
2468 * | ... |
2469 * | |
2470 * -----------------------
2471 */
2472 struct {
2473 /**
2474 * Offset of the entire plane (whenever the image is disjoint this is
2475 * set to 0).
2476 */
2477 uint32_t offset;
2478
2479 VkDeviceSize size;
2480 uint32_t alignment;
2481
2482 struct anv_surface surface;
2483
2484 /**
2485 * A surface which shadows the main surface and may have different
2486 * tiling. This is used for sampling using a tiling that isn't supported
2487 * for other operations.
2488 */
2489 struct anv_surface shadow_surface;
2490
2491 /**
2492 * For color images, this is the aux usage for this image when not used
2493 * as a color attachment.
2494 *
2495 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2496 * image has a HiZ buffer.
2497 */
2498 enum isl_aux_usage aux_usage;
2499
2500 struct anv_surface aux_surface;
2501
2502 /**
2503 * Offset of the fast clear state (used to compute the
2504 * fast_clear_state_offset of the following planes).
2505 */
2506 uint32_t fast_clear_state_offset;
2507
2508 /**
2509 * BO associated with this plane, set when bound.
2510 */
2511 struct anv_bo *bo;
2512 VkDeviceSize bo_offset;
2513
2514 /**
2515 * When destroying the image, also free the bo.
2516 * */
2517 bool bo_is_owned;
2518 } planes[3];
2519 };
2520
2521 /* The ordering of this enum is important */
2522 enum anv_fast_clear_type {
2523 /** Image does not have/support any fast-clear blocks */
2524 ANV_FAST_CLEAR_NONE = 0,
2525 /** Image has/supports fast-clear but only to the default value */
2526 ANV_FAST_CLEAR_DEFAULT_VALUE = 1,
2527 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2528 ANV_FAST_CLEAR_ANY = 2,
2529 };
2530
2531 /* Returns the number of auxiliary buffer levels attached to an image. */
2532 static inline uint8_t
2533 anv_image_aux_levels(const struct anv_image * const image,
2534 VkImageAspectFlagBits aspect)
2535 {
2536 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2537 return image->planes[plane].aux_surface.isl.size > 0 ?
2538 image->planes[plane].aux_surface.isl.levels : 0;
2539 }
2540
2541 /* Returns the number of auxiliary buffer layers attached to an image. */
2542 static inline uint32_t
2543 anv_image_aux_layers(const struct anv_image * const image,
2544 VkImageAspectFlagBits aspect,
2545 const uint8_t miplevel)
2546 {
2547 assert(image);
2548
2549 /* The miplevel must exist in the main buffer. */
2550 assert(miplevel < image->levels);
2551
2552 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2553 /* There are no layers with auxiliary data because the miplevel has no
2554 * auxiliary data.
2555 */
2556 return 0;
2557 } else {
2558 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2559 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2560 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2561 }
2562 }
2563
2564 static inline struct anv_address
2565 anv_image_get_clear_color_addr(const struct anv_device *device,
2566 const struct anv_image *image,
2567 VkImageAspectFlagBits aspect)
2568 {
2569 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
2570
2571 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2572 return (struct anv_address) {
2573 .bo = image->planes[plane].bo,
2574 .offset = image->planes[plane].bo_offset +
2575 image->planes[plane].fast_clear_state_offset,
2576 };
2577 }
2578
2579 static inline struct anv_address
2580 anv_image_get_fast_clear_type_addr(const struct anv_device *device,
2581 const struct anv_image *image,
2582 VkImageAspectFlagBits aspect)
2583 {
2584 struct anv_address addr =
2585 anv_image_get_clear_color_addr(device, image, aspect);
2586 addr.offset += device->isl_dev.ss.clear_value_size;
2587 return addr;
2588 }
2589
2590 static inline struct anv_address
2591 anv_image_get_compression_state_addr(const struct anv_device *device,
2592 const struct anv_image *image,
2593 VkImageAspectFlagBits aspect,
2594 uint32_t level, uint32_t array_layer)
2595 {
2596 assert(level < anv_image_aux_levels(image, aspect));
2597 assert(array_layer < anv_image_aux_layers(image, aspect, level));
2598 UNUSED uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2599 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E);
2600
2601 struct anv_address addr =
2602 anv_image_get_fast_clear_type_addr(device, image, aspect);
2603 addr.offset += 4; /* Go past the fast clear type */
2604
2605 if (image->type == VK_IMAGE_TYPE_3D) {
2606 for (uint32_t l = 0; l < level; l++)
2607 addr.offset += anv_minify(image->extent.depth, l) * 4;
2608 } else {
2609 addr.offset += level * image->array_size * 4;
2610 }
2611 addr.offset += array_layer * 4;
2612
2613 return addr;
2614 }
2615
2616 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2617 static inline bool
2618 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2619 const struct anv_image *image)
2620 {
2621 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2622 return false;
2623
2624 if (devinfo->gen < 8)
2625 return false;
2626
2627 return image->samples == 1;
2628 }
2629
2630 void
2631 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
2632 const struct anv_image *image,
2633 VkImageAspectFlagBits aspect,
2634 enum isl_aux_usage aux_usage,
2635 uint32_t level,
2636 uint32_t base_layer,
2637 uint32_t layer_count);
2638
2639 void
2640 anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
2641 const struct anv_image *image,
2642 VkImageAspectFlagBits aspect,
2643 enum isl_aux_usage aux_usage,
2644 enum isl_format format, struct isl_swizzle swizzle,
2645 uint32_t level, uint32_t base_layer, uint32_t layer_count,
2646 VkRect2D area, union isl_color_value clear_color);
2647 void
2648 anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
2649 const struct anv_image *image,
2650 VkImageAspectFlags aspects,
2651 enum isl_aux_usage depth_aux_usage,
2652 uint32_t level,
2653 uint32_t base_layer, uint32_t layer_count,
2654 VkRect2D area,
2655 float depth_value, uint8_t stencil_value);
2656 void
2657 anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
2658 const struct anv_image *image,
2659 VkImageAspectFlagBits aspect, uint32_t level,
2660 uint32_t base_layer, uint32_t layer_count,
2661 enum isl_aux_op hiz_op);
2662 void
2663 anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
2664 const struct anv_image *image,
2665 VkImageAspectFlags aspects,
2666 uint32_t level,
2667 uint32_t base_layer, uint32_t layer_count,
2668 VkRect2D area, uint8_t stencil_value);
2669 void
2670 anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
2671 const struct anv_image *image,
2672 VkImageAspectFlagBits aspect,
2673 uint32_t base_layer, uint32_t layer_count,
2674 enum isl_aux_op mcs_op, bool predicate);
2675 void
2676 anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
2677 const struct anv_image *image,
2678 VkImageAspectFlagBits aspect, uint32_t level,
2679 uint32_t base_layer, uint32_t layer_count,
2680 enum isl_aux_op ccs_op, bool predicate);
2681
2682 void
2683 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2684 const struct anv_image *image,
2685 uint32_t base_level, uint32_t level_count,
2686 uint32_t base_layer, uint32_t layer_count);
2687
2688 enum isl_aux_usage
2689 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2690 const struct anv_image *image,
2691 const VkImageAspectFlagBits aspect,
2692 const VkImageLayout layout);
2693
2694 enum anv_fast_clear_type
2695 anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
2696 const struct anv_image * const image,
2697 const VkImageAspectFlagBits aspect,
2698 const VkImageLayout layout);
2699
2700 /* This is defined as a macro so that it works for both
2701 * VkImageSubresourceRange and VkImageSubresourceLayers
2702 */
2703 #define anv_get_layerCount(_image, _range) \
2704 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2705 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2706
2707 static inline uint32_t
2708 anv_get_levelCount(const struct anv_image *image,
2709 const VkImageSubresourceRange *range)
2710 {
2711 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2712 image->levels - range->baseMipLevel : range->levelCount;
2713 }
2714
2715 static inline VkImageAspectFlags
2716 anv_image_expand_aspects(const struct anv_image *image,
2717 VkImageAspectFlags aspects)
2718 {
2719 /* If the underlying image has color plane aspects and
2720 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2721 * the underlying image. */
2722 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
2723 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2724 return image->aspects;
2725
2726 return aspects;
2727 }
2728
2729 static inline bool
2730 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2731 VkImageAspectFlags aspects2)
2732 {
2733 if (aspects1 == aspects2)
2734 return true;
2735
2736 /* Only 1 color aspects are compatibles. */
2737 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2738 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2739 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2740 return true;
2741
2742 return false;
2743 }
2744
2745 struct anv_image_view {
2746 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2747
2748 VkImageAspectFlags aspect_mask;
2749 VkFormat vk_format;
2750 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2751
2752 unsigned n_planes;
2753 struct {
2754 uint32_t image_plane;
2755
2756 struct isl_view isl;
2757
2758 /**
2759 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2760 * image layout of SHADER_READ_ONLY_OPTIMAL or
2761 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2762 */
2763 struct anv_surface_state optimal_sampler_surface_state;
2764
2765 /**
2766 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2767 * image layout of GENERAL.
2768 */
2769 struct anv_surface_state general_sampler_surface_state;
2770
2771 /**
2772 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2773 * states for write-only and readable, using the real format for
2774 * write-only and the lowered format for readable.
2775 */
2776 struct anv_surface_state storage_surface_state;
2777 struct anv_surface_state writeonly_storage_surface_state;
2778
2779 struct brw_image_param storage_image_param;
2780 } planes[3];
2781 };
2782
2783 enum anv_image_view_state_flags {
2784 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2785 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2786 };
2787
2788 void anv_image_fill_surface_state(struct anv_device *device,
2789 const struct anv_image *image,
2790 VkImageAspectFlagBits aspect,
2791 const struct isl_view *view,
2792 isl_surf_usage_flags_t view_usage,
2793 enum isl_aux_usage aux_usage,
2794 const union isl_color_value *clear_color,
2795 enum anv_image_view_state_flags flags,
2796 struct anv_surface_state *state_inout,
2797 struct brw_image_param *image_param_out);
2798
2799 struct anv_image_create_info {
2800 const VkImageCreateInfo *vk_info;
2801
2802 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2803 isl_tiling_flags_t isl_tiling_flags;
2804
2805 /** These flags will be added to any derived from VkImageCreateInfo. */
2806 isl_surf_usage_flags_t isl_extra_usage_flags;
2807
2808 uint32_t stride;
2809 };
2810
2811 VkResult anv_image_create(VkDevice _device,
2812 const struct anv_image_create_info *info,
2813 const VkAllocationCallbacks* alloc,
2814 VkImage *pImage);
2815
2816 #ifdef ANDROID
2817 VkResult anv_image_from_gralloc(VkDevice device_h,
2818 const VkImageCreateInfo *base_info,
2819 const VkNativeBufferANDROID *gralloc_info,
2820 const VkAllocationCallbacks *alloc,
2821 VkImage *pImage);
2822 #endif
2823
2824 const struct anv_surface *
2825 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2826 VkImageAspectFlags aspect_mask);
2827
2828 enum isl_format
2829 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2830
2831 static inline struct VkExtent3D
2832 anv_sanitize_image_extent(const VkImageType imageType,
2833 const struct VkExtent3D imageExtent)
2834 {
2835 switch (imageType) {
2836 case VK_IMAGE_TYPE_1D:
2837 return (VkExtent3D) { imageExtent.width, 1, 1 };
2838 case VK_IMAGE_TYPE_2D:
2839 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2840 case VK_IMAGE_TYPE_3D:
2841 return imageExtent;
2842 default:
2843 unreachable("invalid image type");
2844 }
2845 }
2846
2847 static inline struct VkOffset3D
2848 anv_sanitize_image_offset(const VkImageType imageType,
2849 const struct VkOffset3D imageOffset)
2850 {
2851 switch (imageType) {
2852 case VK_IMAGE_TYPE_1D:
2853 return (VkOffset3D) { imageOffset.x, 0, 0 };
2854 case VK_IMAGE_TYPE_2D:
2855 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2856 case VK_IMAGE_TYPE_3D:
2857 return imageOffset;
2858 default:
2859 unreachable("invalid image type");
2860 }
2861 }
2862
2863
2864 void anv_fill_buffer_surface_state(struct anv_device *device,
2865 struct anv_state state,
2866 enum isl_format format,
2867 uint32_t offset, uint32_t range,
2868 uint32_t stride);
2869
2870
2871 struct anv_ycbcr_conversion {
2872 const struct anv_format * format;
2873 VkSamplerYcbcrModelConversionKHR ycbcr_model;
2874 VkSamplerYcbcrRangeKHR ycbcr_range;
2875 VkComponentSwizzle mapping[4];
2876 VkChromaLocationKHR chroma_offsets[2];
2877 VkFilter chroma_filter;
2878 bool chroma_reconstruction;
2879 };
2880
2881 struct anv_sampler {
2882 uint32_t state[3][4];
2883 uint32_t n_planes;
2884 struct anv_ycbcr_conversion *conversion;
2885 };
2886
2887 struct anv_framebuffer {
2888 uint32_t width;
2889 uint32_t height;
2890 uint32_t layers;
2891
2892 uint32_t attachment_count;
2893 struct anv_image_view * attachments[0];
2894 };
2895
2896 struct anv_subpass_attachment {
2897 VkImageUsageFlagBits usage;
2898 uint32_t attachment;
2899 VkImageLayout layout;
2900 };
2901
2902 struct anv_subpass {
2903 uint32_t attachment_count;
2904
2905 /**
2906 * A pointer to all attachment references used in this subpass.
2907 * Only valid if ::attachment_count > 0.
2908 */
2909 struct anv_subpass_attachment * attachments;
2910 uint32_t input_count;
2911 struct anv_subpass_attachment * input_attachments;
2912 uint32_t color_count;
2913 struct anv_subpass_attachment * color_attachments;
2914 struct anv_subpass_attachment * resolve_attachments;
2915
2916 struct anv_subpass_attachment depth_stencil_attachment;
2917
2918 uint32_t view_mask;
2919
2920 /** Subpass has a depth/stencil self-dependency */
2921 bool has_ds_self_dep;
2922
2923 /** Subpass has at least one resolve attachment */
2924 bool has_resolve;
2925 };
2926
2927 static inline unsigned
2928 anv_subpass_view_count(const struct anv_subpass *subpass)
2929 {
2930 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2931 }
2932
2933 struct anv_render_pass_attachment {
2934 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2935 * its members individually.
2936 */
2937 VkFormat format;
2938 uint32_t samples;
2939 VkImageUsageFlags usage;
2940 VkAttachmentLoadOp load_op;
2941 VkAttachmentStoreOp store_op;
2942 VkAttachmentLoadOp stencil_load_op;
2943 VkImageLayout initial_layout;
2944 VkImageLayout final_layout;
2945 VkImageLayout first_subpass_layout;
2946
2947 /* The subpass id in which the attachment will be used last. */
2948 uint32_t last_subpass_idx;
2949 };
2950
2951 struct anv_render_pass {
2952 uint32_t attachment_count;
2953 uint32_t subpass_count;
2954 /* An array of subpass_count+1 flushes, one per subpass boundary */
2955 enum anv_pipe_bits * subpass_flushes;
2956 struct anv_render_pass_attachment * attachments;
2957 struct anv_subpass subpasses[0];
2958 };
2959
2960 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2961
2962 struct anv_query_pool {
2963 VkQueryType type;
2964 VkQueryPipelineStatisticFlags pipeline_statistics;
2965 /** Stride between slots, in bytes */
2966 uint32_t stride;
2967 /** Number of slots in this query pool */
2968 uint32_t slots;
2969 struct anv_bo bo;
2970 };
2971
2972 int anv_get_entrypoint_index(const char *name);
2973
2974 bool
2975 anv_entrypoint_is_enabled(int index, uint32_t core_version,
2976 const struct anv_instance_extension_table *instance,
2977 const struct anv_device_extension_table *device);
2978
2979 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2980 const char *name);
2981
2982 void anv_dump_image_to_ppm(struct anv_device *device,
2983 struct anv_image *image, unsigned miplevel,
2984 unsigned array_layer, VkImageAspectFlagBits aspect,
2985 const char *filename);
2986
2987 enum anv_dump_action {
2988 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2989 };
2990
2991 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2992 void anv_dump_finish(void);
2993
2994 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2995 struct anv_framebuffer *fb);
2996
2997 static inline uint32_t
2998 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2999 {
3000 /* This function must be called from within a subpass. */
3001 assert(cmd_state->pass && cmd_state->subpass);
3002
3003 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
3004
3005 /* The id of this subpass shouldn't exceed the number of subpasses in this
3006 * render pass minus 1.
3007 */
3008 assert(subpass_id < cmd_state->pass->subpass_count);
3009 return subpass_id;
3010 }
3011
3012 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3013 \
3014 static inline struct __anv_type * \
3015 __anv_type ## _from_handle(__VkType _handle) \
3016 { \
3017 return (struct __anv_type *) _handle; \
3018 } \
3019 \
3020 static inline __VkType \
3021 __anv_type ## _to_handle(struct __anv_type *_obj) \
3022 { \
3023 return (__VkType) _obj; \
3024 }
3025
3026 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3027 \
3028 static inline struct __anv_type * \
3029 __anv_type ## _from_handle(__VkType _handle) \
3030 { \
3031 return (struct __anv_type *)(uintptr_t) _handle; \
3032 } \
3033 \
3034 static inline __VkType \
3035 __anv_type ## _to_handle(struct __anv_type *_obj) \
3036 { \
3037 return (__VkType)(uintptr_t) _obj; \
3038 }
3039
3040 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3041 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3042
3043 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
3044 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
3045 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
3046 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
3047 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
3048
3049 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
3050 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
3051 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
3052 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
3053 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
3054 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
3055 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
3056 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
3057 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
3058 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
3059 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
3060 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
3061 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
3062 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
3063 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
3064 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
3065 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
3066 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
3067 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
3068 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
3069 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
3070 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback, VkDebugReportCallbackEXT)
3071 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversionKHR)
3072
3073 /* Gen-specific function declarations */
3074 #ifdef genX
3075 # include "anv_genX.h"
3076 #else
3077 # define genX(x) gen7_##x
3078 # include "anv_genX.h"
3079 # undef genX
3080 # define genX(x) gen75_##x
3081 # include "anv_genX.h"
3082 # undef genX
3083 # define genX(x) gen8_##x
3084 # include "anv_genX.h"
3085 # undef genX
3086 # define genX(x) gen9_##x
3087 # include "anv_genX.h"
3088 # undef genX
3089 # define genX(x) gen10_##x
3090 # include "anv_genX.h"
3091 # undef genX
3092 # define genX(x) gen11_##x
3093 # include "anv_genX.h"
3094 # undef genX
3095 #endif
3096
3097 #endif /* ANV_PRIVATE_H */