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anv/cmd_state: Drop the scratch_size field
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 /* Pre-declarations needed for WSI entrypoints */
56 struct wl_surface;
57 struct wl_display;
58 typedef struct xcb_connection_t xcb_connection_t;
59 typedef uint32_t xcb_visualid_t;
60 typedef uint32_t xcb_window_t;
61
62 struct anv_buffer;
63 struct anv_buffer_view;
64 struct anv_image_view;
65 struct anv_instance;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72 #include <vulkan/vk_android_native_buffer.h>
73
74 #include "anv_entrypoints.h"
75 #include "anv_extensions.h"
76 #include "isl/isl.h"
77
78 #include "common/gen_debug.h"
79 #include "common/intel_log.h"
80 #include "wsi_common.h"
81
82 /* Allowing different clear colors requires us to perform a depth resolve at
83 * the end of certain render passes. This is because while slow clears store
84 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
85 * See the PRMs for examples describing when additional resolves would be
86 * necessary. To enable fast clears without requiring extra resolves, we set
87 * the clear value to a globally-defined one. We could allow different values
88 * if the user doesn't expect coherent data during or after a render passes
89 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
90 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
91 * 1.0f seems to be the only value used. The only application that doesn't set
92 * this value does so through the usage of an seemingly uninitialized clear
93 * value.
94 */
95 #define ANV_HZ_FC_VAL 1.0f
96
97 #define MAX_VBS 28
98 #define MAX_SETS 8
99 #define MAX_RTS 8
100 #define MAX_VIEWPORTS 16
101 #define MAX_SCISSORS 16
102 #define MAX_PUSH_CONSTANTS_SIZE 128
103 #define MAX_DYNAMIC_BUFFERS 16
104 #define MAX_IMAGES 8
105 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
106
107 #define ANV_SVGS_VB_INDEX MAX_VBS
108 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
109
110 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
111
112 static inline uint32_t
113 align_down_npot_u32(uint32_t v, uint32_t a)
114 {
115 return v - (v % a);
116 }
117
118 static inline uint32_t
119 align_u32(uint32_t v, uint32_t a)
120 {
121 assert(a != 0 && a == (a & -a));
122 return (v + a - 1) & ~(a - 1);
123 }
124
125 static inline uint64_t
126 align_u64(uint64_t v, uint64_t a)
127 {
128 assert(a != 0 && a == (a & -a));
129 return (v + a - 1) & ~(a - 1);
130 }
131
132 static inline int32_t
133 align_i32(int32_t v, int32_t a)
134 {
135 assert(a != 0 && a == (a & -a));
136 return (v + a - 1) & ~(a - 1);
137 }
138
139 /** Alignment must be a power of 2. */
140 static inline bool
141 anv_is_aligned(uintmax_t n, uintmax_t a)
142 {
143 assert(a == (a & -a));
144 return (n & (a - 1)) == 0;
145 }
146
147 static inline uint32_t
148 anv_minify(uint32_t n, uint32_t levels)
149 {
150 if (unlikely(n == 0))
151 return 0;
152 else
153 return MAX2(n >> levels, 1);
154 }
155
156 static inline float
157 anv_clamp_f(float f, float min, float max)
158 {
159 assert(min < max);
160
161 if (f > max)
162 return max;
163 else if (f < min)
164 return min;
165 else
166 return f;
167 }
168
169 static inline bool
170 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
171 {
172 if (*inout_mask & clear_mask) {
173 *inout_mask &= ~clear_mask;
174 return true;
175 } else {
176 return false;
177 }
178 }
179
180 static inline union isl_color_value
181 vk_to_isl_color(VkClearColorValue color)
182 {
183 return (union isl_color_value) {
184 .u32 = {
185 color.uint32[0],
186 color.uint32[1],
187 color.uint32[2],
188 color.uint32[3],
189 },
190 };
191 }
192
193 #define for_each_bit(b, dword) \
194 for (uint32_t __dword = (dword); \
195 (b) = __builtin_ffs(__dword) - 1, __dword; \
196 __dword &= ~(1 << (b)))
197
198 #define typed_memcpy(dest, src, count) ({ \
199 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
200 memcpy((dest), (src), (count) * sizeof(*(src))); \
201 })
202
203 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
204 * to be added here in order to utilize mapping in debug/error/perf macros.
205 */
206 #define REPORT_OBJECT_TYPE(o) \
207 __builtin_choose_expr ( \
208 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
209 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
210 __builtin_choose_expr ( \
211 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
212 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
213 __builtin_choose_expr ( \
214 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
215 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
216 __builtin_choose_expr ( \
217 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
218 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
219 __builtin_choose_expr ( \
220 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
221 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
222 __builtin_choose_expr ( \
223 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
224 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
225 __builtin_choose_expr ( \
226 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
227 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
228 __builtin_choose_expr ( \
229 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
230 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
231 __builtin_choose_expr ( \
232 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
233 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
234 __builtin_choose_expr ( \
235 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
236 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
237 __builtin_choose_expr ( \
238 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
239 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
240 __builtin_choose_expr ( \
241 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
242 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
243 __builtin_choose_expr ( \
244 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
245 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
246 __builtin_choose_expr ( \
247 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
248 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
249 __builtin_choose_expr ( \
250 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
251 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
252 __builtin_choose_expr ( \
253 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
254 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
255 __builtin_choose_expr ( \
256 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
257 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
258 __builtin_choose_expr ( \
259 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
260 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
261 __builtin_choose_expr ( \
262 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
263 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
264 __builtin_choose_expr ( \
265 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
266 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
267 __builtin_choose_expr ( \
268 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
269 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
270 __builtin_choose_expr ( \
271 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
272 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
273 __builtin_choose_expr ( \
274 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
275 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
276 __builtin_choose_expr ( \
277 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
278 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
279 __builtin_choose_expr ( \
280 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
281 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
282 __builtin_choose_expr ( \
283 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
284 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
285 __builtin_choose_expr ( \
286 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
287 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
288 __builtin_choose_expr ( \
289 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
290 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
291 __builtin_choose_expr ( \
292 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
293 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
294 __builtin_choose_expr ( \
295 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
296 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
297 __builtin_choose_expr ( \
298 __builtin_types_compatible_p (__typeof (o), void*), \
299 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
300 /* The void expression results in a compile-time error \
301 when assigning the result to something. */ \
302 (void)0)))))))))))))))))))))))))))))))
303
304 /* Whenever we generate an error, pass it through this function. Useful for
305 * debugging, where we can break on it. Only call at error site, not when
306 * propagating errors. Might be useful to plug in a stack trace here.
307 */
308
309 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
310 VkDebugReportObjectTypeEXT type, VkResult error,
311 const char *file, int line, const char *format, ...);
312
313 #ifdef DEBUG
314 #define vk_error(error) __vk_errorf(NULL, NULL,\
315 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
316 error, __FILE__, __LINE__, NULL);
317 #define vk_errorf(instance, obj, error, format, ...)\
318 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
319 __FILE__, __LINE__, format, ## __VA_ARGS__);
320 #else
321 #define vk_error(error) error
322 #define vk_errorf(instance, obj, error, format, ...) error
323 #endif
324
325 /**
326 * Warn on ignored extension structs.
327 *
328 * The Vulkan spec requires us to ignore unsupported or unknown structs in
329 * a pNext chain. In debug mode, emitting warnings for ignored structs may
330 * help us discover structs that we should not have ignored.
331 *
332 *
333 * From the Vulkan 1.0.38 spec:
334 *
335 * Any component of the implementation (the loader, any enabled layers,
336 * and drivers) must skip over, without processing (other than reading the
337 * sType and pNext members) any chained structures with sType values not
338 * defined by extensions supported by that component.
339 */
340 #define anv_debug_ignored_stype(sType) \
341 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
342
343 void __anv_perf_warn(struct anv_instance *instance, const void *object,
344 VkDebugReportObjectTypeEXT type, const char *file,
345 int line, const char *format, ...)
346 anv_printflike(6, 7);
347 void anv_loge(const char *format, ...) anv_printflike(1, 2);
348 void anv_loge_v(const char *format, va_list va);
349
350 /**
351 * Print a FINISHME message, including its source location.
352 */
353 #define anv_finishme(format, ...) \
354 do { \
355 static bool reported = false; \
356 if (!reported) { \
357 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
358 ##__VA_ARGS__); \
359 reported = true; \
360 } \
361 } while (0)
362
363 /**
364 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
365 */
366 #define anv_perf_warn(instance, obj, format, ...) \
367 do { \
368 static bool reported = false; \
369 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
370 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
371 format, ##__VA_ARGS__); \
372 reported = true; \
373 } \
374 } while (0)
375
376 /* A non-fatal assert. Useful for debugging. */
377 #ifdef DEBUG
378 #define anv_assert(x) ({ \
379 if (unlikely(!(x))) \
380 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
381 })
382 #else
383 #define anv_assert(x)
384 #endif
385
386 /* A multi-pointer allocator
387 *
388 * When copying data structures from the user (such as a render pass), it's
389 * common to need to allocate data for a bunch of different things. Instead
390 * of doing several allocations and having to handle all of the error checking
391 * that entails, it can be easier to do a single allocation. This struct
392 * helps facilitate that. The intended usage looks like this:
393 *
394 * ANV_MULTIALLOC(ma)
395 * anv_multialloc_add(&ma, &main_ptr, 1);
396 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
397 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
398 *
399 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
400 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
401 */
402 struct anv_multialloc {
403 size_t size;
404 size_t align;
405
406 uint32_t ptr_count;
407 void **ptrs[8];
408 };
409
410 #define ANV_MULTIALLOC_INIT \
411 ((struct anv_multialloc) { 0, })
412
413 #define ANV_MULTIALLOC(_name) \
414 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
415
416 __attribute__((always_inline))
417 static inline void
418 _anv_multialloc_add(struct anv_multialloc *ma,
419 void **ptr, size_t size, size_t align)
420 {
421 size_t offset = align_u64(ma->size, align);
422 ma->size = offset + size;
423 ma->align = MAX2(ma->align, align);
424
425 /* Store the offset in the pointer. */
426 *ptr = (void *)(uintptr_t)offset;
427
428 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
429 ma->ptrs[ma->ptr_count++] = ptr;
430 }
431
432 #define anv_multialloc_add_size(_ma, _ptr, _size) \
433 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
434
435 #define anv_multialloc_add(_ma, _ptr, _count) \
436 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
437
438 __attribute__((always_inline))
439 static inline void *
440 anv_multialloc_alloc(struct anv_multialloc *ma,
441 const VkAllocationCallbacks *alloc,
442 VkSystemAllocationScope scope)
443 {
444 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
445 if (!ptr)
446 return NULL;
447
448 /* Fill out each of the pointers with their final value.
449 *
450 * for (uint32_t i = 0; i < ma->ptr_count; i++)
451 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
452 *
453 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
454 * constant, GCC is incapable of figuring this out and unrolling the loop
455 * so we have to give it a little help.
456 */
457 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
458 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
459 if ((_i) < ma->ptr_count) \
460 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
461 _ANV_MULTIALLOC_UPDATE_POINTER(0);
462 _ANV_MULTIALLOC_UPDATE_POINTER(1);
463 _ANV_MULTIALLOC_UPDATE_POINTER(2);
464 _ANV_MULTIALLOC_UPDATE_POINTER(3);
465 _ANV_MULTIALLOC_UPDATE_POINTER(4);
466 _ANV_MULTIALLOC_UPDATE_POINTER(5);
467 _ANV_MULTIALLOC_UPDATE_POINTER(6);
468 _ANV_MULTIALLOC_UPDATE_POINTER(7);
469 #undef _ANV_MULTIALLOC_UPDATE_POINTER
470
471 return ptr;
472 }
473
474 __attribute__((always_inline))
475 static inline void *
476 anv_multialloc_alloc2(struct anv_multialloc *ma,
477 const VkAllocationCallbacks *parent_alloc,
478 const VkAllocationCallbacks *alloc,
479 VkSystemAllocationScope scope)
480 {
481 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
482 }
483
484 struct anv_bo {
485 uint32_t gem_handle;
486
487 /* Index into the current validation list. This is used by the
488 * validation list building alrogithm to track which buffers are already
489 * in the validation list so that we can ensure uniqueness.
490 */
491 uint32_t index;
492
493 /* Last known offset. This value is provided by the kernel when we
494 * execbuf and is used as the presumed offset for the next bunch of
495 * relocations.
496 */
497 uint64_t offset;
498
499 uint64_t size;
500 void *map;
501
502 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
503 uint32_t flags;
504 };
505
506 static inline void
507 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
508 {
509 bo->gem_handle = gem_handle;
510 bo->index = 0;
511 bo->offset = -1;
512 bo->size = size;
513 bo->map = NULL;
514 bo->flags = 0;
515 }
516
517 /* Represents a lock-free linked list of "free" things. This is used by
518 * both the block pool and the state pools. Unfortunately, in order to
519 * solve the ABA problem, we can't use a single uint32_t head.
520 */
521 union anv_free_list {
522 struct {
523 int32_t offset;
524
525 /* A simple count that is incremented every time the head changes. */
526 uint32_t count;
527 };
528 uint64_t u64;
529 };
530
531 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
532
533 struct anv_block_state {
534 union {
535 struct {
536 uint32_t next;
537 uint32_t end;
538 };
539 uint64_t u64;
540 };
541 };
542
543 struct anv_block_pool {
544 struct anv_device *device;
545
546 uint64_t bo_flags;
547
548 struct anv_bo bo;
549
550 /* The offset from the start of the bo to the "center" of the block
551 * pool. Pointers to allocated blocks are given by
552 * bo.map + center_bo_offset + offsets.
553 */
554 uint32_t center_bo_offset;
555
556 /* Current memory map of the block pool. This pointer may or may not
557 * point to the actual beginning of the block pool memory. If
558 * anv_block_pool_alloc_back has ever been called, then this pointer
559 * will point to the "center" position of the buffer and all offsets
560 * (negative or positive) given out by the block pool alloc functions
561 * will be valid relative to this pointer.
562 *
563 * In particular, map == bo.map + center_offset
564 */
565 void *map;
566 int fd;
567
568 /**
569 * Array of mmaps and gem handles owned by the block pool, reclaimed when
570 * the block pool is destroyed.
571 */
572 struct u_vector mmap_cleanups;
573
574 struct anv_block_state state;
575
576 struct anv_block_state back_state;
577 };
578
579 /* Block pools are backed by a fixed-size 1GB memfd */
580 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
581
582 /* The center of the block pool is also the middle of the memfd. This may
583 * change in the future if we decide differently for some reason.
584 */
585 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
586
587 static inline uint32_t
588 anv_block_pool_size(struct anv_block_pool *pool)
589 {
590 return pool->state.end + pool->back_state.end;
591 }
592
593 struct anv_state {
594 int32_t offset;
595 uint32_t alloc_size;
596 void *map;
597 };
598
599 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
600
601 struct anv_fixed_size_state_pool {
602 union anv_free_list free_list;
603 struct anv_block_state block;
604 };
605
606 #define ANV_MIN_STATE_SIZE_LOG2 6
607 #define ANV_MAX_STATE_SIZE_LOG2 20
608
609 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
610
611 struct anv_state_pool {
612 struct anv_block_pool block_pool;
613
614 /* The size of blocks which will be allocated from the block pool */
615 uint32_t block_size;
616
617 /** Free list for "back" allocations */
618 union anv_free_list back_alloc_free_list;
619
620 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
621 };
622
623 struct anv_state_stream_block;
624
625 struct anv_state_stream {
626 struct anv_state_pool *state_pool;
627
628 /* The size of blocks to allocate from the state pool */
629 uint32_t block_size;
630
631 /* Current block we're allocating from */
632 struct anv_state block;
633
634 /* Offset into the current block at which to allocate the next state */
635 uint32_t next;
636
637 /* List of all blocks allocated from this pool */
638 struct anv_state_stream_block *block_list;
639 };
640
641 /* The block_pool functions exported for testing only. The block pool should
642 * only be used via a state pool (see below).
643 */
644 VkResult anv_block_pool_init(struct anv_block_pool *pool,
645 struct anv_device *device,
646 uint32_t initial_size,
647 uint64_t bo_flags);
648 void anv_block_pool_finish(struct anv_block_pool *pool);
649 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
650 uint32_t block_size);
651 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
652 uint32_t block_size);
653
654 VkResult anv_state_pool_init(struct anv_state_pool *pool,
655 struct anv_device *device,
656 uint32_t block_size,
657 uint64_t bo_flags);
658 void anv_state_pool_finish(struct anv_state_pool *pool);
659 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
660 uint32_t state_size, uint32_t alignment);
661 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
662 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
663 void anv_state_stream_init(struct anv_state_stream *stream,
664 struct anv_state_pool *state_pool,
665 uint32_t block_size);
666 void anv_state_stream_finish(struct anv_state_stream *stream);
667 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
668 uint32_t size, uint32_t alignment);
669
670 /**
671 * Implements a pool of re-usable BOs. The interface is identical to that
672 * of block_pool except that each block is its own BO.
673 */
674 struct anv_bo_pool {
675 struct anv_device *device;
676
677 uint64_t bo_flags;
678
679 void *free_list[16];
680 };
681
682 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
683 uint64_t bo_flags);
684 void anv_bo_pool_finish(struct anv_bo_pool *pool);
685 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
686 uint32_t size);
687 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
688
689 struct anv_scratch_bo {
690 bool exists;
691 struct anv_bo bo;
692 };
693
694 struct anv_scratch_pool {
695 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
696 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
697 };
698
699 void anv_scratch_pool_init(struct anv_device *device,
700 struct anv_scratch_pool *pool);
701 void anv_scratch_pool_finish(struct anv_device *device,
702 struct anv_scratch_pool *pool);
703 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
704 struct anv_scratch_pool *pool,
705 gl_shader_stage stage,
706 unsigned per_thread_scratch);
707
708 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
709 struct anv_bo_cache {
710 struct hash_table *bo_map;
711 pthread_mutex_t mutex;
712 };
713
714 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
715 void anv_bo_cache_finish(struct anv_bo_cache *cache);
716 VkResult anv_bo_cache_alloc(struct anv_device *device,
717 struct anv_bo_cache *cache,
718 uint64_t size, struct anv_bo **bo);
719 VkResult anv_bo_cache_import(struct anv_device *device,
720 struct anv_bo_cache *cache,
721 int fd, struct anv_bo **bo);
722 VkResult anv_bo_cache_export(struct anv_device *device,
723 struct anv_bo_cache *cache,
724 struct anv_bo *bo_in, int *fd_out);
725 void anv_bo_cache_release(struct anv_device *device,
726 struct anv_bo_cache *cache,
727 struct anv_bo *bo);
728
729 struct anv_memory_type {
730 /* Standard bits passed on to the client */
731 VkMemoryPropertyFlags propertyFlags;
732 uint32_t heapIndex;
733
734 /* Driver-internal book-keeping */
735 VkBufferUsageFlags valid_buffer_usage;
736 };
737
738 struct anv_memory_heap {
739 /* Standard bits passed on to the client */
740 VkDeviceSize size;
741 VkMemoryHeapFlags flags;
742
743 /* Driver-internal book-keeping */
744 bool supports_48bit_addresses;
745 };
746
747 struct anv_physical_device {
748 VK_LOADER_DATA _loader_data;
749
750 struct anv_instance * instance;
751 uint32_t chipset_id;
752 char path[20];
753 const char * name;
754 struct gen_device_info info;
755 /** Amount of "GPU memory" we want to advertise
756 *
757 * Clearly, this value is bogus since Intel is a UMA architecture. On
758 * gen7 platforms, we are limited by GTT size unless we want to implement
759 * fine-grained tracking and GTT splitting. On Broadwell and above we are
760 * practically unlimited. However, we will never report more than 3/4 of
761 * the total system ram to try and avoid running out of RAM.
762 */
763 bool supports_48bit_addresses;
764 struct brw_compiler * compiler;
765 struct isl_device isl_dev;
766 int cmd_parser_version;
767 bool has_exec_async;
768 bool has_exec_capture;
769 bool has_exec_fence;
770 bool has_syncobj;
771 bool has_syncobj_wait;
772
773 struct anv_device_extension_table supported_extensions;
774
775 uint32_t eu_total;
776 uint32_t subslice_total;
777
778 struct {
779 uint32_t type_count;
780 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
781 uint32_t heap_count;
782 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
783 } memory;
784
785 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
786 uint8_t driver_uuid[VK_UUID_SIZE];
787 uint8_t device_uuid[VK_UUID_SIZE];
788
789 struct wsi_device wsi_device;
790 int local_fd;
791 };
792
793 struct anv_instance {
794 VK_LOADER_DATA _loader_data;
795
796 VkAllocationCallbacks alloc;
797
798 uint32_t apiVersion;
799 struct anv_instance_extension_table enabled_extensions;
800 struct anv_dispatch_table dispatch;
801
802 int physicalDeviceCount;
803 struct anv_physical_device physicalDevice;
804
805 struct vk_debug_report_instance debug_report_callbacks;
806 };
807
808 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
809 void anv_finish_wsi(struct anv_physical_device *physical_device);
810
811 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
812 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
813 const char *name);
814
815 struct anv_queue {
816 VK_LOADER_DATA _loader_data;
817
818 struct anv_device * device;
819
820 struct anv_state_pool * pool;
821 };
822
823 struct anv_pipeline_cache {
824 struct anv_device * device;
825 pthread_mutex_t mutex;
826
827 struct hash_table * cache;
828 };
829
830 struct anv_pipeline_bind_map;
831
832 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
833 struct anv_device *device,
834 bool cache_enabled);
835 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
836
837 struct anv_shader_bin *
838 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
839 const void *key, uint32_t key_size);
840 struct anv_shader_bin *
841 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
842 const void *key_data, uint32_t key_size,
843 const void *kernel_data, uint32_t kernel_size,
844 const struct brw_stage_prog_data *prog_data,
845 uint32_t prog_data_size,
846 const struct anv_pipeline_bind_map *bind_map);
847
848 struct anv_device {
849 VK_LOADER_DATA _loader_data;
850
851 VkAllocationCallbacks alloc;
852
853 struct anv_instance * instance;
854 uint32_t chipset_id;
855 struct gen_device_info info;
856 struct isl_device isl_dev;
857 int context_id;
858 int fd;
859 bool can_chain_batches;
860 bool robust_buffer_access;
861 struct anv_device_extension_table enabled_extensions;
862 struct anv_dispatch_table dispatch;
863
864 struct anv_bo_pool batch_bo_pool;
865
866 struct anv_bo_cache bo_cache;
867
868 struct anv_state_pool dynamic_state_pool;
869 struct anv_state_pool instruction_state_pool;
870 struct anv_state_pool surface_state_pool;
871
872 struct anv_bo workaround_bo;
873 struct anv_bo trivial_batch_bo;
874
875 struct anv_pipeline_cache blorp_shader_cache;
876 struct blorp_context blorp;
877
878 struct anv_state border_colors;
879
880 struct anv_queue queue;
881
882 struct anv_scratch_pool scratch_pool;
883
884 uint32_t default_mocs;
885
886 pthread_mutex_t mutex;
887 pthread_cond_t queue_submit;
888 bool lost;
889 };
890
891 static void inline
892 anv_state_flush(struct anv_device *device, struct anv_state state)
893 {
894 if (device->info.has_llc)
895 return;
896
897 gen_flush_range(state.map, state.alloc_size);
898 }
899
900 void anv_device_init_blorp(struct anv_device *device);
901 void anv_device_finish_blorp(struct anv_device *device);
902
903 VkResult anv_device_execbuf(struct anv_device *device,
904 struct drm_i915_gem_execbuffer2 *execbuf,
905 struct anv_bo **execbuf_bos);
906 VkResult anv_device_query_status(struct anv_device *device);
907 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
908 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
909 int64_t timeout);
910
911 void* anv_gem_mmap(struct anv_device *device,
912 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
913 void anv_gem_munmap(void *p, uint64_t size);
914 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
915 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
916 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
917 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
918 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
919 int anv_gem_execbuffer(struct anv_device *device,
920 struct drm_i915_gem_execbuffer2 *execbuf);
921 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
922 uint32_t stride, uint32_t tiling);
923 int anv_gem_create_context(struct anv_device *device);
924 int anv_gem_destroy_context(struct anv_device *device, int context);
925 int anv_gem_get_context_param(int fd, int context, uint32_t param,
926 uint64_t *value);
927 int anv_gem_get_param(int fd, uint32_t param);
928 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
929 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
930 int anv_gem_get_aperture(int fd, uint64_t *size);
931 bool anv_gem_supports_48b_addresses(int fd);
932 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
933 uint32_t *active, uint32_t *pending);
934 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
935 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
936 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
937 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
938 uint32_t read_domains, uint32_t write_domain);
939 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
940 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
941 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
942 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
943 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
944 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
945 uint32_t handle);
946 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
947 uint32_t handle, int fd);
948 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
949 bool anv_gem_supports_syncobj_wait(int fd);
950 int anv_gem_syncobj_wait(struct anv_device *device,
951 uint32_t *handles, uint32_t num_handles,
952 int64_t abs_timeout_ns, bool wait_all);
953
954 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
955
956 struct anv_reloc_list {
957 uint32_t num_relocs;
958 uint32_t array_length;
959 struct drm_i915_gem_relocation_entry * relocs;
960 struct anv_bo ** reloc_bos;
961 };
962
963 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
964 const VkAllocationCallbacks *alloc);
965 void anv_reloc_list_finish(struct anv_reloc_list *list,
966 const VkAllocationCallbacks *alloc);
967
968 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
969 const VkAllocationCallbacks *alloc,
970 uint32_t offset, struct anv_bo *target_bo,
971 uint32_t delta);
972
973 struct anv_batch_bo {
974 /* Link in the anv_cmd_buffer.owned_batch_bos list */
975 struct list_head link;
976
977 struct anv_bo bo;
978
979 /* Bytes actually consumed in this batch BO */
980 uint32_t length;
981
982 struct anv_reloc_list relocs;
983 };
984
985 struct anv_batch {
986 const VkAllocationCallbacks * alloc;
987
988 void * start;
989 void * end;
990 void * next;
991
992 struct anv_reloc_list * relocs;
993
994 /* This callback is called (with the associated user data) in the event
995 * that the batch runs out of space.
996 */
997 VkResult (*extend_cb)(struct anv_batch *, void *);
998 void * user_data;
999
1000 /**
1001 * Current error status of the command buffer. Used to track inconsistent
1002 * or incomplete command buffer states that are the consequence of run-time
1003 * errors such as out of memory scenarios. We want to track this in the
1004 * batch because the command buffer object is not visible to some parts
1005 * of the driver.
1006 */
1007 VkResult status;
1008 };
1009
1010 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1011 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1012 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1013 void *location, struct anv_bo *bo, uint32_t offset);
1014 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1015 struct anv_batch *batch);
1016
1017 static inline VkResult
1018 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1019 {
1020 assert(error != VK_SUCCESS);
1021 if (batch->status == VK_SUCCESS)
1022 batch->status = error;
1023 return batch->status;
1024 }
1025
1026 static inline bool
1027 anv_batch_has_error(struct anv_batch *batch)
1028 {
1029 return batch->status != VK_SUCCESS;
1030 }
1031
1032 struct anv_address {
1033 struct anv_bo *bo;
1034 uint32_t offset;
1035 };
1036
1037 static inline uint64_t
1038 _anv_combine_address(struct anv_batch *batch, void *location,
1039 const struct anv_address address, uint32_t delta)
1040 {
1041 if (address.bo == NULL) {
1042 return address.offset + delta;
1043 } else {
1044 assert(batch->start <= location && location < batch->end);
1045
1046 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1047 }
1048 }
1049
1050 #define __gen_address_type struct anv_address
1051 #define __gen_user_data struct anv_batch
1052 #define __gen_combine_address _anv_combine_address
1053
1054 /* Wrapper macros needed to work around preprocessor argument issues. In
1055 * particular, arguments don't get pre-evaluated if they are concatenated.
1056 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1057 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1058 * We can work around this easily enough with these helpers.
1059 */
1060 #define __anv_cmd_length(cmd) cmd ## _length
1061 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1062 #define __anv_cmd_header(cmd) cmd ## _header
1063 #define __anv_cmd_pack(cmd) cmd ## _pack
1064 #define __anv_reg_num(reg) reg ## _num
1065
1066 #define anv_pack_struct(dst, struc, ...) do { \
1067 struct struc __template = { \
1068 __VA_ARGS__ \
1069 }; \
1070 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1071 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1072 } while (0)
1073
1074 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1075 void *__dst = anv_batch_emit_dwords(batch, n); \
1076 if (__dst) { \
1077 struct cmd __template = { \
1078 __anv_cmd_header(cmd), \
1079 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1080 __VA_ARGS__ \
1081 }; \
1082 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1083 } \
1084 __dst; \
1085 })
1086
1087 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1088 do { \
1089 uint32_t *dw; \
1090 \
1091 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1092 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1093 if (!dw) \
1094 break; \
1095 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1096 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1097 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1098 } while (0)
1099
1100 #define anv_batch_emit(batch, cmd, name) \
1101 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1102 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1103 __builtin_expect(_dst != NULL, 1); \
1104 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1105 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1106 _dst = NULL; \
1107 }))
1108
1109 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1110 .GraphicsDataTypeGFDT = 0, \
1111 .LLCCacheabilityControlLLCCC = 0, \
1112 .L3CacheabilityControlL3CC = 1, \
1113 }
1114
1115 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1116 .LLCeLLCCacheabilityControlLLCCC = 0, \
1117 .L3CacheabilityControlL3CC = 1, \
1118 }
1119
1120 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1121 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1122 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1123 .AgeforQUADLRU = 0 \
1124 }
1125
1126 /* Skylake: MOCS is now an index into an array of 62 different caching
1127 * configurations programmed by the kernel.
1128 */
1129
1130 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1131 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1132 .IndextoMOCSTables = 2 \
1133 }
1134
1135 #define GEN9_MOCS_PTE { \
1136 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1137 .IndextoMOCSTables = 1 \
1138 }
1139
1140 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1141 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1142 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1143 .IndextoMOCSTables = 2 \
1144 }
1145
1146 #define GEN10_MOCS_PTE { \
1147 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1148 .IndextoMOCSTables = 1 \
1149 }
1150
1151 struct anv_device_memory {
1152 struct anv_bo * bo;
1153 struct anv_memory_type * type;
1154 VkDeviceSize map_size;
1155 void * map;
1156 };
1157
1158 /**
1159 * Header for Vertex URB Entry (VUE)
1160 */
1161 struct anv_vue_header {
1162 uint32_t Reserved;
1163 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1164 uint32_t ViewportIndex;
1165 float PointWidth;
1166 };
1167
1168 struct anv_descriptor_set_binding_layout {
1169 #ifndef NDEBUG
1170 /* The type of the descriptors in this binding */
1171 VkDescriptorType type;
1172 #endif
1173
1174 /* Number of array elements in this binding */
1175 uint16_t array_size;
1176
1177 /* Index into the flattend descriptor set */
1178 uint16_t descriptor_index;
1179
1180 /* Index into the dynamic state array for a dynamic buffer */
1181 int16_t dynamic_offset_index;
1182
1183 /* Index into the descriptor set buffer views */
1184 int16_t buffer_index;
1185
1186 struct {
1187 /* Index into the binding table for the associated surface */
1188 int16_t surface_index;
1189
1190 /* Index into the sampler table for the associated sampler */
1191 int16_t sampler_index;
1192
1193 /* Index into the image table for the associated image */
1194 int16_t image_index;
1195 } stage[MESA_SHADER_STAGES];
1196
1197 /* Immutable samplers (or NULL if no immutable samplers) */
1198 struct anv_sampler **immutable_samplers;
1199 };
1200
1201 struct anv_descriptor_set_layout {
1202 /* Number of bindings in this descriptor set */
1203 uint16_t binding_count;
1204
1205 /* Total size of the descriptor set with room for all array entries */
1206 uint16_t size;
1207
1208 /* Shader stages affected by this descriptor set */
1209 uint16_t shader_stages;
1210
1211 /* Number of buffers in this descriptor set */
1212 uint16_t buffer_count;
1213
1214 /* Number of dynamic offsets used by this descriptor set */
1215 uint16_t dynamic_offset_count;
1216
1217 /* Bindings in this descriptor set */
1218 struct anv_descriptor_set_binding_layout binding[0];
1219 };
1220
1221 struct anv_descriptor {
1222 VkDescriptorType type;
1223
1224 union {
1225 struct {
1226 VkImageLayout layout;
1227 struct anv_image_view *image_view;
1228 struct anv_sampler *sampler;
1229 };
1230
1231 struct {
1232 struct anv_buffer *buffer;
1233 uint64_t offset;
1234 uint64_t range;
1235 };
1236
1237 struct anv_buffer_view *buffer_view;
1238 };
1239 };
1240
1241 struct anv_descriptor_set {
1242 const struct anv_descriptor_set_layout *layout;
1243 uint32_t size;
1244 uint32_t buffer_count;
1245 struct anv_buffer_view *buffer_views;
1246 struct anv_descriptor descriptors[0];
1247 };
1248
1249 struct anv_buffer_view {
1250 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1251 struct anv_bo *bo;
1252 uint32_t offset; /**< Offset into bo. */
1253 uint64_t range; /**< VkBufferViewCreateInfo::range */
1254
1255 struct anv_state surface_state;
1256 struct anv_state storage_surface_state;
1257 struct anv_state writeonly_storage_surface_state;
1258
1259 struct brw_image_param storage_image_param;
1260 };
1261
1262 struct anv_push_descriptor_set {
1263 struct anv_descriptor_set set;
1264
1265 /* Put this field right behind anv_descriptor_set so it fills up the
1266 * descriptors[0] field. */
1267 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1268 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1269 };
1270
1271 struct anv_descriptor_pool {
1272 uint32_t size;
1273 uint32_t next;
1274 uint32_t free_list;
1275
1276 struct anv_state_stream surface_state_stream;
1277 void *surface_state_free_list;
1278
1279 char data[0];
1280 };
1281
1282 enum anv_descriptor_template_entry_type {
1283 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1284 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1285 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1286 };
1287
1288 struct anv_descriptor_template_entry {
1289 /* The type of descriptor in this entry */
1290 VkDescriptorType type;
1291
1292 /* Binding in the descriptor set */
1293 uint32_t binding;
1294
1295 /* Offset at which to write into the descriptor set binding */
1296 uint32_t array_element;
1297
1298 /* Number of elements to write into the descriptor set binding */
1299 uint32_t array_count;
1300
1301 /* Offset into the user provided data */
1302 size_t offset;
1303
1304 /* Stride between elements into the user provided data */
1305 size_t stride;
1306 };
1307
1308 struct anv_descriptor_update_template {
1309 /* The descriptor set this template corresponds to. This value is only
1310 * valid if the template was created with the templateType
1311 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1312 */
1313 uint8_t set;
1314
1315 /* Number of entries in this template */
1316 uint32_t entry_count;
1317
1318 /* Entries of the template */
1319 struct anv_descriptor_template_entry entries[0];
1320 };
1321
1322 size_t
1323 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1324
1325 size_t
1326 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1327
1328 void
1329 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1330 const struct gen_device_info * const devinfo,
1331 const VkDescriptorImageInfo * const info,
1332 VkDescriptorType type,
1333 uint32_t binding,
1334 uint32_t element);
1335
1336 void
1337 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1338 VkDescriptorType type,
1339 struct anv_buffer_view *buffer_view,
1340 uint32_t binding,
1341 uint32_t element);
1342
1343 void
1344 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1345 struct anv_device *device,
1346 struct anv_state_stream *alloc_stream,
1347 VkDescriptorType type,
1348 struct anv_buffer *buffer,
1349 uint32_t binding,
1350 uint32_t element,
1351 VkDeviceSize offset,
1352 VkDeviceSize range);
1353
1354 void
1355 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1356 struct anv_device *device,
1357 struct anv_state_stream *alloc_stream,
1358 const struct anv_descriptor_update_template *template,
1359 const void *data);
1360
1361 VkResult
1362 anv_descriptor_set_create(struct anv_device *device,
1363 struct anv_descriptor_pool *pool,
1364 const struct anv_descriptor_set_layout *layout,
1365 struct anv_descriptor_set **out_set);
1366
1367 void
1368 anv_descriptor_set_destroy(struct anv_device *device,
1369 struct anv_descriptor_pool *pool,
1370 struct anv_descriptor_set *set);
1371
1372 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1373
1374 struct anv_pipeline_binding {
1375 /* The descriptor set this surface corresponds to. The special value of
1376 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1377 * to a color attachment and not a regular descriptor.
1378 */
1379 uint8_t set;
1380
1381 /* Binding in the descriptor set */
1382 uint32_t binding;
1383
1384 /* Index in the binding */
1385 uint32_t index;
1386
1387 /* Plane in the binding index */
1388 uint8_t plane;
1389
1390 /* Input attachment index (relative to the subpass) */
1391 uint8_t input_attachment_index;
1392
1393 /* For a storage image, whether it is write-only */
1394 bool write_only;
1395 };
1396
1397 struct anv_pipeline_layout {
1398 struct {
1399 struct anv_descriptor_set_layout *layout;
1400 uint32_t dynamic_offset_start;
1401 } set[MAX_SETS];
1402
1403 uint32_t num_sets;
1404
1405 struct {
1406 bool has_dynamic_offsets;
1407 } stage[MESA_SHADER_STAGES];
1408
1409 unsigned char sha1[20];
1410 };
1411
1412 struct anv_buffer {
1413 struct anv_device * device;
1414 VkDeviceSize size;
1415
1416 VkBufferUsageFlags usage;
1417
1418 /* Set when bound */
1419 struct anv_bo * bo;
1420 VkDeviceSize offset;
1421 };
1422
1423 static inline uint64_t
1424 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1425 {
1426 assert(offset <= buffer->size);
1427 if (range == VK_WHOLE_SIZE) {
1428 return buffer->size - offset;
1429 } else {
1430 assert(range <= buffer->size);
1431 return range;
1432 }
1433 }
1434
1435 enum anv_cmd_dirty_bits {
1436 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1437 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1438 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1439 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1440 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1441 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1442 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1443 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1444 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1445 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1446 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1447 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1448 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1449 };
1450 typedef uint32_t anv_cmd_dirty_mask_t;
1451
1452 enum anv_pipe_bits {
1453 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1454 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1455 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1456 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1457 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1458 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1459 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1460 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1461 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1462 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1463 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1464
1465 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1466 * a flush has happened but not a CS stall. The next time we do any sort
1467 * of invalidation we need to insert a CS stall at that time. Otherwise,
1468 * we would have to CS stall on every flush which could be bad.
1469 */
1470 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1471 };
1472
1473 #define ANV_PIPE_FLUSH_BITS ( \
1474 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1475 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1476 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1477
1478 #define ANV_PIPE_STALL_BITS ( \
1479 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1480 ANV_PIPE_DEPTH_STALL_BIT | \
1481 ANV_PIPE_CS_STALL_BIT)
1482
1483 #define ANV_PIPE_INVALIDATE_BITS ( \
1484 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1485 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1486 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1487 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1488 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1489 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1490
1491 static inline enum anv_pipe_bits
1492 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1493 {
1494 enum anv_pipe_bits pipe_bits = 0;
1495
1496 unsigned b;
1497 for_each_bit(b, flags) {
1498 switch ((VkAccessFlagBits)(1 << b)) {
1499 case VK_ACCESS_SHADER_WRITE_BIT:
1500 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1501 break;
1502 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1503 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1504 break;
1505 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1506 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1507 break;
1508 case VK_ACCESS_TRANSFER_WRITE_BIT:
1509 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1510 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1511 break;
1512 default:
1513 break; /* Nothing to do */
1514 }
1515 }
1516
1517 return pipe_bits;
1518 }
1519
1520 static inline enum anv_pipe_bits
1521 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1522 {
1523 enum anv_pipe_bits pipe_bits = 0;
1524
1525 unsigned b;
1526 for_each_bit(b, flags) {
1527 switch ((VkAccessFlagBits)(1 << b)) {
1528 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1529 case VK_ACCESS_INDEX_READ_BIT:
1530 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1531 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1532 break;
1533 case VK_ACCESS_UNIFORM_READ_BIT:
1534 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1535 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1536 break;
1537 case VK_ACCESS_SHADER_READ_BIT:
1538 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1539 case VK_ACCESS_TRANSFER_READ_BIT:
1540 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1541 break;
1542 default:
1543 break; /* Nothing to do */
1544 }
1545 }
1546
1547 return pipe_bits;
1548 }
1549
1550 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1551 VK_IMAGE_ASPECT_COLOR_BIT | \
1552 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1553 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1554 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1555 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1556 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1557 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1558 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1559
1560 struct anv_vertex_binding {
1561 struct anv_buffer * buffer;
1562 VkDeviceSize offset;
1563 };
1564
1565 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1566 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1567
1568 struct anv_push_constants {
1569 /* Current allocated size of this push constants data structure.
1570 * Because a decent chunk of it may not be used (images on SKL, for
1571 * instance), we won't actually allocate the entire structure up-front.
1572 */
1573 uint32_t size;
1574
1575 /* Push constant data provided by the client through vkPushConstants */
1576 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1577
1578 /* Image data for image_load_store on pre-SKL */
1579 struct brw_image_param images[MAX_IMAGES];
1580 };
1581
1582 struct anv_dynamic_state {
1583 struct {
1584 uint32_t count;
1585 VkViewport viewports[MAX_VIEWPORTS];
1586 } viewport;
1587
1588 struct {
1589 uint32_t count;
1590 VkRect2D scissors[MAX_SCISSORS];
1591 } scissor;
1592
1593 float line_width;
1594
1595 struct {
1596 float bias;
1597 float clamp;
1598 float slope;
1599 } depth_bias;
1600
1601 float blend_constants[4];
1602
1603 struct {
1604 float min;
1605 float max;
1606 } depth_bounds;
1607
1608 struct {
1609 uint32_t front;
1610 uint32_t back;
1611 } stencil_compare_mask;
1612
1613 struct {
1614 uint32_t front;
1615 uint32_t back;
1616 } stencil_write_mask;
1617
1618 struct {
1619 uint32_t front;
1620 uint32_t back;
1621 } stencil_reference;
1622 };
1623
1624 extern const struct anv_dynamic_state default_dynamic_state;
1625
1626 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1627 const struct anv_dynamic_state *src,
1628 uint32_t copy_mask);
1629
1630 struct anv_surface_state {
1631 struct anv_state state;
1632 /** Address of the surface referred to by this state
1633 *
1634 * This address is relative to the start of the BO.
1635 */
1636 uint64_t address;
1637 /* Address of the aux surface, if any
1638 *
1639 * This field is 0 if and only if no aux surface exists.
1640 *
1641 * This address is relative to the start of the BO. On gen7, the bottom 12
1642 * bits of this address include extra aux information.
1643 */
1644 uint64_t aux_address;
1645 };
1646
1647 /**
1648 * Attachment state when recording a renderpass instance.
1649 *
1650 * The clear value is valid only if there exists a pending clear.
1651 */
1652 struct anv_attachment_state {
1653 enum isl_aux_usage aux_usage;
1654 enum isl_aux_usage input_aux_usage;
1655 struct anv_surface_state color;
1656 struct anv_surface_state input;
1657
1658 VkImageLayout current_layout;
1659 VkImageAspectFlags pending_clear_aspects;
1660 bool fast_clear;
1661 VkClearValue clear_value;
1662 bool clear_color_is_zero_one;
1663 bool clear_color_is_zero;
1664 };
1665
1666 /** State required while building cmd buffer */
1667 struct anv_cmd_state {
1668 /* PIPELINE_SELECT.PipelineSelection */
1669 uint32_t current_pipeline;
1670 const struct gen_l3_config * current_l3_config;
1671 uint32_t vb_dirty;
1672 anv_cmd_dirty_mask_t dirty;
1673 anv_cmd_dirty_mask_t compute_dirty;
1674 enum anv_pipe_bits pending_pipe_bits;
1675 uint32_t num_workgroups_offset;
1676 struct anv_bo *num_workgroups_bo;
1677 VkShaderStageFlags descriptors_dirty;
1678 VkShaderStageFlags push_constants_dirty;
1679 struct anv_pipeline * pipeline;
1680 struct anv_pipeline * compute_pipeline;
1681 struct anv_framebuffer * framebuffer;
1682 struct anv_render_pass * pass;
1683 struct anv_subpass * subpass;
1684 VkRect2D render_area;
1685 uint32_t restart_index;
1686 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1687 struct anv_descriptor_set * descriptors[MAX_SETS];
1688 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1689 VkShaderStageFlags push_constant_stages;
1690 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1691 struct anv_state binding_tables[MESA_SHADER_STAGES];
1692 struct anv_state samplers[MESA_SHADER_STAGES];
1693 struct anv_dynamic_state dynamic;
1694 bool need_query_wa;
1695
1696 struct anv_push_descriptor_set * push_descriptors[MAX_SETS];
1697
1698 /**
1699 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1700 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1701 * and before invoking the secondary in ExecuteCommands.
1702 */
1703 bool pma_fix_enabled;
1704
1705 /**
1706 * Whether or not we know for certain that HiZ is enabled for the current
1707 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1708 * enabled or not, this will be false.
1709 */
1710 bool hiz_enabled;
1711
1712 /**
1713 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1714 * valid only when recording a render pass instance.
1715 */
1716 struct anv_attachment_state * attachments;
1717
1718 /**
1719 * Surface states for color render targets. These are stored in a single
1720 * flat array. For depth-stencil attachments, the surface state is simply
1721 * left blank.
1722 */
1723 struct anv_state render_pass_states;
1724
1725 /**
1726 * A null surface state of the right size to match the framebuffer. This
1727 * is one of the states in render_pass_states.
1728 */
1729 struct anv_state null_surface_state;
1730
1731 struct {
1732 struct anv_buffer * index_buffer;
1733 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1734 uint32_t index_offset;
1735 } gen7;
1736 };
1737
1738 struct anv_cmd_pool {
1739 VkAllocationCallbacks alloc;
1740 struct list_head cmd_buffers;
1741 };
1742
1743 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1744
1745 enum anv_cmd_buffer_exec_mode {
1746 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1747 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1748 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1749 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1750 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1751 };
1752
1753 struct anv_cmd_buffer {
1754 VK_LOADER_DATA _loader_data;
1755
1756 struct anv_device * device;
1757
1758 struct anv_cmd_pool * pool;
1759 struct list_head pool_link;
1760
1761 struct anv_batch batch;
1762
1763 /* Fields required for the actual chain of anv_batch_bo's.
1764 *
1765 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1766 */
1767 struct list_head batch_bos;
1768 enum anv_cmd_buffer_exec_mode exec_mode;
1769
1770 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1771 * referenced by this command buffer
1772 *
1773 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1774 */
1775 struct u_vector seen_bbos;
1776
1777 /* A vector of int32_t's for every block of binding tables.
1778 *
1779 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1780 */
1781 struct u_vector bt_block_states;
1782 uint32_t bt_next;
1783
1784 struct anv_reloc_list surface_relocs;
1785 /** Last seen surface state block pool center bo offset */
1786 uint32_t last_ss_pool_center;
1787
1788 /* Serial for tracking buffer completion */
1789 uint32_t serial;
1790
1791 /* Stream objects for storing temporary data */
1792 struct anv_state_stream surface_state_stream;
1793 struct anv_state_stream dynamic_state_stream;
1794
1795 VkCommandBufferUsageFlags usage_flags;
1796 VkCommandBufferLevel level;
1797
1798 struct anv_cmd_state state;
1799 };
1800
1801 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1802 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1803 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1804 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1805 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1806 struct anv_cmd_buffer *secondary);
1807 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1808 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1809 struct anv_cmd_buffer *cmd_buffer,
1810 const VkSemaphore *in_semaphores,
1811 uint32_t num_in_semaphores,
1812 const VkSemaphore *out_semaphores,
1813 uint32_t num_out_semaphores,
1814 VkFence fence);
1815
1816 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1817
1818 VkResult
1819 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1820 gl_shader_stage stage, uint32_t size);
1821 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1822 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1823 (offsetof(struct anv_push_constants, field) + \
1824 sizeof(cmd_buffer->state.push_constants[0]->field)))
1825
1826 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1827 const void *data, uint32_t size, uint32_t alignment);
1828 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1829 uint32_t *a, uint32_t *b,
1830 uint32_t dwords, uint32_t alignment);
1831
1832 struct anv_address
1833 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1834 struct anv_state
1835 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1836 uint32_t entries, uint32_t *state_offset);
1837 struct anv_state
1838 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1839 struct anv_state
1840 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1841 uint32_t size, uint32_t alignment);
1842
1843 VkResult
1844 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1845
1846 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1847 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1848 bool depth_clamp_enable);
1849 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1850
1851 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1852 struct anv_render_pass *pass,
1853 struct anv_framebuffer *framebuffer,
1854 const VkClearValue *clear_values);
1855
1856 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1857
1858 struct anv_state
1859 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1860 gl_shader_stage stage);
1861 struct anv_state
1862 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1863
1864 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1865 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1866
1867 const struct anv_image_view *
1868 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1869
1870 VkResult
1871 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1872 uint32_t num_entries,
1873 uint32_t *state_offset,
1874 struct anv_state *bt_state);
1875
1876 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1877
1878 enum anv_fence_type {
1879 ANV_FENCE_TYPE_NONE = 0,
1880 ANV_FENCE_TYPE_BO,
1881 ANV_FENCE_TYPE_SYNCOBJ,
1882 };
1883
1884 enum anv_bo_fence_state {
1885 /** Indicates that this is a new (or newly reset fence) */
1886 ANV_BO_FENCE_STATE_RESET,
1887
1888 /** Indicates that this fence has been submitted to the GPU but is still
1889 * (as far as we know) in use by the GPU.
1890 */
1891 ANV_BO_FENCE_STATE_SUBMITTED,
1892
1893 ANV_BO_FENCE_STATE_SIGNALED,
1894 };
1895
1896 struct anv_fence_impl {
1897 enum anv_fence_type type;
1898
1899 union {
1900 /** Fence implementation for BO fences
1901 *
1902 * These fences use a BO and a set of CPU-tracked state flags. The BO
1903 * is added to the object list of the last execbuf call in a QueueSubmit
1904 * and is marked EXEC_WRITE. The state flags track when the BO has been
1905 * submitted to the kernel. We need to do this because Vulkan lets you
1906 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1907 * will say it's idle in this case.
1908 */
1909 struct {
1910 struct anv_bo bo;
1911 enum anv_bo_fence_state state;
1912 } bo;
1913
1914 /** DRM syncobj handle for syncobj-based fences */
1915 uint32_t syncobj;
1916 };
1917 };
1918
1919 struct anv_fence {
1920 /* Permanent fence state. Every fence has some form of permanent state
1921 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
1922 * cross-process fences) or it could just be a dummy for use internally.
1923 */
1924 struct anv_fence_impl permanent;
1925
1926 /* Temporary fence state. A fence *may* have temporary state. That state
1927 * is added to the fence by an import operation and is reset back to
1928 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
1929 * state cannot be signaled because the fence must already be signaled
1930 * before the temporary state can be exported from the fence in the other
1931 * process and imported here.
1932 */
1933 struct anv_fence_impl temporary;
1934 };
1935
1936 struct anv_event {
1937 uint64_t semaphore;
1938 struct anv_state state;
1939 };
1940
1941 enum anv_semaphore_type {
1942 ANV_SEMAPHORE_TYPE_NONE = 0,
1943 ANV_SEMAPHORE_TYPE_DUMMY,
1944 ANV_SEMAPHORE_TYPE_BO,
1945 ANV_SEMAPHORE_TYPE_SYNC_FILE,
1946 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
1947 };
1948
1949 struct anv_semaphore_impl {
1950 enum anv_semaphore_type type;
1951
1952 union {
1953 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1954 * This BO will be added to the object list on any execbuf2 calls for
1955 * which this semaphore is used as a wait or signal fence. When used as
1956 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1957 */
1958 struct anv_bo *bo;
1959
1960 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
1961 * If the semaphore is in the unsignaled state due to either just being
1962 * created or because it has been used for a wait, fd will be -1.
1963 */
1964 int fd;
1965
1966 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
1967 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
1968 * import so we don't need to bother with a userspace cache.
1969 */
1970 uint32_t syncobj;
1971 };
1972 };
1973
1974 struct anv_semaphore {
1975 /* Permanent semaphore state. Every semaphore has some form of permanent
1976 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1977 * (for cross-process semaphores0 or it could just be a dummy for use
1978 * internally.
1979 */
1980 struct anv_semaphore_impl permanent;
1981
1982 /* Temporary semaphore state. A semaphore *may* have temporary state.
1983 * That state is added to the semaphore by an import operation and is reset
1984 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1985 * semaphore with temporary state cannot be signaled because the semaphore
1986 * must already be signaled before the temporary state can be exported from
1987 * the semaphore in the other process and imported here.
1988 */
1989 struct anv_semaphore_impl temporary;
1990 };
1991
1992 void anv_semaphore_reset_temporary(struct anv_device *device,
1993 struct anv_semaphore *semaphore);
1994
1995 struct anv_shader_module {
1996 unsigned char sha1[20];
1997 uint32_t size;
1998 char data[0];
1999 };
2000
2001 static inline gl_shader_stage
2002 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2003 {
2004 assert(__builtin_popcount(vk_stage) == 1);
2005 return ffs(vk_stage) - 1;
2006 }
2007
2008 static inline VkShaderStageFlagBits
2009 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2010 {
2011 return (1 << mesa_stage);
2012 }
2013
2014 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2015
2016 #define anv_foreach_stage(stage, stage_bits) \
2017 for (gl_shader_stage stage, \
2018 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2019 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2020 __tmp &= ~(1 << (stage)))
2021
2022 struct anv_pipeline_bind_map {
2023 uint32_t surface_count;
2024 uint32_t sampler_count;
2025 uint32_t image_count;
2026
2027 struct anv_pipeline_binding * surface_to_descriptor;
2028 struct anv_pipeline_binding * sampler_to_descriptor;
2029 };
2030
2031 struct anv_shader_bin_key {
2032 uint32_t size;
2033 uint8_t data[0];
2034 };
2035
2036 struct anv_shader_bin {
2037 uint32_t ref_cnt;
2038
2039 const struct anv_shader_bin_key *key;
2040
2041 struct anv_state kernel;
2042 uint32_t kernel_size;
2043
2044 const struct brw_stage_prog_data *prog_data;
2045 uint32_t prog_data_size;
2046
2047 struct anv_pipeline_bind_map bind_map;
2048 };
2049
2050 struct anv_shader_bin *
2051 anv_shader_bin_create(struct anv_device *device,
2052 const void *key, uint32_t key_size,
2053 const void *kernel, uint32_t kernel_size,
2054 const struct brw_stage_prog_data *prog_data,
2055 uint32_t prog_data_size, const void *prog_data_param,
2056 const struct anv_pipeline_bind_map *bind_map);
2057
2058 void
2059 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2060
2061 static inline void
2062 anv_shader_bin_ref(struct anv_shader_bin *shader)
2063 {
2064 assert(shader && shader->ref_cnt >= 1);
2065 p_atomic_inc(&shader->ref_cnt);
2066 }
2067
2068 static inline void
2069 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2070 {
2071 assert(shader && shader->ref_cnt >= 1);
2072 if (p_atomic_dec_zero(&shader->ref_cnt))
2073 anv_shader_bin_destroy(device, shader);
2074 }
2075
2076 struct anv_pipeline {
2077 struct anv_device * device;
2078 struct anv_batch batch;
2079 uint32_t batch_data[512];
2080 struct anv_reloc_list batch_relocs;
2081 uint32_t dynamic_state_mask;
2082 struct anv_dynamic_state dynamic_state;
2083
2084 struct anv_subpass * subpass;
2085 struct anv_pipeline_layout * layout;
2086
2087 bool needs_data_cache;
2088
2089 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2090
2091 struct {
2092 const struct gen_l3_config * l3_config;
2093 uint32_t total_size;
2094 } urb;
2095
2096 VkShaderStageFlags active_stages;
2097 struct anv_state blend_state;
2098
2099 uint32_t vb_used;
2100 uint32_t binding_stride[MAX_VBS];
2101 bool instancing_enable[MAX_VBS];
2102 bool primitive_restart;
2103 uint32_t topology;
2104
2105 uint32_t cs_right_mask;
2106
2107 bool writes_depth;
2108 bool depth_test_enable;
2109 bool writes_stencil;
2110 bool stencil_test_enable;
2111 bool depth_clamp_enable;
2112 bool sample_shading_enable;
2113 bool kill_pixel;
2114
2115 struct {
2116 uint32_t sf[7];
2117 uint32_t depth_stencil_state[3];
2118 } gen7;
2119
2120 struct {
2121 uint32_t sf[4];
2122 uint32_t raster[5];
2123 uint32_t wm_depth_stencil[3];
2124 } gen8;
2125
2126 struct {
2127 uint32_t wm_depth_stencil[4];
2128 } gen9;
2129
2130 uint32_t interface_descriptor_data[8];
2131 };
2132
2133 static inline bool
2134 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2135 gl_shader_stage stage)
2136 {
2137 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2138 }
2139
2140 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2141 static inline const struct brw_##prefix##_prog_data * \
2142 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2143 { \
2144 if (anv_pipeline_has_stage(pipeline, stage)) { \
2145 return (const struct brw_##prefix##_prog_data *) \
2146 pipeline->shaders[stage]->prog_data; \
2147 } else { \
2148 return NULL; \
2149 } \
2150 }
2151
2152 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2153 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2154 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2155 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2156 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2157 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2158
2159 static inline const struct brw_vue_prog_data *
2160 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2161 {
2162 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2163 return &get_gs_prog_data(pipeline)->base;
2164 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2165 return &get_tes_prog_data(pipeline)->base;
2166 else
2167 return &get_vs_prog_data(pipeline)->base;
2168 }
2169
2170 VkResult
2171 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2172 struct anv_pipeline_cache *cache,
2173 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2174 const VkAllocationCallbacks *alloc);
2175
2176 VkResult
2177 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2178 struct anv_pipeline_cache *cache,
2179 const VkComputePipelineCreateInfo *info,
2180 struct anv_shader_module *module,
2181 const char *entrypoint,
2182 const VkSpecializationInfo *spec_info);
2183
2184 struct anv_format_plane {
2185 enum isl_format isl_format:16;
2186 struct isl_swizzle swizzle;
2187
2188 /* Whether this plane contains chroma channels */
2189 bool has_chroma;
2190
2191 /* For downscaling of YUV planes */
2192 uint8_t denominator_scales[2];
2193
2194 /* How to map sampled ycbcr planes to a single 4 component element. */
2195 struct isl_swizzle ycbcr_swizzle;
2196 };
2197
2198
2199 struct anv_format {
2200 struct anv_format_plane planes[3];
2201 uint8_t n_planes;
2202 bool can_ycbcr;
2203 };
2204
2205 static inline uint32_t
2206 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2207 VkImageAspectFlags aspect_mask)
2208 {
2209 switch (aspect_mask) {
2210 case VK_IMAGE_ASPECT_COLOR_BIT:
2211 case VK_IMAGE_ASPECT_DEPTH_BIT:
2212 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
2213 return 0;
2214 case VK_IMAGE_ASPECT_STENCIL_BIT:
2215 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2216 return 0;
2217 /* Fall-through */
2218 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
2219 return 1;
2220 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
2221 return 2;
2222 default:
2223 /* Purposefully assert with depth/stencil aspects. */
2224 unreachable("invalid image aspect");
2225 }
2226 }
2227
2228 static inline uint32_t
2229 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2230 {
2231 uint32_t planes = 0;
2232
2233 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2234 VK_IMAGE_ASPECT_DEPTH_BIT |
2235 VK_IMAGE_ASPECT_STENCIL_BIT |
2236 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR))
2237 planes++;
2238 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT_KHR)
2239 planes++;
2240 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
2241 planes++;
2242
2243 return planes;
2244 }
2245
2246 static inline VkImageAspectFlags
2247 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2248 uint32_t plane)
2249 {
2250 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2251 if (_mesa_bitcount(image_aspects) > 1)
2252 return VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << plane;
2253 return VK_IMAGE_ASPECT_COLOR_BIT;
2254 }
2255 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2256 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2257 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2258 return VK_IMAGE_ASPECT_STENCIL_BIT;
2259 }
2260
2261 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2262 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2263
2264 const struct anv_format *
2265 anv_get_format(VkFormat format);
2266
2267 static inline uint32_t
2268 anv_get_format_planes(VkFormat vk_format)
2269 {
2270 const struct anv_format *format = anv_get_format(vk_format);
2271
2272 return format != NULL ? format->n_planes : 0;
2273 }
2274
2275 struct anv_format_plane
2276 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2277 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2278
2279 static inline enum isl_format
2280 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2281 VkImageAspectFlags aspect, VkImageTiling tiling)
2282 {
2283 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2284 }
2285
2286 static inline struct isl_swizzle
2287 anv_swizzle_for_render(struct isl_swizzle swizzle)
2288 {
2289 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2290 * RGB as RGBA for texturing
2291 */
2292 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2293 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2294
2295 /* But it doesn't matter what we render to that channel */
2296 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2297
2298 return swizzle;
2299 }
2300
2301 void
2302 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2303
2304 /**
2305 * Subsurface of an anv_image.
2306 */
2307 struct anv_surface {
2308 /** Valid only if isl_surf::size > 0. */
2309 struct isl_surf isl;
2310
2311 /**
2312 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2313 */
2314 uint32_t offset;
2315 };
2316
2317 struct anv_image {
2318 VkImageType type;
2319 /* The original VkFormat provided by the client. This may not match any
2320 * of the actual surface formats.
2321 */
2322 VkFormat vk_format;
2323 const struct anv_format *format;
2324
2325 VkImageAspectFlags aspects;
2326 VkExtent3D extent;
2327 uint32_t levels;
2328 uint32_t array_size;
2329 uint32_t samples; /**< VkImageCreateInfo::samples */
2330 uint32_t n_planes;
2331 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2332 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2333
2334 /**
2335 * DRM format modifier for this image or DRM_FORMAT_MOD_INVALID.
2336 */
2337 uint64_t drm_format_mod;
2338
2339 VkDeviceSize size;
2340 uint32_t alignment;
2341
2342 /* Whether the image is made of several underlying buffer objects rather a
2343 * single one with different offsets.
2344 */
2345 bool disjoint;
2346
2347 /**
2348 * Image subsurfaces
2349 *
2350 * For each foo, anv_image::planes[x].surface is valid if and only if
2351 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2352 * to figure the number associated with a given aspect.
2353 *
2354 * The hardware requires that the depth buffer and stencil buffer be
2355 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2356 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2357 * allocate the depth and stencil buffers as separate surfaces in the same
2358 * bo.
2359 *
2360 * Memory layout :
2361 *
2362 * -----------------------
2363 * | surface0 | /|\
2364 * ----------------------- |
2365 * | shadow surface0 | |
2366 * ----------------------- | Plane 0
2367 * | aux surface0 | |
2368 * ----------------------- |
2369 * | fast clear colors0 | \|/
2370 * -----------------------
2371 * | surface1 | /|\
2372 * ----------------------- |
2373 * | shadow surface1 | |
2374 * ----------------------- | Plane 1
2375 * | aux surface1 | |
2376 * ----------------------- |
2377 * | fast clear colors1 | \|/
2378 * -----------------------
2379 * | ... |
2380 * | |
2381 * -----------------------
2382 */
2383 struct {
2384 /**
2385 * Offset of the entire plane (whenever the image is disjoint this is
2386 * set to 0).
2387 */
2388 uint32_t offset;
2389
2390 VkDeviceSize size;
2391 uint32_t alignment;
2392
2393 struct anv_surface surface;
2394
2395 /**
2396 * A surface which shadows the main surface and may have different
2397 * tiling. This is used for sampling using a tiling that isn't supported
2398 * for other operations.
2399 */
2400 struct anv_surface shadow_surface;
2401
2402 /**
2403 * For color images, this is the aux usage for this image when not used
2404 * as a color attachment.
2405 *
2406 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2407 * image has a HiZ buffer.
2408 */
2409 enum isl_aux_usage aux_usage;
2410
2411 struct anv_surface aux_surface;
2412
2413 /**
2414 * Offset of the fast clear state (used to compute the
2415 * fast_clear_state_offset of the following planes).
2416 */
2417 uint32_t fast_clear_state_offset;
2418
2419 /**
2420 * BO associated with this plane, set when bound.
2421 */
2422 struct anv_bo *bo;
2423 VkDeviceSize bo_offset;
2424
2425 /**
2426 * When destroying the image, also free the bo.
2427 * */
2428 bool bo_is_owned;
2429 } planes[3];
2430 };
2431
2432 /* Returns the number of auxiliary buffer levels attached to an image. */
2433 static inline uint8_t
2434 anv_image_aux_levels(const struct anv_image * const image,
2435 VkImageAspectFlagBits aspect)
2436 {
2437 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2438 return image->planes[plane].aux_surface.isl.size > 0 ?
2439 image->planes[plane].aux_surface.isl.levels : 0;
2440 }
2441
2442 /* Returns the number of auxiliary buffer layers attached to an image. */
2443 static inline uint32_t
2444 anv_image_aux_layers(const struct anv_image * const image,
2445 VkImageAspectFlagBits aspect,
2446 const uint8_t miplevel)
2447 {
2448 assert(image);
2449
2450 /* The miplevel must exist in the main buffer. */
2451 assert(miplevel < image->levels);
2452
2453 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2454 /* There are no layers with auxiliary data because the miplevel has no
2455 * auxiliary data.
2456 */
2457 return 0;
2458 } else {
2459 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2460 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2461 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2462 }
2463 }
2464
2465 static inline unsigned
2466 anv_fast_clear_state_entry_size(const struct anv_device *device)
2467 {
2468 assert(device);
2469 /* Entry contents:
2470 * +--------------------------------------------+
2471 * | clear value dword(s) | needs resolve dword |
2472 * +--------------------------------------------+
2473 */
2474
2475 /* Ensure that the needs resolve dword is in fact dword-aligned to enable
2476 * GPU memcpy operations.
2477 */
2478 assert(device->isl_dev.ss.clear_value_size % 4 == 0);
2479 return device->isl_dev.ss.clear_value_size + 4;
2480 }
2481
2482 static inline struct anv_address
2483 anv_image_get_clear_color_addr(const struct anv_device *device,
2484 const struct anv_image *image,
2485 VkImageAspectFlagBits aspect,
2486 unsigned level)
2487 {
2488 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2489 return (struct anv_address) {
2490 .bo = image->planes[plane].bo,
2491 .offset = image->planes[plane].bo_offset +
2492 image->planes[plane].fast_clear_state_offset +
2493 anv_fast_clear_state_entry_size(device) * level,
2494 };
2495 }
2496
2497 static inline struct anv_address
2498 anv_image_get_needs_resolve_addr(const struct anv_device *device,
2499 const struct anv_image *image,
2500 VkImageAspectFlagBits aspect,
2501 unsigned level)
2502 {
2503 struct anv_address addr =
2504 anv_image_get_clear_color_addr(device, image, aspect, level);
2505 addr.offset += device->isl_dev.ss.clear_value_size;
2506 return addr;
2507 }
2508
2509 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2510 static inline bool
2511 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2512 const struct anv_image *image)
2513 {
2514 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2515 return false;
2516
2517 if (devinfo->gen < 8)
2518 return false;
2519
2520 return image->samples == 1;
2521 }
2522
2523 void
2524 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
2525 const struct anv_image *image,
2526 enum blorp_hiz_op op);
2527 void
2528 anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
2529 const struct anv_image * const image,
2530 VkImageAspectFlagBits aspect,
2531 const uint8_t level,
2532 const uint32_t start_layer, const uint32_t layer_count,
2533 const enum blorp_fast_clear_op op);
2534
2535 void
2536 anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
2537 const struct anv_image *image,
2538 VkImageAspectFlagBits aspect,
2539 const uint32_t base_level, const uint32_t level_count,
2540 const uint32_t base_layer, uint32_t layer_count);
2541
2542 void
2543 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2544 const struct anv_image *image,
2545 uint32_t base_level, uint32_t level_count,
2546 uint32_t base_layer, uint32_t layer_count);
2547
2548 enum isl_aux_usage
2549 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2550 const struct anv_image *image,
2551 const VkImageAspectFlagBits aspect,
2552 const VkImageLayout layout);
2553
2554 /* This is defined as a macro so that it works for both
2555 * VkImageSubresourceRange and VkImageSubresourceLayers
2556 */
2557 #define anv_get_layerCount(_image, _range) \
2558 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2559 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2560
2561 static inline uint32_t
2562 anv_get_levelCount(const struct anv_image *image,
2563 const VkImageSubresourceRange *range)
2564 {
2565 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2566 image->levels - range->baseMipLevel : range->levelCount;
2567 }
2568
2569 static inline VkImageAspectFlags
2570 anv_image_expand_aspects(const struct anv_image *image,
2571 VkImageAspectFlags aspects)
2572 {
2573 /* If the underlying image has color plane aspects and
2574 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2575 * the underlying image. */
2576 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
2577 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2578 return image->aspects;
2579
2580 return aspects;
2581 }
2582
2583 static inline bool
2584 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2585 VkImageAspectFlags aspects2)
2586 {
2587 if (aspects1 == aspects2)
2588 return true;
2589
2590 /* Only 1 color aspects are compatibles. */
2591 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2592 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2593 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2594 return true;
2595
2596 return false;
2597 }
2598
2599 struct anv_image_view {
2600 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2601
2602 VkImageAspectFlags aspect_mask;
2603 VkFormat vk_format;
2604 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2605
2606 unsigned n_planes;
2607 struct {
2608 uint32_t image_plane;
2609
2610 struct isl_view isl;
2611
2612 /**
2613 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2614 * image layout of SHADER_READ_ONLY_OPTIMAL or
2615 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2616 */
2617 struct anv_surface_state optimal_sampler_surface_state;
2618
2619 /**
2620 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2621 * image layout of GENERAL.
2622 */
2623 struct anv_surface_state general_sampler_surface_state;
2624
2625 /**
2626 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2627 * states for write-only and readable, using the real format for
2628 * write-only and the lowered format for readable.
2629 */
2630 struct anv_surface_state storage_surface_state;
2631 struct anv_surface_state writeonly_storage_surface_state;
2632
2633 struct brw_image_param storage_image_param;
2634 } planes[3];
2635 };
2636
2637 enum anv_image_view_state_flags {
2638 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2639 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2640 };
2641
2642 void anv_image_fill_surface_state(struct anv_device *device,
2643 const struct anv_image *image,
2644 VkImageAspectFlagBits aspect,
2645 const struct isl_view *view,
2646 isl_surf_usage_flags_t view_usage,
2647 enum isl_aux_usage aux_usage,
2648 const union isl_color_value *clear_color,
2649 enum anv_image_view_state_flags flags,
2650 struct anv_surface_state *state_inout,
2651 struct brw_image_param *image_param_out);
2652
2653 struct anv_image_create_info {
2654 const VkImageCreateInfo *vk_info;
2655
2656 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2657 isl_tiling_flags_t isl_tiling_flags;
2658
2659 /** These flags will be added to any derived from VkImageCreateInfo. */
2660 isl_surf_usage_flags_t isl_extra_usage_flags;
2661
2662 uint32_t stride;
2663 };
2664
2665 VkResult anv_image_create(VkDevice _device,
2666 const struct anv_image_create_info *info,
2667 const VkAllocationCallbacks* alloc,
2668 VkImage *pImage);
2669
2670 #ifdef ANDROID
2671 VkResult anv_image_from_gralloc(VkDevice device_h,
2672 const VkImageCreateInfo *base_info,
2673 const VkNativeBufferANDROID *gralloc_info,
2674 const VkAllocationCallbacks *alloc,
2675 VkImage *pImage);
2676 #endif
2677
2678 const struct anv_surface *
2679 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2680 VkImageAspectFlags aspect_mask);
2681
2682 enum isl_format
2683 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2684
2685 static inline struct VkExtent3D
2686 anv_sanitize_image_extent(const VkImageType imageType,
2687 const struct VkExtent3D imageExtent)
2688 {
2689 switch (imageType) {
2690 case VK_IMAGE_TYPE_1D:
2691 return (VkExtent3D) { imageExtent.width, 1, 1 };
2692 case VK_IMAGE_TYPE_2D:
2693 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2694 case VK_IMAGE_TYPE_3D:
2695 return imageExtent;
2696 default:
2697 unreachable("invalid image type");
2698 }
2699 }
2700
2701 static inline struct VkOffset3D
2702 anv_sanitize_image_offset(const VkImageType imageType,
2703 const struct VkOffset3D imageOffset)
2704 {
2705 switch (imageType) {
2706 case VK_IMAGE_TYPE_1D:
2707 return (VkOffset3D) { imageOffset.x, 0, 0 };
2708 case VK_IMAGE_TYPE_2D:
2709 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2710 case VK_IMAGE_TYPE_3D:
2711 return imageOffset;
2712 default:
2713 unreachable("invalid image type");
2714 }
2715 }
2716
2717
2718 void anv_fill_buffer_surface_state(struct anv_device *device,
2719 struct anv_state state,
2720 enum isl_format format,
2721 uint32_t offset, uint32_t range,
2722 uint32_t stride);
2723
2724
2725 struct anv_ycbcr_conversion {
2726 const struct anv_format * format;
2727 VkSamplerYcbcrModelConversionKHR ycbcr_model;
2728 VkSamplerYcbcrRangeKHR ycbcr_range;
2729 VkComponentSwizzle mapping[4];
2730 VkChromaLocationKHR chroma_offsets[2];
2731 VkFilter chroma_filter;
2732 bool chroma_reconstruction;
2733 };
2734
2735 struct anv_sampler {
2736 uint32_t state[3][4];
2737 uint32_t n_planes;
2738 struct anv_ycbcr_conversion *conversion;
2739 };
2740
2741 struct anv_framebuffer {
2742 uint32_t width;
2743 uint32_t height;
2744 uint32_t layers;
2745
2746 uint32_t attachment_count;
2747 struct anv_image_view * attachments[0];
2748 };
2749
2750 struct anv_subpass {
2751 uint32_t attachment_count;
2752
2753 /**
2754 * A pointer to all attachment references used in this subpass.
2755 * Only valid if ::attachment_count > 0.
2756 */
2757 VkAttachmentReference * attachments;
2758 uint32_t input_count;
2759 VkAttachmentReference * input_attachments;
2760 uint32_t color_count;
2761 VkAttachmentReference * color_attachments;
2762 VkAttachmentReference * resolve_attachments;
2763
2764 VkAttachmentReference depth_stencil_attachment;
2765
2766 uint32_t view_mask;
2767
2768 /** Subpass has a depth/stencil self-dependency */
2769 bool has_ds_self_dep;
2770
2771 /** Subpass has at least one resolve attachment */
2772 bool has_resolve;
2773 };
2774
2775 static inline unsigned
2776 anv_subpass_view_count(const struct anv_subpass *subpass)
2777 {
2778 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2779 }
2780
2781 struct anv_render_pass_attachment {
2782 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2783 * its members individually.
2784 */
2785 VkFormat format;
2786 uint32_t samples;
2787 VkImageUsageFlags usage;
2788 VkAttachmentLoadOp load_op;
2789 VkAttachmentStoreOp store_op;
2790 VkAttachmentLoadOp stencil_load_op;
2791 VkImageLayout initial_layout;
2792 VkImageLayout final_layout;
2793 VkImageLayout first_subpass_layout;
2794
2795 /* The subpass id in which the attachment will be used last. */
2796 uint32_t last_subpass_idx;
2797 };
2798
2799 struct anv_render_pass {
2800 uint32_t attachment_count;
2801 uint32_t subpass_count;
2802 /* An array of subpass_count+1 flushes, one per subpass boundary */
2803 enum anv_pipe_bits * subpass_flushes;
2804 struct anv_render_pass_attachment * attachments;
2805 struct anv_subpass subpasses[0];
2806 };
2807
2808 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2809
2810 struct anv_query_pool {
2811 VkQueryType type;
2812 VkQueryPipelineStatisticFlags pipeline_statistics;
2813 /** Stride between slots, in bytes */
2814 uint32_t stride;
2815 /** Number of slots in this query pool */
2816 uint32_t slots;
2817 struct anv_bo bo;
2818 };
2819
2820 int anv_get_entrypoint_index(const char *name);
2821
2822 bool
2823 anv_entrypoint_is_enabled(int index, uint32_t core_version,
2824 const struct anv_instance_extension_table *instance,
2825 const struct anv_device_extension_table *device);
2826
2827 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2828 const char *name);
2829
2830 void anv_dump_image_to_ppm(struct anv_device *device,
2831 struct anv_image *image, unsigned miplevel,
2832 unsigned array_layer, VkImageAspectFlagBits aspect,
2833 const char *filename);
2834
2835 enum anv_dump_action {
2836 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2837 };
2838
2839 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2840 void anv_dump_finish(void);
2841
2842 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2843 struct anv_framebuffer *fb);
2844
2845 static inline uint32_t
2846 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2847 {
2848 /* This function must be called from within a subpass. */
2849 assert(cmd_state->pass && cmd_state->subpass);
2850
2851 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
2852
2853 /* The id of this subpass shouldn't exceed the number of subpasses in this
2854 * render pass minus 1.
2855 */
2856 assert(subpass_id < cmd_state->pass->subpass_count);
2857 return subpass_id;
2858 }
2859
2860 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2861 \
2862 static inline struct __anv_type * \
2863 __anv_type ## _from_handle(__VkType _handle) \
2864 { \
2865 return (struct __anv_type *) _handle; \
2866 } \
2867 \
2868 static inline __VkType \
2869 __anv_type ## _to_handle(struct __anv_type *_obj) \
2870 { \
2871 return (__VkType) _obj; \
2872 }
2873
2874 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2875 \
2876 static inline struct __anv_type * \
2877 __anv_type ## _from_handle(__VkType _handle) \
2878 { \
2879 return (struct __anv_type *)(uintptr_t) _handle; \
2880 } \
2881 \
2882 static inline __VkType \
2883 __anv_type ## _to_handle(struct __anv_type *_obj) \
2884 { \
2885 return (__VkType)(uintptr_t) _obj; \
2886 }
2887
2888 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2889 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2890
2891 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
2892 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
2893 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
2894 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
2895 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
2896
2897 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
2898 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
2899 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
2900 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
2901 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
2902 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
2903 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
2904 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
2905 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
2906 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
2907 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
2908 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
2909 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
2910 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
2911 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
2912 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
2913 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
2914 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
2915 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
2916 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
2917 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
2918 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback, VkDebugReportCallbackEXT)
2919 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversionKHR)
2920
2921 /* Gen-specific function declarations */
2922 #ifdef genX
2923 # include "anv_genX.h"
2924 #else
2925 # define genX(x) gen7_##x
2926 # include "anv_genX.h"
2927 # undef genX
2928 # define genX(x) gen75_##x
2929 # include "anv_genX.h"
2930 # undef genX
2931 # define genX(x) gen8_##x
2932 # include "anv_genX.h"
2933 # undef genX
2934 # define genX(x) gen9_##x
2935 # include "anv_genX.h"
2936 # undef genX
2937 # define genX(x) gen10_##x
2938 # include "anv_genX.h"
2939 # undef genX
2940 #endif
2941
2942 #endif /* ANV_PRIVATE_H */