2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/macros.h"
53 #include "util/hash_table.h"
54 #include "util/list.h"
56 #include "util/sparse_array.h"
57 #include "util/u_atomic.h"
58 #include "util/u_vector.h"
59 #include "util/u_math.h"
61 #include "util/xmlconfig.h"
63 #include "vk_debug_report.h"
65 /* Pre-declarations needed for WSI entrypoints */
68 typedef struct xcb_connection_t xcb_connection_t
;
69 typedef uint32_t xcb_visualid_t
;
70 typedef uint32_t xcb_window_t
;
73 struct anv_buffer_view
;
74 struct anv_image_view
;
77 struct gen_aux_map_context
;
79 struct gen_perf_config
;
81 #include <vulkan/vulkan.h>
82 #include <vulkan/vulkan_intel.h>
83 #include <vulkan/vk_icd.h>
85 #include "anv_android.h"
86 #include "anv_entrypoints.h"
87 #include "anv_extensions.h"
90 #include "dev/gen_debug.h"
91 #include "common/intel_log.h"
92 #include "wsi_common.h"
94 /* anv Virtual Memory Layout
95 * =========================
97 * When the anv driver is determining the virtual graphics addresses of memory
98 * objects itself using the softpin mechanism, the following memory ranges
101 * Three special considerations to notice:
103 * (1) the dynamic state pool is located within the same 4 GiB as the low
104 * heap. This is to work around a VF cache issue described in a comment in
105 * anv_physical_device_init_heaps.
107 * (2) the binding table pool is located at lower addresses than the surface
108 * state pool, within a 4 GiB range. This allows surface state base addresses
109 * to cover both binding tables (16 bit offsets) and surface states (32 bit
112 * (3) the last 4 GiB of the address space is withheld from the high
113 * heap. Various hardware units will read past the end of an object for
114 * various reasons. This healthy margin prevents reads from wrapping around
117 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
118 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
119 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
120 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
121 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
122 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
123 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
124 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
125 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
126 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
127 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
129 #define LOW_HEAP_SIZE \
130 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
131 #define DYNAMIC_STATE_POOL_SIZE \
132 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
133 #define BINDING_TABLE_POOL_SIZE \
134 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
135 #define SURFACE_STATE_POOL_SIZE \
136 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
137 #define INSTRUCTION_STATE_POOL_SIZE \
138 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
140 /* Allowing different clear colors requires us to perform a depth resolve at
141 * the end of certain render passes. This is because while slow clears store
142 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
143 * See the PRMs for examples describing when additional resolves would be
144 * necessary. To enable fast clears without requiring extra resolves, we set
145 * the clear value to a globally-defined one. We could allow different values
146 * if the user doesn't expect coherent data during or after a render passes
147 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
148 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
149 * 1.0f seems to be the only value used. The only application that doesn't set
150 * this value does so through the usage of an seemingly uninitialized clear
153 #define ANV_HZ_FC_VAL 1.0f
156 #define MAX_XFB_BUFFERS 4
157 #define MAX_XFB_STREAMS 4
160 #define MAX_VIEWPORTS 16
161 #define MAX_SCISSORS 16
162 #define MAX_PUSH_CONSTANTS_SIZE 128
163 #define MAX_DYNAMIC_BUFFERS 16
164 #define MAX_IMAGES 64
165 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
166 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
167 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
169 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
171 * "The surface state model is used when a Binding Table Index (specified
172 * in the message descriptor) of less than 240 is specified. In this model,
173 * the Binding Table Index is used to index into the binding table, and the
174 * binding table entry contains a pointer to the SURFACE_STATE."
176 * Binding table values above 240 are used for various things in the hardware
177 * such as stateless, stateless with incoherent cache, SLM, and bindless.
179 #define MAX_BINDING_TABLE_SIZE 240
181 /* The kernel relocation API has a limitation of a 32-bit delta value
182 * applied to the address before it is written which, in spite of it being
183 * unsigned, is treated as signed . Because of the way that this maps to
184 * the Vulkan API, we cannot handle an offset into a buffer that does not
185 * fit into a signed 32 bits. The only mechanism we have for dealing with
186 * this at the moment is to limit all VkDeviceMemory objects to a maximum
187 * of 2GB each. The Vulkan spec allows us to do this:
189 * "Some platforms may have a limit on the maximum size of a single
190 * allocation. For example, certain systems may fail to create
191 * allocations with a size greater than or equal to 4GB. Such a limit is
192 * implementation-dependent, and if such a failure occurs then the error
193 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
195 * We don't use vk_error here because it's not an error so much as an
196 * indication to the application that the allocation is too large.
198 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
200 #define ANV_SVGS_VB_INDEX MAX_VBS
201 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
203 /* We reserve this MI ALU register for the purpose of handling predication.
204 * Other code which uses the MI ALU should leave it alone.
206 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
208 /* For gen12 we set the streamout buffers using 4 separate commands
209 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
210 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
211 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
212 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
213 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
214 * 3DSTATE_SO_BUFFER_INDEX_0.
216 #define SO_BUFFER_INDEX_0_CMD 0x60
217 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
219 static inline uint32_t
220 align_down_npot_u32(uint32_t v
, uint32_t a
)
225 static inline uint32_t
226 align_u32(uint32_t v
, uint32_t a
)
228 assert(a
!= 0 && a
== (a
& -a
));
229 return (v
+ a
- 1) & ~(a
- 1);
232 static inline uint64_t
233 align_u64(uint64_t v
, uint64_t a
)
235 assert(a
!= 0 && a
== (a
& -a
));
236 return (v
+ a
- 1) & ~(a
- 1);
239 static inline int32_t
240 align_i32(int32_t v
, int32_t a
)
242 assert(a
!= 0 && a
== (a
& -a
));
243 return (v
+ a
- 1) & ~(a
- 1);
246 /** Alignment must be a power of 2. */
248 anv_is_aligned(uintmax_t n
, uintmax_t a
)
250 assert(a
== (a
& -a
));
251 return (n
& (a
- 1)) == 0;
254 static inline uint32_t
255 anv_minify(uint32_t n
, uint32_t levels
)
257 if (unlikely(n
== 0))
260 return MAX2(n
>> levels
, 1);
264 anv_clamp_f(float f
, float min
, float max
)
277 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
279 if (*inout_mask
& clear_mask
) {
280 *inout_mask
&= ~clear_mask
;
287 static inline union isl_color_value
288 vk_to_isl_color(VkClearColorValue color
)
290 return (union isl_color_value
) {
300 #define for_each_bit(b, dword) \
301 for (uint32_t __dword = (dword); \
302 (b) = __builtin_ffs(__dword) - 1, __dword; \
303 __dword &= ~(1 << (b)))
305 #define typed_memcpy(dest, src, count) ({ \
306 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
307 memcpy((dest), (src), (count) * sizeof(*(src))); \
310 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
311 * to be added here in order to utilize mapping in debug/error/perf macros.
313 #define REPORT_OBJECT_TYPE(o) \
314 __builtin_choose_expr ( \
315 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
316 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
317 __builtin_choose_expr ( \
318 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
319 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
320 __builtin_choose_expr ( \
321 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
322 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
323 __builtin_choose_expr ( \
324 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
325 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
326 __builtin_choose_expr ( \
327 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
328 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
329 __builtin_choose_expr ( \
330 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
331 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
332 __builtin_choose_expr ( \
333 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
334 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
335 __builtin_choose_expr ( \
336 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
337 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
338 __builtin_choose_expr ( \
339 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
340 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), void*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
407 /* The void expression results in a compile-time error \
408 when assigning the result to something. */ \
409 (void)0)))))))))))))))))))))))))))))))
411 /* Whenever we generate an error, pass it through this function. Useful for
412 * debugging, where we can break on it. Only call at error site, not when
413 * propagating errors. Might be useful to plug in a stack trace here.
416 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
417 VkDebugReportObjectTypeEXT type
, VkResult error
,
418 const char *file
, int line
, const char *format
,
421 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
422 VkDebugReportObjectTypeEXT type
, VkResult error
,
423 const char *file
, int line
, const char *format
, ...)
424 anv_printflike(7, 8);
427 #define vk_error(error) __vk_errorf(NULL, NULL,\
428 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
429 error, __FILE__, __LINE__, NULL)
430 #define vk_errorv(instance, obj, error, format, args)\
431 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
432 __FILE__, __LINE__, format, args)
433 #define vk_errorf(instance, obj, error, format, ...)\
434 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
435 __FILE__, __LINE__, format, ## __VA_ARGS__)
437 #define vk_error(error) error
438 #define vk_errorf(instance, obj, error, format, ...) error
442 * Warn on ignored extension structs.
444 * The Vulkan spec requires us to ignore unsupported or unknown structs in
445 * a pNext chain. In debug mode, emitting warnings for ignored structs may
446 * help us discover structs that we should not have ignored.
449 * From the Vulkan 1.0.38 spec:
451 * Any component of the implementation (the loader, any enabled layers,
452 * and drivers) must skip over, without processing (other than reading the
453 * sType and pNext members) any chained structures with sType values not
454 * defined by extensions supported by that component.
456 #define anv_debug_ignored_stype(sType) \
457 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
459 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
460 VkDebugReportObjectTypeEXT type
, const char *file
,
461 int line
, const char *format
, ...)
462 anv_printflike(6, 7);
463 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
464 void anv_loge_v(const char *format
, va_list va
);
467 * Print a FINISHME message, including its source location.
469 #define anv_finishme(format, ...) \
471 static bool reported = false; \
473 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
480 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
482 #define anv_perf_warn(instance, obj, format, ...) \
484 static bool reported = false; \
485 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
486 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
487 format, ##__VA_ARGS__); \
492 /* A non-fatal assert. Useful for debugging. */
494 #define anv_assert(x) ({ \
495 if (unlikely(!(x))) \
496 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
499 #define anv_assert(x)
502 /* A multi-pointer allocator
504 * When copying data structures from the user (such as a render pass), it's
505 * common to need to allocate data for a bunch of different things. Instead
506 * of doing several allocations and having to handle all of the error checking
507 * that entails, it can be easier to do a single allocation. This struct
508 * helps facilitate that. The intended usage looks like this:
511 * anv_multialloc_add(&ma, &main_ptr, 1);
512 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
513 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
515 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
516 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
518 struct anv_multialloc
{
526 #define ANV_MULTIALLOC_INIT \
527 ((struct anv_multialloc) { 0, })
529 #define ANV_MULTIALLOC(_name) \
530 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
532 __attribute__((always_inline
))
534 _anv_multialloc_add(struct anv_multialloc
*ma
,
535 void **ptr
, size_t size
, size_t align
)
537 size_t offset
= align_u64(ma
->size
, align
);
538 ma
->size
= offset
+ size
;
539 ma
->align
= MAX2(ma
->align
, align
);
541 /* Store the offset in the pointer. */
542 *ptr
= (void *)(uintptr_t)offset
;
544 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
545 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
548 #define anv_multialloc_add_size(_ma, _ptr, _size) \
549 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
551 #define anv_multialloc_add(_ma, _ptr, _count) \
552 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
554 __attribute__((always_inline
))
556 anv_multialloc_alloc(struct anv_multialloc
*ma
,
557 const VkAllocationCallbacks
*alloc
,
558 VkSystemAllocationScope scope
)
560 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
564 /* Fill out each of the pointers with their final value.
566 * for (uint32_t i = 0; i < ma->ptr_count; i++)
567 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
569 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
570 * constant, GCC is incapable of figuring this out and unrolling the loop
571 * so we have to give it a little help.
573 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
574 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
575 if ((_i) < ma->ptr_count) \
576 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
577 _ANV_MULTIALLOC_UPDATE_POINTER(0);
578 _ANV_MULTIALLOC_UPDATE_POINTER(1);
579 _ANV_MULTIALLOC_UPDATE_POINTER(2);
580 _ANV_MULTIALLOC_UPDATE_POINTER(3);
581 _ANV_MULTIALLOC_UPDATE_POINTER(4);
582 _ANV_MULTIALLOC_UPDATE_POINTER(5);
583 _ANV_MULTIALLOC_UPDATE_POINTER(6);
584 _ANV_MULTIALLOC_UPDATE_POINTER(7);
585 #undef _ANV_MULTIALLOC_UPDATE_POINTER
590 __attribute__((always_inline
))
592 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
593 const VkAllocationCallbacks
*parent_alloc
,
594 const VkAllocationCallbacks
*alloc
,
595 VkSystemAllocationScope scope
)
597 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
605 /* Index into the current validation list. This is used by the
606 * validation list building alrogithm to track which buffers are already
607 * in the validation list so that we can ensure uniqueness.
611 /* Last known offset. This value is provided by the kernel when we
612 * execbuf and is used as the presumed offset for the next bunch of
620 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
623 /** True if this BO may be shared with other processes */
628 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
630 bo
->gem_handle
= gem_handle
;
637 bo
->is_external
= false;
640 /* Represents a lock-free linked list of "free" things. This is used by
641 * both the block pool and the state pools. Unfortunately, in order to
642 * solve the ABA problem, we can't use a single uint32_t head.
644 union anv_free_list
{
648 /* A simple count that is incremented every time the head changes. */
651 /* Make sure it's aligned to 64 bits. This will make atomic operations
652 * faster on 32 bit platforms.
654 uint64_t u64
__attribute__ ((aligned (8)));
657 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
659 struct anv_block_state
{
665 /* Make sure it's aligned to 64 bits. This will make atomic operations
666 * faster on 32 bit platforms.
668 uint64_t u64
__attribute__ ((aligned (8)));
672 #define anv_block_pool_foreach_bo(bo, pool) \
673 for (struct anv_bo *bo = (pool)->bos; bo != &(pool)->bos[(pool)->nbos]; bo++)
675 #define ANV_MAX_BLOCK_POOL_BOS 20
677 struct anv_block_pool
{
678 struct anv_device
*device
;
682 struct anv_bo bos
[ANV_MAX_BLOCK_POOL_BOS
];
688 /* The address where the start of the pool is pinned. The various bos that
689 * are created as the pool grows will have addresses in the range
690 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
692 uint64_t start_address
;
694 /* The offset from the start of the bo to the "center" of the block
695 * pool. Pointers to allocated blocks are given by
696 * bo.map + center_bo_offset + offsets.
698 uint32_t center_bo_offset
;
700 /* Current memory map of the block pool. This pointer may or may not
701 * point to the actual beginning of the block pool memory. If
702 * anv_block_pool_alloc_back has ever been called, then this pointer
703 * will point to the "center" position of the buffer and all offsets
704 * (negative or positive) given out by the block pool alloc functions
705 * will be valid relative to this pointer.
707 * In particular, map == bo.map + center_offset
709 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
710 * since it will handle the softpin case as well, where this points to NULL.
716 * Array of mmaps and gem handles owned by the block pool, reclaimed when
717 * the block pool is destroyed.
719 struct u_vector mmap_cleanups
;
721 struct anv_block_state state
;
723 struct anv_block_state back_state
;
726 /* Block pools are backed by a fixed-size 1GB memfd */
727 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
729 /* The center of the block pool is also the middle of the memfd. This may
730 * change in the future if we decide differently for some reason.
732 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
734 static inline uint32_t
735 anv_block_pool_size(struct anv_block_pool
*pool
)
737 return pool
->state
.end
+ pool
->back_state
.end
;
747 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
749 struct anv_fixed_size_state_pool
{
750 union anv_free_list free_list
;
751 struct anv_block_state block
;
754 #define ANV_MIN_STATE_SIZE_LOG2 6
755 #define ANV_MAX_STATE_SIZE_LOG2 21
757 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
759 struct anv_free_entry
{
761 struct anv_state state
;
764 struct anv_state_table
{
765 struct anv_device
*device
;
767 struct anv_free_entry
*map
;
769 struct anv_block_state state
;
770 struct u_vector cleanups
;
773 struct anv_state_pool
{
774 struct anv_block_pool block_pool
;
776 struct anv_state_table table
;
778 /* The size of blocks which will be allocated from the block pool */
781 /** Free list for "back" allocations */
782 union anv_free_list back_alloc_free_list
;
784 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
787 struct anv_state_stream_block
;
789 struct anv_state_stream
{
790 struct anv_state_pool
*state_pool
;
792 /* The size of blocks to allocate from the state pool */
795 /* Current block we're allocating from */
796 struct anv_state block
;
798 /* Offset into the current block at which to allocate the next state */
801 /* List of all blocks allocated from this pool */
802 struct anv_state_stream_block
*block_list
;
805 /* The block_pool functions exported for testing only. The block pool should
806 * only be used via a state pool (see below).
808 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
809 struct anv_device
*device
,
810 uint64_t start_address
,
811 uint32_t initial_size
,
813 void anv_block_pool_finish(struct anv_block_pool
*pool
);
814 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
815 uint32_t block_size
, uint32_t *padding
);
816 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
817 uint32_t block_size
);
818 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
820 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
821 struct anv_device
*device
,
822 uint64_t start_address
,
825 void anv_state_pool_finish(struct anv_state_pool
*pool
);
826 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
827 uint32_t state_size
, uint32_t alignment
);
828 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
829 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
830 void anv_state_stream_init(struct anv_state_stream
*stream
,
831 struct anv_state_pool
*state_pool
,
832 uint32_t block_size
);
833 void anv_state_stream_finish(struct anv_state_stream
*stream
);
834 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
835 uint32_t size
, uint32_t alignment
);
837 VkResult
anv_state_table_init(struct anv_state_table
*table
,
838 struct anv_device
*device
,
839 uint32_t initial_entries
);
840 void anv_state_table_finish(struct anv_state_table
*table
);
841 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
843 void anv_free_list_push(union anv_free_list
*list
,
844 struct anv_state_table
*table
,
845 uint32_t idx
, uint32_t count
);
846 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
847 struct anv_state_table
*table
);
850 static inline struct anv_state
*
851 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
853 return &table
->map
[idx
].state
;
856 * Implements a pool of re-usable BOs. The interface is identical to that
857 * of block_pool except that each block is its own BO.
860 struct anv_device
*device
;
867 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
869 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
870 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
872 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
874 struct anv_scratch_bo
{
879 struct anv_scratch_pool
{
880 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
881 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
884 void anv_scratch_pool_init(struct anv_device
*device
,
885 struct anv_scratch_pool
*pool
);
886 void anv_scratch_pool_finish(struct anv_device
*device
,
887 struct anv_scratch_pool
*pool
);
888 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
889 struct anv_scratch_pool
*pool
,
890 gl_shader_stage stage
,
891 unsigned per_thread_scratch
);
893 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
894 struct anv_bo_cache
{
895 struct util_sparse_array bo_map
;
896 pthread_mutex_t mutex
;
899 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
900 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
901 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
902 struct anv_bo_cache
*cache
,
903 uint64_t size
, uint64_t bo_flags
,
906 VkResult
anv_bo_cache_import_host_ptr(struct anv_device
*device
,
907 struct anv_bo_cache
*cache
,
908 void *host_ptr
, uint32_t size
,
909 uint64_t bo_flags
, struct anv_bo
**bo_out
);
910 VkResult
anv_bo_cache_import(struct anv_device
*device
,
911 struct anv_bo_cache
*cache
,
912 int fd
, uint64_t bo_flags
,
914 VkResult
anv_bo_cache_export(struct anv_device
*device
,
915 struct anv_bo_cache
*cache
,
916 struct anv_bo
*bo_in
, int *fd_out
);
917 void anv_bo_cache_release(struct anv_device
*device
,
918 struct anv_bo_cache
*cache
,
921 struct anv_memory_type
{
922 /* Standard bits passed on to the client */
923 VkMemoryPropertyFlags propertyFlags
;
926 /* Driver-internal book-keeping */
927 VkBufferUsageFlags valid_buffer_usage
;
930 struct anv_memory_heap
{
931 /* Standard bits passed on to the client */
933 VkMemoryHeapFlags flags
;
935 /* Driver-internal book-keeping */
938 bool supports_48bit_addresses
;
942 struct anv_physical_device
{
943 VK_LOADER_DATA _loader_data
;
945 struct anv_instance
* instance
;
956 struct gen_device_info info
;
957 /** Amount of "GPU memory" we want to advertise
959 * Clearly, this value is bogus since Intel is a UMA architecture. On
960 * gen7 platforms, we are limited by GTT size unless we want to implement
961 * fine-grained tracking and GTT splitting. On Broadwell and above we are
962 * practically unlimited. However, we will never report more than 3/4 of
963 * the total system ram to try and avoid running out of RAM.
965 bool supports_48bit_addresses
;
966 struct brw_compiler
* compiler
;
967 struct isl_device isl_dev
;
968 struct gen_perf_config
* perf
;
969 int cmd_parser_version
;
971 bool has_exec_capture
;
974 bool has_syncobj_wait
;
975 bool has_context_priority
;
977 bool has_context_isolation
;
978 bool has_mem_available
;
979 bool always_use_bindless
;
981 /** True if we can access buffers using A64 messages */
982 bool has_a64_buffer_access
;
983 /** True if we can use bindless access for images */
984 bool has_bindless_images
;
985 /** True if we can use bindless access for samplers */
986 bool has_bindless_samplers
;
988 struct anv_device_extension_table supported_extensions
;
989 struct anv_physical_device_dispatch_table dispatch
;
992 uint32_t subslice_total
;
996 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
998 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1001 uint8_t driver_build_sha1
[20];
1002 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1003 uint8_t driver_uuid
[VK_UUID_SIZE
];
1004 uint8_t device_uuid
[VK_UUID_SIZE
];
1006 struct disk_cache
* disk_cache
;
1008 struct wsi_device wsi_device
;
1013 struct anv_app_info
{
1014 const char* app_name
;
1015 uint32_t app_version
;
1016 const char* engine_name
;
1017 uint32_t engine_version
;
1018 uint32_t api_version
;
1021 struct anv_instance
{
1022 VK_LOADER_DATA _loader_data
;
1024 VkAllocationCallbacks alloc
;
1026 struct anv_app_info app_info
;
1028 struct anv_instance_extension_table enabled_extensions
;
1029 struct anv_instance_dispatch_table dispatch
;
1030 struct anv_device_dispatch_table device_dispatch
;
1032 int physicalDeviceCount
;
1033 struct anv_physical_device physicalDevice
;
1035 bool pipeline_cache_enabled
;
1037 struct vk_debug_report_instance debug_report_callbacks
;
1039 struct driOptionCache dri_options
;
1040 struct driOptionCache available_dri_options
;
1043 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1044 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1046 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1047 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1051 VK_LOADER_DATA _loader_data
;
1053 struct anv_device
* device
;
1055 VkDeviceQueueCreateFlags flags
;
1058 struct anv_pipeline_cache
{
1059 struct anv_device
* device
;
1060 pthread_mutex_t mutex
;
1062 struct hash_table
* nir_cache
;
1064 struct hash_table
* cache
;
1067 struct nir_xfb_info
;
1068 struct anv_pipeline_bind_map
;
1070 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1071 struct anv_device
*device
,
1072 bool cache_enabled
);
1073 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1075 struct anv_shader_bin
*
1076 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1077 const void *key
, uint32_t key_size
);
1078 struct anv_shader_bin
*
1079 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1080 const void *key_data
, uint32_t key_size
,
1081 const void *kernel_data
, uint32_t kernel_size
,
1082 const void *constant_data
,
1083 uint32_t constant_data_size
,
1084 const struct brw_stage_prog_data
*prog_data
,
1085 uint32_t prog_data_size
,
1086 const struct brw_compile_stats
*stats
,
1088 const struct nir_xfb_info
*xfb_info
,
1089 const struct anv_pipeline_bind_map
*bind_map
);
1091 struct anv_shader_bin
*
1092 anv_device_search_for_kernel(struct anv_device
*device
,
1093 struct anv_pipeline_cache
*cache
,
1094 const void *key_data
, uint32_t key_size
,
1095 bool *user_cache_bit
);
1097 struct anv_shader_bin
*
1098 anv_device_upload_kernel(struct anv_device
*device
,
1099 struct anv_pipeline_cache
*cache
,
1100 const void *key_data
, uint32_t key_size
,
1101 const void *kernel_data
, uint32_t kernel_size
,
1102 const void *constant_data
,
1103 uint32_t constant_data_size
,
1104 const struct brw_stage_prog_data
*prog_data
,
1105 uint32_t prog_data_size
,
1106 const struct brw_compile_stats
*stats
,
1108 const struct nir_xfb_info
*xfb_info
,
1109 const struct anv_pipeline_bind_map
*bind_map
);
1112 struct nir_shader_compiler_options
;
1115 anv_device_search_for_nir(struct anv_device
*device
,
1116 struct anv_pipeline_cache
*cache
,
1117 const struct nir_shader_compiler_options
*nir_options
,
1118 unsigned char sha1_key
[20],
1122 anv_device_upload_nir(struct anv_device
*device
,
1123 struct anv_pipeline_cache
*cache
,
1124 const struct nir_shader
*nir
,
1125 unsigned char sha1_key
[20]);
1128 VK_LOADER_DATA _loader_data
;
1130 VkAllocationCallbacks alloc
;
1132 struct anv_instance
* instance
;
1133 uint32_t chipset_id
;
1135 struct gen_device_info info
;
1136 struct isl_device isl_dev
;
1139 bool can_chain_batches
;
1140 bool robust_buffer_access
;
1141 struct anv_device_extension_table enabled_extensions
;
1142 struct anv_device_dispatch_table dispatch
;
1144 pthread_mutex_t vma_mutex
;
1145 struct util_vma_heap vma_lo
;
1146 struct util_vma_heap vma_hi
;
1147 uint64_t vma_lo_available
;
1148 uint64_t vma_hi_available
;
1150 /** List of all anv_device_memory objects */
1151 struct list_head memory_objects
;
1153 struct anv_bo_pool batch_bo_pool
;
1155 struct anv_bo_cache bo_cache
;
1157 struct anv_state_pool dynamic_state_pool
;
1158 struct anv_state_pool instruction_state_pool
;
1159 struct anv_state_pool binding_table_pool
;
1160 struct anv_state_pool surface_state_pool
;
1162 struct anv_bo workaround_bo
;
1163 struct anv_bo trivial_batch_bo
;
1164 struct anv_bo hiz_clear_bo
;
1166 struct anv_pipeline_cache default_pipeline_cache
;
1167 struct blorp_context blorp
;
1169 struct anv_state border_colors
;
1171 struct anv_state slice_hash
;
1173 struct anv_queue queue
;
1175 struct anv_scratch_pool scratch_pool
;
1177 uint32_t default_mocs
;
1178 uint32_t external_mocs
;
1180 pthread_mutex_t mutex
;
1181 pthread_cond_t queue_submit
;
1184 struct gen_batch_decode_ctx decoder_ctx
;
1186 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1187 * the cmd_buffer's list.
1189 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1191 int perf_fd
; /* -1 if no opened */
1192 uint64_t perf_metric
; /* 0 if unset */
1194 struct gen_aux_map_context
*aux_map_ctx
;
1197 static inline struct anv_state_pool
*
1198 anv_binding_table_pool(struct anv_device
*device
)
1200 if (device
->instance
->physicalDevice
.use_softpin
)
1201 return &device
->binding_table_pool
;
1203 return &device
->surface_state_pool
;
1206 static inline struct anv_state
1207 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1208 if (device
->instance
->physicalDevice
.use_softpin
)
1209 return anv_state_pool_alloc(&device
->binding_table_pool
,
1210 device
->binding_table_pool
.block_size
, 0);
1212 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1216 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1217 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1220 static inline uint32_t
1221 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1223 if (bo
->is_external
)
1224 return device
->external_mocs
;
1226 return device
->default_mocs
;
1229 void anv_device_init_blorp(struct anv_device
*device
);
1230 void anv_device_finish_blorp(struct anv_device
*device
);
1232 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1233 const char *file
, int line
,
1234 const char *msg
, ...)
1235 anv_printflike(4, 5);
1236 #define anv_device_set_lost(dev, ...) \
1237 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1240 anv_device_is_lost(struct anv_device
*device
)
1242 return unlikely(device
->_lost
);
1245 VkResult
anv_device_execbuf(struct anv_device
*device
,
1246 struct drm_i915_gem_execbuffer2
*execbuf
,
1247 struct anv_bo
**execbuf_bos
);
1248 VkResult
anv_device_query_status(struct anv_device
*device
);
1249 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1250 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1253 void* anv_gem_mmap(struct anv_device
*device
,
1254 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1255 void anv_gem_munmap(void *p
, uint64_t size
);
1256 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1257 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1258 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1259 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1260 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1261 int anv_gem_execbuffer(struct anv_device
*device
,
1262 struct drm_i915_gem_execbuffer2
*execbuf
);
1263 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1264 uint32_t stride
, uint32_t tiling
);
1265 int anv_gem_create_context(struct anv_device
*device
);
1266 bool anv_gem_has_context_priority(int fd
);
1267 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1268 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1270 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1272 int anv_gem_get_param(int fd
, uint32_t param
);
1273 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1274 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1275 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1276 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1277 uint32_t *active
, uint32_t *pending
);
1278 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1279 int anv_gem_reg_read(struct anv_device
*device
,
1280 uint32_t offset
, uint64_t *result
);
1281 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1282 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1283 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1284 uint32_t read_domains
, uint32_t write_domain
);
1285 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1286 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1287 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1288 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1289 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1290 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1292 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1293 uint32_t handle
, int fd
);
1294 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1295 bool anv_gem_supports_syncobj_wait(int fd
);
1296 int anv_gem_syncobj_wait(struct anv_device
*device
,
1297 uint32_t *handles
, uint32_t num_handles
,
1298 int64_t abs_timeout_ns
, bool wait_all
);
1300 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1301 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1303 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1305 struct anv_reloc_list
{
1306 uint32_t num_relocs
;
1307 uint32_t array_length
;
1308 struct drm_i915_gem_relocation_entry
* relocs
;
1309 struct anv_bo
** reloc_bos
;
1313 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1314 const VkAllocationCallbacks
*alloc
);
1315 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1316 const VkAllocationCallbacks
*alloc
);
1318 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1319 const VkAllocationCallbacks
*alloc
,
1320 uint32_t offset
, struct anv_bo
*target_bo
,
1321 uint32_t delta
, uint64_t *address_u64_out
);
1323 struct anv_batch_bo
{
1324 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1325 struct list_head link
;
1329 /* Bytes actually consumed in this batch BO */
1332 struct anv_reloc_list relocs
;
1336 const VkAllocationCallbacks
* alloc
;
1342 struct anv_reloc_list
* relocs
;
1344 /* This callback is called (with the associated user data) in the event
1345 * that the batch runs out of space.
1347 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1351 * Current error status of the command buffer. Used to track inconsistent
1352 * or incomplete command buffer states that are the consequence of run-time
1353 * errors such as out of memory scenarios. We want to track this in the
1354 * batch because the command buffer object is not visible to some parts
1360 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1361 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1362 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1363 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1364 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1365 struct anv_batch
*batch
);
1367 static inline VkResult
1368 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1370 assert(error
!= VK_SUCCESS
);
1371 if (batch
->status
== VK_SUCCESS
)
1372 batch
->status
= error
;
1373 return batch
->status
;
1377 anv_batch_has_error(struct anv_batch
*batch
)
1379 return batch
->status
!= VK_SUCCESS
;
1382 struct anv_address
{
1387 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1390 anv_address_is_null(struct anv_address addr
)
1392 return addr
.bo
== NULL
&& addr
.offset
== 0;
1395 static inline uint64_t
1396 anv_address_physical(struct anv_address addr
)
1398 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1399 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1401 return gen_canonical_address(addr
.offset
);
1404 static inline struct anv_address
1405 anv_address_add(struct anv_address addr
, uint64_t offset
)
1407 addr
.offset
+= offset
;
1412 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1414 unsigned reloc_size
= 0;
1415 if (device
->info
.gen
>= 8) {
1416 reloc_size
= sizeof(uint64_t);
1417 *(uint64_t *)p
= gen_canonical_address(v
);
1419 reloc_size
= sizeof(uint32_t);
1423 if (flush
&& !device
->info
.has_llc
)
1424 gen_flush_range(p
, reloc_size
);
1427 static inline uint64_t
1428 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1429 const struct anv_address address
, uint32_t delta
)
1431 if (address
.bo
== NULL
) {
1432 return address
.offset
+ delta
;
1434 assert(batch
->start
<= location
&& location
< batch
->end
);
1436 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1440 #define __gen_address_type struct anv_address
1441 #define __gen_user_data struct anv_batch
1442 #define __gen_combine_address _anv_combine_address
1444 /* Wrapper macros needed to work around preprocessor argument issues. In
1445 * particular, arguments don't get pre-evaluated if they are concatenated.
1446 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1447 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1448 * We can work around this easily enough with these helpers.
1450 #define __anv_cmd_length(cmd) cmd ## _length
1451 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1452 #define __anv_cmd_header(cmd) cmd ## _header
1453 #define __anv_cmd_pack(cmd) cmd ## _pack
1454 #define __anv_reg_num(reg) reg ## _num
1456 #define anv_pack_struct(dst, struc, ...) do { \
1457 struct struc __template = { \
1460 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1461 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1464 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1465 void *__dst = anv_batch_emit_dwords(batch, n); \
1467 struct cmd __template = { \
1468 __anv_cmd_header(cmd), \
1469 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1472 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1477 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1481 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1482 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1485 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1486 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1487 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1490 #define anv_batch_emit(batch, cmd, name) \
1491 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1492 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1493 __builtin_expect(_dst != NULL, 1); \
1494 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1495 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1499 /* MEMORY_OBJECT_CONTROL_STATE:
1500 * .GraphicsDataTypeGFDT = 0,
1501 * .LLCCacheabilityControlLLCCC = 0,
1502 * .L3CacheabilityControlL3CC = 1,
1506 /* MEMORY_OBJECT_CONTROL_STATE:
1507 * .LLCeLLCCacheabilityControlLLCCC = 0,
1508 * .L3CacheabilityControlL3CC = 1,
1510 #define GEN75_MOCS 1
1512 /* MEMORY_OBJECT_CONTROL_STATE:
1513 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1514 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1515 * .AgeforQUADLRU = 0
1517 #define GEN8_MOCS 0x78
1519 /* MEMORY_OBJECT_CONTROL_STATE:
1520 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1521 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1522 * .AgeforQUADLRU = 0
1524 #define GEN8_EXTERNAL_MOCS 0x18
1526 /* Skylake: MOCS is now an index into an array of 62 different caching
1527 * configurations programmed by the kernel.
1530 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1531 #define GEN9_MOCS (2 << 1)
1533 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1534 #define GEN9_EXTERNAL_MOCS (1 << 1)
1536 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1537 #define GEN10_MOCS GEN9_MOCS
1538 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1540 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1541 #define GEN11_MOCS GEN9_MOCS
1542 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1544 /* TigerLake MOCS */
1545 #define GEN12_MOCS GEN9_MOCS
1546 /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
1547 #define GEN12_EXTERNAL_MOCS (3 << 1)
1549 struct anv_device_memory
{
1550 struct list_head link
;
1553 struct anv_memory_type
* type
;
1554 VkDeviceSize map_size
;
1557 /* If set, we are holding reference to AHardwareBuffer
1558 * which we must release when memory is freed.
1560 struct AHardwareBuffer
* ahw
;
1562 /* If set, this memory comes from a host pointer. */
1567 * Header for Vertex URB Entry (VUE)
1569 struct anv_vue_header
{
1571 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1572 uint32_t ViewportIndex
;
1576 /** Struct representing a sampled image descriptor
1578 * This descriptor layout is used for sampled images, bare sampler, and
1579 * combined image/sampler descriptors.
1581 struct anv_sampled_image_descriptor
{
1582 /** Bindless image handle
1584 * This is expected to already be shifted such that the 20-bit
1585 * SURFACE_STATE table index is in the top 20 bits.
1589 /** Bindless sampler handle
1591 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1592 * to the dynamic state base address.
1597 struct anv_texture_swizzle_descriptor
{
1600 * See also nir_intrinsic_channel_select_intel
1604 /** Unused padding to ensure the struct is a multiple of 64 bits */
1608 /** Struct representing a storage image descriptor */
1609 struct anv_storage_image_descriptor
{
1610 /** Bindless image handles
1612 * These are expected to already be shifted such that the 20-bit
1613 * SURFACE_STATE table index is in the top 20 bits.
1615 uint32_t read_write
;
1616 uint32_t write_only
;
1619 /** Struct representing a address/range descriptor
1621 * The fields of this struct correspond directly to the data layout of
1622 * nir_address_format_64bit_bounded_global addresses. The last field is the
1623 * offset in the NIR address so it must be zero so that when you load the
1624 * descriptor you get a pointer to the start of the range.
1626 struct anv_address_range_descriptor
{
1632 enum anv_descriptor_data
{
1633 /** The descriptor contains a BTI reference to a surface state */
1634 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1635 /** The descriptor contains a BTI reference to a sampler state */
1636 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1637 /** The descriptor contains an actual buffer view */
1638 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1639 /** The descriptor contains auxiliary image layout data */
1640 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1641 /** The descriptor contains auxiliary image layout data */
1642 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1643 /** anv_address_range_descriptor with a buffer address and range */
1644 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1645 /** Bindless surface handle */
1646 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1647 /** Storage image handles */
1648 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1649 /** Storage image handles */
1650 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1653 struct anv_descriptor_set_binding_layout
{
1655 /* The type of the descriptors in this binding */
1656 VkDescriptorType type
;
1659 /* Flags provided when this binding was created */
1660 VkDescriptorBindingFlagsEXT flags
;
1662 /* Bitfield representing the type of data this descriptor contains */
1663 enum anv_descriptor_data data
;
1665 /* Maximum number of YCbCr texture/sampler planes */
1666 uint8_t max_plane_count
;
1668 /* Number of array elements in this binding (or size in bytes for inline
1671 uint16_t array_size
;
1673 /* Index into the flattend descriptor set */
1674 uint16_t descriptor_index
;
1676 /* Index into the dynamic state array for a dynamic buffer */
1677 int16_t dynamic_offset_index
;
1679 /* Index into the descriptor set buffer views */
1680 int16_t buffer_view_index
;
1682 /* Offset into the descriptor buffer where this descriptor lives */
1683 uint32_t descriptor_offset
;
1685 /* Immutable samplers (or NULL if no immutable samplers) */
1686 struct anv_sampler
**immutable_samplers
;
1689 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1691 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1692 VkDescriptorType type
);
1694 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1695 const struct anv_descriptor_set_binding_layout
*binding
,
1698 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1699 const struct anv_descriptor_set_binding_layout
*binding
,
1702 struct anv_descriptor_set_layout
{
1703 /* Descriptor set layouts can be destroyed at almost any time */
1706 /* Number of bindings in this descriptor set */
1707 uint16_t binding_count
;
1709 /* Total size of the descriptor set with room for all array entries */
1712 /* Shader stages affected by this descriptor set */
1713 uint16_t shader_stages
;
1715 /* Number of buffer views in this descriptor set */
1716 uint16_t buffer_view_count
;
1718 /* Number of dynamic offsets used by this descriptor set */
1719 uint16_t dynamic_offset_count
;
1721 /* Size of the descriptor buffer for this descriptor set */
1722 uint32_t descriptor_buffer_size
;
1724 /* Bindings in this descriptor set */
1725 struct anv_descriptor_set_binding_layout binding
[0];
1729 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1731 assert(layout
&& layout
->ref_cnt
>= 1);
1732 p_atomic_inc(&layout
->ref_cnt
);
1736 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1737 struct anv_descriptor_set_layout
*layout
)
1739 assert(layout
&& layout
->ref_cnt
>= 1);
1740 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1741 vk_free(&device
->alloc
, layout
);
1744 struct anv_descriptor
{
1745 VkDescriptorType type
;
1749 VkImageLayout layout
;
1750 struct anv_image_view
*image_view
;
1751 struct anv_sampler
*sampler
;
1755 struct anv_buffer
*buffer
;
1760 struct anv_buffer_view
*buffer_view
;
1764 struct anv_descriptor_set
{
1765 struct anv_descriptor_pool
*pool
;
1766 struct anv_descriptor_set_layout
*layout
;
1769 /* State relative to anv_descriptor_pool::bo */
1770 struct anv_state desc_mem
;
1771 /* Surface state for the descriptor buffer */
1772 struct anv_state desc_surface_state
;
1774 uint32_t buffer_view_count
;
1775 struct anv_buffer_view
*buffer_views
;
1777 /* Link to descriptor pool's desc_sets list . */
1778 struct list_head pool_link
;
1780 struct anv_descriptor descriptors
[0];
1783 struct anv_buffer_view
{
1784 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1785 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1787 struct anv_address address
;
1789 struct anv_state surface_state
;
1790 struct anv_state storage_surface_state
;
1791 struct anv_state writeonly_storage_surface_state
;
1793 struct brw_image_param storage_image_param
;
1796 struct anv_push_descriptor_set
{
1797 struct anv_descriptor_set set
;
1799 /* Put this field right behind anv_descriptor_set so it fills up the
1800 * descriptors[0] field. */
1801 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1803 /** True if the descriptor set buffer has been referenced by a draw or
1806 bool set_used_on_gpu
;
1808 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1811 struct anv_descriptor_pool
{
1817 struct util_vma_heap bo_heap
;
1819 struct anv_state_stream surface_state_stream
;
1820 void *surface_state_free_list
;
1822 struct list_head desc_sets
;
1827 enum anv_descriptor_template_entry_type
{
1828 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1829 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1830 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1833 struct anv_descriptor_template_entry
{
1834 /* The type of descriptor in this entry */
1835 VkDescriptorType type
;
1837 /* Binding in the descriptor set */
1840 /* Offset at which to write into the descriptor set binding */
1841 uint32_t array_element
;
1843 /* Number of elements to write into the descriptor set binding */
1844 uint32_t array_count
;
1846 /* Offset into the user provided data */
1849 /* Stride between elements into the user provided data */
1853 struct anv_descriptor_update_template
{
1854 VkPipelineBindPoint bind_point
;
1856 /* The descriptor set this template corresponds to. This value is only
1857 * valid if the template was created with the templateType
1858 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1862 /* Number of entries in this template */
1863 uint32_t entry_count
;
1865 /* Entries of the template */
1866 struct anv_descriptor_template_entry entries
[0];
1870 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1873 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1874 struct anv_descriptor_set
*set
,
1875 const VkDescriptorImageInfo
* const info
,
1876 VkDescriptorType type
,
1881 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1882 struct anv_descriptor_set
*set
,
1883 VkDescriptorType type
,
1884 struct anv_buffer_view
*buffer_view
,
1889 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1890 struct anv_descriptor_set
*set
,
1891 struct anv_state_stream
*alloc_stream
,
1892 VkDescriptorType type
,
1893 struct anv_buffer
*buffer
,
1896 VkDeviceSize offset
,
1897 VkDeviceSize range
);
1899 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1900 struct anv_descriptor_set
*set
,
1907 anv_descriptor_set_write_template(struct anv_device
*device
,
1908 struct anv_descriptor_set
*set
,
1909 struct anv_state_stream
*alloc_stream
,
1910 const struct anv_descriptor_update_template
*template,
1914 anv_descriptor_set_create(struct anv_device
*device
,
1915 struct anv_descriptor_pool
*pool
,
1916 struct anv_descriptor_set_layout
*layout
,
1917 struct anv_descriptor_set
**out_set
);
1920 anv_descriptor_set_destroy(struct anv_device
*device
,
1921 struct anv_descriptor_pool
*pool
,
1922 struct anv_descriptor_set
*set
);
1924 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
1925 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
1926 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1927 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1929 struct anv_pipeline_binding
{
1930 /* The descriptor set this surface corresponds to. The special value of
1931 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1932 * to a color attachment and not a regular descriptor.
1936 /* Binding in the descriptor set */
1939 /* Index in the binding */
1942 /* Plane in the binding index */
1945 /* Input attachment index (relative to the subpass) */
1946 uint8_t input_attachment_index
;
1948 /* For a storage image, whether it is write-only */
1952 struct anv_pipeline_layout
{
1954 struct anv_descriptor_set_layout
*layout
;
1955 uint32_t dynamic_offset_start
;
1960 unsigned char sha1
[20];
1964 struct anv_device
* device
;
1967 VkBufferUsageFlags usage
;
1969 /* Set when bound */
1970 struct anv_address address
;
1973 static inline uint64_t
1974 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1976 assert(offset
<= buffer
->size
);
1977 if (range
== VK_WHOLE_SIZE
) {
1978 return buffer
->size
- offset
;
1980 assert(range
+ offset
>= range
);
1981 assert(range
+ offset
<= buffer
->size
);
1986 enum anv_cmd_dirty_bits
{
1987 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1988 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1989 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1990 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1991 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1992 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1993 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1994 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1995 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1996 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1997 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1998 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1999 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2000 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2002 typedef uint32_t anv_cmd_dirty_mask_t
;
2004 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2005 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2006 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2007 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2008 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2009 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2010 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2011 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2012 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2013 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2014 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2016 static inline enum anv_cmd_dirty_bits
2017 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2020 case VK_DYNAMIC_STATE_VIEWPORT
:
2021 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2022 case VK_DYNAMIC_STATE_SCISSOR
:
2023 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2024 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2025 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2026 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2027 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2028 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2029 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2030 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2031 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2032 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2033 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2034 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2035 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2036 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2037 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2038 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2039 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2041 assert(!"Unsupported dynamic state");
2047 enum anv_pipe_bits
{
2048 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2049 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2050 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2051 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2052 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2053 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2054 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2055 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2056 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2057 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2058 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2059 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2061 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2062 * a flush has happened but not a CS stall. The next time we do any sort
2063 * of invalidation we need to insert a CS stall at that time. Otherwise,
2064 * we would have to CS stall on every flush which could be bad.
2066 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2068 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2069 * target operations related to transfer commands with VkBuffer as
2070 * destination are ongoing. Some operations like copies on the command
2071 * streamer might need to be aware of this to trigger the appropriate stall
2072 * before they can proceed with the copy.
2074 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2077 #define ANV_PIPE_FLUSH_BITS ( \
2078 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2079 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2080 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2081 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2083 #define ANV_PIPE_STALL_BITS ( \
2084 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2085 ANV_PIPE_DEPTH_STALL_BIT | \
2086 ANV_PIPE_CS_STALL_BIT)
2088 #define ANV_PIPE_INVALIDATE_BITS ( \
2089 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2090 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2091 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2092 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2093 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2094 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2096 static inline enum anv_pipe_bits
2097 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2099 enum anv_pipe_bits pipe_bits
= 0;
2102 for_each_bit(b
, flags
) {
2103 switch ((VkAccessFlagBits
)(1 << b
)) {
2104 case VK_ACCESS_SHADER_WRITE_BIT
:
2105 /* We're transitioning a buffer that was previously used as write
2106 * destination through the data port. To make its content available
2107 * to future operations, flush the data cache.
2109 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2111 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2112 /* We're transitioning a buffer that was previously used as render
2113 * target. To make its content available to future operations, flush
2114 * the render target cache.
2116 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2118 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2119 /* We're transitioning a buffer that was previously used as depth
2120 * buffer. To make its content available to future operations, flush
2123 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2125 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2126 /* We're transitioning a buffer that was previously used as a
2127 * transfer write destination. Generic write operations include color
2128 * & depth operations as well as buffer operations like :
2129 * - vkCmdClearColorImage()
2130 * - vkCmdClearDepthStencilImage()
2131 * - vkCmdBlitImage()
2132 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2134 * Most of these operations are implemented using Blorp which writes
2135 * through the render target, so flush that cache to make it visible
2136 * to future operations. And for depth related operations we also
2137 * need to flush the depth cache.
2139 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2140 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2142 case VK_ACCESS_MEMORY_WRITE_BIT
:
2143 /* We're transitioning a buffer for generic write operations. Flush
2146 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2149 break; /* Nothing to do */
2156 static inline enum anv_pipe_bits
2157 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2159 enum anv_pipe_bits pipe_bits
= 0;
2162 for_each_bit(b
, flags
) {
2163 switch ((VkAccessFlagBits
)(1 << b
)) {
2164 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2165 /* Indirect draw commands take a buffer as input that we're going to
2166 * read from the command streamer to load some of the HW registers
2167 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2168 * command streamer stall so that all the cache flushes have
2169 * completed before the command streamer loads from memory.
2171 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2172 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2173 * through a vertex buffer, so invalidate that cache.
2175 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2176 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2177 * UBO from the buffer, so we need to invalidate constant cache.
2179 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2181 case VK_ACCESS_INDEX_READ_BIT
:
2182 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2183 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2184 * commands, so we invalidate the VF cache to make sure there is no
2185 * stale data when we start rendering.
2187 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2189 case VK_ACCESS_UNIFORM_READ_BIT
:
2190 /* We transitioning a buffer to be used as uniform data. Because
2191 * uniform is accessed through the data port & sampler, we need to
2192 * invalidate the texture cache (sampler) & constant cache (data
2193 * port) to avoid stale data.
2195 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2196 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2198 case VK_ACCESS_SHADER_READ_BIT
:
2199 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2200 case VK_ACCESS_TRANSFER_READ_BIT
:
2201 /* Transitioning a buffer to be read through the sampler, so
2202 * invalidate the texture cache, we don't want any stale data.
2204 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2206 case VK_ACCESS_MEMORY_READ_BIT
:
2207 /* Transitioning a buffer for generic read, invalidate all the
2210 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2212 case VK_ACCESS_MEMORY_WRITE_BIT
:
2213 /* Generic write, make sure all previously written things land in
2216 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2218 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2219 /* Transitioning a buffer for conditional rendering. We'll load the
2220 * content of this buffer into HW registers using the command
2221 * streamer, so we need to stall the command streamer to make sure
2222 * any in-flight flush operations have completed.
2224 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2227 break; /* Nothing to do */
2234 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2235 VK_IMAGE_ASPECT_COLOR_BIT | \
2236 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2237 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2238 VK_IMAGE_ASPECT_PLANE_2_BIT)
2239 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2240 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2241 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2242 VK_IMAGE_ASPECT_PLANE_2_BIT)
2244 struct anv_vertex_binding
{
2245 struct anv_buffer
* buffer
;
2246 VkDeviceSize offset
;
2249 struct anv_xfb_binding
{
2250 struct anv_buffer
* buffer
;
2251 VkDeviceSize offset
;
2255 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
2256 #define ANV_PARAM_IS_PUSH(param) ((uint32_t)(param) >> 16 == 1)
2257 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2259 #define ANV_PARAM_DYN_OFFSET(offset) ((2 << 16) | (uint32_t)(offset))
2260 #define ANV_PARAM_IS_DYN_OFFSET(param) ((uint32_t)(param) >> 16 == 2)
2261 #define ANV_PARAM_DYN_OFFSET_IDX(param) ((param) & 0xffff)
2263 struct anv_push_constants
{
2264 /* Push constant data provided by the client through vkPushConstants */
2265 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2267 /* Used for vkCmdDispatchBase */
2268 uint32_t base_work_group_id
[3];
2271 struct anv_dynamic_state
{
2274 VkViewport viewports
[MAX_VIEWPORTS
];
2279 VkRect2D scissors
[MAX_SCISSORS
];
2290 float blend_constants
[4];
2300 } stencil_compare_mask
;
2305 } stencil_write_mask
;
2310 } stencil_reference
;
2318 extern const struct anv_dynamic_state default_dynamic_state
;
2320 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2321 const struct anv_dynamic_state
*src
,
2322 uint32_t copy_mask
);
2324 struct anv_surface_state
{
2325 struct anv_state state
;
2326 /** Address of the surface referred to by this state
2328 * This address is relative to the start of the BO.
2330 struct anv_address address
;
2331 /* Address of the aux surface, if any
2333 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2335 * With the exception of gen8, the bottom 12 bits of this address' offset
2336 * include extra aux information.
2338 struct anv_address aux_address
;
2339 /* Address of the clear color, if any
2341 * This address is relative to the start of the BO.
2343 struct anv_address clear_address
;
2347 * Attachment state when recording a renderpass instance.
2349 * The clear value is valid only if there exists a pending clear.
2351 struct anv_attachment_state
{
2352 enum isl_aux_usage aux_usage
;
2353 enum isl_aux_usage input_aux_usage
;
2354 struct anv_surface_state color
;
2355 struct anv_surface_state input
;
2357 VkImageLayout current_layout
;
2358 VkImageAspectFlags pending_clear_aspects
;
2359 VkImageAspectFlags pending_load_aspects
;
2361 VkClearValue clear_value
;
2362 bool clear_color_is_zero_one
;
2363 bool clear_color_is_zero
;
2365 /* When multiview is active, attachments with a renderpass clear
2366 * operation have their respective layers cleared on the first
2367 * subpass that uses them, and only in that subpass. We keep track
2368 * of this using a bitfield to indicate which layers of an attachment
2369 * have not been cleared yet when multiview is active.
2371 uint32_t pending_clear_views
;
2372 struct anv_image_view
* image_view
;
2375 /** State tracking for particular pipeline bind point
2377 * This struct is the base struct for anv_cmd_graphics_state and
2378 * anv_cmd_compute_state. These are used to track state which is bound to a
2379 * particular type of pipeline. Generic state that applies per-stage such as
2380 * binding table offsets and push constants is tracked generically with a
2381 * per-stage array in anv_cmd_state.
2383 struct anv_cmd_pipeline_state
{
2384 struct anv_pipeline
*pipeline
;
2385 struct anv_pipeline_layout
*layout
;
2387 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2388 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2390 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2393 /** State tracking for graphics pipeline
2395 * This has anv_cmd_pipeline_state as a base struct to track things which get
2396 * bound to a graphics pipeline. Along with general pipeline bind point state
2397 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2398 * state which is graphics-specific.
2400 struct anv_cmd_graphics_state
{
2401 struct anv_cmd_pipeline_state base
;
2403 anv_cmd_dirty_mask_t dirty
;
2406 struct anv_dynamic_state dynamic
;
2409 struct anv_buffer
*index_buffer
;
2410 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2411 uint32_t index_offset
;
2415 /** State tracking for compute pipeline
2417 * This has anv_cmd_pipeline_state as a base struct to track things which get
2418 * bound to a compute pipeline. Along with general pipeline bind point state
2419 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2420 * state which is compute-specific.
2422 struct anv_cmd_compute_state
{
2423 struct anv_cmd_pipeline_state base
;
2425 bool pipeline_dirty
;
2427 struct anv_address num_workgroups
;
2430 /** State required while building cmd buffer */
2431 struct anv_cmd_state
{
2432 /* PIPELINE_SELECT.PipelineSelection */
2433 uint32_t current_pipeline
;
2434 const struct gen_l3_config
* current_l3_config
;
2435 uint32_t last_aux_map_state
;
2437 struct anv_cmd_graphics_state gfx
;
2438 struct anv_cmd_compute_state compute
;
2440 enum anv_pipe_bits pending_pipe_bits
;
2441 VkShaderStageFlags descriptors_dirty
;
2442 VkShaderStageFlags push_constants_dirty
;
2444 struct anv_framebuffer
* framebuffer
;
2445 struct anv_render_pass
* pass
;
2446 struct anv_subpass
* subpass
;
2447 VkRect2D render_area
;
2448 uint32_t restart_index
;
2449 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2451 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2452 VkShaderStageFlags push_constant_stages
;
2453 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2454 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2455 struct anv_state samplers
[MESA_SHADER_STAGES
];
2458 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2459 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2460 * and before invoking the secondary in ExecuteCommands.
2462 bool pma_fix_enabled
;
2465 * Whether or not we know for certain that HiZ is enabled for the current
2466 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2467 * enabled or not, this will be false.
2471 bool conditional_render_enabled
;
2474 * Last rendering scale argument provided to
2475 * genX(cmd_buffer_emit_hashing_mode)().
2477 unsigned current_hash_scale
;
2480 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2481 * valid only when recording a render pass instance.
2483 struct anv_attachment_state
* attachments
;
2486 * Surface states for color render targets. These are stored in a single
2487 * flat array. For depth-stencil attachments, the surface state is simply
2490 struct anv_state render_pass_states
;
2493 * A null surface state of the right size to match the framebuffer. This
2494 * is one of the states in render_pass_states.
2496 struct anv_state null_surface_state
;
2499 struct anv_cmd_pool
{
2500 VkAllocationCallbacks alloc
;
2501 struct list_head cmd_buffers
;
2504 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2506 enum anv_cmd_buffer_exec_mode
{
2507 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2508 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2509 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2510 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2511 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2514 struct anv_cmd_buffer
{
2515 VK_LOADER_DATA _loader_data
;
2517 struct anv_device
* device
;
2519 struct anv_cmd_pool
* pool
;
2520 struct list_head pool_link
;
2522 struct anv_batch batch
;
2524 /* Fields required for the actual chain of anv_batch_bo's.
2526 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2528 struct list_head batch_bos
;
2529 enum anv_cmd_buffer_exec_mode exec_mode
;
2531 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2532 * referenced by this command buffer
2534 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2536 struct u_vector seen_bbos
;
2538 /* A vector of int32_t's for every block of binding tables.
2540 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2542 struct u_vector bt_block_states
;
2545 struct anv_reloc_list surface_relocs
;
2546 /** Last seen surface state block pool center bo offset */
2547 uint32_t last_ss_pool_center
;
2549 /* Serial for tracking buffer completion */
2552 /* Stream objects for storing temporary data */
2553 struct anv_state_stream surface_state_stream
;
2554 struct anv_state_stream dynamic_state_stream
;
2556 VkCommandBufferUsageFlags usage_flags
;
2557 VkCommandBufferLevel level
;
2559 struct anv_cmd_state state
;
2561 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2562 uint64_t intel_perf_marker
;
2565 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2566 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2567 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2568 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2569 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2570 struct anv_cmd_buffer
*secondary
);
2571 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2572 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2573 struct anv_cmd_buffer
*cmd_buffer
,
2574 const VkSemaphore
*in_semaphores
,
2575 uint32_t num_in_semaphores
,
2576 const VkSemaphore
*out_semaphores
,
2577 uint32_t num_out_semaphores
,
2580 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2582 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2583 const void *data
, uint32_t size
, uint32_t alignment
);
2584 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2585 uint32_t *a
, uint32_t *b
,
2586 uint32_t dwords
, uint32_t alignment
);
2589 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2591 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2592 uint32_t entries
, uint32_t *state_offset
);
2594 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2596 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2597 uint32_t size
, uint32_t alignment
);
2600 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2602 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2603 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2604 bool depth_clamp_enable
);
2605 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2607 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2608 struct anv_render_pass
*pass
,
2609 struct anv_framebuffer
*framebuffer
,
2610 const VkClearValue
*clear_values
);
2612 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2615 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2616 gl_shader_stage stage
);
2618 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2620 const struct anv_image_view
*
2621 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2624 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2625 uint32_t num_entries
,
2626 uint32_t *state_offset
,
2627 struct anv_state
*bt_state
);
2629 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2631 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2633 enum anv_fence_type
{
2634 ANV_FENCE_TYPE_NONE
= 0,
2636 ANV_FENCE_TYPE_SYNCOBJ
,
2640 enum anv_bo_fence_state
{
2641 /** Indicates that this is a new (or newly reset fence) */
2642 ANV_BO_FENCE_STATE_RESET
,
2644 /** Indicates that this fence has been submitted to the GPU but is still
2645 * (as far as we know) in use by the GPU.
2647 ANV_BO_FENCE_STATE_SUBMITTED
,
2649 ANV_BO_FENCE_STATE_SIGNALED
,
2652 struct anv_fence_impl
{
2653 enum anv_fence_type type
;
2656 /** Fence implementation for BO fences
2658 * These fences use a BO and a set of CPU-tracked state flags. The BO
2659 * is added to the object list of the last execbuf call in a QueueSubmit
2660 * and is marked EXEC_WRITE. The state flags track when the BO has been
2661 * submitted to the kernel. We need to do this because Vulkan lets you
2662 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2663 * will say it's idle in this case.
2667 enum anv_bo_fence_state state
;
2670 /** DRM syncobj handle for syncobj-based fences */
2674 struct wsi_fence
*fence_wsi
;
2679 /* Permanent fence state. Every fence has some form of permanent state
2680 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2681 * cross-process fences) or it could just be a dummy for use internally.
2683 struct anv_fence_impl permanent
;
2685 /* Temporary fence state. A fence *may* have temporary state. That state
2686 * is added to the fence by an import operation and is reset back to
2687 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2688 * state cannot be signaled because the fence must already be signaled
2689 * before the temporary state can be exported from the fence in the other
2690 * process and imported here.
2692 struct anv_fence_impl temporary
;
2697 struct anv_state state
;
2700 enum anv_semaphore_type
{
2701 ANV_SEMAPHORE_TYPE_NONE
= 0,
2702 ANV_SEMAPHORE_TYPE_DUMMY
,
2703 ANV_SEMAPHORE_TYPE_BO
,
2704 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2705 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2708 struct anv_semaphore_impl
{
2709 enum anv_semaphore_type type
;
2712 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2713 * This BO will be added to the object list on any execbuf2 calls for
2714 * which this semaphore is used as a wait or signal fence. When used as
2715 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2719 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2720 * If the semaphore is in the unsignaled state due to either just being
2721 * created or because it has been used for a wait, fd will be -1.
2725 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2726 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2727 * import so we don't need to bother with a userspace cache.
2733 struct anv_semaphore
{
2734 /* Permanent semaphore state. Every semaphore has some form of permanent
2735 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2736 * (for cross-process semaphores0 or it could just be a dummy for use
2739 struct anv_semaphore_impl permanent
;
2741 /* Temporary semaphore state. A semaphore *may* have temporary state.
2742 * That state is added to the semaphore by an import operation and is reset
2743 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2744 * semaphore with temporary state cannot be signaled because the semaphore
2745 * must already be signaled before the temporary state can be exported from
2746 * the semaphore in the other process and imported here.
2748 struct anv_semaphore_impl temporary
;
2751 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2752 struct anv_semaphore
*semaphore
);
2754 struct anv_shader_module
{
2755 unsigned char sha1
[20];
2760 static inline gl_shader_stage
2761 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2763 assert(__builtin_popcount(vk_stage
) == 1);
2764 return ffs(vk_stage
) - 1;
2767 static inline VkShaderStageFlagBits
2768 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2770 return (1 << mesa_stage
);
2773 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2775 #define anv_foreach_stage(stage, stage_bits) \
2776 for (gl_shader_stage stage, \
2777 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2778 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2779 __tmp &= ~(1 << (stage)))
2781 struct anv_pipeline_bind_map
{
2782 uint32_t surface_count
;
2783 uint32_t sampler_count
;
2785 struct anv_pipeline_binding
* surface_to_descriptor
;
2786 struct anv_pipeline_binding
* sampler_to_descriptor
;
2789 struct anv_shader_bin_key
{
2794 struct anv_shader_bin
{
2797 const struct anv_shader_bin_key
*key
;
2799 struct anv_state kernel
;
2800 uint32_t kernel_size
;
2802 struct anv_state constant_data
;
2803 uint32_t constant_data_size
;
2805 const struct brw_stage_prog_data
*prog_data
;
2806 uint32_t prog_data_size
;
2808 struct brw_compile_stats stats
[3];
2811 struct nir_xfb_info
*xfb_info
;
2813 struct anv_pipeline_bind_map bind_map
;
2816 struct anv_shader_bin
*
2817 anv_shader_bin_create(struct anv_device
*device
,
2818 const void *key
, uint32_t key_size
,
2819 const void *kernel
, uint32_t kernel_size
,
2820 const void *constant_data
, uint32_t constant_data_size
,
2821 const struct brw_stage_prog_data
*prog_data
,
2822 uint32_t prog_data_size
, const void *prog_data_param
,
2823 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
2824 const struct nir_xfb_info
*xfb_info
,
2825 const struct anv_pipeline_bind_map
*bind_map
);
2828 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2831 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2833 assert(shader
&& shader
->ref_cnt
>= 1);
2834 p_atomic_inc(&shader
->ref_cnt
);
2838 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2840 assert(shader
&& shader
->ref_cnt
>= 1);
2841 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2842 anv_shader_bin_destroy(device
, shader
);
2845 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
2846 #define MAX_PIPELINE_EXECUTABLES 7
2848 struct anv_pipeline_executable
{
2849 gl_shader_stage stage
;
2851 struct brw_compile_stats stats
;
2857 struct anv_pipeline
{
2858 struct anv_device
* device
;
2859 struct anv_batch batch
;
2860 uint32_t batch_data
[512];
2861 struct anv_reloc_list batch_relocs
;
2862 anv_cmd_dirty_mask_t dynamic_state_mask
;
2863 struct anv_dynamic_state dynamic_state
;
2867 VkPipelineCreateFlags flags
;
2868 struct anv_subpass
* subpass
;
2870 bool needs_data_cache
;
2872 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2874 uint32_t num_executables
;
2875 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
2878 const struct gen_l3_config
* l3_config
;
2879 uint32_t total_size
;
2882 VkShaderStageFlags active_stages
;
2883 struct anv_state blend_state
;
2886 struct anv_pipeline_vertex_binding
{
2889 uint32_t instance_divisor
;
2894 bool primitive_restart
;
2897 uint32_t cs_right_mask
;
2900 bool depth_test_enable
;
2901 bool writes_stencil
;
2902 bool stencil_test_enable
;
2903 bool depth_clamp_enable
;
2904 bool depth_clip_enable
;
2905 bool sample_shading_enable
;
2907 bool depth_bounds_test_enable
;
2911 uint32_t depth_stencil_state
[3];
2917 uint32_t wm_depth_stencil
[3];
2921 uint32_t wm_depth_stencil
[4];
2924 uint32_t interface_descriptor_data
[8];
2928 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2929 gl_shader_stage stage
)
2931 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2934 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2935 static inline const struct brw_##prefix##_prog_data * \
2936 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2938 if (anv_pipeline_has_stage(pipeline, stage)) { \
2939 return (const struct brw_##prefix##_prog_data *) \
2940 pipeline->shaders[stage]->prog_data; \
2946 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2947 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2948 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2949 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2950 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2951 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2953 static inline const struct brw_vue_prog_data
*
2954 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2956 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2957 return &get_gs_prog_data(pipeline
)->base
;
2958 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2959 return &get_tes_prog_data(pipeline
)->base
;
2961 return &get_vs_prog_data(pipeline
)->base
;
2965 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2966 struct anv_pipeline_cache
*cache
,
2967 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2968 const VkAllocationCallbacks
*alloc
);
2971 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2972 struct anv_pipeline_cache
*cache
,
2973 const VkComputePipelineCreateInfo
*info
,
2974 const struct anv_shader_module
*module
,
2975 const char *entrypoint
,
2976 const VkSpecializationInfo
*spec_info
);
2978 struct anv_format_plane
{
2979 enum isl_format isl_format
:16;
2980 struct isl_swizzle swizzle
;
2982 /* Whether this plane contains chroma channels */
2985 /* For downscaling of YUV planes */
2986 uint8_t denominator_scales
[2];
2988 /* How to map sampled ycbcr planes to a single 4 component element. */
2989 struct isl_swizzle ycbcr_swizzle
;
2991 /* What aspect is associated to this plane */
2992 VkImageAspectFlags aspect
;
2997 struct anv_format_plane planes
[3];
3003 static inline uint32_t
3004 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3005 VkImageAspectFlags aspect_mask
)
3007 switch (aspect_mask
) {
3008 case VK_IMAGE_ASPECT_COLOR_BIT
:
3009 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3010 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3012 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3013 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3016 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3018 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3021 /* Purposefully assert with depth/stencil aspects. */
3022 unreachable("invalid image aspect");
3026 static inline VkImageAspectFlags
3027 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3030 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3031 if (util_bitcount(image_aspects
) > 1)
3032 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3033 return VK_IMAGE_ASPECT_COLOR_BIT
;
3035 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3036 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3037 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3038 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3041 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3042 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3044 const struct anv_format
*
3045 anv_get_format(VkFormat format
);
3047 static inline uint32_t
3048 anv_get_format_planes(VkFormat vk_format
)
3050 const struct anv_format
*format
= anv_get_format(vk_format
);
3052 return format
!= NULL
? format
->n_planes
: 0;
3055 struct anv_format_plane
3056 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3057 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3059 static inline enum isl_format
3060 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3061 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3063 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3066 static inline struct isl_swizzle
3067 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3069 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3070 * RGB as RGBA for texturing
3072 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3073 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3075 /* But it doesn't matter what we render to that channel */
3076 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3082 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3085 * Subsurface of an anv_image.
3087 struct anv_surface
{
3088 /** Valid only if isl_surf::size_B > 0. */
3089 struct isl_surf isl
;
3092 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3098 VkImageType type
; /**< VkImageCreateInfo::imageType */
3099 /* The original VkFormat provided by the client. This may not match any
3100 * of the actual surface formats.
3103 const struct anv_format
*format
;
3105 VkImageAspectFlags aspects
;
3108 uint32_t array_size
;
3109 uint32_t samples
; /**< VkImageCreateInfo::samples */
3111 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3112 VkImageUsageFlags stencil_usage
;
3113 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3114 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3116 /** True if this is needs to be bound to an appropriately tiled BO.
3118 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3119 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3120 * we require a dedicated allocation so that we can know to allocate a
3123 bool needs_set_tiling
;
3126 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3127 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3129 uint64_t drm_format_mod
;
3134 /* Whether the image is made of several underlying buffer objects rather a
3135 * single one with different offsets.
3139 /* All the formats that can be used when creating views of this image
3140 * are CCS_E compatible.
3142 bool ccs_e_compatible
;
3144 /* Image was created with external format. */
3145 bool external_format
;
3150 * For each foo, anv_image::planes[x].surface is valid if and only if
3151 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3152 * to figure the number associated with a given aspect.
3154 * The hardware requires that the depth buffer and stencil buffer be
3155 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3156 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3157 * allocate the depth and stencil buffers as separate surfaces in the same
3162 * -----------------------
3164 * ----------------------- |
3165 * | shadow surface0 | |
3166 * ----------------------- | Plane 0
3167 * | aux surface0 | |
3168 * ----------------------- |
3169 * | fast clear colors0 | \|/
3170 * -----------------------
3172 * ----------------------- |
3173 * | shadow surface1 | |
3174 * ----------------------- | Plane 1
3175 * | aux surface1 | |
3176 * ----------------------- |
3177 * | fast clear colors1 | \|/
3178 * -----------------------
3181 * -----------------------
3185 * Offset of the entire plane (whenever the image is disjoint this is
3193 struct anv_surface surface
;
3196 * A surface which shadows the main surface and may have different
3197 * tiling. This is used for sampling using a tiling that isn't supported
3198 * for other operations.
3200 struct anv_surface shadow_surface
;
3203 * For color images, this is the aux usage for this image when not used
3204 * as a color attachment.
3206 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3207 * image has a HiZ buffer.
3209 enum isl_aux_usage aux_usage
;
3211 struct anv_surface aux_surface
;
3214 * Offset of the fast clear state (used to compute the
3215 * fast_clear_state_offset of the following planes).
3217 uint32_t fast_clear_state_offset
;
3220 * BO associated with this plane, set when bound.
3222 struct anv_address address
;
3225 * Address of the main surface used to fill the aux map table. This is
3226 * used at destruction of the image since the Vulkan spec does not
3227 * guarantee that the address.bo field we still be valid at destruction.
3229 uint64_t aux_map_surface_address
;
3232 * When destroying the image, also free the bo.
3238 /* The ordering of this enum is important */
3239 enum anv_fast_clear_type
{
3240 /** Image does not have/support any fast-clear blocks */
3241 ANV_FAST_CLEAR_NONE
= 0,
3242 /** Image has/supports fast-clear but only to the default value */
3243 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3244 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3245 ANV_FAST_CLEAR_ANY
= 2,
3248 /* Returns the number of auxiliary buffer levels attached to an image. */
3249 static inline uint8_t
3250 anv_image_aux_levels(const struct anv_image
* const image
,
3251 VkImageAspectFlagBits aspect
)
3253 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3255 /* The Gen12 CCS aux surface is represented with only one level. */
3256 const uint8_t aux_logical_levels
=
3257 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3258 image
->planes
[plane
].surface
.isl
.levels
:
3259 image
->planes
[plane
].aux_surface
.isl
.levels
;
3261 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3262 aux_logical_levels
: 0;
3265 /* Returns the number of auxiliary buffer layers attached to an image. */
3266 static inline uint32_t
3267 anv_image_aux_layers(const struct anv_image
* const image
,
3268 VkImageAspectFlagBits aspect
,
3269 const uint8_t miplevel
)
3273 /* The miplevel must exist in the main buffer. */
3274 assert(miplevel
< image
->levels
);
3276 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3277 /* There are no layers with auxiliary data because the miplevel has no
3282 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3284 /* The Gen12 CCS aux surface is represented with only one layer. */
3285 const struct isl_extent4d
*aux_logical_level0_px
=
3286 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3287 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3288 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3290 return MAX2(aux_logical_level0_px
->array_len
,
3291 aux_logical_level0_px
->depth
>> miplevel
);
3295 static inline struct anv_address
3296 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3297 const struct anv_image
*image
,
3298 VkImageAspectFlagBits aspect
)
3300 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3302 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3303 return anv_address_add(image
->planes
[plane
].address
,
3304 image
->planes
[plane
].fast_clear_state_offset
);
3307 static inline struct anv_address
3308 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3309 const struct anv_image
*image
,
3310 VkImageAspectFlagBits aspect
)
3312 struct anv_address addr
=
3313 anv_image_get_clear_color_addr(device
, image
, aspect
);
3315 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3316 device
->isl_dev
.ss
.clear_color_state_size
:
3317 device
->isl_dev
.ss
.clear_value_size
;
3318 return anv_address_add(addr
, clear_color_state_size
);
3321 static inline struct anv_address
3322 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3323 const struct anv_image
*image
,
3324 VkImageAspectFlagBits aspect
,
3325 uint32_t level
, uint32_t array_layer
)
3327 assert(level
< anv_image_aux_levels(image
, aspect
));
3328 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3329 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3330 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3332 struct anv_address addr
=
3333 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3334 addr
.offset
+= 4; /* Go past the fast clear type */
3336 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3337 for (uint32_t l
= 0; l
< level
; l
++)
3338 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3340 addr
.offset
+= level
* image
->array_size
* 4;
3342 addr
.offset
+= array_layer
* 4;
3344 assert(addr
.offset
<
3345 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3349 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3351 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3352 const struct anv_image
*image
)
3354 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3357 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3358 * struct. There's documentation which suggests that this feature actually
3359 * reduces performance on BDW, but it has only been observed to help so
3360 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3361 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3363 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3366 return image
->samples
== 1;
3370 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3371 const struct anv_image
*image
,
3374 return device
->info
.has_aux_map
&&
3375 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3379 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3380 const struct anv_image
*image
,
3381 VkImageAspectFlagBits aspect
,
3382 enum isl_aux_usage aux_usage
,
3384 uint32_t base_layer
,
3385 uint32_t layer_count
);
3388 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3389 const struct anv_image
*image
,
3390 VkImageAspectFlagBits aspect
,
3391 enum isl_aux_usage aux_usage
,
3392 enum isl_format format
, struct isl_swizzle swizzle
,
3393 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3394 VkRect2D area
, union isl_color_value clear_color
);
3396 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3397 const struct anv_image
*image
,
3398 VkImageAspectFlags aspects
,
3399 enum isl_aux_usage depth_aux_usage
,
3401 uint32_t base_layer
, uint32_t layer_count
,
3403 float depth_value
, uint8_t stencil_value
);
3405 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3406 const struct anv_image
*src_image
,
3407 enum isl_aux_usage src_aux_usage
,
3408 uint32_t src_level
, uint32_t src_base_layer
,
3409 const struct anv_image
*dst_image
,
3410 enum isl_aux_usage dst_aux_usage
,
3411 uint32_t dst_level
, uint32_t dst_base_layer
,
3412 VkImageAspectFlagBits aspect
,
3413 uint32_t src_x
, uint32_t src_y
,
3414 uint32_t dst_x
, uint32_t dst_y
,
3415 uint32_t width
, uint32_t height
,
3416 uint32_t layer_count
,
3417 enum blorp_filter filter
);
3419 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3420 const struct anv_image
*image
,
3421 VkImageAspectFlagBits aspect
, uint32_t level
,
3422 uint32_t base_layer
, uint32_t layer_count
,
3423 enum isl_aux_op hiz_op
);
3425 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3426 const struct anv_image
*image
,
3427 VkImageAspectFlags aspects
,
3429 uint32_t base_layer
, uint32_t layer_count
,
3430 VkRect2D area
, uint8_t stencil_value
);
3432 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3433 const struct anv_image
*image
,
3434 enum isl_format format
,
3435 VkImageAspectFlagBits aspect
,
3436 uint32_t base_layer
, uint32_t layer_count
,
3437 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3440 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3441 const struct anv_image
*image
,
3442 enum isl_format format
,
3443 VkImageAspectFlagBits aspect
, uint32_t level
,
3444 uint32_t base_layer
, uint32_t layer_count
,
3445 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3449 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3450 const struct anv_image
*image
,
3451 VkImageAspectFlagBits aspect
,
3452 uint32_t base_level
, uint32_t level_count
,
3453 uint32_t base_layer
, uint32_t layer_count
);
3456 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3457 const struct anv_image
*image
,
3458 const VkImageAspectFlagBits aspect
,
3459 const VkImageLayout layout
);
3461 enum anv_fast_clear_type
3462 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3463 const struct anv_image
* const image
,
3464 const VkImageAspectFlagBits aspect
,
3465 const VkImageLayout layout
);
3467 /* This is defined as a macro so that it works for both
3468 * VkImageSubresourceRange and VkImageSubresourceLayers
3470 #define anv_get_layerCount(_image, _range) \
3471 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3472 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3474 static inline uint32_t
3475 anv_get_levelCount(const struct anv_image
*image
,
3476 const VkImageSubresourceRange
*range
)
3478 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3479 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3482 static inline VkImageAspectFlags
3483 anv_image_expand_aspects(const struct anv_image
*image
,
3484 VkImageAspectFlags aspects
)
3486 /* If the underlying image has color plane aspects and
3487 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3488 * the underlying image. */
3489 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3490 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3491 return image
->aspects
;
3497 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3498 VkImageAspectFlags aspects2
)
3500 if (aspects1
== aspects2
)
3503 /* Only 1 color aspects are compatibles. */
3504 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3505 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3506 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3512 struct anv_image_view
{
3513 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3515 VkImageAspectFlags aspect_mask
;
3517 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3521 uint32_t image_plane
;
3523 struct isl_view isl
;
3526 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3527 * image layout of SHADER_READ_ONLY_OPTIMAL or
3528 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3530 struct anv_surface_state optimal_sampler_surface_state
;
3533 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3534 * image layout of GENERAL.
3536 struct anv_surface_state general_sampler_surface_state
;
3539 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3540 * states for write-only and readable, using the real format for
3541 * write-only and the lowered format for readable.
3543 struct anv_surface_state storage_surface_state
;
3544 struct anv_surface_state writeonly_storage_surface_state
;
3546 struct brw_image_param storage_image_param
;
3550 enum anv_image_view_state_flags
{
3551 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3552 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3555 void anv_image_fill_surface_state(struct anv_device
*device
,
3556 const struct anv_image
*image
,
3557 VkImageAspectFlagBits aspect
,
3558 const struct isl_view
*view
,
3559 isl_surf_usage_flags_t view_usage
,
3560 enum isl_aux_usage aux_usage
,
3561 const union isl_color_value
*clear_color
,
3562 enum anv_image_view_state_flags flags
,
3563 struct anv_surface_state
*state_inout
,
3564 struct brw_image_param
*image_param_out
);
3566 struct anv_image_create_info
{
3567 const VkImageCreateInfo
*vk_info
;
3569 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3570 isl_tiling_flags_t isl_tiling_flags
;
3572 /** These flags will be added to any derived from VkImageCreateInfo. */
3573 isl_surf_usage_flags_t isl_extra_usage_flags
;
3576 bool external_format
;
3579 VkResult
anv_image_create(VkDevice _device
,
3580 const struct anv_image_create_info
*info
,
3581 const VkAllocationCallbacks
* alloc
,
3584 const struct anv_surface
*
3585 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3586 VkImageAspectFlags aspect_mask
);
3589 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3591 static inline struct VkExtent3D
3592 anv_sanitize_image_extent(const VkImageType imageType
,
3593 const struct VkExtent3D imageExtent
)
3595 switch (imageType
) {
3596 case VK_IMAGE_TYPE_1D
:
3597 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3598 case VK_IMAGE_TYPE_2D
:
3599 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3600 case VK_IMAGE_TYPE_3D
:
3603 unreachable("invalid image type");
3607 static inline struct VkOffset3D
3608 anv_sanitize_image_offset(const VkImageType imageType
,
3609 const struct VkOffset3D imageOffset
)
3611 switch (imageType
) {
3612 case VK_IMAGE_TYPE_1D
:
3613 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3614 case VK_IMAGE_TYPE_2D
:
3615 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3616 case VK_IMAGE_TYPE_3D
:
3619 unreachable("invalid image type");
3623 VkFormatFeatureFlags
3624 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3626 const struct anv_format
*anv_format
,
3627 VkImageTiling vk_tiling
);
3629 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3630 struct anv_state state
,
3631 enum isl_format format
,
3632 struct anv_address address
,
3633 uint32_t range
, uint32_t stride
);
3636 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3637 const struct anv_attachment_state
*att_state
,
3638 const struct anv_image_view
*iview
)
3640 const struct isl_format_layout
*view_fmtl
=
3641 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3643 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3644 if (view_fmtl->channels.c.bits) \
3645 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3647 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3648 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3649 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3650 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3652 #undef COPY_CLEAR_COLOR_CHANNEL
3656 struct anv_ycbcr_conversion
{
3657 const struct anv_format
* format
;
3658 VkSamplerYcbcrModelConversion ycbcr_model
;
3659 VkSamplerYcbcrRange ycbcr_range
;
3660 VkComponentSwizzle mapping
[4];
3661 VkChromaLocation chroma_offsets
[2];
3662 VkFilter chroma_filter
;
3663 bool chroma_reconstruction
;
3666 struct anv_sampler
{
3667 uint32_t state
[3][4];
3669 struct anv_ycbcr_conversion
*conversion
;
3671 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3672 * and with a 32-byte stride for use as bindless samplers.
3674 struct anv_state bindless_state
;
3677 struct anv_framebuffer
{
3682 uint32_t attachment_count
;
3683 struct anv_image_view
* attachments
[0];
3686 struct anv_subpass_attachment
{
3687 VkImageUsageFlagBits usage
;
3688 uint32_t attachment
;
3689 VkImageLayout layout
;
3692 struct anv_subpass
{
3693 uint32_t attachment_count
;
3696 * A pointer to all attachment references used in this subpass.
3697 * Only valid if ::attachment_count > 0.
3699 struct anv_subpass_attachment
* attachments
;
3700 uint32_t input_count
;
3701 struct anv_subpass_attachment
* input_attachments
;
3702 uint32_t color_count
;
3703 struct anv_subpass_attachment
* color_attachments
;
3704 struct anv_subpass_attachment
* resolve_attachments
;
3706 struct anv_subpass_attachment
* depth_stencil_attachment
;
3707 struct anv_subpass_attachment
* ds_resolve_attachment
;
3708 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3709 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3713 /** Subpass has a depth/stencil self-dependency */
3714 bool has_ds_self_dep
;
3716 /** Subpass has at least one color resolve attachment */
3717 bool has_color_resolve
;
3720 static inline unsigned
3721 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3723 return MAX2(1, util_bitcount(subpass
->view_mask
));
3726 struct anv_render_pass_attachment
{
3727 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3728 * its members individually.
3732 VkImageUsageFlags usage
;
3733 VkAttachmentLoadOp load_op
;
3734 VkAttachmentStoreOp store_op
;
3735 VkAttachmentLoadOp stencil_load_op
;
3736 VkImageLayout initial_layout
;
3737 VkImageLayout final_layout
;
3738 VkImageLayout first_subpass_layout
;
3740 /* The subpass id in which the attachment will be used last. */
3741 uint32_t last_subpass_idx
;
3744 struct anv_render_pass
{
3745 uint32_t attachment_count
;
3746 uint32_t subpass_count
;
3747 /* An array of subpass_count+1 flushes, one per subpass boundary */
3748 enum anv_pipe_bits
* subpass_flushes
;
3749 struct anv_render_pass_attachment
* attachments
;
3750 struct anv_subpass subpasses
[0];
3753 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3755 struct anv_query_pool
{
3757 VkQueryPipelineStatisticFlags pipeline_statistics
;
3758 /** Stride between slots, in bytes */
3760 /** Number of slots in this query pool */
3765 int anv_get_instance_entrypoint_index(const char *name
);
3766 int anv_get_device_entrypoint_index(const char *name
);
3767 int anv_get_physical_device_entrypoint_index(const char *name
);
3769 const char *anv_get_instance_entry_name(int index
);
3770 const char *anv_get_physical_device_entry_name(int index
);
3771 const char *anv_get_device_entry_name(int index
);
3774 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3775 const struct anv_instance_extension_table
*instance
);
3777 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3778 const struct anv_instance_extension_table
*instance
);
3780 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3781 const struct anv_instance_extension_table
*instance
,
3782 const struct anv_device_extension_table
*device
);
3784 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3787 void anv_dump_image_to_ppm(struct anv_device
*device
,
3788 struct anv_image
*image
, unsigned miplevel
,
3789 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3790 const char *filename
);
3792 enum anv_dump_action
{
3793 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3796 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3797 void anv_dump_finish(void);
3799 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
3801 static inline uint32_t
3802 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3804 /* This function must be called from within a subpass. */
3805 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3807 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3809 /* The id of this subpass shouldn't exceed the number of subpasses in this
3810 * render pass minus 1.
3812 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3816 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
3817 void anv_device_perf_init(struct anv_device
*device
);
3819 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3821 static inline struct __anv_type * \
3822 __anv_type ## _from_handle(__VkType _handle) \
3824 return (struct __anv_type *) _handle; \
3827 static inline __VkType \
3828 __anv_type ## _to_handle(struct __anv_type *_obj) \
3830 return (__VkType) _obj; \
3833 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3835 static inline struct __anv_type * \
3836 __anv_type ## _from_handle(__VkType _handle) \
3838 return (struct __anv_type *)(uintptr_t) _handle; \
3841 static inline __VkType \
3842 __anv_type ## _to_handle(struct __anv_type *_obj) \
3844 return (__VkType)(uintptr_t) _obj; \
3847 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3848 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3850 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3851 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3852 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3853 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3854 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3856 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3857 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3858 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3859 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3860 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3861 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3862 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3863 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3864 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3865 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3866 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3867 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3868 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3869 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3870 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3871 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3872 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3873 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3874 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3875 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3876 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3877 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3878 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3880 /* Gen-specific function declarations */
3882 # include "anv_genX.h"
3884 # define genX(x) gen7_##x
3885 # include "anv_genX.h"
3887 # define genX(x) gen75_##x
3888 # include "anv_genX.h"
3890 # define genX(x) gen8_##x
3891 # include "anv_genX.h"
3893 # define genX(x) gen9_##x
3894 # include "anv_genX.h"
3896 # define genX(x) gen10_##x
3897 # include "anv_genX.h"
3899 # define genX(x) gen11_##x
3900 # include "anv_genX.h"
3902 # define genX(x) gen12_##x
3903 # include "anv_genX.h"
3907 #endif /* ANV_PRIVATE_H */