2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
46 #include "common/gen_clflush.h"
47 #include "common/gen_gem.h"
48 #include "dev/gen_device_info.h"
49 #include "blorp/blorp.h"
50 #include "compiler/brw_compiler.h"
51 #include "util/macros.h"
52 #include "util/hash_table.h"
53 #include "util/list.h"
55 #include "util/u_atomic.h"
56 #include "util/u_vector.h"
57 #include "util/u_math.h"
60 #include "vk_debug_report.h"
62 /* Pre-declarations needed for WSI entrypoints */
65 typedef struct xcb_connection_t xcb_connection_t
;
66 typedef uint32_t xcb_visualid_t
;
67 typedef uint32_t xcb_window_t
;
70 struct anv_buffer_view
;
71 struct anv_image_view
;
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78 #include <vulkan/vk_icd.h>
80 #include "anv_android.h"
81 #include "anv_entrypoints.h"
82 #include "anv_extensions.h"
85 #include "common/gen_debug.h"
86 #include "common/intel_log.h"
87 #include "wsi_common.h"
89 /* anv Virtual Memory Layout
90 * =========================
92 * When the anv driver is determining the virtual graphics addresses of memory
93 * objects itself using the softpin mechanism, the following memory ranges
96 * Three special considerations to notice:
98 * (1) the dynamic state pool is located within the same 4 GiB as the low
99 * heap. This is to work around a VF cache issue described in a comment in
100 * anv_physical_device_init_heaps.
102 * (2) the binding table pool is located at lower addresses than the surface
103 * state pool, within a 4 GiB range. This allows surface state base addresses
104 * to cover both binding tables (16 bit offsets) and surface states (32 bit
107 * (3) the last 4 GiB of the address space is withheld from the high
108 * heap. Various hardware units will read past the end of an object for
109 * various reasons. This healthy margin prevents reads from wrapping around
112 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
113 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
114 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
115 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
116 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
117 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
118 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
119 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
120 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
121 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
122 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
123 #define HIGH_HEAP_MAX_ADDRESS 0xfffeffffffffULL
125 #define LOW_HEAP_SIZE \
126 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
127 #define HIGH_HEAP_SIZE \
128 (HIGH_HEAP_MAX_ADDRESS - HIGH_HEAP_MIN_ADDRESS + 1)
129 #define DYNAMIC_STATE_POOL_SIZE \
130 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
131 #define BINDING_TABLE_POOL_SIZE \
132 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
133 #define SURFACE_STATE_POOL_SIZE \
134 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
135 #define INSTRUCTION_STATE_POOL_SIZE \
136 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
138 /* Allowing different clear colors requires us to perform a depth resolve at
139 * the end of certain render passes. This is because while slow clears store
140 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
141 * See the PRMs for examples describing when additional resolves would be
142 * necessary. To enable fast clears without requiring extra resolves, we set
143 * the clear value to a globally-defined one. We could allow different values
144 * if the user doesn't expect coherent data during or after a render passes
145 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
146 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
147 * 1.0f seems to be the only value used. The only application that doesn't set
148 * this value does so through the usage of an seemingly uninitialized clear
151 #define ANV_HZ_FC_VAL 1.0f
156 #define MAX_VIEWPORTS 16
157 #define MAX_SCISSORS 16
158 #define MAX_PUSH_CONSTANTS_SIZE 128
159 #define MAX_DYNAMIC_BUFFERS 16
160 #define MAX_IMAGES 64
161 #define MAX_GEN8_IMAGES 8
162 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
164 /* The kernel relocation API has a limitation of a 32-bit delta value
165 * applied to the address before it is written which, in spite of it being
166 * unsigned, is treated as signed . Because of the way that this maps to
167 * the Vulkan API, we cannot handle an offset into a buffer that does not
168 * fit into a signed 32 bits. The only mechanism we have for dealing with
169 * this at the moment is to limit all VkDeviceMemory objects to a maximum
170 * of 2GB each. The Vulkan spec allows us to do this:
172 * "Some platforms may have a limit on the maximum size of a single
173 * allocation. For example, certain systems may fail to create
174 * allocations with a size greater than or equal to 4GB. Such a limit is
175 * implementation-dependent, and if such a failure occurs then the error
176 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
178 * We don't use vk_error here because it's not an error so much as an
179 * indication to the application that the allocation is too large.
181 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
183 #define ANV_SVGS_VB_INDEX MAX_VBS
184 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
186 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
188 static inline uint32_t
189 align_down_npot_u32(uint32_t v
, uint32_t a
)
194 static inline uint32_t
195 align_u32(uint32_t v
, uint32_t a
)
197 assert(a
!= 0 && a
== (a
& -a
));
198 return (v
+ a
- 1) & ~(a
- 1);
201 static inline uint64_t
202 align_u64(uint64_t v
, uint64_t a
)
204 assert(a
!= 0 && a
== (a
& -a
));
205 return (v
+ a
- 1) & ~(a
- 1);
208 static inline int32_t
209 align_i32(int32_t v
, int32_t a
)
211 assert(a
!= 0 && a
== (a
& -a
));
212 return (v
+ a
- 1) & ~(a
- 1);
215 /** Alignment must be a power of 2. */
217 anv_is_aligned(uintmax_t n
, uintmax_t a
)
219 assert(a
== (a
& -a
));
220 return (n
& (a
- 1)) == 0;
223 static inline uint32_t
224 anv_minify(uint32_t n
, uint32_t levels
)
226 if (unlikely(n
== 0))
229 return MAX2(n
>> levels
, 1);
233 anv_clamp_f(float f
, float min
, float max
)
246 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
248 if (*inout_mask
& clear_mask
) {
249 *inout_mask
&= ~clear_mask
;
256 static inline union isl_color_value
257 vk_to_isl_color(VkClearColorValue color
)
259 return (union isl_color_value
) {
269 #define for_each_bit(b, dword) \
270 for (uint32_t __dword = (dword); \
271 (b) = __builtin_ffs(__dword) - 1, __dword; \
272 __dword &= ~(1 << (b)))
274 #define typed_memcpy(dest, src, count) ({ \
275 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
276 memcpy((dest), (src), (count) * sizeof(*(src))); \
279 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
280 * to be added here in order to utilize mapping in debug/error/perf macros.
282 #define REPORT_OBJECT_TYPE(o) \
283 __builtin_choose_expr ( \
284 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
285 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
286 __builtin_choose_expr ( \
287 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
288 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
289 __builtin_choose_expr ( \
290 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
291 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
292 __builtin_choose_expr ( \
293 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
294 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
295 __builtin_choose_expr ( \
296 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
297 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
298 __builtin_choose_expr ( \
299 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
300 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
301 __builtin_choose_expr ( \
302 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
303 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
304 __builtin_choose_expr ( \
305 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
306 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
307 __builtin_choose_expr ( \
308 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
309 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
310 __builtin_choose_expr ( \
311 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
312 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
313 __builtin_choose_expr ( \
314 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
315 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
316 __builtin_choose_expr ( \
317 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
318 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
319 __builtin_choose_expr ( \
320 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
321 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
322 __builtin_choose_expr ( \
323 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
324 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
325 __builtin_choose_expr ( \
326 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
327 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
328 __builtin_choose_expr ( \
329 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
330 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
331 __builtin_choose_expr ( \
332 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
333 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
334 __builtin_choose_expr ( \
335 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
336 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
337 __builtin_choose_expr ( \
338 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
339 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
340 __builtin_choose_expr ( \
341 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
342 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
343 __builtin_choose_expr ( \
344 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
345 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
346 __builtin_choose_expr ( \
347 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
348 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
349 __builtin_choose_expr ( \
350 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
351 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
352 __builtin_choose_expr ( \
353 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
354 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
355 __builtin_choose_expr ( \
356 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
357 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
358 __builtin_choose_expr ( \
359 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
360 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
361 __builtin_choose_expr ( \
362 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
363 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
364 __builtin_choose_expr ( \
365 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
366 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
367 __builtin_choose_expr ( \
368 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
369 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
370 __builtin_choose_expr ( \
371 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
372 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
373 __builtin_choose_expr ( \
374 __builtin_types_compatible_p (__typeof (o), void*), \
375 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
376 /* The void expression results in a compile-time error \
377 when assigning the result to something. */ \
378 (void)0)))))))))))))))))))))))))))))))
380 /* Whenever we generate an error, pass it through this function. Useful for
381 * debugging, where we can break on it. Only call at error site, not when
382 * propagating errors. Might be useful to plug in a stack trace here.
385 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
386 VkDebugReportObjectTypeEXT type
, VkResult error
,
387 const char *file
, int line
, const char *format
,
390 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
391 VkDebugReportObjectTypeEXT type
, VkResult error
,
392 const char *file
, int line
, const char *format
, ...);
395 #define vk_error(error) __vk_errorf(NULL, NULL,\
396 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
397 error, __FILE__, __LINE__, NULL)
398 #define vk_errorv(instance, obj, error, format, args)\
399 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
400 __FILE__, __LINE__, format, args)
401 #define vk_errorf(instance, obj, error, format, ...)\
402 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
403 __FILE__, __LINE__, format, ## __VA_ARGS__)
405 #define vk_error(error) error
406 #define vk_errorf(instance, obj, error, format, ...) error
410 * Warn on ignored extension structs.
412 * The Vulkan spec requires us to ignore unsupported or unknown structs in
413 * a pNext chain. In debug mode, emitting warnings for ignored structs may
414 * help us discover structs that we should not have ignored.
417 * From the Vulkan 1.0.38 spec:
419 * Any component of the implementation (the loader, any enabled layers,
420 * and drivers) must skip over, without processing (other than reading the
421 * sType and pNext members) any chained structures with sType values not
422 * defined by extensions supported by that component.
424 #define anv_debug_ignored_stype(sType) \
425 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
427 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
428 VkDebugReportObjectTypeEXT type
, const char *file
,
429 int line
, const char *format
, ...)
430 anv_printflike(6, 7);
431 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
432 void anv_loge_v(const char *format
, va_list va
);
435 * Print a FINISHME message, including its source location.
437 #define anv_finishme(format, ...) \
439 static bool reported = false; \
441 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
448 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
450 #define anv_perf_warn(instance, obj, format, ...) \
452 static bool reported = false; \
453 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
454 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
455 format, ##__VA_ARGS__); \
460 /* A non-fatal assert. Useful for debugging. */
462 #define anv_assert(x) ({ \
463 if (unlikely(!(x))) \
464 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
467 #define anv_assert(x)
470 /* A multi-pointer allocator
472 * When copying data structures from the user (such as a render pass), it's
473 * common to need to allocate data for a bunch of different things. Instead
474 * of doing several allocations and having to handle all of the error checking
475 * that entails, it can be easier to do a single allocation. This struct
476 * helps facilitate that. The intended usage looks like this:
479 * anv_multialloc_add(&ma, &main_ptr, 1);
480 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
481 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
483 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
484 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
486 struct anv_multialloc
{
494 #define ANV_MULTIALLOC_INIT \
495 ((struct anv_multialloc) { 0, })
497 #define ANV_MULTIALLOC(_name) \
498 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
500 __attribute__((always_inline
))
502 _anv_multialloc_add(struct anv_multialloc
*ma
,
503 void **ptr
, size_t size
, size_t align
)
505 size_t offset
= align_u64(ma
->size
, align
);
506 ma
->size
= offset
+ size
;
507 ma
->align
= MAX2(ma
->align
, align
);
509 /* Store the offset in the pointer. */
510 *ptr
= (void *)(uintptr_t)offset
;
512 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
513 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
516 #define anv_multialloc_add_size(_ma, _ptr, _size) \
517 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
519 #define anv_multialloc_add(_ma, _ptr, _count) \
520 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
522 __attribute__((always_inline
))
524 anv_multialloc_alloc(struct anv_multialloc
*ma
,
525 const VkAllocationCallbacks
*alloc
,
526 VkSystemAllocationScope scope
)
528 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
532 /* Fill out each of the pointers with their final value.
534 * for (uint32_t i = 0; i < ma->ptr_count; i++)
535 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
537 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
538 * constant, GCC is incapable of figuring this out and unrolling the loop
539 * so we have to give it a little help.
541 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
542 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
543 if ((_i) < ma->ptr_count) \
544 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
545 _ANV_MULTIALLOC_UPDATE_POINTER(0);
546 _ANV_MULTIALLOC_UPDATE_POINTER(1);
547 _ANV_MULTIALLOC_UPDATE_POINTER(2);
548 _ANV_MULTIALLOC_UPDATE_POINTER(3);
549 _ANV_MULTIALLOC_UPDATE_POINTER(4);
550 _ANV_MULTIALLOC_UPDATE_POINTER(5);
551 _ANV_MULTIALLOC_UPDATE_POINTER(6);
552 _ANV_MULTIALLOC_UPDATE_POINTER(7);
553 #undef _ANV_MULTIALLOC_UPDATE_POINTER
558 __attribute__((always_inline
))
560 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
561 const VkAllocationCallbacks
*parent_alloc
,
562 const VkAllocationCallbacks
*alloc
,
563 VkSystemAllocationScope scope
)
565 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
568 /* Extra ANV-defined BO flags which won't be passed to the kernel */
569 #define ANV_BO_EXTERNAL (1ull << 31)
570 #define ANV_BO_FLAG_MASK (1ull << 31)
575 /* Index into the current validation list. This is used by the
576 * validation list building alrogithm to track which buffers are already
577 * in the validation list so that we can ensure uniqueness.
581 /* Last known offset. This value is provided by the kernel when we
582 * execbuf and is used as the presumed offset for the next bunch of
590 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
595 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
597 bo
->gem_handle
= gem_handle
;
605 /* Represents a lock-free linked list of "free" things. This is used by
606 * both the block pool and the state pools. Unfortunately, in order to
607 * solve the ABA problem, we can't use a single uint32_t head.
609 union anv_free_list
{
613 /* A simple count that is incremented every time the head changes. */
619 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
621 struct anv_block_state
{
631 struct anv_block_pool
{
632 struct anv_device
*device
;
638 /* A single BO for now */
641 /* The address where the start of the pool is pinned. The various bos that
642 * are created as the pool grows will have addresses in the range
643 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
645 uint64_t start_address
;
647 /* The offset from the start of the bo to the "center" of the block
648 * pool. Pointers to allocated blocks are given by
649 * bo.map + center_bo_offset + offsets.
651 uint32_t center_bo_offset
;
656 * Array of mmaps and gem handles owned by the block pool, reclaimed when
657 * the block pool is destroyed.
659 struct u_vector mmap_cleanups
;
661 struct anv_block_state state
;
663 struct anv_block_state back_state
;
666 /* Block pools are backed by a fixed-size 1GB memfd */
667 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
669 /* The center of the block pool is also the middle of the memfd. This may
670 * change in the future if we decide differently for some reason.
672 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
674 static inline uint32_t
675 anv_block_pool_size(struct anv_block_pool
*pool
)
677 return pool
->state
.end
+ pool
->back_state
.end
;
687 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
689 struct anv_fixed_size_state_pool
{
690 union anv_free_list free_list
;
691 struct anv_block_state block
;
694 #define ANV_MIN_STATE_SIZE_LOG2 6
695 #define ANV_MAX_STATE_SIZE_LOG2 20
697 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
699 struct anv_free_entry
{
701 struct anv_state state
;
704 struct anv_state_table
{
705 struct anv_device
*device
;
707 struct anv_free_entry
*map
;
709 struct anv_block_state state
;
710 struct u_vector mmap_cleanups
;
713 struct anv_state_pool
{
714 struct anv_block_pool block_pool
;
716 struct anv_state_table table
;
718 /* The size of blocks which will be allocated from the block pool */
721 /** Free list for "back" allocations */
722 union anv_free_list back_alloc_free_list
;
724 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
727 struct anv_state_stream_block
;
729 struct anv_state_stream
{
730 struct anv_state_pool
*state_pool
;
732 /* The size of blocks to allocate from the state pool */
735 /* Current block we're allocating from */
736 struct anv_state block
;
738 /* Offset into the current block at which to allocate the next state */
741 /* List of all blocks allocated from this pool */
742 struct anv_state_stream_block
*block_list
;
745 /* The block_pool functions exported for testing only. The block pool should
746 * only be used via a state pool (see below).
748 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
749 struct anv_device
*device
,
750 uint64_t start_address
,
751 uint32_t initial_size
,
753 void anv_block_pool_finish(struct anv_block_pool
*pool
);
754 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
755 uint32_t block_size
);
756 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
757 uint32_t block_size
);
758 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
760 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
761 struct anv_device
*device
,
762 uint64_t start_address
,
765 void anv_state_pool_finish(struct anv_state_pool
*pool
);
766 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
767 uint32_t state_size
, uint32_t alignment
);
768 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
769 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
770 void anv_state_stream_init(struct anv_state_stream
*stream
,
771 struct anv_state_pool
*state_pool
,
772 uint32_t block_size
);
773 void anv_state_stream_finish(struct anv_state_stream
*stream
);
774 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
775 uint32_t size
, uint32_t alignment
);
777 VkResult
anv_state_table_init(struct anv_state_table
*table
,
778 struct anv_device
*device
,
779 uint32_t initial_entries
);
780 void anv_state_table_finish(struct anv_state_table
*table
);
781 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
783 void anv_free_list_push(union anv_free_list
*list
,
784 struct anv_state_table
*table
,
785 uint32_t idx
, uint32_t count
);
786 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
787 struct anv_state_table
*table
);
790 static inline struct anv_state
*
791 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
793 return &table
->map
[idx
].state
;
796 * Implements a pool of re-usable BOs. The interface is identical to that
797 * of block_pool except that each block is its own BO.
800 struct anv_device
*device
;
807 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
809 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
810 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
812 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
814 struct anv_scratch_bo
{
819 struct anv_scratch_pool
{
820 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
821 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
824 void anv_scratch_pool_init(struct anv_device
*device
,
825 struct anv_scratch_pool
*pool
);
826 void anv_scratch_pool_finish(struct anv_device
*device
,
827 struct anv_scratch_pool
*pool
);
828 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
829 struct anv_scratch_pool
*pool
,
830 gl_shader_stage stage
,
831 unsigned per_thread_scratch
);
833 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
834 struct anv_bo_cache
{
835 struct hash_table
*bo_map
;
836 pthread_mutex_t mutex
;
839 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
840 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
841 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
842 struct anv_bo_cache
*cache
,
843 uint64_t size
, uint64_t bo_flags
,
845 VkResult
anv_bo_cache_import(struct anv_device
*device
,
846 struct anv_bo_cache
*cache
,
847 int fd
, uint64_t bo_flags
,
849 VkResult
anv_bo_cache_export(struct anv_device
*device
,
850 struct anv_bo_cache
*cache
,
851 struct anv_bo
*bo_in
, int *fd_out
);
852 void anv_bo_cache_release(struct anv_device
*device
,
853 struct anv_bo_cache
*cache
,
856 struct anv_memory_type
{
857 /* Standard bits passed on to the client */
858 VkMemoryPropertyFlags propertyFlags
;
861 /* Driver-internal book-keeping */
862 VkBufferUsageFlags valid_buffer_usage
;
865 struct anv_memory_heap
{
866 /* Standard bits passed on to the client */
868 VkMemoryHeapFlags flags
;
870 /* Driver-internal book-keeping */
871 bool supports_48bit_addresses
;
874 struct anv_physical_device
{
875 VK_LOADER_DATA _loader_data
;
877 struct anv_instance
* instance
;
888 struct gen_device_info info
;
889 /** Amount of "GPU memory" we want to advertise
891 * Clearly, this value is bogus since Intel is a UMA architecture. On
892 * gen7 platforms, we are limited by GTT size unless we want to implement
893 * fine-grained tracking and GTT splitting. On Broadwell and above we are
894 * practically unlimited. However, we will never report more than 3/4 of
895 * the total system ram to try and avoid running out of RAM.
897 bool supports_48bit_addresses
;
898 struct brw_compiler
* compiler
;
899 struct isl_device isl_dev
;
900 int cmd_parser_version
;
902 bool has_exec_capture
;
905 bool has_syncobj_wait
;
906 bool has_context_priority
;
908 bool has_context_isolation
;
910 struct anv_device_extension_table supported_extensions
;
913 uint32_t subslice_total
;
917 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
919 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
922 uint8_t driver_build_sha1
[20];
923 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
924 uint8_t driver_uuid
[VK_UUID_SIZE
];
925 uint8_t device_uuid
[VK_UUID_SIZE
];
927 struct disk_cache
* disk_cache
;
929 struct wsi_device wsi_device
;
934 struct anv_app_info
{
935 const char* app_name
;
936 uint32_t app_version
;
937 const char* engine_name
;
938 uint32_t engine_version
;
939 uint32_t api_version
;
942 struct anv_instance
{
943 VK_LOADER_DATA _loader_data
;
945 VkAllocationCallbacks alloc
;
947 struct anv_app_info app_info
;
949 struct anv_instance_extension_table enabled_extensions
;
950 struct anv_instance_dispatch_table dispatch
;
951 struct anv_device_dispatch_table device_dispatch
;
953 int physicalDeviceCount
;
954 struct anv_physical_device physicalDevice
;
956 bool pipeline_cache_enabled
;
958 struct vk_debug_report_instance debug_report_callbacks
;
961 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
962 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
964 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
965 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
969 VK_LOADER_DATA _loader_data
;
971 struct anv_device
* device
;
973 VkDeviceQueueCreateFlags flags
;
976 struct anv_pipeline_cache
{
977 struct anv_device
* device
;
978 pthread_mutex_t mutex
;
980 struct hash_table
* nir_cache
;
982 struct hash_table
* cache
;
985 struct anv_pipeline_bind_map
;
987 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
988 struct anv_device
*device
,
990 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
992 struct anv_shader_bin
*
993 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
994 const void *key
, uint32_t key_size
);
995 struct anv_shader_bin
*
996 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
997 const void *key_data
, uint32_t key_size
,
998 const void *kernel_data
, uint32_t kernel_size
,
999 const void *constant_data
,
1000 uint32_t constant_data_size
,
1001 const struct brw_stage_prog_data
*prog_data
,
1002 uint32_t prog_data_size
,
1003 const struct anv_pipeline_bind_map
*bind_map
);
1005 struct anv_shader_bin
*
1006 anv_device_search_for_kernel(struct anv_device
*device
,
1007 struct anv_pipeline_cache
*cache
,
1008 const void *key_data
, uint32_t key_size
);
1010 struct anv_shader_bin
*
1011 anv_device_upload_kernel(struct anv_device
*device
,
1012 struct anv_pipeline_cache
*cache
,
1013 const void *key_data
, uint32_t key_size
,
1014 const void *kernel_data
, uint32_t kernel_size
,
1015 const void *constant_data
,
1016 uint32_t constant_data_size
,
1017 const struct brw_stage_prog_data
*prog_data
,
1018 uint32_t prog_data_size
,
1019 const struct anv_pipeline_bind_map
*bind_map
);
1022 struct nir_shader_compiler_options
;
1025 anv_device_search_for_nir(struct anv_device
*device
,
1026 struct anv_pipeline_cache
*cache
,
1027 const struct nir_shader_compiler_options
*nir_options
,
1028 unsigned char sha1_key
[20],
1032 anv_device_upload_nir(struct anv_device
*device
,
1033 struct anv_pipeline_cache
*cache
,
1034 const struct nir_shader
*nir
,
1035 unsigned char sha1_key
[20]);
1038 VK_LOADER_DATA _loader_data
;
1040 VkAllocationCallbacks alloc
;
1042 struct anv_instance
* instance
;
1043 uint32_t chipset_id
;
1045 struct gen_device_info info
;
1046 struct isl_device isl_dev
;
1049 bool can_chain_batches
;
1050 bool robust_buffer_access
;
1051 struct anv_device_extension_table enabled_extensions
;
1052 struct anv_device_dispatch_table dispatch
;
1054 pthread_mutex_t vma_mutex
;
1055 struct util_vma_heap vma_lo
;
1056 struct util_vma_heap vma_hi
;
1057 uint64_t vma_lo_available
;
1058 uint64_t vma_hi_available
;
1060 struct anv_bo_pool batch_bo_pool
;
1062 struct anv_bo_cache bo_cache
;
1064 struct anv_state_pool dynamic_state_pool
;
1065 struct anv_state_pool instruction_state_pool
;
1066 struct anv_state_pool binding_table_pool
;
1067 struct anv_state_pool surface_state_pool
;
1069 struct anv_bo workaround_bo
;
1070 struct anv_bo trivial_batch_bo
;
1071 struct anv_bo hiz_clear_bo
;
1073 struct anv_pipeline_cache default_pipeline_cache
;
1074 struct blorp_context blorp
;
1076 struct anv_state border_colors
;
1078 struct anv_queue queue
;
1080 struct anv_scratch_pool scratch_pool
;
1082 uint32_t default_mocs
;
1083 uint32_t external_mocs
;
1085 pthread_mutex_t mutex
;
1086 pthread_cond_t queue_submit
;
1090 static inline struct anv_state_pool
*
1091 anv_binding_table_pool(struct anv_device
*device
)
1093 if (device
->instance
->physicalDevice
.use_softpin
)
1094 return &device
->binding_table_pool
;
1096 return &device
->surface_state_pool
;
1099 static inline struct anv_state
1100 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1101 if (device
->instance
->physicalDevice
.use_softpin
)
1102 return anv_state_pool_alloc(&device
->binding_table_pool
,
1103 device
->binding_table_pool
.block_size
, 0);
1105 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1109 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1110 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1113 static inline uint32_t
1114 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1116 if (bo
->flags
& ANV_BO_EXTERNAL
)
1117 return device
->external_mocs
;
1119 return device
->default_mocs
;
1123 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
1125 if (device
->info
.has_llc
)
1128 gen_flush_range(state
.map
, state
.alloc_size
);
1131 void anv_device_init_blorp(struct anv_device
*device
);
1132 void anv_device_finish_blorp(struct anv_device
*device
);
1134 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1135 const char *file
, int line
,
1136 const char *msg
, ...);
1137 #define anv_device_set_lost(dev, ...) \
1138 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1141 anv_device_is_lost(struct anv_device
*device
)
1143 return unlikely(device
->_lost
);
1146 VkResult
anv_device_execbuf(struct anv_device
*device
,
1147 struct drm_i915_gem_execbuffer2
*execbuf
,
1148 struct anv_bo
**execbuf_bos
);
1149 VkResult
anv_device_query_status(struct anv_device
*device
);
1150 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1151 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1154 void* anv_gem_mmap(struct anv_device
*device
,
1155 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1156 void anv_gem_munmap(void *p
, uint64_t size
);
1157 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1158 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1159 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1160 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1161 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1162 int anv_gem_execbuffer(struct anv_device
*device
,
1163 struct drm_i915_gem_execbuffer2
*execbuf
);
1164 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1165 uint32_t stride
, uint32_t tiling
);
1166 int anv_gem_create_context(struct anv_device
*device
);
1167 bool anv_gem_has_context_priority(int fd
);
1168 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1169 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1171 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1173 int anv_gem_get_param(int fd
, uint32_t param
);
1174 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1175 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1176 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1177 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1178 uint32_t *active
, uint32_t *pending
);
1179 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1180 int anv_gem_reg_read(struct anv_device
*device
,
1181 uint32_t offset
, uint64_t *result
);
1182 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1183 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1184 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1185 uint32_t read_domains
, uint32_t write_domain
);
1186 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1187 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1188 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1189 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1190 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1191 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1193 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1194 uint32_t handle
, int fd
);
1195 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1196 bool anv_gem_supports_syncobj_wait(int fd
);
1197 int anv_gem_syncobj_wait(struct anv_device
*device
,
1198 uint32_t *handles
, uint32_t num_handles
,
1199 int64_t abs_timeout_ns
, bool wait_all
);
1201 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1202 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1204 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1206 struct anv_reloc_list
{
1207 uint32_t num_relocs
;
1208 uint32_t array_length
;
1209 struct drm_i915_gem_relocation_entry
* relocs
;
1210 struct anv_bo
** reloc_bos
;
1214 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1215 const VkAllocationCallbacks
*alloc
);
1216 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1217 const VkAllocationCallbacks
*alloc
);
1219 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1220 const VkAllocationCallbacks
*alloc
,
1221 uint32_t offset
, struct anv_bo
*target_bo
,
1224 struct anv_batch_bo
{
1225 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1226 struct list_head link
;
1230 /* Bytes actually consumed in this batch BO */
1233 struct anv_reloc_list relocs
;
1237 const VkAllocationCallbacks
* alloc
;
1243 struct anv_reloc_list
* relocs
;
1245 /* This callback is called (with the associated user data) in the event
1246 * that the batch runs out of space.
1248 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1252 * Current error status of the command buffer. Used to track inconsistent
1253 * or incomplete command buffer states that are the consequence of run-time
1254 * errors such as out of memory scenarios. We want to track this in the
1255 * batch because the command buffer object is not visible to some parts
1261 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1262 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1263 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1264 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1265 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1266 struct anv_batch
*batch
);
1268 static inline VkResult
1269 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1271 assert(error
!= VK_SUCCESS
);
1272 if (batch
->status
== VK_SUCCESS
)
1273 batch
->status
= error
;
1274 return batch
->status
;
1278 anv_batch_has_error(struct anv_batch
*batch
)
1280 return batch
->status
!= VK_SUCCESS
;
1283 struct anv_address
{
1288 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1291 anv_address_is_null(struct anv_address addr
)
1293 return addr
.bo
== NULL
&& addr
.offset
== 0;
1296 static inline uint64_t
1297 anv_address_physical(struct anv_address addr
)
1299 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1300 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1302 return gen_canonical_address(addr
.offset
);
1305 static inline struct anv_address
1306 anv_address_add(struct anv_address addr
, uint64_t offset
)
1308 addr
.offset
+= offset
;
1313 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1315 unsigned reloc_size
= 0;
1316 if (device
->info
.gen
>= 8) {
1317 reloc_size
= sizeof(uint64_t);
1318 *(uint64_t *)p
= gen_canonical_address(v
);
1320 reloc_size
= sizeof(uint32_t);
1324 if (flush
&& !device
->info
.has_llc
)
1325 gen_flush_range(p
, reloc_size
);
1328 static inline uint64_t
1329 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1330 const struct anv_address address
, uint32_t delta
)
1332 if (address
.bo
== NULL
) {
1333 return address
.offset
+ delta
;
1335 assert(batch
->start
<= location
&& location
< batch
->end
);
1337 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1341 #define __gen_address_type struct anv_address
1342 #define __gen_user_data struct anv_batch
1343 #define __gen_combine_address _anv_combine_address
1345 /* Wrapper macros needed to work around preprocessor argument issues. In
1346 * particular, arguments don't get pre-evaluated if they are concatenated.
1347 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1348 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1349 * We can work around this easily enough with these helpers.
1351 #define __anv_cmd_length(cmd) cmd ## _length
1352 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1353 #define __anv_cmd_header(cmd) cmd ## _header
1354 #define __anv_cmd_pack(cmd) cmd ## _pack
1355 #define __anv_reg_num(reg) reg ## _num
1357 #define anv_pack_struct(dst, struc, ...) do { \
1358 struct struc __template = { \
1361 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1362 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1365 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1366 void *__dst = anv_batch_emit_dwords(batch, n); \
1368 struct cmd __template = { \
1369 __anv_cmd_header(cmd), \
1370 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1373 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1378 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1382 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1383 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1386 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1387 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1388 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1391 #define anv_batch_emit(batch, cmd, name) \
1392 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1393 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1394 __builtin_expect(_dst != NULL, 1); \
1395 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1396 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1400 /* MEMORY_OBJECT_CONTROL_STATE:
1401 * .GraphicsDataTypeGFDT = 0,
1402 * .LLCCacheabilityControlLLCCC = 0,
1403 * .L3CacheabilityControlL3CC = 1,
1407 /* MEMORY_OBJECT_CONTROL_STATE:
1408 * .LLCeLLCCacheabilityControlLLCCC = 0,
1409 * .L3CacheabilityControlL3CC = 1,
1411 #define GEN75_MOCS 1
1413 /* MEMORY_OBJECT_CONTROL_STATE:
1414 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1415 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1416 * .AgeforQUADLRU = 0
1418 #define GEN8_MOCS 0x78
1420 /* MEMORY_OBJECT_CONTROL_STATE:
1421 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1422 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1423 * .AgeforQUADLRU = 0
1425 #define GEN8_EXTERNAL_MOCS 0x18
1427 /* Skylake: MOCS is now an index into an array of 62 different caching
1428 * configurations programmed by the kernel.
1431 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1434 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1435 #define GEN9_EXTERNAL_MOCS 1
1437 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1438 #define GEN10_MOCS GEN9_MOCS
1439 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1441 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1442 #define GEN11_MOCS GEN9_MOCS
1443 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1445 struct anv_device_memory
{
1447 struct anv_memory_type
* type
;
1448 VkDeviceSize map_size
;
1451 /* If set, we are holding reference to AHardwareBuffer
1452 * which we must release when memory is freed.
1454 struct AHardwareBuffer
* ahw
;
1458 * Header for Vertex URB Entry (VUE)
1460 struct anv_vue_header
{
1462 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1463 uint32_t ViewportIndex
;
1467 struct anv_descriptor_set_binding_layout
{
1469 /* The type of the descriptors in this binding */
1470 VkDescriptorType type
;
1473 /* Number of array elements in this binding */
1474 uint16_t array_size
;
1476 /* Index into the flattend descriptor set */
1477 uint16_t descriptor_index
;
1479 /* Index into the dynamic state array for a dynamic buffer */
1480 int16_t dynamic_offset_index
;
1482 /* Index into the descriptor set buffer views */
1483 int16_t buffer_index
;
1486 /* Index into the binding table for the associated surface */
1487 int16_t surface_index
;
1489 /* Index into the sampler table for the associated sampler */
1490 int16_t sampler_index
;
1492 /* Index into the image table for the associated image */
1493 int16_t image_index
;
1494 } stage
[MESA_SHADER_STAGES
];
1496 /* Immutable samplers (or NULL if no immutable samplers) */
1497 struct anv_sampler
**immutable_samplers
;
1500 struct anv_descriptor_set_layout
{
1501 /* Descriptor set layouts can be destroyed at almost any time */
1504 /* Number of bindings in this descriptor set */
1505 uint16_t binding_count
;
1507 /* Total size of the descriptor set with room for all array entries */
1510 /* Shader stages affected by this descriptor set */
1511 uint16_t shader_stages
;
1513 /* Number of buffers in this descriptor set */
1514 uint16_t buffer_count
;
1516 /* Number of dynamic offsets used by this descriptor set */
1517 uint16_t dynamic_offset_count
;
1519 /* Bindings in this descriptor set */
1520 struct anv_descriptor_set_binding_layout binding
[0];
1524 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1526 assert(layout
&& layout
->ref_cnt
>= 1);
1527 p_atomic_inc(&layout
->ref_cnt
);
1531 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1532 struct anv_descriptor_set_layout
*layout
)
1534 assert(layout
&& layout
->ref_cnt
>= 1);
1535 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1536 vk_free(&device
->alloc
, layout
);
1539 struct anv_descriptor
{
1540 VkDescriptorType type
;
1544 VkImageLayout layout
;
1545 struct anv_image_view
*image_view
;
1546 struct anv_sampler
*sampler
;
1550 struct anv_buffer
*buffer
;
1555 struct anv_buffer_view
*buffer_view
;
1559 struct anv_descriptor_set
{
1560 struct anv_descriptor_set_layout
*layout
;
1562 uint32_t buffer_count
;
1563 struct anv_buffer_view
*buffer_views
;
1564 struct anv_descriptor descriptors
[0];
1567 struct anv_buffer_view
{
1568 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1569 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1571 struct anv_address address
;
1573 struct anv_state surface_state
;
1574 struct anv_state storage_surface_state
;
1575 struct anv_state writeonly_storage_surface_state
;
1577 struct brw_image_param storage_image_param
;
1580 struct anv_push_descriptor_set
{
1581 struct anv_descriptor_set set
;
1583 /* Put this field right behind anv_descriptor_set so it fills up the
1584 * descriptors[0] field. */
1585 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1586 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1589 struct anv_descriptor_pool
{
1594 struct anv_state_stream surface_state_stream
;
1595 void *surface_state_free_list
;
1600 enum anv_descriptor_template_entry_type
{
1601 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1602 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1603 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1606 struct anv_descriptor_template_entry
{
1607 /* The type of descriptor in this entry */
1608 VkDescriptorType type
;
1610 /* Binding in the descriptor set */
1613 /* Offset at which to write into the descriptor set binding */
1614 uint32_t array_element
;
1616 /* Number of elements to write into the descriptor set binding */
1617 uint32_t array_count
;
1619 /* Offset into the user provided data */
1622 /* Stride between elements into the user provided data */
1626 struct anv_descriptor_update_template
{
1627 VkPipelineBindPoint bind_point
;
1629 /* The descriptor set this template corresponds to. This value is only
1630 * valid if the template was created with the templateType
1631 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1635 /* Number of entries in this template */
1636 uint32_t entry_count
;
1638 /* Entries of the template */
1639 struct anv_descriptor_template_entry entries
[0];
1643 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1646 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1647 const struct gen_device_info
* const devinfo
,
1648 const VkDescriptorImageInfo
* const info
,
1649 VkDescriptorType type
,
1654 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1655 VkDescriptorType type
,
1656 struct anv_buffer_view
*buffer_view
,
1661 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1662 struct anv_device
*device
,
1663 struct anv_state_stream
*alloc_stream
,
1664 VkDescriptorType type
,
1665 struct anv_buffer
*buffer
,
1668 VkDeviceSize offset
,
1669 VkDeviceSize range
);
1672 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1673 struct anv_device
*device
,
1674 struct anv_state_stream
*alloc_stream
,
1675 const struct anv_descriptor_update_template
*template,
1679 anv_descriptor_set_create(struct anv_device
*device
,
1680 struct anv_descriptor_pool
*pool
,
1681 struct anv_descriptor_set_layout
*layout
,
1682 struct anv_descriptor_set
**out_set
);
1685 anv_descriptor_set_destroy(struct anv_device
*device
,
1686 struct anv_descriptor_pool
*pool
,
1687 struct anv_descriptor_set
*set
);
1689 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1690 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1692 struct anv_pipeline_binding
{
1693 /* The descriptor set this surface corresponds to. The special value of
1694 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1695 * to a color attachment and not a regular descriptor.
1699 /* Binding in the descriptor set */
1702 /* Index in the binding */
1705 /* Plane in the binding index */
1708 /* Input attachment index (relative to the subpass) */
1709 uint8_t input_attachment_index
;
1711 /* For a storage image, whether it is write-only */
1715 struct anv_pipeline_layout
{
1717 struct anv_descriptor_set_layout
*layout
;
1718 uint32_t dynamic_offset_start
;
1724 bool has_dynamic_offsets
;
1725 } stage
[MESA_SHADER_STAGES
];
1727 unsigned char sha1
[20];
1731 struct anv_device
* device
;
1734 VkBufferUsageFlags usage
;
1736 /* Set when bound */
1737 struct anv_address address
;
1740 static inline uint64_t
1741 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1743 assert(offset
<= buffer
->size
);
1744 if (range
== VK_WHOLE_SIZE
) {
1745 return buffer
->size
- offset
;
1747 assert(range
+ offset
>= range
);
1748 assert(range
+ offset
<= buffer
->size
);
1753 enum anv_cmd_dirty_bits
{
1754 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1755 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1756 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1757 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1758 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1759 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1760 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1761 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1762 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1763 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1764 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1765 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1766 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1768 typedef uint32_t anv_cmd_dirty_mask_t
;
1770 enum anv_pipe_bits
{
1771 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1772 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1773 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1774 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1775 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1776 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1777 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1778 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1779 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1780 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1781 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1783 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1784 * a flush has happened but not a CS stall. The next time we do any sort
1785 * of invalidation we need to insert a CS stall at that time. Otherwise,
1786 * we would have to CS stall on every flush which could be bad.
1788 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1790 /* This bit does not exist directly in PIPE_CONTROL. It means that render
1791 * target operations are ongoing. Some operations like copies on the
1792 * command streamer might need to be aware of this to trigger the
1793 * appropriate stall before they can proceed with the copy.
1795 ANV_PIPE_RENDER_TARGET_WRITES
= (1 << 22),
1798 #define ANV_PIPE_FLUSH_BITS ( \
1799 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1800 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1801 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1803 #define ANV_PIPE_STALL_BITS ( \
1804 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1805 ANV_PIPE_DEPTH_STALL_BIT | \
1806 ANV_PIPE_CS_STALL_BIT)
1808 #define ANV_PIPE_INVALIDATE_BITS ( \
1809 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1810 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1811 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1812 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1813 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1814 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1816 static inline enum anv_pipe_bits
1817 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1819 enum anv_pipe_bits pipe_bits
= 0;
1822 for_each_bit(b
, flags
) {
1823 switch ((VkAccessFlagBits
)(1 << b
)) {
1824 case VK_ACCESS_SHADER_WRITE_BIT
:
1825 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1827 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1828 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1830 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1831 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1833 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1834 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1835 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1837 case VK_ACCESS_MEMORY_WRITE_BIT
:
1838 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
1841 break; /* Nothing to do */
1848 static inline enum anv_pipe_bits
1849 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1851 enum anv_pipe_bits pipe_bits
= 0;
1854 for_each_bit(b
, flags
) {
1855 switch ((VkAccessFlagBits
)(1 << b
)) {
1856 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1857 case VK_ACCESS_INDEX_READ_BIT
:
1858 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1859 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1861 case VK_ACCESS_UNIFORM_READ_BIT
:
1862 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1863 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1865 case VK_ACCESS_SHADER_READ_BIT
:
1866 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1867 case VK_ACCESS_TRANSFER_READ_BIT
:
1868 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1870 case VK_ACCESS_MEMORY_READ_BIT
:
1871 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
1873 case VK_ACCESS_MEMORY_WRITE_BIT
:
1874 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
1877 break; /* Nothing to do */
1884 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1885 VK_IMAGE_ASPECT_COLOR_BIT | \
1886 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1887 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1888 VK_IMAGE_ASPECT_PLANE_2_BIT)
1889 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1890 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1891 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1892 VK_IMAGE_ASPECT_PLANE_2_BIT)
1894 struct anv_vertex_binding
{
1895 struct anv_buffer
* buffer
;
1896 VkDeviceSize offset
;
1899 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1900 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1902 struct anv_push_constants
{
1903 /* Current allocated size of this push constants data structure.
1904 * Because a decent chunk of it may not be used (images on SKL, for
1905 * instance), we won't actually allocate the entire structure up-front.
1909 /* Push constant data provided by the client through vkPushConstants */
1910 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1912 /* Used for vkCmdDispatchBase */
1913 uint32_t base_work_group_id
[3];
1915 /* Image data for image_load_store on pre-SKL */
1916 struct brw_image_param images
[MAX_GEN8_IMAGES
];
1919 struct anv_dynamic_state
{
1922 VkViewport viewports
[MAX_VIEWPORTS
];
1927 VkRect2D scissors
[MAX_SCISSORS
];
1938 float blend_constants
[4];
1948 } stencil_compare_mask
;
1953 } stencil_write_mask
;
1958 } stencil_reference
;
1961 extern const struct anv_dynamic_state default_dynamic_state
;
1963 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1964 const struct anv_dynamic_state
*src
,
1965 uint32_t copy_mask
);
1967 struct anv_surface_state
{
1968 struct anv_state state
;
1969 /** Address of the surface referred to by this state
1971 * This address is relative to the start of the BO.
1973 struct anv_address address
;
1974 /* Address of the aux surface, if any
1976 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
1978 * With the exception of gen8, the bottom 12 bits of this address' offset
1979 * include extra aux information.
1981 struct anv_address aux_address
;
1982 /* Address of the clear color, if any
1984 * This address is relative to the start of the BO.
1986 struct anv_address clear_address
;
1990 * Attachment state when recording a renderpass instance.
1992 * The clear value is valid only if there exists a pending clear.
1994 struct anv_attachment_state
{
1995 enum isl_aux_usage aux_usage
;
1996 enum isl_aux_usage input_aux_usage
;
1997 struct anv_surface_state color
;
1998 struct anv_surface_state input
;
2000 VkImageLayout current_layout
;
2001 VkImageAspectFlags pending_clear_aspects
;
2002 VkImageAspectFlags pending_load_aspects
;
2004 VkClearValue clear_value
;
2005 bool clear_color_is_zero_one
;
2006 bool clear_color_is_zero
;
2008 /* When multiview is active, attachments with a renderpass clear
2009 * operation have their respective layers cleared on the first
2010 * subpass that uses them, and only in that subpass. We keep track
2011 * of this using a bitfield to indicate which layers of an attachment
2012 * have not been cleared yet when multiview is active.
2014 uint32_t pending_clear_views
;
2017 /** State tracking for particular pipeline bind point
2019 * This struct is the base struct for anv_cmd_graphics_state and
2020 * anv_cmd_compute_state. These are used to track state which is bound to a
2021 * particular type of pipeline. Generic state that applies per-stage such as
2022 * binding table offsets and push constants is tracked generically with a
2023 * per-stage array in anv_cmd_state.
2025 struct anv_cmd_pipeline_state
{
2026 struct anv_pipeline
*pipeline
;
2027 struct anv_pipeline_layout
*layout
;
2029 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2030 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2032 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2035 /** State tracking for graphics pipeline
2037 * This has anv_cmd_pipeline_state as a base struct to track things which get
2038 * bound to a graphics pipeline. Along with general pipeline bind point state
2039 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2040 * state which is graphics-specific.
2042 struct anv_cmd_graphics_state
{
2043 struct anv_cmd_pipeline_state base
;
2045 anv_cmd_dirty_mask_t dirty
;
2048 struct anv_dynamic_state dynamic
;
2051 struct anv_buffer
*index_buffer
;
2052 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2053 uint32_t index_offset
;
2057 /** State tracking for compute pipeline
2059 * This has anv_cmd_pipeline_state as a base struct to track things which get
2060 * bound to a compute pipeline. Along with general pipeline bind point state
2061 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2062 * state which is compute-specific.
2064 struct anv_cmd_compute_state
{
2065 struct anv_cmd_pipeline_state base
;
2067 bool pipeline_dirty
;
2069 struct anv_address num_workgroups
;
2072 /** State required while building cmd buffer */
2073 struct anv_cmd_state
{
2074 /* PIPELINE_SELECT.PipelineSelection */
2075 uint32_t current_pipeline
;
2076 const struct gen_l3_config
* current_l3_config
;
2078 struct anv_cmd_graphics_state gfx
;
2079 struct anv_cmd_compute_state compute
;
2081 enum anv_pipe_bits pending_pipe_bits
;
2082 VkShaderStageFlags descriptors_dirty
;
2083 VkShaderStageFlags push_constants_dirty
;
2085 struct anv_framebuffer
* framebuffer
;
2086 struct anv_render_pass
* pass
;
2087 struct anv_subpass
* subpass
;
2088 VkRect2D render_area
;
2089 uint32_t restart_index
;
2090 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2091 VkShaderStageFlags push_constant_stages
;
2092 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
2093 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2094 struct anv_state samplers
[MESA_SHADER_STAGES
];
2097 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2098 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2099 * and before invoking the secondary in ExecuteCommands.
2101 bool pma_fix_enabled
;
2104 * Whether or not we know for certain that HiZ is enabled for the current
2105 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2106 * enabled or not, this will be false.
2111 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2112 * valid only when recording a render pass instance.
2114 struct anv_attachment_state
* attachments
;
2117 * Surface states for color render targets. These are stored in a single
2118 * flat array. For depth-stencil attachments, the surface state is simply
2121 struct anv_state render_pass_states
;
2124 * A null surface state of the right size to match the framebuffer. This
2125 * is one of the states in render_pass_states.
2127 struct anv_state null_surface_state
;
2130 struct anv_cmd_pool
{
2131 VkAllocationCallbacks alloc
;
2132 struct list_head cmd_buffers
;
2135 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2137 enum anv_cmd_buffer_exec_mode
{
2138 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2139 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2140 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2141 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2142 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2145 struct anv_cmd_buffer
{
2146 VK_LOADER_DATA _loader_data
;
2148 struct anv_device
* device
;
2150 struct anv_cmd_pool
* pool
;
2151 struct list_head pool_link
;
2153 struct anv_batch batch
;
2155 /* Fields required for the actual chain of anv_batch_bo's.
2157 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2159 struct list_head batch_bos
;
2160 enum anv_cmd_buffer_exec_mode exec_mode
;
2162 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2163 * referenced by this command buffer
2165 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2167 struct u_vector seen_bbos
;
2169 /* A vector of int32_t's for every block of binding tables.
2171 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2173 struct u_vector bt_block_states
;
2176 struct anv_reloc_list surface_relocs
;
2177 /** Last seen surface state block pool center bo offset */
2178 uint32_t last_ss_pool_center
;
2180 /* Serial for tracking buffer completion */
2183 /* Stream objects for storing temporary data */
2184 struct anv_state_stream surface_state_stream
;
2185 struct anv_state_stream dynamic_state_stream
;
2187 VkCommandBufferUsageFlags usage_flags
;
2188 VkCommandBufferLevel level
;
2190 struct anv_cmd_state state
;
2193 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2194 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2195 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2196 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2197 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2198 struct anv_cmd_buffer
*secondary
);
2199 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2200 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2201 struct anv_cmd_buffer
*cmd_buffer
,
2202 const VkSemaphore
*in_semaphores
,
2203 uint32_t num_in_semaphores
,
2204 const VkSemaphore
*out_semaphores
,
2205 uint32_t num_out_semaphores
,
2208 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2211 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
2212 gl_shader_stage stage
, uint32_t size
);
2213 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
2214 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
2215 (offsetof(struct anv_push_constants, field) + \
2216 sizeof(cmd_buffer->state.push_constants[0]->field)))
2218 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2219 const void *data
, uint32_t size
, uint32_t alignment
);
2220 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2221 uint32_t *a
, uint32_t *b
,
2222 uint32_t dwords
, uint32_t alignment
);
2225 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2227 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2228 uint32_t entries
, uint32_t *state_offset
);
2230 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2232 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2233 uint32_t size
, uint32_t alignment
);
2236 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2238 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2239 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2240 bool depth_clamp_enable
);
2241 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2243 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2244 struct anv_render_pass
*pass
,
2245 struct anv_framebuffer
*framebuffer
,
2246 const VkClearValue
*clear_values
);
2248 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2251 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2252 gl_shader_stage stage
);
2254 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2256 const struct anv_image_view
*
2257 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2260 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2261 uint32_t num_entries
,
2262 uint32_t *state_offset
,
2263 struct anv_state
*bt_state
);
2265 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2267 enum anv_fence_type
{
2268 ANV_FENCE_TYPE_NONE
= 0,
2270 ANV_FENCE_TYPE_SYNCOBJ
,
2274 enum anv_bo_fence_state
{
2275 /** Indicates that this is a new (or newly reset fence) */
2276 ANV_BO_FENCE_STATE_RESET
,
2278 /** Indicates that this fence has been submitted to the GPU but is still
2279 * (as far as we know) in use by the GPU.
2281 ANV_BO_FENCE_STATE_SUBMITTED
,
2283 ANV_BO_FENCE_STATE_SIGNALED
,
2286 struct anv_fence_impl
{
2287 enum anv_fence_type type
;
2290 /** Fence implementation for BO fences
2292 * These fences use a BO and a set of CPU-tracked state flags. The BO
2293 * is added to the object list of the last execbuf call in a QueueSubmit
2294 * and is marked EXEC_WRITE. The state flags track when the BO has been
2295 * submitted to the kernel. We need to do this because Vulkan lets you
2296 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2297 * will say it's idle in this case.
2301 enum anv_bo_fence_state state
;
2304 /** DRM syncobj handle for syncobj-based fences */
2308 struct wsi_fence
*fence_wsi
;
2313 /* Permanent fence state. Every fence has some form of permanent state
2314 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2315 * cross-process fences) or it could just be a dummy for use internally.
2317 struct anv_fence_impl permanent
;
2319 /* Temporary fence state. A fence *may* have temporary state. That state
2320 * is added to the fence by an import operation and is reset back to
2321 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2322 * state cannot be signaled because the fence must already be signaled
2323 * before the temporary state can be exported from the fence in the other
2324 * process and imported here.
2326 struct anv_fence_impl temporary
;
2331 struct anv_state state
;
2334 enum anv_semaphore_type
{
2335 ANV_SEMAPHORE_TYPE_NONE
= 0,
2336 ANV_SEMAPHORE_TYPE_DUMMY
,
2337 ANV_SEMAPHORE_TYPE_BO
,
2338 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2339 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2342 struct anv_semaphore_impl
{
2343 enum anv_semaphore_type type
;
2346 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2347 * This BO will be added to the object list on any execbuf2 calls for
2348 * which this semaphore is used as a wait or signal fence. When used as
2349 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2353 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2354 * If the semaphore is in the unsignaled state due to either just being
2355 * created or because it has been used for a wait, fd will be -1.
2359 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2360 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2361 * import so we don't need to bother with a userspace cache.
2367 struct anv_semaphore
{
2368 /* Permanent semaphore state. Every semaphore has some form of permanent
2369 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2370 * (for cross-process semaphores0 or it could just be a dummy for use
2373 struct anv_semaphore_impl permanent
;
2375 /* Temporary semaphore state. A semaphore *may* have temporary state.
2376 * That state is added to the semaphore by an import operation and is reset
2377 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2378 * semaphore with temporary state cannot be signaled because the semaphore
2379 * must already be signaled before the temporary state can be exported from
2380 * the semaphore in the other process and imported here.
2382 struct anv_semaphore_impl temporary
;
2385 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2386 struct anv_semaphore
*semaphore
);
2388 struct anv_shader_module
{
2389 unsigned char sha1
[20];
2394 static inline gl_shader_stage
2395 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2397 assert(__builtin_popcount(vk_stage
) == 1);
2398 return ffs(vk_stage
) - 1;
2401 static inline VkShaderStageFlagBits
2402 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2404 return (1 << mesa_stage
);
2407 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2409 #define anv_foreach_stage(stage, stage_bits) \
2410 for (gl_shader_stage stage, \
2411 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2412 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2413 __tmp &= ~(1 << (stage)))
2415 struct anv_pipeline_bind_map
{
2416 uint32_t surface_count
;
2417 uint32_t sampler_count
;
2418 uint32_t image_count
;
2420 struct anv_pipeline_binding
* surface_to_descriptor
;
2421 struct anv_pipeline_binding
* sampler_to_descriptor
;
2424 struct anv_shader_bin_key
{
2429 struct anv_shader_bin
{
2432 const struct anv_shader_bin_key
*key
;
2434 struct anv_state kernel
;
2435 uint32_t kernel_size
;
2437 struct anv_state constant_data
;
2438 uint32_t constant_data_size
;
2440 const struct brw_stage_prog_data
*prog_data
;
2441 uint32_t prog_data_size
;
2443 struct anv_pipeline_bind_map bind_map
;
2446 struct anv_shader_bin
*
2447 anv_shader_bin_create(struct anv_device
*device
,
2448 const void *key
, uint32_t key_size
,
2449 const void *kernel
, uint32_t kernel_size
,
2450 const void *constant_data
, uint32_t constant_data_size
,
2451 const struct brw_stage_prog_data
*prog_data
,
2452 uint32_t prog_data_size
, const void *prog_data_param
,
2453 const struct anv_pipeline_bind_map
*bind_map
);
2456 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2459 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2461 assert(shader
&& shader
->ref_cnt
>= 1);
2462 p_atomic_inc(&shader
->ref_cnt
);
2466 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2468 assert(shader
&& shader
->ref_cnt
>= 1);
2469 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2470 anv_shader_bin_destroy(device
, shader
);
2473 struct anv_pipeline
{
2474 struct anv_device
* device
;
2475 struct anv_batch batch
;
2476 uint32_t batch_data
[512];
2477 struct anv_reloc_list batch_relocs
;
2478 uint32_t dynamic_state_mask
;
2479 struct anv_dynamic_state dynamic_state
;
2481 struct anv_subpass
* subpass
;
2483 bool needs_data_cache
;
2485 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2488 const struct gen_l3_config
* l3_config
;
2489 uint32_t total_size
;
2492 VkShaderStageFlags active_stages
;
2493 struct anv_state blend_state
;
2496 struct anv_pipeline_vertex_binding
{
2499 uint32_t instance_divisor
;
2502 bool primitive_restart
;
2505 uint32_t cs_right_mask
;
2508 bool depth_test_enable
;
2509 bool writes_stencil
;
2510 bool stencil_test_enable
;
2511 bool depth_clamp_enable
;
2512 bool sample_shading_enable
;
2517 uint32_t depth_stencil_state
[3];
2523 uint32_t wm_depth_stencil
[3];
2527 uint32_t wm_depth_stencil
[4];
2530 uint32_t interface_descriptor_data
[8];
2534 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2535 gl_shader_stage stage
)
2537 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2540 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2541 static inline const struct brw_##prefix##_prog_data * \
2542 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2544 if (anv_pipeline_has_stage(pipeline, stage)) { \
2545 return (const struct brw_##prefix##_prog_data *) \
2546 pipeline->shaders[stage]->prog_data; \
2552 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2553 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2554 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2555 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2556 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2557 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2559 static inline const struct brw_vue_prog_data
*
2560 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2562 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2563 return &get_gs_prog_data(pipeline
)->base
;
2564 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2565 return &get_tes_prog_data(pipeline
)->base
;
2567 return &get_vs_prog_data(pipeline
)->base
;
2571 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2572 struct anv_pipeline_cache
*cache
,
2573 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2574 const VkAllocationCallbacks
*alloc
);
2577 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2578 struct anv_pipeline_cache
*cache
,
2579 const VkComputePipelineCreateInfo
*info
,
2580 const struct anv_shader_module
*module
,
2581 const char *entrypoint
,
2582 const VkSpecializationInfo
*spec_info
);
2584 struct anv_format_plane
{
2585 enum isl_format isl_format
:16;
2586 struct isl_swizzle swizzle
;
2588 /* Whether this plane contains chroma channels */
2591 /* For downscaling of YUV planes */
2592 uint8_t denominator_scales
[2];
2594 /* How to map sampled ycbcr planes to a single 4 component element. */
2595 struct isl_swizzle ycbcr_swizzle
;
2597 /* What aspect is associated to this plane */
2598 VkImageAspectFlags aspect
;
2603 struct anv_format_plane planes
[3];
2609 static inline uint32_t
2610 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2611 VkImageAspectFlags aspect_mask
)
2613 switch (aspect_mask
) {
2614 case VK_IMAGE_ASPECT_COLOR_BIT
:
2615 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2616 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2618 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2619 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2622 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2624 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2627 /* Purposefully assert with depth/stencil aspects. */
2628 unreachable("invalid image aspect");
2632 static inline VkImageAspectFlags
2633 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
2636 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2637 if (util_bitcount(image_aspects
) > 1)
2638 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
2639 return VK_IMAGE_ASPECT_COLOR_BIT
;
2641 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
2642 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
2643 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
2644 return VK_IMAGE_ASPECT_STENCIL_BIT
;
2647 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2648 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2650 const struct anv_format
*
2651 anv_get_format(VkFormat format
);
2653 static inline uint32_t
2654 anv_get_format_planes(VkFormat vk_format
)
2656 const struct anv_format
*format
= anv_get_format(vk_format
);
2658 return format
!= NULL
? format
->n_planes
: 0;
2661 struct anv_format_plane
2662 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2663 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
2665 static inline enum isl_format
2666 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2667 VkImageAspectFlags aspect
, VkImageTiling tiling
)
2669 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
2672 static inline struct isl_swizzle
2673 anv_swizzle_for_render(struct isl_swizzle swizzle
)
2675 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2676 * RGB as RGBA for texturing
2678 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
2679 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
2681 /* But it doesn't matter what we render to that channel */
2682 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
2688 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
2691 * Subsurface of an anv_image.
2693 struct anv_surface
{
2694 /** Valid only if isl_surf::size_B > 0. */
2695 struct isl_surf isl
;
2698 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2705 /* The original VkFormat provided by the client. This may not match any
2706 * of the actual surface formats.
2709 const struct anv_format
*format
;
2711 VkImageAspectFlags aspects
;
2714 uint32_t array_size
;
2715 uint32_t samples
; /**< VkImageCreateInfo::samples */
2717 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2718 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
2719 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2721 /** True if this is needs to be bound to an appropriately tiled BO.
2723 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2724 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2725 * we require a dedicated allocation so that we can know to allocate a
2728 bool needs_set_tiling
;
2731 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2732 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2734 uint64_t drm_format_mod
;
2739 /* Whether the image is made of several underlying buffer objects rather a
2740 * single one with different offsets.
2744 /* All the formats that can be used when creating views of this image
2745 * are CCS_E compatible.
2747 bool ccs_e_compatible
;
2749 /* Image was created with external format. */
2750 bool external_format
;
2755 * For each foo, anv_image::planes[x].surface is valid if and only if
2756 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2757 * to figure the number associated with a given aspect.
2759 * The hardware requires that the depth buffer and stencil buffer be
2760 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2761 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2762 * allocate the depth and stencil buffers as separate surfaces in the same
2767 * -----------------------
2769 * ----------------------- |
2770 * | shadow surface0 | |
2771 * ----------------------- | Plane 0
2772 * | aux surface0 | |
2773 * ----------------------- |
2774 * | fast clear colors0 | \|/
2775 * -----------------------
2777 * ----------------------- |
2778 * | shadow surface1 | |
2779 * ----------------------- | Plane 1
2780 * | aux surface1 | |
2781 * ----------------------- |
2782 * | fast clear colors1 | \|/
2783 * -----------------------
2786 * -----------------------
2790 * Offset of the entire plane (whenever the image is disjoint this is
2798 struct anv_surface surface
;
2801 * A surface which shadows the main surface and may have different
2802 * tiling. This is used for sampling using a tiling that isn't supported
2803 * for other operations.
2805 struct anv_surface shadow_surface
;
2808 * For color images, this is the aux usage for this image when not used
2809 * as a color attachment.
2811 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2812 * image has a HiZ buffer.
2814 enum isl_aux_usage aux_usage
;
2816 struct anv_surface aux_surface
;
2819 * Offset of the fast clear state (used to compute the
2820 * fast_clear_state_offset of the following planes).
2822 uint32_t fast_clear_state_offset
;
2825 * BO associated with this plane, set when bound.
2827 struct anv_address address
;
2830 * When destroying the image, also free the bo.
2836 /* The ordering of this enum is important */
2837 enum anv_fast_clear_type
{
2838 /** Image does not have/support any fast-clear blocks */
2839 ANV_FAST_CLEAR_NONE
= 0,
2840 /** Image has/supports fast-clear but only to the default value */
2841 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
2842 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2843 ANV_FAST_CLEAR_ANY
= 2,
2846 /* Returns the number of auxiliary buffer levels attached to an image. */
2847 static inline uint8_t
2848 anv_image_aux_levels(const struct anv_image
* const image
,
2849 VkImageAspectFlagBits aspect
)
2851 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2852 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
2853 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
2856 /* Returns the number of auxiliary buffer layers attached to an image. */
2857 static inline uint32_t
2858 anv_image_aux_layers(const struct anv_image
* const image
,
2859 VkImageAspectFlagBits aspect
,
2860 const uint8_t miplevel
)
2864 /* The miplevel must exist in the main buffer. */
2865 assert(miplevel
< image
->levels
);
2867 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
2868 /* There are no layers with auxiliary data because the miplevel has no
2873 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2874 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
2875 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
2879 static inline struct anv_address
2880 anv_image_get_clear_color_addr(const struct anv_device
*device
,
2881 const struct anv_image
*image
,
2882 VkImageAspectFlagBits aspect
)
2884 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
2886 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2887 return anv_address_add(image
->planes
[plane
].address
,
2888 image
->planes
[plane
].fast_clear_state_offset
);
2891 static inline struct anv_address
2892 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
2893 const struct anv_image
*image
,
2894 VkImageAspectFlagBits aspect
)
2896 struct anv_address addr
=
2897 anv_image_get_clear_color_addr(device
, image
, aspect
);
2899 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
2900 device
->isl_dev
.ss
.clear_color_state_size
:
2901 device
->isl_dev
.ss
.clear_value_size
;
2902 return anv_address_add(addr
, clear_color_state_size
);
2905 static inline struct anv_address
2906 anv_image_get_compression_state_addr(const struct anv_device
*device
,
2907 const struct anv_image
*image
,
2908 VkImageAspectFlagBits aspect
,
2909 uint32_t level
, uint32_t array_layer
)
2911 assert(level
< anv_image_aux_levels(image
, aspect
));
2912 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
2913 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2914 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
2916 struct anv_address addr
=
2917 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
2918 addr
.offset
+= 4; /* Go past the fast clear type */
2920 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2921 for (uint32_t l
= 0; l
< level
; l
++)
2922 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
2924 addr
.offset
+= level
* image
->array_size
* 4;
2926 addr
.offset
+= array_layer
* 4;
2931 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2933 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
2934 const struct anv_image
*image
)
2936 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
2939 if (devinfo
->gen
< 8)
2942 return image
->samples
== 1;
2946 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
2947 const struct anv_image
*image
,
2948 VkImageAspectFlagBits aspect
,
2949 enum isl_aux_usage aux_usage
,
2951 uint32_t base_layer
,
2952 uint32_t layer_count
);
2955 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
2956 const struct anv_image
*image
,
2957 VkImageAspectFlagBits aspect
,
2958 enum isl_aux_usage aux_usage
,
2959 enum isl_format format
, struct isl_swizzle swizzle
,
2960 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
2961 VkRect2D area
, union isl_color_value clear_color
);
2963 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
2964 const struct anv_image
*image
,
2965 VkImageAspectFlags aspects
,
2966 enum isl_aux_usage depth_aux_usage
,
2968 uint32_t base_layer
, uint32_t layer_count
,
2970 float depth_value
, uint8_t stencil_value
);
2972 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
2973 const struct anv_image
*src_image
,
2974 enum isl_aux_usage src_aux_usage
,
2975 uint32_t src_level
, uint32_t src_base_layer
,
2976 const struct anv_image
*dst_image
,
2977 enum isl_aux_usage dst_aux_usage
,
2978 uint32_t dst_level
, uint32_t dst_base_layer
,
2979 VkImageAspectFlagBits aspect
,
2980 uint32_t src_x
, uint32_t src_y
,
2981 uint32_t dst_x
, uint32_t dst_y
,
2982 uint32_t width
, uint32_t height
,
2983 uint32_t layer_count
,
2984 enum blorp_filter filter
);
2986 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
2987 const struct anv_image
*image
,
2988 VkImageAspectFlagBits aspect
, uint32_t level
,
2989 uint32_t base_layer
, uint32_t layer_count
,
2990 enum isl_aux_op hiz_op
);
2992 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
2993 const struct anv_image
*image
,
2994 VkImageAspectFlags aspects
,
2996 uint32_t base_layer
, uint32_t layer_count
,
2997 VkRect2D area
, uint8_t stencil_value
);
2999 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3000 const struct anv_image
*image
,
3001 enum isl_format format
,
3002 VkImageAspectFlagBits aspect
,
3003 uint32_t base_layer
, uint32_t layer_count
,
3004 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3007 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3008 const struct anv_image
*image
,
3009 enum isl_format format
,
3010 VkImageAspectFlagBits aspect
, uint32_t level
,
3011 uint32_t base_layer
, uint32_t layer_count
,
3012 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3016 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3017 const struct anv_image
*image
,
3018 uint32_t base_level
, uint32_t level_count
,
3019 uint32_t base_layer
, uint32_t layer_count
);
3022 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3023 const struct anv_image
*image
,
3024 const VkImageAspectFlagBits aspect
,
3025 const VkImageLayout layout
);
3027 enum anv_fast_clear_type
3028 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3029 const struct anv_image
* const image
,
3030 const VkImageAspectFlagBits aspect
,
3031 const VkImageLayout layout
);
3033 /* This is defined as a macro so that it works for both
3034 * VkImageSubresourceRange and VkImageSubresourceLayers
3036 #define anv_get_layerCount(_image, _range) \
3037 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3038 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3040 static inline uint32_t
3041 anv_get_levelCount(const struct anv_image
*image
,
3042 const VkImageSubresourceRange
*range
)
3044 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3045 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3048 static inline VkImageAspectFlags
3049 anv_image_expand_aspects(const struct anv_image
*image
,
3050 VkImageAspectFlags aspects
)
3052 /* If the underlying image has color plane aspects and
3053 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3054 * the underlying image. */
3055 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3056 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3057 return image
->aspects
;
3063 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3064 VkImageAspectFlags aspects2
)
3066 if (aspects1
== aspects2
)
3069 /* Only 1 color aspects are compatibles. */
3070 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3071 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3072 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3078 struct anv_image_view
{
3079 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3081 VkImageAspectFlags aspect_mask
;
3083 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3087 uint32_t image_plane
;
3089 struct isl_view isl
;
3092 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3093 * image layout of SHADER_READ_ONLY_OPTIMAL or
3094 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3096 struct anv_surface_state optimal_sampler_surface_state
;
3099 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3100 * image layout of GENERAL.
3102 struct anv_surface_state general_sampler_surface_state
;
3105 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3106 * states for write-only and readable, using the real format for
3107 * write-only and the lowered format for readable.
3109 struct anv_surface_state storage_surface_state
;
3110 struct anv_surface_state writeonly_storage_surface_state
;
3112 struct brw_image_param storage_image_param
;
3116 enum anv_image_view_state_flags
{
3117 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3118 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3121 void anv_image_fill_surface_state(struct anv_device
*device
,
3122 const struct anv_image
*image
,
3123 VkImageAspectFlagBits aspect
,
3124 const struct isl_view
*view
,
3125 isl_surf_usage_flags_t view_usage
,
3126 enum isl_aux_usage aux_usage
,
3127 const union isl_color_value
*clear_color
,
3128 enum anv_image_view_state_flags flags
,
3129 struct anv_surface_state
*state_inout
,
3130 struct brw_image_param
*image_param_out
);
3132 struct anv_image_create_info
{
3133 const VkImageCreateInfo
*vk_info
;
3135 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3136 isl_tiling_flags_t isl_tiling_flags
;
3138 /** These flags will be added to any derived from VkImageCreateInfo. */
3139 isl_surf_usage_flags_t isl_extra_usage_flags
;
3142 bool external_format
;
3145 VkResult
anv_image_create(VkDevice _device
,
3146 const struct anv_image_create_info
*info
,
3147 const VkAllocationCallbacks
* alloc
,
3150 const struct anv_surface
*
3151 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3152 VkImageAspectFlags aspect_mask
);
3155 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3157 static inline struct VkExtent3D
3158 anv_sanitize_image_extent(const VkImageType imageType
,
3159 const struct VkExtent3D imageExtent
)
3161 switch (imageType
) {
3162 case VK_IMAGE_TYPE_1D
:
3163 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3164 case VK_IMAGE_TYPE_2D
:
3165 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3166 case VK_IMAGE_TYPE_3D
:
3169 unreachable("invalid image type");
3173 static inline struct VkOffset3D
3174 anv_sanitize_image_offset(const VkImageType imageType
,
3175 const struct VkOffset3D imageOffset
)
3177 switch (imageType
) {
3178 case VK_IMAGE_TYPE_1D
:
3179 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3180 case VK_IMAGE_TYPE_2D
:
3181 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3182 case VK_IMAGE_TYPE_3D
:
3185 unreachable("invalid image type");
3189 VkFormatFeatureFlags
3190 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3192 const struct anv_format
*anv_format
,
3193 VkImageTiling vk_tiling
);
3195 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3196 struct anv_state state
,
3197 enum isl_format format
,
3198 struct anv_address address
,
3199 uint32_t range
, uint32_t stride
);
3202 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3203 const struct anv_attachment_state
*att_state
,
3204 const struct anv_image_view
*iview
)
3206 const struct isl_format_layout
*view_fmtl
=
3207 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3209 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3210 if (view_fmtl->channels.c.bits) \
3211 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3213 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3214 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3215 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3216 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3218 #undef COPY_CLEAR_COLOR_CHANNEL
3222 struct anv_ycbcr_conversion
{
3223 const struct anv_format
* format
;
3224 VkSamplerYcbcrModelConversion ycbcr_model
;
3225 VkSamplerYcbcrRange ycbcr_range
;
3226 VkComponentSwizzle mapping
[4];
3227 VkChromaLocation chroma_offsets
[2];
3228 VkFilter chroma_filter
;
3229 bool chroma_reconstruction
;
3232 struct anv_sampler
{
3233 uint32_t state
[3][4];
3235 struct anv_ycbcr_conversion
*conversion
;
3238 struct anv_framebuffer
{
3243 uint32_t attachment_count
;
3244 struct anv_image_view
* attachments
[0];
3247 struct anv_subpass_attachment
{
3248 VkImageUsageFlagBits usage
;
3249 uint32_t attachment
;
3250 VkImageLayout layout
;
3253 struct anv_subpass
{
3254 uint32_t attachment_count
;
3257 * A pointer to all attachment references used in this subpass.
3258 * Only valid if ::attachment_count > 0.
3260 struct anv_subpass_attachment
* attachments
;
3261 uint32_t input_count
;
3262 struct anv_subpass_attachment
* input_attachments
;
3263 uint32_t color_count
;
3264 struct anv_subpass_attachment
* color_attachments
;
3265 struct anv_subpass_attachment
* resolve_attachments
;
3267 struct anv_subpass_attachment
* depth_stencil_attachment
;
3268 struct anv_subpass_attachment
* ds_resolve_attachment
;
3269 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3270 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3274 /** Subpass has a depth/stencil self-dependency */
3275 bool has_ds_self_dep
;
3277 /** Subpass has at least one color resolve attachment */
3278 bool has_color_resolve
;
3281 static inline unsigned
3282 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3284 return MAX2(1, util_bitcount(subpass
->view_mask
));
3287 struct anv_render_pass_attachment
{
3288 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3289 * its members individually.
3293 VkImageUsageFlags usage
;
3294 VkAttachmentLoadOp load_op
;
3295 VkAttachmentStoreOp store_op
;
3296 VkAttachmentLoadOp stencil_load_op
;
3297 VkImageLayout initial_layout
;
3298 VkImageLayout final_layout
;
3299 VkImageLayout first_subpass_layout
;
3301 /* The subpass id in which the attachment will be used last. */
3302 uint32_t last_subpass_idx
;
3305 struct anv_render_pass
{
3306 uint32_t attachment_count
;
3307 uint32_t subpass_count
;
3308 /* An array of subpass_count+1 flushes, one per subpass boundary */
3309 enum anv_pipe_bits
* subpass_flushes
;
3310 struct anv_render_pass_attachment
* attachments
;
3311 struct anv_subpass subpasses
[0];
3314 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3316 struct anv_query_pool
{
3318 VkQueryPipelineStatisticFlags pipeline_statistics
;
3319 /** Stride between slots, in bytes */
3321 /** Number of slots in this query pool */
3326 int anv_get_instance_entrypoint_index(const char *name
);
3327 int anv_get_device_entrypoint_index(const char *name
);
3330 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3331 const struct anv_instance_extension_table
*instance
);
3334 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3335 const struct anv_instance_extension_table
*instance
,
3336 const struct anv_device_extension_table
*device
);
3338 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3341 void anv_dump_image_to_ppm(struct anv_device
*device
,
3342 struct anv_image
*image
, unsigned miplevel
,
3343 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3344 const char *filename
);
3346 enum anv_dump_action
{
3347 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3350 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3351 void anv_dump_finish(void);
3353 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
3354 struct anv_framebuffer
*fb
);
3356 static inline uint32_t
3357 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3359 /* This function must be called from within a subpass. */
3360 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3362 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3364 /* The id of this subpass shouldn't exceed the number of subpasses in this
3365 * render pass minus 1.
3367 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3371 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3373 static inline struct __anv_type * \
3374 __anv_type ## _from_handle(__VkType _handle) \
3376 return (struct __anv_type *) _handle; \
3379 static inline __VkType \
3380 __anv_type ## _to_handle(struct __anv_type *_obj) \
3382 return (__VkType) _obj; \
3385 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3387 static inline struct __anv_type * \
3388 __anv_type ## _from_handle(__VkType _handle) \
3390 return (struct __anv_type *)(uintptr_t) _handle; \
3393 static inline __VkType \
3394 __anv_type ## _to_handle(struct __anv_type *_obj) \
3396 return (__VkType)(uintptr_t) _obj; \
3399 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3400 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3402 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3403 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3404 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3405 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3406 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3408 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3409 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3410 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3411 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3412 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3413 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3414 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3415 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3416 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3417 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3418 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3419 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3420 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3421 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3422 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3423 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3424 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3425 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3426 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3427 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3428 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3429 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3430 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3432 /* Gen-specific function declarations */
3434 # include "anv_genX.h"
3436 # define genX(x) gen7_##x
3437 # include "anv_genX.h"
3439 # define genX(x) gen75_##x
3440 # include "anv_genX.h"
3442 # define genX(x) gen8_##x
3443 # include "anv_genX.h"
3445 # define genX(x) gen9_##x
3446 # include "anv_genX.h"
3448 # define genX(x) gen10_##x
3449 # include "anv_genX.h"
3451 # define genX(x) gen11_##x
3452 # include "anv_genX.h"
3456 #endif /* ANV_PRIVATE_H */