2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
62 #include "util/xmlconfig.h"
64 #include "vk_debug_report.h"
65 #include "vk_object.h"
67 /* Pre-declarations needed for WSI entrypoints */
70 typedef struct xcb_connection_t xcb_connection_t
;
71 typedef uint32_t xcb_visualid_t
;
72 typedef uint32_t xcb_window_t
;
76 struct anv_buffer_view
;
77 struct anv_image_view
;
80 struct gen_aux_map_context
;
81 struct gen_perf_config
;
82 struct gen_perf_counter_pass
;
83 struct gen_perf_query_result
;
85 #include <vulkan/vulkan.h>
86 #include <vulkan/vulkan_intel.h>
87 #include <vulkan/vk_icd.h>
89 #include "anv_android.h"
90 #include "anv_entrypoints.h"
91 #include "anv_extensions.h"
94 #include "dev/gen_debug.h"
95 #include "common/intel_log.h"
96 #include "wsi_common.h"
98 #define NSEC_PER_SEC 1000000000ull
100 /* anv Virtual Memory Layout
101 * =========================
103 * When the anv driver is determining the virtual graphics addresses of memory
104 * objects itself using the softpin mechanism, the following memory ranges
107 * Three special considerations to notice:
109 * (1) the dynamic state pool is located within the same 4 GiB as the low
110 * heap. This is to work around a VF cache issue described in a comment in
111 * anv_physical_device_init_heaps.
113 * (2) the binding table pool is located at lower addresses than the surface
114 * state pool, within a 4 GiB range. This allows surface state base addresses
115 * to cover both binding tables (16 bit offsets) and surface states (32 bit
118 * (3) the last 4 GiB of the address space is withheld from the high
119 * heap. Various hardware units will read past the end of an object for
120 * various reasons. This healthy margin prevents reads from wrapping around
123 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
124 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
125 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
126 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
127 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
128 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
129 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
130 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
131 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
132 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
133 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
134 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
135 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
137 #define LOW_HEAP_SIZE \
138 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
139 #define DYNAMIC_STATE_POOL_SIZE \
140 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
141 #define BINDING_TABLE_POOL_SIZE \
142 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
143 #define SURFACE_STATE_POOL_SIZE \
144 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
145 #define INSTRUCTION_STATE_POOL_SIZE \
146 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
147 #define CLIENT_VISIBLE_HEAP_SIZE \
148 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
150 /* Allowing different clear colors requires us to perform a depth resolve at
151 * the end of certain render passes. This is because while slow clears store
152 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
153 * See the PRMs for examples describing when additional resolves would be
154 * necessary. To enable fast clears without requiring extra resolves, we set
155 * the clear value to a globally-defined one. We could allow different values
156 * if the user doesn't expect coherent data during or after a render passes
157 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
158 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
159 * 1.0f seems to be the only value used. The only application that doesn't set
160 * this value does so through the usage of an seemingly uninitialized clear
163 #define ANV_HZ_FC_VAL 1.0f
166 #define MAX_XFB_BUFFERS 4
167 #define MAX_XFB_STREAMS 4
170 #define MAX_VIEWPORTS 16
171 #define MAX_SCISSORS 16
172 #define MAX_PUSH_CONSTANTS_SIZE 128
173 #define MAX_DYNAMIC_BUFFERS 16
174 #define MAX_IMAGES 64
175 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
176 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
177 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
178 /* We need 16 for UBO block reads to work and 32 for push UBOs. However, we
179 * use 64 here to avoid cache issues. This could most likely bring it back to
180 * 32 if we had different virtual addresses for the different views on a given
183 #define ANV_UBO_ALIGNMENT 64
184 #define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
185 #define MAX_VIEWS_FOR_PRIMITIVE_REPLICATION 16
187 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
189 * "The surface state model is used when a Binding Table Index (specified
190 * in the message descriptor) of less than 240 is specified. In this model,
191 * the Binding Table Index is used to index into the binding table, and the
192 * binding table entry contains a pointer to the SURFACE_STATE."
194 * Binding table values above 240 are used for various things in the hardware
195 * such as stateless, stateless with incoherent cache, SLM, and bindless.
197 #define MAX_BINDING_TABLE_SIZE 240
199 /* The kernel relocation API has a limitation of a 32-bit delta value
200 * applied to the address before it is written which, in spite of it being
201 * unsigned, is treated as signed . Because of the way that this maps to
202 * the Vulkan API, we cannot handle an offset into a buffer that does not
203 * fit into a signed 32 bits. The only mechanism we have for dealing with
204 * this at the moment is to limit all VkDeviceMemory objects to a maximum
205 * of 2GB each. The Vulkan spec allows us to do this:
207 * "Some platforms may have a limit on the maximum size of a single
208 * allocation. For example, certain systems may fail to create
209 * allocations with a size greater than or equal to 4GB. Such a limit is
210 * implementation-dependent, and if such a failure occurs then the error
211 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
213 * We don't use vk_error here because it's not an error so much as an
214 * indication to the application that the allocation is too large.
216 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
218 #define ANV_SVGS_VB_INDEX MAX_VBS
219 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
221 /* We reserve this MI ALU register for the purpose of handling predication.
222 * Other code which uses the MI ALU should leave it alone.
224 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
226 /* We reserve this MI ALU register to pass around an offset computed from
227 * VkPerformanceQuerySubmitInfoKHR::counterPassIndex VK_KHR_performance_query.
228 * Other code which uses the MI ALU should leave it alone.
230 #define ANV_PERF_QUERY_OFFSET_REG 0x2670 /* MI_ALU_REG14 */
232 /* For gen12 we set the streamout buffers using 4 separate commands
233 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
234 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
235 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
236 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
237 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
238 * 3DSTATE_SO_BUFFER_INDEX_0.
240 #define SO_BUFFER_INDEX_0_CMD 0x60
241 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
243 static inline uint32_t
244 align_down_npot_u32(uint32_t v
, uint32_t a
)
249 static inline uint32_t
250 align_down_u32(uint32_t v
, uint32_t a
)
252 assert(a
!= 0 && a
== (a
& -a
));
256 static inline uint32_t
257 align_u32(uint32_t v
, uint32_t a
)
259 assert(a
!= 0 && a
== (a
& -a
));
260 return align_down_u32(v
+ a
- 1, a
);
263 static inline uint64_t
264 align_down_u64(uint64_t v
, uint64_t a
)
266 assert(a
!= 0 && a
== (a
& -a
));
270 static inline uint64_t
271 align_u64(uint64_t v
, uint64_t a
)
273 return align_down_u64(v
+ a
- 1, a
);
276 static inline int32_t
277 align_i32(int32_t v
, int32_t a
)
279 assert(a
!= 0 && a
== (a
& -a
));
280 return (v
+ a
- 1) & ~(a
- 1);
283 /** Alignment must be a power of 2. */
285 anv_is_aligned(uintmax_t n
, uintmax_t a
)
287 assert(a
== (a
& -a
));
288 return (n
& (a
- 1)) == 0;
291 static inline uint32_t
292 anv_minify(uint32_t n
, uint32_t levels
)
294 if (unlikely(n
== 0))
297 return MAX2(n
>> levels
, 1);
301 anv_clamp_f(float f
, float min
, float max
)
314 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
316 if (*inout_mask
& clear_mask
) {
317 *inout_mask
&= ~clear_mask
;
324 static inline union isl_color_value
325 vk_to_isl_color(VkClearColorValue color
)
327 return (union isl_color_value
) {
337 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
339 uintptr_t mask
= (1ull << bits
) - 1;
341 return (void *) (ptr
& ~mask
);
344 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
346 uintptr_t value
= (uintptr_t) ptr
;
347 uintptr_t mask
= (1ull << bits
) - 1;
348 return value
| (mask
& flags
);
351 #define for_each_bit(b, dword) \
352 for (uint32_t __dword = (dword); \
353 (b) = __builtin_ffs(__dword) - 1, __dword; \
354 __dword &= ~(1 << (b)))
356 #define typed_memcpy(dest, src, count) ({ \
357 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
358 memcpy((dest), (src), (count) * sizeof(*(src))); \
361 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
362 * to be added here in order to utilize mapping in debug/error/perf macros.
364 #define REPORT_OBJECT_TYPE(o) \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
407 __builtin_choose_expr ( \
408 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
409 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
410 __builtin_choose_expr ( \
411 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
412 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
413 __builtin_choose_expr ( \
414 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
415 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
416 __builtin_choose_expr ( \
417 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
418 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
419 __builtin_choose_expr ( \
420 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
421 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
422 __builtin_choose_expr ( \
423 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
424 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
425 __builtin_choose_expr ( \
426 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
427 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
428 __builtin_choose_expr ( \
429 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
430 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
431 __builtin_choose_expr ( \
432 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
433 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
434 __builtin_choose_expr ( \
435 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
436 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
437 __builtin_choose_expr ( \
438 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
439 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
440 __builtin_choose_expr ( \
441 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
442 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
443 __builtin_choose_expr ( \
444 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
445 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
446 __builtin_choose_expr ( \
447 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
448 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
449 __builtin_choose_expr ( \
450 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
451 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
452 __builtin_choose_expr ( \
453 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
454 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
455 __builtin_choose_expr ( \
456 __builtin_types_compatible_p (__typeof (o), void*), \
457 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
458 /* The void expression results in a compile-time error \
459 when assigning the result to something. */ \
460 (void)0)))))))))))))))))))))))))))))))
462 /* Whenever we generate an error, pass it through this function. Useful for
463 * debugging, where we can break on it. Only call at error site, not when
464 * propagating errors. Might be useful to plug in a stack trace here.
467 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
468 VkDebugReportObjectTypeEXT type
, VkResult error
,
469 const char *file
, int line
, const char *format
,
472 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
473 VkDebugReportObjectTypeEXT type
, VkResult error
,
474 const char *file
, int line
, const char *format
, ...)
475 anv_printflike(7, 8);
478 #define vk_error(error) __vk_errorf(NULL, NULL,\
479 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
480 error, __FILE__, __LINE__, NULL)
481 #define vk_errorfi(instance, obj, error, format, ...)\
482 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
483 __FILE__, __LINE__, format, ## __VA_ARGS__)
484 #define vk_errorf(device, obj, error, format, ...)\
485 vk_errorfi(anv_device_instance_or_null(device),\
486 obj, error, format, ## __VA_ARGS__)
488 #define vk_error(error) error
489 #define vk_errorfi(instance, obj, error, format, ...) error
490 #define vk_errorf(device, obj, error, format, ...) error
494 * Warn on ignored extension structs.
496 * The Vulkan spec requires us to ignore unsupported or unknown structs in
497 * a pNext chain. In debug mode, emitting warnings for ignored structs may
498 * help us discover structs that we should not have ignored.
501 * From the Vulkan 1.0.38 spec:
503 * Any component of the implementation (the loader, any enabled layers,
504 * and drivers) must skip over, without processing (other than reading the
505 * sType and pNext members) any chained structures with sType values not
506 * defined by extensions supported by that component.
508 #define anv_debug_ignored_stype(sType) \
509 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
511 void __anv_perf_warn(struct anv_device
*device
, const void *object
,
512 VkDebugReportObjectTypeEXT type
, const char *file
,
513 int line
, const char *format
, ...)
514 anv_printflike(6, 7);
515 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
516 void anv_loge_v(const char *format
, va_list va
);
519 * Print a FINISHME message, including its source location.
521 #define anv_finishme(format, ...) \
523 static bool reported = false; \
525 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
532 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
534 #define anv_perf_warn(instance, obj, format, ...) \
536 static bool reported = false; \
537 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
538 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
539 format, ##__VA_ARGS__); \
544 /* A non-fatal assert. Useful for debugging. */
546 #define anv_assert(x) ({ \
547 if (unlikely(!(x))) \
548 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
551 #define anv_assert(x)
554 /* A multi-pointer allocator
556 * When copying data structures from the user (such as a render pass), it's
557 * common to need to allocate data for a bunch of different things. Instead
558 * of doing several allocations and having to handle all of the error checking
559 * that entails, it can be easier to do a single allocation. This struct
560 * helps facilitate that. The intended usage looks like this:
563 * anv_multialloc_add(&ma, &main_ptr, 1);
564 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
565 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
567 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
568 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
570 struct anv_multialloc
{
578 #define ANV_MULTIALLOC_INIT \
579 ((struct anv_multialloc) { 0, })
581 #define ANV_MULTIALLOC(_name) \
582 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
584 __attribute__((always_inline
))
586 _anv_multialloc_add(struct anv_multialloc
*ma
,
587 void **ptr
, size_t size
, size_t align
)
589 size_t offset
= align_u64(ma
->size
, align
);
590 ma
->size
= offset
+ size
;
591 ma
->align
= MAX2(ma
->align
, align
);
593 /* Store the offset in the pointer. */
594 *ptr
= (void *)(uintptr_t)offset
;
596 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
597 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
600 #define anv_multialloc_add_size(_ma, _ptr, _size) \
601 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
603 #define anv_multialloc_add(_ma, _ptr, _count) \
604 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
606 __attribute__((always_inline
))
608 anv_multialloc_alloc(struct anv_multialloc
*ma
,
609 const VkAllocationCallbacks
*alloc
,
610 VkSystemAllocationScope scope
)
612 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
616 /* Fill out each of the pointers with their final value.
618 * for (uint32_t i = 0; i < ma->ptr_count; i++)
619 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
621 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
622 * constant, GCC is incapable of figuring this out and unrolling the loop
623 * so we have to give it a little help.
625 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
626 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
627 if ((_i) < ma->ptr_count) \
628 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
629 _ANV_MULTIALLOC_UPDATE_POINTER(0);
630 _ANV_MULTIALLOC_UPDATE_POINTER(1);
631 _ANV_MULTIALLOC_UPDATE_POINTER(2);
632 _ANV_MULTIALLOC_UPDATE_POINTER(3);
633 _ANV_MULTIALLOC_UPDATE_POINTER(4);
634 _ANV_MULTIALLOC_UPDATE_POINTER(5);
635 _ANV_MULTIALLOC_UPDATE_POINTER(6);
636 _ANV_MULTIALLOC_UPDATE_POINTER(7);
637 #undef _ANV_MULTIALLOC_UPDATE_POINTER
642 __attribute__((always_inline
))
644 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
645 const VkAllocationCallbacks
*parent_alloc
,
646 const VkAllocationCallbacks
*alloc
,
647 VkSystemAllocationScope scope
)
649 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
657 /* Index into the current validation list. This is used by the
658 * validation list building alrogithm to track which buffers are already
659 * in the validation list so that we can ensure uniqueness.
663 /* Index for use with util_sparse_array_free_list */
666 /* Last known offset. This value is provided by the kernel when we
667 * execbuf and is used as the presumed offset for the next bunch of
672 /** Size of the buffer not including implicit aux */
675 /* Map for internally mapped BOs.
677 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
681 /** Size of the implicit CCS range at the end of the buffer
683 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
684 * page of main surface data maps to a 256B chunk of CCS data and that
685 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
686 * addresses in the main surface to virtual memory addresses for CCS data.
688 * Because we can't change these maps around easily and because Vulkan
689 * allows two VkImages to be bound to overlapping memory regions (as long
690 * as the app is careful), it's not feasible to make this mapping part of
691 * the image. (On Gen11 and earlier, the mapping was provided via
692 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
693 * Instead, we attach the CCS data directly to the buffer object and setup
694 * the AUX table mapping at BO creation time.
696 * This field is for internal tracking use by the BO allocator only and
697 * should not be touched by other parts of the code. If something wants to
698 * know if a BO has implicit CCS data, it should instead look at the
699 * has_implicit_ccs boolean below.
701 * This data is not included in maps of this buffer.
705 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
708 /** True if this BO may be shared with other processes */
711 /** True if this BO is a wrapper
713 * When set to true, none of the fields in this BO are meaningful except
714 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
715 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
716 * is set in the physical device.
720 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
721 bool has_fixed_address
:1;
723 /** True if this BO wraps a host pointer */
724 bool from_host_ptr
:1;
726 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
727 bool has_client_visible_address
:1;
729 /** True if this BO has implicit CCS data attached to it */
730 bool has_implicit_ccs
:1;
733 static inline struct anv_bo
*
734 anv_bo_ref(struct anv_bo
*bo
)
736 p_atomic_inc(&bo
->refcount
);
740 static inline struct anv_bo
*
741 anv_bo_unwrap(struct anv_bo
*bo
)
743 while (bo
->is_wrapper
)
748 /* Represents a lock-free linked list of "free" things. This is used by
749 * both the block pool and the state pools. Unfortunately, in order to
750 * solve the ABA problem, we can't use a single uint32_t head.
752 union anv_free_list
{
756 /* A simple count that is incremented every time the head changes. */
759 /* Make sure it's aligned to 64 bits. This will make atomic operations
760 * faster on 32 bit platforms.
762 uint64_t u64
__attribute__ ((aligned (8)));
765 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
767 struct anv_block_state
{
773 /* Make sure it's aligned to 64 bits. This will make atomic operations
774 * faster on 32 bit platforms.
776 uint64_t u64
__attribute__ ((aligned (8)));
780 #define anv_block_pool_foreach_bo(bo, pool) \
781 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
782 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
785 #define ANV_MAX_BLOCK_POOL_BOS 20
787 struct anv_block_pool
{
788 struct anv_device
*device
;
791 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
792 * around the actual BO so that we grow the pool after the wrapper BO has
793 * been put in a relocation list. This is only used in the non-softpin
796 struct anv_bo wrapper_bo
;
798 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
804 /* The address where the start of the pool is pinned. The various bos that
805 * are created as the pool grows will have addresses in the range
806 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
808 uint64_t start_address
;
810 /* The offset from the start of the bo to the "center" of the block
811 * pool. Pointers to allocated blocks are given by
812 * bo.map + center_bo_offset + offsets.
814 uint32_t center_bo_offset
;
816 /* Current memory map of the block pool. This pointer may or may not
817 * point to the actual beginning of the block pool memory. If
818 * anv_block_pool_alloc_back has ever been called, then this pointer
819 * will point to the "center" position of the buffer and all offsets
820 * (negative or positive) given out by the block pool alloc functions
821 * will be valid relative to this pointer.
823 * In particular, map == bo.map + center_offset
825 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
826 * since it will handle the softpin case as well, where this points to NULL.
832 * Array of mmaps and gem handles owned by the block pool, reclaimed when
833 * the block pool is destroyed.
835 struct u_vector mmap_cleanups
;
837 struct anv_block_state state
;
839 struct anv_block_state back_state
;
842 /* Block pools are backed by a fixed-size 1GB memfd */
843 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
845 /* The center of the block pool is also the middle of the memfd. This may
846 * change in the future if we decide differently for some reason.
848 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
850 static inline uint32_t
851 anv_block_pool_size(struct anv_block_pool
*pool
)
853 return pool
->state
.end
+ pool
->back_state
.end
;
863 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
865 struct anv_fixed_size_state_pool
{
866 union anv_free_list free_list
;
867 struct anv_block_state block
;
870 #define ANV_MIN_STATE_SIZE_LOG2 6
871 #define ANV_MAX_STATE_SIZE_LOG2 21
873 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
875 struct anv_free_entry
{
877 struct anv_state state
;
880 struct anv_state_table
{
881 struct anv_device
*device
;
883 struct anv_free_entry
*map
;
885 struct anv_block_state state
;
886 struct u_vector cleanups
;
889 struct anv_state_pool
{
890 struct anv_block_pool block_pool
;
892 /* Offset into the relevant state base address where the state pool starts
895 int32_t start_offset
;
897 struct anv_state_table table
;
899 /* The size of blocks which will be allocated from the block pool */
902 /** Free list for "back" allocations */
903 union anv_free_list back_alloc_free_list
;
905 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
908 struct anv_state_reserved_pool
{
909 struct anv_state_pool
*pool
;
910 union anv_free_list reserved_blocks
;
914 struct anv_state_stream
{
915 struct anv_state_pool
*state_pool
;
917 /* The size of blocks to allocate from the state pool */
920 /* Current block we're allocating from */
921 struct anv_state block
;
923 /* Offset into the current block at which to allocate the next state */
926 /* List of all blocks allocated from this pool */
927 struct util_dynarray all_blocks
;
930 /* The block_pool functions exported for testing only. The block pool should
931 * only be used via a state pool (see below).
933 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
934 struct anv_device
*device
,
935 uint64_t start_address
,
936 uint32_t initial_size
);
937 void anv_block_pool_finish(struct anv_block_pool
*pool
);
938 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
939 uint32_t block_size
, uint32_t *padding
);
940 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
941 uint32_t block_size
);
942 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
, uint32_t
945 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
946 struct anv_device
*device
,
947 uint64_t base_address
,
948 int32_t start_offset
,
949 uint32_t block_size
);
950 void anv_state_pool_finish(struct anv_state_pool
*pool
);
951 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
952 uint32_t state_size
, uint32_t alignment
);
953 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
954 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
955 void anv_state_stream_init(struct anv_state_stream
*stream
,
956 struct anv_state_pool
*state_pool
,
957 uint32_t block_size
);
958 void anv_state_stream_finish(struct anv_state_stream
*stream
);
959 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
960 uint32_t size
, uint32_t alignment
);
962 void anv_state_reserved_pool_init(struct anv_state_reserved_pool
*pool
,
963 struct anv_state_pool
*parent
,
964 uint32_t count
, uint32_t size
,
966 void anv_state_reserved_pool_finish(struct anv_state_reserved_pool
*pool
);
967 struct anv_state
anv_state_reserved_pool_alloc(struct anv_state_reserved_pool
*pool
);
968 void anv_state_reserved_pool_free(struct anv_state_reserved_pool
*pool
,
969 struct anv_state state
);
971 VkResult
anv_state_table_init(struct anv_state_table
*table
,
972 struct anv_device
*device
,
973 uint32_t initial_entries
);
974 void anv_state_table_finish(struct anv_state_table
*table
);
975 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
977 void anv_free_list_push(union anv_free_list
*list
,
978 struct anv_state_table
*table
,
979 uint32_t idx
, uint32_t count
);
980 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
981 struct anv_state_table
*table
);
984 static inline struct anv_state
*
985 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
987 return &table
->map
[idx
].state
;
990 * Implements a pool of re-usable BOs. The interface is identical to that
991 * of block_pool except that each block is its own BO.
994 struct anv_device
*device
;
996 struct util_sparse_array_free_list free_list
[16];
999 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
1000 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
1001 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
1002 struct anv_bo
**bo_out
);
1003 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
1005 struct anv_scratch_pool
{
1006 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
1007 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
1010 void anv_scratch_pool_init(struct anv_device
*device
,
1011 struct anv_scratch_pool
*pool
);
1012 void anv_scratch_pool_finish(struct anv_device
*device
,
1013 struct anv_scratch_pool
*pool
);
1014 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
1015 struct anv_scratch_pool
*pool
,
1016 gl_shader_stage stage
,
1017 unsigned per_thread_scratch
);
1019 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
1020 struct anv_bo_cache
{
1021 struct util_sparse_array bo_map
;
1022 pthread_mutex_t mutex
;
1025 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
1026 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
1028 struct anv_memory_type
{
1029 /* Standard bits passed on to the client */
1030 VkMemoryPropertyFlags propertyFlags
;
1034 struct anv_memory_heap
{
1035 /* Standard bits passed on to the client */
1037 VkMemoryHeapFlags flags
;
1039 /* Driver-internal book-keeping */
1043 struct anv_physical_device
{
1044 struct vk_object_base base
;
1046 /* Link in anv_instance::physical_devices */
1047 struct list_head link
;
1049 struct anv_instance
* instance
;
1059 struct gen_device_info info
;
1060 /** Amount of "GPU memory" we want to advertise
1062 * Clearly, this value is bogus since Intel is a UMA architecture. On
1063 * gen7 platforms, we are limited by GTT size unless we want to implement
1064 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1065 * practically unlimited. However, we will never report more than 3/4 of
1066 * the total system ram to try and avoid running out of RAM.
1068 bool supports_48bit_addresses
;
1069 struct brw_compiler
* compiler
;
1070 struct isl_device isl_dev
;
1071 struct gen_perf_config
* perf
;
1072 int cmd_parser_version
;
1074 bool has_exec_async
;
1075 bool has_exec_capture
;
1076 bool has_exec_fence
;
1078 bool has_syncobj_wait
;
1079 bool has_context_priority
;
1080 bool has_context_isolation
;
1081 bool has_mem_available
;
1082 bool has_mmap_offset
;
1086 bool always_use_bindless
;
1088 /** True if we can access buffers using A64 messages */
1089 bool has_a64_buffer_access
;
1090 /** True if we can use bindless access for images */
1091 bool has_bindless_images
;
1092 /** True if we can use bindless access for samplers */
1093 bool has_bindless_samplers
;
1095 /** True if we can read the GPU timestamp register
1097 * When running in a virtual context, the timestamp register is unreadable
1100 bool has_reg_timestamp
;
1102 /** True if this device has implicit AUX
1104 * If true, CCS is handled as an implicit attachment to the BO rather than
1105 * as an explicitly bound surface.
1107 bool has_implicit_ccs
;
1109 bool always_flush_cache
;
1111 struct anv_device_extension_table supported_extensions
;
1114 uint32_t subslice_total
;
1117 uint32_t type_count
;
1118 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1119 uint32_t heap_count
;
1120 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1123 uint8_t driver_build_sha1
[20];
1124 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1125 uint8_t driver_uuid
[VK_UUID_SIZE
];
1126 uint8_t device_uuid
[VK_UUID_SIZE
];
1128 struct disk_cache
* disk_cache
;
1130 struct wsi_device wsi_device
;
1135 struct anv_app_info
{
1136 const char* app_name
;
1137 uint32_t app_version
;
1138 const char* engine_name
;
1139 uint32_t engine_version
;
1140 uint32_t api_version
;
1143 struct anv_instance
{
1144 struct vk_object_base base
;
1146 VkAllocationCallbacks alloc
;
1148 struct anv_app_info app_info
;
1150 struct anv_instance_extension_table enabled_extensions
;
1151 struct anv_instance_dispatch_table dispatch
;
1152 struct anv_physical_device_dispatch_table physical_device_dispatch
;
1153 struct anv_device_dispatch_table device_dispatch
;
1155 bool physical_devices_enumerated
;
1156 struct list_head physical_devices
;
1158 bool pipeline_cache_enabled
;
1160 struct vk_debug_report_instance debug_report_callbacks
;
1162 struct driOptionCache dri_options
;
1163 struct driOptionCache available_dri_options
;
1166 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1167 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1169 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1170 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1173 struct anv_queue_submit
{
1174 struct anv_cmd_buffer
* cmd_buffer
;
1176 uint32_t fence_count
;
1177 uint32_t fence_array_length
;
1178 struct drm_i915_gem_exec_fence
* fences
;
1180 uint32_t temporary_semaphore_count
;
1181 uint32_t temporary_semaphore_array_length
;
1182 struct anv_semaphore_impl
* temporary_semaphores
;
1184 /* Semaphores to be signaled with a SYNC_FD. */
1185 struct anv_semaphore
** sync_fd_semaphores
;
1186 uint32_t sync_fd_semaphore_count
;
1187 uint32_t sync_fd_semaphore_array_length
;
1189 /* Allocated only with non shareable timelines. */
1190 struct anv_timeline
** wait_timelines
;
1191 uint32_t wait_timeline_count
;
1192 uint32_t wait_timeline_array_length
;
1193 uint64_t * wait_timeline_values
;
1195 struct anv_timeline
** signal_timelines
;
1196 uint32_t signal_timeline_count
;
1197 uint32_t signal_timeline_array_length
;
1198 uint64_t * signal_timeline_values
;
1201 bool need_out_fence
;
1204 uint32_t fence_bo_count
;
1205 uint32_t fence_bo_array_length
;
1206 /* An array of struct anv_bo pointers with lower bit used as a flag to
1207 * signal we will wait on that BO (see anv_(un)pack_ptr).
1209 uintptr_t * fence_bos
;
1211 int perf_query_pass
;
1213 const VkAllocationCallbacks
* alloc
;
1214 VkSystemAllocationScope alloc_scope
;
1216 struct anv_bo
* simple_bo
;
1217 uint32_t simple_bo_size
;
1219 struct list_head link
;
1223 struct vk_object_base base
;
1225 struct anv_device
* device
;
1228 * A list of struct anv_queue_submit to be submitted to i915.
1230 struct list_head queued_submits
;
1232 VkDeviceQueueCreateFlags flags
;
1235 struct anv_pipeline_cache
{
1236 struct vk_object_base base
;
1237 struct anv_device
* device
;
1238 pthread_mutex_t mutex
;
1240 struct hash_table
* nir_cache
;
1242 struct hash_table
* cache
;
1245 struct nir_xfb_info
;
1246 struct anv_pipeline_bind_map
;
1248 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1249 struct anv_device
*device
,
1250 bool cache_enabled
);
1251 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1253 struct anv_shader_bin
*
1254 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1255 const void *key
, uint32_t key_size
);
1256 struct anv_shader_bin
*
1257 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1258 gl_shader_stage stage
,
1259 const void *key_data
, uint32_t key_size
,
1260 const void *kernel_data
, uint32_t kernel_size
,
1261 const void *constant_data
,
1262 uint32_t constant_data_size
,
1263 const struct brw_stage_prog_data
*prog_data
,
1264 uint32_t prog_data_size
,
1265 const struct brw_compile_stats
*stats
,
1267 const struct nir_xfb_info
*xfb_info
,
1268 const struct anv_pipeline_bind_map
*bind_map
);
1270 struct anv_shader_bin
*
1271 anv_device_search_for_kernel(struct anv_device
*device
,
1272 struct anv_pipeline_cache
*cache
,
1273 const void *key_data
, uint32_t key_size
,
1274 bool *user_cache_bit
);
1276 struct anv_shader_bin
*
1277 anv_device_upload_kernel(struct anv_device
*device
,
1278 struct anv_pipeline_cache
*cache
,
1279 gl_shader_stage stage
,
1280 const void *key_data
, uint32_t key_size
,
1281 const void *kernel_data
, uint32_t kernel_size
,
1282 const void *constant_data
,
1283 uint32_t constant_data_size
,
1284 const struct brw_stage_prog_data
*prog_data
,
1285 uint32_t prog_data_size
,
1286 const struct brw_compile_stats
*stats
,
1288 const struct nir_xfb_info
*xfb_info
,
1289 const struct anv_pipeline_bind_map
*bind_map
);
1292 struct nir_shader_compiler_options
;
1295 anv_device_search_for_nir(struct anv_device
*device
,
1296 struct anv_pipeline_cache
*cache
,
1297 const struct nir_shader_compiler_options
*nir_options
,
1298 unsigned char sha1_key
[20],
1302 anv_device_upload_nir(struct anv_device
*device
,
1303 struct anv_pipeline_cache
*cache
,
1304 const struct nir_shader
*nir
,
1305 unsigned char sha1_key
[20]);
1307 struct anv_address
{
1313 struct vk_device vk
;
1315 struct anv_physical_device
* physical
;
1317 struct gen_device_info info
;
1318 struct isl_device isl_dev
;
1321 bool can_chain_batches
;
1322 bool robust_buffer_access
;
1323 struct anv_device_extension_table enabled_extensions
;
1324 struct anv_device_dispatch_table dispatch
;
1326 pthread_mutex_t vma_mutex
;
1327 struct util_vma_heap vma_lo
;
1328 struct util_vma_heap vma_cva
;
1329 struct util_vma_heap vma_hi
;
1331 /** List of all anv_device_memory objects */
1332 struct list_head memory_objects
;
1334 struct anv_bo_pool batch_bo_pool
;
1336 struct anv_bo_cache bo_cache
;
1338 struct anv_state_pool dynamic_state_pool
;
1339 struct anv_state_pool instruction_state_pool
;
1340 struct anv_state_pool binding_table_pool
;
1341 struct anv_state_pool surface_state_pool
;
1343 struct anv_state_reserved_pool custom_border_colors
;
1345 /** BO used for various workarounds
1347 * There are a number of workarounds on our hardware which require writing
1348 * data somewhere and it doesn't really matter where. For that, we use
1349 * this BO and just write to the first dword or so.
1351 * We also need to be able to handle NULL buffers bound as pushed UBOs.
1352 * For that, we use the high bytes (>= 1024) of the workaround BO.
1354 struct anv_bo
* workaround_bo
;
1355 struct anv_address workaround_address
;
1357 struct anv_bo
* trivial_batch_bo
;
1358 struct anv_bo
* hiz_clear_bo
;
1359 struct anv_state null_surface_state
;
1361 struct anv_pipeline_cache default_pipeline_cache
;
1362 struct blorp_context blorp
;
1364 struct anv_state border_colors
;
1366 struct anv_state slice_hash
;
1368 struct anv_queue queue
;
1370 struct anv_scratch_pool scratch_pool
;
1372 pthread_mutex_t mutex
;
1373 pthread_cond_t queue_submit
;
1376 struct gen_batch_decode_ctx decoder_ctx
;
1378 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1379 * the cmd_buffer's list.
1381 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1383 int perf_fd
; /* -1 if no opened */
1384 uint64_t perf_metric
; /* 0 if unset */
1386 struct gen_aux_map_context
*aux_map_ctx
;
1389 static inline struct anv_instance
*
1390 anv_device_instance_or_null(const struct anv_device
*device
)
1392 return device
? device
->physical
->instance
: NULL
;
1395 static inline struct anv_state_pool
*
1396 anv_binding_table_pool(struct anv_device
*device
)
1398 if (device
->physical
->use_softpin
)
1399 return &device
->binding_table_pool
;
1401 return &device
->surface_state_pool
;
1404 static inline struct anv_state
1405 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1406 if (device
->physical
->use_softpin
)
1407 return anv_state_pool_alloc(&device
->binding_table_pool
,
1408 device
->binding_table_pool
.block_size
, 0);
1410 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1414 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1415 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1418 static inline uint32_t
1419 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1421 if (bo
->is_external
)
1422 return device
->isl_dev
.mocs
.external
;
1424 return device
->isl_dev
.mocs
.internal
;
1427 void anv_device_init_blorp(struct anv_device
*device
);
1428 void anv_device_finish_blorp(struct anv_device
*device
);
1430 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1431 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1432 const char *file
, int line
,
1433 const char *msg
, ...)
1434 anv_printflike(4, 5);
1435 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1436 const char *file
, int line
,
1437 const char *msg
, ...)
1438 anv_printflike(4, 5);
1439 #define anv_device_set_lost(dev, ...) \
1440 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1441 #define anv_queue_set_lost(queue, ...) \
1442 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1445 anv_device_is_lost(struct anv_device
*device
)
1447 return unlikely(p_atomic_read(&device
->_lost
));
1450 VkResult
anv_device_query_status(struct anv_device
*device
);
1453 enum anv_bo_alloc_flags
{
1454 /** Specifies that the BO must have a 32-bit address
1456 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1458 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1460 /** Specifies that the BO may be shared externally */
1461 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1463 /** Specifies that the BO should be mapped */
1464 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1466 /** Specifies that the BO should be snooped so we get coherency */
1467 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1469 /** Specifies that the BO should be captured in error states */
1470 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1472 /** Specifies that the BO will have an address assigned by the caller
1474 * Such BOs do not exist in any VMA heap.
1476 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1478 /** Enables implicit synchronization on the BO
1480 * This is the opposite of EXEC_OBJECT_ASYNC.
1482 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1484 /** Enables implicit synchronization on the BO
1486 * This is equivalent to EXEC_OBJECT_WRITE.
1488 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1490 /** Has an address which is visible to the client */
1491 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS
= (1 << 8),
1493 /** This buffer has implicit CCS data attached to it */
1494 ANV_BO_ALLOC_IMPLICIT_CCS
= (1 << 9),
1497 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1498 enum anv_bo_alloc_flags alloc_flags
,
1499 uint64_t explicit_address
,
1500 struct anv_bo
**bo
);
1501 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1502 void *host_ptr
, uint32_t size
,
1503 enum anv_bo_alloc_flags alloc_flags
,
1504 uint64_t client_address
,
1505 struct anv_bo
**bo_out
);
1506 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1507 enum anv_bo_alloc_flags alloc_flags
,
1508 uint64_t client_address
,
1509 struct anv_bo
**bo
);
1510 VkResult
anv_device_export_bo(struct anv_device
*device
,
1511 struct anv_bo
*bo
, int *fd_out
);
1512 void anv_device_release_bo(struct anv_device
*device
,
1515 static inline struct anv_bo
*
1516 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1518 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1521 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1522 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1525 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1526 void anv_queue_finish(struct anv_queue
*queue
);
1528 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1529 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1530 struct anv_batch
*batch
);
1532 uint64_t anv_gettime_ns(void);
1533 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1535 void* anv_gem_mmap(struct anv_device
*device
,
1536 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1537 void anv_gem_munmap(struct anv_device
*device
, void *p
, uint64_t size
);
1538 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1539 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1540 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1541 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1542 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1543 int anv_gem_execbuffer(struct anv_device
*device
,
1544 struct drm_i915_gem_execbuffer2
*execbuf
);
1545 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1546 uint32_t stride
, uint32_t tiling
);
1547 int anv_gem_create_context(struct anv_device
*device
);
1548 bool anv_gem_has_context_priority(int fd
);
1549 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1550 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1552 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1554 int anv_gem_get_param(int fd
, uint32_t param
);
1555 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1556 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1557 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1558 uint32_t *active
, uint32_t *pending
);
1559 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1560 int anv_gem_reg_read(int fd
, uint32_t offset
, uint64_t *result
);
1561 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1562 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1563 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1564 uint32_t read_domains
, uint32_t write_domain
);
1565 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1566 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1567 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1568 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1569 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1570 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1572 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1573 uint32_t handle
, int fd
);
1574 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1575 bool anv_gem_supports_syncobj_wait(int fd
);
1576 int anv_gem_syncobj_wait(struct anv_device
*device
,
1577 uint32_t *handles
, uint32_t num_handles
,
1578 int64_t abs_timeout_ns
, bool wait_all
);
1580 uint64_t anv_vma_alloc(struct anv_device
*device
,
1581 uint64_t size
, uint64_t align
,
1582 enum anv_bo_alloc_flags alloc_flags
,
1583 uint64_t client_address
);
1584 void anv_vma_free(struct anv_device
*device
,
1585 uint64_t address
, uint64_t size
);
1587 struct anv_reloc_list
{
1588 uint32_t num_relocs
;
1589 uint32_t array_length
;
1590 struct drm_i915_gem_relocation_entry
* relocs
;
1591 struct anv_bo
** reloc_bos
;
1596 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1597 const VkAllocationCallbacks
*alloc
);
1598 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1599 const VkAllocationCallbacks
*alloc
);
1601 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1602 const VkAllocationCallbacks
*alloc
,
1603 uint32_t offset
, struct anv_bo
*target_bo
,
1604 uint32_t delta
, uint64_t *address_u64_out
);
1606 struct anv_batch_bo
{
1607 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1608 struct list_head link
;
1612 /* Bytes actually consumed in this batch BO */
1615 struct anv_reloc_list relocs
;
1619 const VkAllocationCallbacks
* alloc
;
1621 struct anv_address start_addr
;
1627 struct anv_reloc_list
* relocs
;
1629 /* This callback is called (with the associated user data) in the event
1630 * that the batch runs out of space.
1632 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1636 * Current error status of the command buffer. Used to track inconsistent
1637 * or incomplete command buffer states that are the consequence of run-time
1638 * errors such as out of memory scenarios. We want to track this in the
1639 * batch because the command buffer object is not visible to some parts
1645 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1646 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1647 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1648 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1649 struct anv_address
anv_batch_address(struct anv_batch
*batch
, void *batch_location
);
1652 anv_batch_set_storage(struct anv_batch
*batch
, struct anv_address addr
,
1653 void *map
, size_t size
)
1655 batch
->start_addr
= addr
;
1656 batch
->next
= batch
->start
= map
;
1657 batch
->end
= map
+ size
;
1660 static inline VkResult
1661 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1663 assert(error
!= VK_SUCCESS
);
1664 if (batch
->status
== VK_SUCCESS
)
1665 batch
->status
= error
;
1666 return batch
->status
;
1670 anv_batch_has_error(struct anv_batch
*batch
)
1672 return batch
->status
!= VK_SUCCESS
;
1675 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1678 anv_address_is_null(struct anv_address addr
)
1680 return addr
.bo
== NULL
&& addr
.offset
== 0;
1683 static inline uint64_t
1684 anv_address_physical(struct anv_address addr
)
1686 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1687 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1689 return gen_canonical_address(addr
.offset
);
1692 static inline struct anv_address
1693 anv_address_add(struct anv_address addr
, uint64_t offset
)
1695 addr
.offset
+= offset
;
1700 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1702 unsigned reloc_size
= 0;
1703 if (device
->info
.gen
>= 8) {
1704 reloc_size
= sizeof(uint64_t);
1705 *(uint64_t *)p
= gen_canonical_address(v
);
1707 reloc_size
= sizeof(uint32_t);
1711 if (flush
&& !device
->info
.has_llc
)
1712 gen_flush_range(p
, reloc_size
);
1715 static inline uint64_t
1716 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1717 const struct anv_address address
, uint32_t delta
)
1719 if (address
.bo
== NULL
) {
1720 return address
.offset
+ delta
;
1722 assert(batch
->start
<= location
&& location
< batch
->end
);
1724 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1728 #define __gen_address_type struct anv_address
1729 #define __gen_user_data struct anv_batch
1730 #define __gen_combine_address _anv_combine_address
1732 /* Wrapper macros needed to work around preprocessor argument issues. In
1733 * particular, arguments don't get pre-evaluated if they are concatenated.
1734 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1735 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1736 * We can work around this easily enough with these helpers.
1738 #define __anv_cmd_length(cmd) cmd ## _length
1739 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1740 #define __anv_cmd_header(cmd) cmd ## _header
1741 #define __anv_cmd_pack(cmd) cmd ## _pack
1742 #define __anv_reg_num(reg) reg ## _num
1744 #define anv_pack_struct(dst, struc, ...) do { \
1745 struct struc __template = { \
1748 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1749 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1752 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1753 void *__dst = anv_batch_emit_dwords(batch, n); \
1755 struct cmd __template = { \
1756 __anv_cmd_header(cmd), \
1757 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1760 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1765 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1769 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1770 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1773 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1774 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1775 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1778 #define anv_batch_emit(batch, cmd, name) \
1779 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1780 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1781 __builtin_expect(_dst != NULL, 1); \
1782 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1783 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1787 /* #define __gen_get_batch_dwords anv_batch_emit_dwords */
1788 /* #define __gen_get_batch_address anv_batch_address */
1789 /* #define __gen_address_value anv_address_physical */
1790 /* #define __gen_address_offset anv_address_add */
1792 struct anv_device_memory
{
1793 struct vk_object_base base
;
1795 struct list_head link
;
1798 struct anv_memory_type
* type
;
1799 VkDeviceSize map_size
;
1802 /* If set, we are holding reference to AHardwareBuffer
1803 * which we must release when memory is freed.
1805 struct AHardwareBuffer
* ahw
;
1807 /* If set, this memory comes from a host pointer. */
1812 * Header for Vertex URB Entry (VUE)
1814 struct anv_vue_header
{
1816 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1817 uint32_t ViewportIndex
;
1821 /** Struct representing a sampled image descriptor
1823 * This descriptor layout is used for sampled images, bare sampler, and
1824 * combined image/sampler descriptors.
1826 struct anv_sampled_image_descriptor
{
1827 /** Bindless image handle
1829 * This is expected to already be shifted such that the 20-bit
1830 * SURFACE_STATE table index is in the top 20 bits.
1834 /** Bindless sampler handle
1836 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1837 * to the dynamic state base address.
1842 struct anv_texture_swizzle_descriptor
{
1845 * See also nir_intrinsic_channel_select_intel
1849 /** Unused padding to ensure the struct is a multiple of 64 bits */
1853 /** Struct representing a storage image descriptor */
1854 struct anv_storage_image_descriptor
{
1855 /** Bindless image handles
1857 * These are expected to already be shifted such that the 20-bit
1858 * SURFACE_STATE table index is in the top 20 bits.
1860 uint32_t read_write
;
1861 uint32_t write_only
;
1864 /** Struct representing a address/range descriptor
1866 * The fields of this struct correspond directly to the data layout of
1867 * nir_address_format_64bit_bounded_global addresses. The last field is the
1868 * offset in the NIR address so it must be zero so that when you load the
1869 * descriptor you get a pointer to the start of the range.
1871 struct anv_address_range_descriptor
{
1877 enum anv_descriptor_data
{
1878 /** The descriptor contains a BTI reference to a surface state */
1879 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1880 /** The descriptor contains a BTI reference to a sampler state */
1881 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1882 /** The descriptor contains an actual buffer view */
1883 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1884 /** The descriptor contains auxiliary image layout data */
1885 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1886 /** The descriptor contains auxiliary image layout data */
1887 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1888 /** anv_address_range_descriptor with a buffer address and range */
1889 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1890 /** Bindless surface handle */
1891 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1892 /** Storage image handles */
1893 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1894 /** Storage image handles */
1895 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1898 struct anv_descriptor_set_binding_layout
{
1900 /* The type of the descriptors in this binding */
1901 VkDescriptorType type
;
1904 /* Flags provided when this binding was created */
1905 VkDescriptorBindingFlagsEXT flags
;
1907 /* Bitfield representing the type of data this descriptor contains */
1908 enum anv_descriptor_data data
;
1910 /* Maximum number of YCbCr texture/sampler planes */
1911 uint8_t max_plane_count
;
1913 /* Number of array elements in this binding (or size in bytes for inline
1916 uint16_t array_size
;
1918 /* Index into the flattend descriptor set */
1919 uint16_t descriptor_index
;
1921 /* Index into the dynamic state array for a dynamic buffer */
1922 int16_t dynamic_offset_index
;
1924 /* Index into the descriptor set buffer views */
1925 int16_t buffer_view_index
;
1927 /* Offset into the descriptor buffer where this descriptor lives */
1928 uint32_t descriptor_offset
;
1930 /* Immutable samplers (or NULL if no immutable samplers) */
1931 struct anv_sampler
**immutable_samplers
;
1934 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1936 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1937 VkDescriptorType type
);
1939 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1940 const struct anv_descriptor_set_binding_layout
*binding
,
1943 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1944 const struct anv_descriptor_set_binding_layout
*binding
,
1947 struct anv_descriptor_set_layout
{
1948 struct vk_object_base base
;
1950 /* Descriptor set layouts can be destroyed at almost any time */
1953 /* Number of bindings in this descriptor set */
1954 uint16_t binding_count
;
1956 /* Total size of the descriptor set with room for all array entries */
1959 /* Shader stages affected by this descriptor set */
1960 uint16_t shader_stages
;
1962 /* Number of buffer views in this descriptor set */
1963 uint16_t buffer_view_count
;
1965 /* Number of dynamic offsets used by this descriptor set */
1966 uint16_t dynamic_offset_count
;
1968 /* For each shader stage, which offsets apply to that stage */
1969 uint16_t stage_dynamic_offsets
[MESA_SHADER_STAGES
];
1971 /* Size of the descriptor buffer for this descriptor set */
1972 uint32_t descriptor_buffer_size
;
1974 /* Bindings in this descriptor set */
1975 struct anv_descriptor_set_binding_layout binding
[0];
1978 void anv_descriptor_set_layout_destroy(struct anv_device
*device
,
1979 struct anv_descriptor_set_layout
*layout
);
1982 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1984 assert(layout
&& layout
->ref_cnt
>= 1);
1985 p_atomic_inc(&layout
->ref_cnt
);
1989 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1990 struct anv_descriptor_set_layout
*layout
)
1992 assert(layout
&& layout
->ref_cnt
>= 1);
1993 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1994 anv_descriptor_set_layout_destroy(device
, layout
);
1997 struct anv_descriptor
{
1998 VkDescriptorType type
;
2002 VkImageLayout layout
;
2003 struct anv_image_view
*image_view
;
2004 struct anv_sampler
*sampler
;
2008 struct anv_buffer
*buffer
;
2013 struct anv_buffer_view
*buffer_view
;
2017 struct anv_descriptor_set
{
2018 struct vk_object_base base
;
2020 struct anv_descriptor_pool
*pool
;
2021 struct anv_descriptor_set_layout
*layout
;
2024 /* State relative to anv_descriptor_pool::bo */
2025 struct anv_state desc_mem
;
2026 /* Surface state for the descriptor buffer */
2027 struct anv_state desc_surface_state
;
2029 uint32_t buffer_view_count
;
2030 struct anv_buffer_view
*buffer_views
;
2032 /* Link to descriptor pool's desc_sets list . */
2033 struct list_head pool_link
;
2035 struct anv_descriptor descriptors
[0];
2038 struct anv_buffer_view
{
2039 struct vk_object_base base
;
2041 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
2042 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2044 struct anv_address address
;
2046 struct anv_state surface_state
;
2047 struct anv_state storage_surface_state
;
2048 struct anv_state writeonly_storage_surface_state
;
2050 struct brw_image_param storage_image_param
;
2053 struct anv_push_descriptor_set
{
2054 struct anv_descriptor_set set
;
2056 /* Put this field right behind anv_descriptor_set so it fills up the
2057 * descriptors[0] field. */
2058 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
2060 /** True if the descriptor set buffer has been referenced by a draw or
2063 bool set_used_on_gpu
;
2065 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
2068 struct anv_descriptor_pool
{
2069 struct vk_object_base base
;
2076 struct util_vma_heap bo_heap
;
2078 struct anv_state_stream surface_state_stream
;
2079 void *surface_state_free_list
;
2081 struct list_head desc_sets
;
2086 enum anv_descriptor_template_entry_type
{
2087 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
2088 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
2089 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
2092 struct anv_descriptor_template_entry
{
2093 /* The type of descriptor in this entry */
2094 VkDescriptorType type
;
2096 /* Binding in the descriptor set */
2099 /* Offset at which to write into the descriptor set binding */
2100 uint32_t array_element
;
2102 /* Number of elements to write into the descriptor set binding */
2103 uint32_t array_count
;
2105 /* Offset into the user provided data */
2108 /* Stride between elements into the user provided data */
2112 struct anv_descriptor_update_template
{
2113 struct vk_object_base base
;
2115 VkPipelineBindPoint bind_point
;
2117 /* The descriptor set this template corresponds to. This value is only
2118 * valid if the template was created with the templateType
2119 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2123 /* Number of entries in this template */
2124 uint32_t entry_count
;
2126 /* Entries of the template */
2127 struct anv_descriptor_template_entry entries
[0];
2131 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
2134 anv_descriptor_set_write_image_view(struct anv_device
*device
,
2135 struct anv_descriptor_set
*set
,
2136 const VkDescriptorImageInfo
* const info
,
2137 VkDescriptorType type
,
2142 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
2143 struct anv_descriptor_set
*set
,
2144 VkDescriptorType type
,
2145 struct anv_buffer_view
*buffer_view
,
2150 anv_descriptor_set_write_buffer(struct anv_device
*device
,
2151 struct anv_descriptor_set
*set
,
2152 struct anv_state_stream
*alloc_stream
,
2153 VkDescriptorType type
,
2154 struct anv_buffer
*buffer
,
2157 VkDeviceSize offset
,
2158 VkDeviceSize range
);
2160 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
2161 struct anv_descriptor_set
*set
,
2168 anv_descriptor_set_write_template(struct anv_device
*device
,
2169 struct anv_descriptor_set
*set
,
2170 struct anv_state_stream
*alloc_stream
,
2171 const struct anv_descriptor_update_template
*template,
2175 anv_descriptor_set_create(struct anv_device
*device
,
2176 struct anv_descriptor_pool
*pool
,
2177 struct anv_descriptor_set_layout
*layout
,
2178 struct anv_descriptor_set
**out_set
);
2181 anv_descriptor_set_destroy(struct anv_device
*device
,
2182 struct anv_descriptor_pool
*pool
,
2183 struct anv_descriptor_set
*set
);
2185 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2186 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2187 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2188 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2189 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2190 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2192 struct anv_pipeline_binding
{
2193 /** Index in the descriptor set
2195 * This is a flattened index; the descriptor set layout is already taken
2200 /** The descriptor set this surface corresponds to.
2202 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2203 * binding is not a normal descriptor set but something else.
2208 /** Plane in the binding index for images */
2211 /** Input attachment index (relative to the subpass) */
2212 uint8_t input_attachment_index
;
2214 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2215 uint8_t dynamic_offset_index
;
2218 /** For a storage image, whether it is write-only */
2221 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2222 * assuming POD zero-initialization.
2227 struct anv_push_range
{
2228 /** Index in the descriptor set */
2231 /** Descriptor set index */
2234 /** Dynamic offset index (for dynamic UBOs) */
2235 uint8_t dynamic_offset_index
;
2237 /** Start offset in units of 32B */
2240 /** Range in units of 32B */
2244 struct anv_pipeline_layout
{
2245 struct vk_object_base base
;
2248 struct anv_descriptor_set_layout
*layout
;
2249 uint32_t dynamic_offset_start
;
2254 unsigned char sha1
[20];
2258 struct vk_object_base base
;
2260 struct anv_device
* device
;
2263 VkBufferUsageFlags usage
;
2265 /* Set when bound */
2266 struct anv_address address
;
2269 static inline uint64_t
2270 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2272 assert(offset
<= buffer
->size
);
2273 if (range
== VK_WHOLE_SIZE
) {
2274 return buffer
->size
- offset
;
2276 assert(range
+ offset
>= range
);
2277 assert(range
+ offset
<= buffer
->size
);
2282 enum anv_cmd_dirty_bits
{
2283 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2284 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2285 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2286 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2287 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2288 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2289 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2290 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2291 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2292 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2293 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2294 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2295 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2296 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2298 typedef uint32_t anv_cmd_dirty_mask_t
;
2300 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2301 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2302 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2303 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2304 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2305 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2306 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2307 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2308 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2309 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2310 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2312 static inline enum anv_cmd_dirty_bits
2313 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2316 case VK_DYNAMIC_STATE_VIEWPORT
:
2317 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2318 case VK_DYNAMIC_STATE_SCISSOR
:
2319 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2320 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2321 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2322 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2323 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2324 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2325 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2326 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2327 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2328 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2329 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2330 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2331 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2332 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2333 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2334 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2335 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2337 assert(!"Unsupported dynamic state");
2343 enum anv_pipe_bits
{
2344 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2345 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2346 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2347 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2348 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2349 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2350 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2351 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2352 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2353 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2354 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2355 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2356 ANV_PIPE_END_OF_PIPE_SYNC_BIT
= (1 << 21),
2358 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2359 * a flush has happened but not a CS stall. The next time we do any sort
2360 * of invalidation we need to insert a CS stall at that time. Otherwise,
2361 * we would have to CS stall on every flush which could be bad.
2363 ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
= (1 << 22),
2365 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2366 * target operations related to transfer commands with VkBuffer as
2367 * destination are ongoing. Some operations like copies on the command
2368 * streamer might need to be aware of this to trigger the appropriate stall
2369 * before they can proceed with the copy.
2371 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 23),
2373 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2374 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2375 * done by writing the AUX-TT register.
2377 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
= (1 << 24),
2379 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2380 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2381 * implement a workaround for Gen9.
2383 ANV_PIPE_POST_SYNC_BIT
= (1 << 25),
2386 #define ANV_PIPE_FLUSH_BITS ( \
2387 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2388 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2389 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2390 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2392 #define ANV_PIPE_STALL_BITS ( \
2393 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2394 ANV_PIPE_DEPTH_STALL_BIT | \
2395 ANV_PIPE_CS_STALL_BIT)
2397 #define ANV_PIPE_INVALIDATE_BITS ( \
2398 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2399 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2400 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2401 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2402 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2403 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2404 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2406 static inline enum anv_pipe_bits
2407 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2409 enum anv_pipe_bits pipe_bits
= 0;
2412 for_each_bit(b
, flags
) {
2413 switch ((VkAccessFlagBits
)(1 << b
)) {
2414 case VK_ACCESS_SHADER_WRITE_BIT
:
2415 /* We're transitioning a buffer that was previously used as write
2416 * destination through the data port. To make its content available
2417 * to future operations, flush the data cache.
2419 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2421 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2422 /* We're transitioning a buffer that was previously used as render
2423 * target. To make its content available to future operations, flush
2424 * the render target cache.
2426 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2428 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2429 /* We're transitioning a buffer that was previously used as depth
2430 * buffer. To make its content available to future operations, flush
2433 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2435 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2436 /* We're transitioning a buffer that was previously used as a
2437 * transfer write destination. Generic write operations include color
2438 * & depth operations as well as buffer operations like :
2439 * - vkCmdClearColorImage()
2440 * - vkCmdClearDepthStencilImage()
2441 * - vkCmdBlitImage()
2442 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2444 * Most of these operations are implemented using Blorp which writes
2445 * through the render target, so flush that cache to make it visible
2446 * to future operations. And for depth related operations we also
2447 * need to flush the depth cache.
2449 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2450 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2452 case VK_ACCESS_MEMORY_WRITE_BIT
:
2453 /* We're transitioning a buffer for generic write operations. Flush
2456 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2459 break; /* Nothing to do */
2466 static inline enum anv_pipe_bits
2467 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2469 enum anv_pipe_bits pipe_bits
= 0;
2472 for_each_bit(b
, flags
) {
2473 switch ((VkAccessFlagBits
)(1 << b
)) {
2474 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2475 /* Indirect draw commands take a buffer as input that we're going to
2476 * read from the command streamer to load some of the HW registers
2477 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2478 * command streamer stall so that all the cache flushes have
2479 * completed before the command streamer loads from memory.
2481 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2482 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2483 * through a vertex buffer, so invalidate that cache.
2485 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2486 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2487 * UBO from the buffer, so we need to invalidate constant cache.
2489 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2491 case VK_ACCESS_INDEX_READ_BIT
:
2492 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2493 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2494 * commands, so we invalidate the VF cache to make sure there is no
2495 * stale data when we start rendering.
2497 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2499 case VK_ACCESS_UNIFORM_READ_BIT
:
2500 /* We transitioning a buffer to be used as uniform data. Because
2501 * uniform is accessed through the data port & sampler, we need to
2502 * invalidate the texture cache (sampler) & constant cache (data
2503 * port) to avoid stale data.
2505 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2506 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2508 case VK_ACCESS_SHADER_READ_BIT
:
2509 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2510 case VK_ACCESS_TRANSFER_READ_BIT
:
2511 /* Transitioning a buffer to be read through the sampler, so
2512 * invalidate the texture cache, we don't want any stale data.
2514 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2516 case VK_ACCESS_MEMORY_READ_BIT
:
2517 /* Transitioning a buffer for generic read, invalidate all the
2520 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2522 case VK_ACCESS_MEMORY_WRITE_BIT
:
2523 /* Generic write, make sure all previously written things land in
2526 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2528 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2529 /* Transitioning a buffer for conditional rendering. We'll load the
2530 * content of this buffer into HW registers using the command
2531 * streamer, so we need to stall the command streamer to make sure
2532 * any in-flight flush operations have completed.
2534 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2537 break; /* Nothing to do */
2544 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2545 VK_IMAGE_ASPECT_COLOR_BIT | \
2546 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2547 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2548 VK_IMAGE_ASPECT_PLANE_2_BIT)
2549 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2550 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2551 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2552 VK_IMAGE_ASPECT_PLANE_2_BIT)
2554 struct anv_vertex_binding
{
2555 struct anv_buffer
* buffer
;
2556 VkDeviceSize offset
;
2559 struct anv_xfb_binding
{
2560 struct anv_buffer
* buffer
;
2561 VkDeviceSize offset
;
2565 struct anv_push_constants
{
2566 /** Push constant data provided by the client through vkPushConstants */
2567 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2569 /** Dynamic offsets for dynamic UBOs and SSBOs */
2570 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2572 uint64_t push_reg_mask
;
2574 /** Pad out to a multiple of 32 bytes */
2578 /** Base workgroup ID
2580 * Used for vkCmdDispatchBase.
2582 uint32_t base_work_group_id
[3];
2586 * This is never set by software but is implicitly filled out when
2587 * uploading the push constants for compute shaders.
2589 uint32_t subgroup_id
;
2593 struct anv_dynamic_state
{
2596 VkViewport viewports
[MAX_VIEWPORTS
];
2601 VkRect2D scissors
[MAX_SCISSORS
];
2612 float blend_constants
[4];
2622 } stencil_compare_mask
;
2627 } stencil_write_mask
;
2632 } stencil_reference
;
2640 extern const struct anv_dynamic_state default_dynamic_state
;
2642 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2643 const struct anv_dynamic_state
*src
,
2644 uint32_t copy_mask
);
2646 struct anv_surface_state
{
2647 struct anv_state state
;
2648 /** Address of the surface referred to by this state
2650 * This address is relative to the start of the BO.
2652 struct anv_address address
;
2653 /* Address of the aux surface, if any
2655 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2657 * With the exception of gen8, the bottom 12 bits of this address' offset
2658 * include extra aux information.
2660 struct anv_address aux_address
;
2661 /* Address of the clear color, if any
2663 * This address is relative to the start of the BO.
2665 struct anv_address clear_address
;
2669 * Attachment state when recording a renderpass instance.
2671 * The clear value is valid only if there exists a pending clear.
2673 struct anv_attachment_state
{
2674 enum isl_aux_usage aux_usage
;
2675 struct anv_surface_state color
;
2676 struct anv_surface_state input
;
2678 VkImageLayout current_layout
;
2679 VkImageLayout current_stencil_layout
;
2680 VkImageAspectFlags pending_clear_aspects
;
2681 VkImageAspectFlags pending_load_aspects
;
2683 VkClearValue clear_value
;
2685 /* When multiview is active, attachments with a renderpass clear
2686 * operation have their respective layers cleared on the first
2687 * subpass that uses them, and only in that subpass. We keep track
2688 * of this using a bitfield to indicate which layers of an attachment
2689 * have not been cleared yet when multiview is active.
2691 uint32_t pending_clear_views
;
2692 struct anv_image_view
* image_view
;
2695 /** State tracking for vertex buffer flushes
2697 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2698 * addresses. If you happen to have two vertex buffers which get placed
2699 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2700 * collisions. In order to solve this problem, we track vertex address ranges
2701 * which are live in the cache and invalidate the cache if one ever exceeds 32
2704 struct anv_vb_cache_range
{
2705 /* Virtual address at which the live vertex buffer cache range starts for
2706 * this vertex buffer index.
2710 /* Virtual address of the byte after where vertex buffer cache range ends.
2711 * This is exclusive such that end - start is the size of the range.
2716 /** State tracking for particular pipeline bind point
2718 * This struct is the base struct for anv_cmd_graphics_state and
2719 * anv_cmd_compute_state. These are used to track state which is bound to a
2720 * particular type of pipeline. Generic state that applies per-stage such as
2721 * binding table offsets and push constants is tracked generically with a
2722 * per-stage array in anv_cmd_state.
2724 struct anv_cmd_pipeline_state
{
2725 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2726 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2729 /** State tracking for graphics pipeline
2731 * This has anv_cmd_pipeline_state as a base struct to track things which get
2732 * bound to a graphics pipeline. Along with general pipeline bind point state
2733 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2734 * state which is graphics-specific.
2736 struct anv_cmd_graphics_state
{
2737 struct anv_cmd_pipeline_state base
;
2739 struct anv_graphics_pipeline
*pipeline
;
2741 anv_cmd_dirty_mask_t dirty
;
2744 struct anv_vb_cache_range ib_bound_range
;
2745 struct anv_vb_cache_range ib_dirty_range
;
2746 struct anv_vb_cache_range vb_bound_ranges
[33];
2747 struct anv_vb_cache_range vb_dirty_ranges
[33];
2749 struct anv_dynamic_state dynamic
;
2752 struct anv_buffer
*index_buffer
;
2753 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2754 uint32_t index_offset
;
2758 /** State tracking for compute pipeline
2760 * This has anv_cmd_pipeline_state as a base struct to track things which get
2761 * bound to a compute pipeline. Along with general pipeline bind point state
2762 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2763 * state which is compute-specific.
2765 struct anv_cmd_compute_state
{
2766 struct anv_cmd_pipeline_state base
;
2768 struct anv_compute_pipeline
*pipeline
;
2770 bool pipeline_dirty
;
2772 struct anv_address num_workgroups
;
2775 /** State required while building cmd buffer */
2776 struct anv_cmd_state
{
2777 /* PIPELINE_SELECT.PipelineSelection */
2778 uint32_t current_pipeline
;
2779 const struct gen_l3_config
* current_l3_config
;
2780 uint32_t last_aux_map_state
;
2782 struct anv_cmd_graphics_state gfx
;
2783 struct anv_cmd_compute_state compute
;
2785 enum anv_pipe_bits pending_pipe_bits
;
2786 VkShaderStageFlags descriptors_dirty
;
2787 VkShaderStageFlags push_constants_dirty
;
2789 struct anv_framebuffer
* framebuffer
;
2790 struct anv_render_pass
* pass
;
2791 struct anv_subpass
* subpass
;
2792 VkRect2D render_area
;
2793 uint32_t restart_index
;
2794 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2796 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2797 VkShaderStageFlags push_constant_stages
;
2798 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2799 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2800 struct anv_state samplers
[MESA_SHADER_STAGES
];
2802 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2803 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2804 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2807 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2808 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2809 * and before invoking the secondary in ExecuteCommands.
2811 bool pma_fix_enabled
;
2814 * Whether or not we know for certain that HiZ is enabled for the current
2815 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2816 * enabled or not, this will be false.
2820 bool conditional_render_enabled
;
2823 * Last rendering scale argument provided to
2824 * genX(cmd_buffer_emit_hashing_mode)().
2826 unsigned current_hash_scale
;
2829 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2830 * valid only when recording a render pass instance.
2832 struct anv_attachment_state
* attachments
;
2835 * Surface states for color render targets. These are stored in a single
2836 * flat array. For depth-stencil attachments, the surface state is simply
2839 struct anv_state attachment_states
;
2842 * A null surface state of the right size to match the framebuffer. This
2843 * is one of the states in attachment_states.
2845 struct anv_state null_surface_state
;
2848 struct anv_cmd_pool
{
2849 struct vk_object_base base
;
2850 VkAllocationCallbacks alloc
;
2851 struct list_head cmd_buffers
;
2854 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2856 enum anv_cmd_buffer_exec_mode
{
2857 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2858 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2859 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2860 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2861 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2862 ANV_CMD_BUFFER_EXEC_MODE_CALL_AND_RETURN
,
2865 struct anv_cmd_buffer
{
2866 struct vk_object_base base
;
2868 struct anv_device
* device
;
2870 struct anv_cmd_pool
* pool
;
2871 struct list_head pool_link
;
2873 struct anv_batch batch
;
2875 /* Fields required for the actual chain of anv_batch_bo's.
2877 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2879 struct list_head batch_bos
;
2880 enum anv_cmd_buffer_exec_mode exec_mode
;
2882 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2883 * referenced by this command buffer
2885 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2887 struct u_vector seen_bbos
;
2889 /* A vector of int32_t's for every block of binding tables.
2891 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2893 struct u_vector bt_block_states
;
2894 struct anv_state bt_next
;
2896 struct anv_reloc_list surface_relocs
;
2897 /** Last seen surface state block pool center bo offset */
2898 uint32_t last_ss_pool_center
;
2900 /* Serial for tracking buffer completion */
2903 /* Stream objects for storing temporary data */
2904 struct anv_state_stream surface_state_stream
;
2905 struct anv_state_stream dynamic_state_stream
;
2907 VkCommandBufferUsageFlags usage_flags
;
2908 VkCommandBufferLevel level
;
2910 struct anv_query_pool
*perf_query_pool
;
2912 struct anv_cmd_state state
;
2914 struct anv_address return_addr
;
2916 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2917 uint64_t intel_perf_marker
;
2920 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2921 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2922 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2923 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2924 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2925 struct anv_cmd_buffer
*secondary
);
2926 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2927 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
2928 struct anv_cmd_buffer
*cmd_buffer
,
2929 const VkSemaphore
*in_semaphores
,
2930 const uint64_t *in_wait_values
,
2931 uint32_t num_in_semaphores
,
2932 const VkSemaphore
*out_semaphores
,
2933 const uint64_t *out_signal_values
,
2934 uint32_t num_out_semaphores
,
2936 int perf_query_pass
);
2938 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2940 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2941 const void *data
, uint32_t size
, uint32_t alignment
);
2942 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2943 uint32_t *a
, uint32_t *b
,
2944 uint32_t dwords
, uint32_t alignment
);
2947 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2949 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2950 uint32_t entries
, uint32_t *state_offset
);
2952 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2954 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2955 uint32_t size
, uint32_t alignment
);
2958 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2960 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2961 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2962 bool depth_clamp_enable
);
2963 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2965 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2966 struct anv_render_pass
*pass
,
2967 struct anv_framebuffer
*framebuffer
,
2968 const VkClearValue
*clear_values
);
2970 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2973 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2974 gl_shader_stage stage
);
2976 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2978 const struct anv_image_view
*
2979 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2982 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2983 uint32_t num_entries
,
2984 uint32_t *state_offset
,
2985 struct anv_state
*bt_state
);
2987 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2989 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2991 enum anv_fence_type
{
2992 ANV_FENCE_TYPE_NONE
= 0,
2994 ANV_FENCE_TYPE_WSI_BO
,
2995 ANV_FENCE_TYPE_SYNCOBJ
,
2999 enum anv_bo_fence_state
{
3000 /** Indicates that this is a new (or newly reset fence) */
3001 ANV_BO_FENCE_STATE_RESET
,
3003 /** Indicates that this fence has been submitted to the GPU but is still
3004 * (as far as we know) in use by the GPU.
3006 ANV_BO_FENCE_STATE_SUBMITTED
,
3008 ANV_BO_FENCE_STATE_SIGNALED
,
3011 struct anv_fence_impl
{
3012 enum anv_fence_type type
;
3015 /** Fence implementation for BO fences
3017 * These fences use a BO and a set of CPU-tracked state flags. The BO
3018 * is added to the object list of the last execbuf call in a QueueSubmit
3019 * and is marked EXEC_WRITE. The state flags track when the BO has been
3020 * submitted to the kernel. We need to do this because Vulkan lets you
3021 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
3022 * will say it's idle in this case.
3026 enum anv_bo_fence_state state
;
3029 /** DRM syncobj handle for syncobj-based fences */
3033 struct wsi_fence
*fence_wsi
;
3038 struct vk_object_base base
;
3040 /* Permanent fence state. Every fence has some form of permanent state
3041 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
3042 * cross-process fences) or it could just be a dummy for use internally.
3044 struct anv_fence_impl permanent
;
3046 /* Temporary fence state. A fence *may* have temporary state. That state
3047 * is added to the fence by an import operation and is reset back to
3048 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
3049 * state cannot be signaled because the fence must already be signaled
3050 * before the temporary state can be exported from the fence in the other
3051 * process and imported here.
3053 struct anv_fence_impl temporary
;
3056 void anv_fence_reset_temporary(struct anv_device
*device
,
3057 struct anv_fence
*fence
);
3060 struct vk_object_base base
;
3062 struct anv_state state
;
3065 enum anv_semaphore_type
{
3066 ANV_SEMAPHORE_TYPE_NONE
= 0,
3067 ANV_SEMAPHORE_TYPE_DUMMY
,
3068 ANV_SEMAPHORE_TYPE_BO
,
3069 ANV_SEMAPHORE_TYPE_WSI_BO
,
3070 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
3071 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
3072 ANV_SEMAPHORE_TYPE_TIMELINE
,
3075 struct anv_timeline_point
{
3076 struct list_head link
;
3080 /* Number of waiter on this point, when > 0 the point should not be garbage
3085 /* BO used for synchronization. */
3089 struct anv_timeline
{
3090 pthread_mutex_t mutex
;
3091 pthread_cond_t cond
;
3093 uint64_t highest_past
;
3094 uint64_t highest_pending
;
3096 struct list_head points
;
3097 struct list_head free_points
;
3100 struct anv_semaphore_impl
{
3101 enum anv_semaphore_type type
;
3104 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
3105 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
3106 * object list on any execbuf2 calls for which this semaphore is used as
3107 * a wait or signal fence. When used as a signal fence or when type ==
3108 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
3112 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
3113 * If the semaphore is in the unsignaled state due to either just being
3114 * created or because it has been used for a wait, fd will be -1.
3118 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3119 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3120 * import so we don't need to bother with a userspace cache.
3124 /* Non shareable timeline semaphore
3126 * Used when kernel don't have support for timeline semaphores.
3128 struct anv_timeline timeline
;
3132 struct anv_semaphore
{
3133 struct vk_object_base base
;
3137 /* Permanent semaphore state. Every semaphore has some form of permanent
3138 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3139 * (for cross-process semaphores0 or it could just be a dummy for use
3142 struct anv_semaphore_impl permanent
;
3144 /* Temporary semaphore state. A semaphore *may* have temporary state.
3145 * That state is added to the semaphore by an import operation and is reset
3146 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3147 * semaphore with temporary state cannot be signaled because the semaphore
3148 * must already be signaled before the temporary state can be exported from
3149 * the semaphore in the other process and imported here.
3151 struct anv_semaphore_impl temporary
;
3154 void anv_semaphore_reset_temporary(struct anv_device
*device
,
3155 struct anv_semaphore
*semaphore
);
3157 struct anv_shader_module
{
3158 struct vk_object_base base
;
3160 unsigned char sha1
[20];
3165 static inline gl_shader_stage
3166 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
3168 assert(__builtin_popcount(vk_stage
) == 1);
3169 return ffs(vk_stage
) - 1;
3172 static inline VkShaderStageFlagBits
3173 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
3175 return (1 << mesa_stage
);
3178 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3180 #define anv_foreach_stage(stage, stage_bits) \
3181 for (gl_shader_stage stage, \
3182 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3183 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3184 __tmp &= ~(1 << (stage)))
3186 struct anv_pipeline_bind_map
{
3187 unsigned char surface_sha1
[20];
3188 unsigned char sampler_sha1
[20];
3189 unsigned char push_sha1
[20];
3191 uint32_t surface_count
;
3192 uint32_t sampler_count
;
3194 struct anv_pipeline_binding
* surface_to_descriptor
;
3195 struct anv_pipeline_binding
* sampler_to_descriptor
;
3197 struct anv_push_range push_ranges
[4];
3200 struct anv_shader_bin_key
{
3205 struct anv_shader_bin
{
3208 gl_shader_stage stage
;
3210 const struct anv_shader_bin_key
*key
;
3212 struct anv_state kernel
;
3213 uint32_t kernel_size
;
3215 struct anv_state constant_data
;
3216 uint32_t constant_data_size
;
3218 const struct brw_stage_prog_data
*prog_data
;
3219 uint32_t prog_data_size
;
3221 struct brw_compile_stats stats
[3];
3224 struct nir_xfb_info
*xfb_info
;
3226 struct anv_pipeline_bind_map bind_map
;
3229 struct anv_shader_bin
*
3230 anv_shader_bin_create(struct anv_device
*device
,
3231 gl_shader_stage stage
,
3232 const void *key
, uint32_t key_size
,
3233 const void *kernel
, uint32_t kernel_size
,
3234 const void *constant_data
, uint32_t constant_data_size
,
3235 const struct brw_stage_prog_data
*prog_data
,
3236 uint32_t prog_data_size
,
3237 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
3238 const struct nir_xfb_info
*xfb_info
,
3239 const struct anv_pipeline_bind_map
*bind_map
);
3242 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3245 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3247 assert(shader
&& shader
->ref_cnt
>= 1);
3248 p_atomic_inc(&shader
->ref_cnt
);
3252 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3254 assert(shader
&& shader
->ref_cnt
>= 1);
3255 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3256 anv_shader_bin_destroy(device
, shader
);
3259 struct anv_pipeline_executable
{
3260 gl_shader_stage stage
;
3262 struct brw_compile_stats stats
;
3268 enum anv_pipeline_type
{
3269 ANV_PIPELINE_GRAPHICS
,
3270 ANV_PIPELINE_COMPUTE
,
3273 struct anv_pipeline
{
3274 struct vk_object_base base
;
3276 struct anv_device
* device
;
3278 struct anv_batch batch
;
3279 struct anv_reloc_list batch_relocs
;
3283 enum anv_pipeline_type type
;
3284 VkPipelineCreateFlags flags
;
3286 struct util_dynarray executables
;
3288 const struct gen_l3_config
* l3_config
;
3291 struct anv_graphics_pipeline
{
3292 struct anv_pipeline base
;
3294 uint32_t batch_data
[512];
3296 anv_cmd_dirty_mask_t dynamic_state_mask
;
3297 struct anv_dynamic_state dynamic_state
;
3301 struct anv_subpass
* subpass
;
3303 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3305 VkShaderStageFlags active_stages
;
3307 bool primitive_restart
;
3309 bool depth_test_enable
;
3310 bool writes_stencil
;
3311 bool stencil_test_enable
;
3312 bool depth_clamp_enable
;
3313 bool depth_clip_enable
;
3314 bool sample_shading_enable
;
3316 bool depth_bounds_test_enable
;
3318 /* When primitive replication is used, subpass->view_mask will describe what
3319 * views to replicate.
3321 bool use_primitive_replication
;
3323 struct anv_state blend_state
;
3326 struct anv_pipeline_vertex_binding
{
3329 uint32_t instance_divisor
;
3334 uint32_t depth_stencil_state
[3];
3340 uint32_t wm_depth_stencil
[3];
3344 uint32_t wm_depth_stencil
[4];
3348 struct anv_compute_pipeline
{
3349 struct anv_pipeline base
;
3351 struct anv_shader_bin
* cs
;
3352 uint32_t cs_right_mask
;
3353 uint32_t batch_data
[9];
3354 uint32_t interface_descriptor_data
[8];
3357 #define ANV_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
3358 static inline struct anv_##pipe_type##_pipeline * \
3359 anv_pipeline_to_##pipe_type(struct anv_pipeline *pipeline) \
3361 assert(pipeline->type == pipe_enum); \
3362 return (struct anv_##pipe_type##_pipeline *) pipeline; \
3365 ANV_DECL_PIPELINE_DOWNCAST(graphics
, ANV_PIPELINE_GRAPHICS
)
3366 ANV_DECL_PIPELINE_DOWNCAST(compute
, ANV_PIPELINE_COMPUTE
)
3369 anv_pipeline_has_stage(const struct anv_graphics_pipeline
*pipeline
,
3370 gl_shader_stage stage
)
3372 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3375 #define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \
3376 static inline const struct brw_##prefix##_prog_data * \
3377 get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \
3379 if (anv_pipeline_has_stage(pipeline, stage)) { \
3380 return (const struct brw_##prefix##_prog_data *) \
3381 pipeline->shaders[stage]->prog_data; \
3387 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3388 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3389 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3390 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3391 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3393 static inline const struct brw_cs_prog_data
*
3394 get_cs_prog_data(const struct anv_compute_pipeline
*pipeline
)
3396 assert(pipeline
->cs
);
3397 return (const struct brw_cs_prog_data
*) pipeline
->cs
->prog_data
;
3400 static inline const struct brw_vue_prog_data
*
3401 anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline
*pipeline
)
3403 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3404 return &get_gs_prog_data(pipeline
)->base
;
3405 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3406 return &get_tes_prog_data(pipeline
)->base
;
3408 return &get_vs_prog_data(pipeline
)->base
;
3412 anv_pipeline_init(struct anv_pipeline
*pipeline
,
3413 struct anv_device
*device
,
3414 enum anv_pipeline_type type
,
3415 VkPipelineCreateFlags flags
,
3416 const VkAllocationCallbacks
*pAllocator
);
3419 anv_pipeline_finish(struct anv_pipeline
*pipeline
,
3420 struct anv_device
*device
,
3421 const VkAllocationCallbacks
*pAllocator
);
3424 anv_graphics_pipeline_init(struct anv_graphics_pipeline
*pipeline
, struct anv_device
*device
,
3425 struct anv_pipeline_cache
*cache
,
3426 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3427 const VkAllocationCallbacks
*alloc
);
3430 anv_pipeline_compile_cs(struct anv_compute_pipeline
*pipeline
,
3431 struct anv_pipeline_cache
*cache
,
3432 const VkComputePipelineCreateInfo
*info
,
3433 const struct anv_shader_module
*module
,
3434 const char *entrypoint
,
3435 const VkSpecializationInfo
*spec_info
);
3437 struct anv_cs_parameters
{
3438 uint32_t group_size
;
3443 struct anv_cs_parameters
3444 anv_cs_parameters(const struct anv_compute_pipeline
*pipeline
);
3446 struct anv_format_plane
{
3447 enum isl_format isl_format
:16;
3448 struct isl_swizzle swizzle
;
3450 /* Whether this plane contains chroma channels */
3453 /* For downscaling of YUV planes */
3454 uint8_t denominator_scales
[2];
3456 /* How to map sampled ycbcr planes to a single 4 component element. */
3457 struct isl_swizzle ycbcr_swizzle
;
3459 /* What aspect is associated to this plane */
3460 VkImageAspectFlags aspect
;
3465 struct anv_format_plane planes
[3];
3472 * Return the aspect's _format_ plane, not its _memory_ plane (using the
3473 * vocabulary of VK_EXT_image_drm_format_modifier). As a consequence, \a
3474 * aspect_mask may contain VK_IMAGE_ASPECT_PLANE_*, but must not contain
3475 * VK_IMAGE_ASPECT_MEMORY_PLANE_* .
3477 static inline uint32_t
3478 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3479 VkImageAspectFlags aspect_mask
)
3481 switch (aspect_mask
) {
3482 case VK_IMAGE_ASPECT_COLOR_BIT
:
3483 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3484 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3486 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3487 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3490 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3492 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3495 /* Purposefully assert with depth/stencil aspects. */
3496 unreachable("invalid image aspect");
3500 static inline VkImageAspectFlags
3501 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3504 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3505 if (util_bitcount(image_aspects
) > 1)
3506 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3507 return VK_IMAGE_ASPECT_COLOR_BIT
;
3509 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3510 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3511 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3512 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3515 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3516 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3518 const struct anv_format
*
3519 anv_get_format(VkFormat format
);
3521 static inline uint32_t
3522 anv_get_format_planes(VkFormat vk_format
)
3524 const struct anv_format
*format
= anv_get_format(vk_format
);
3526 return format
!= NULL
? format
->n_planes
: 0;
3529 struct anv_format_plane
3530 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3531 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3533 static inline enum isl_format
3534 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3535 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3537 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3540 bool anv_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
3541 VkImageCreateFlags create_flags
,
3543 VkImageTiling vk_tiling
,
3544 const VkImageFormatListCreateInfoKHR
*fmt_list
);
3546 static inline struct isl_swizzle
3547 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3549 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3550 * RGB as RGBA for texturing
3552 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3553 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3555 /* But it doesn't matter what we render to that channel */
3556 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3562 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3565 * Subsurface of an anv_image.
3567 struct anv_surface
{
3568 /** Valid only if isl_surf::size_B > 0. */
3569 struct isl_surf isl
;
3572 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3578 struct vk_object_base base
;
3580 VkImageType type
; /**< VkImageCreateInfo::imageType */
3581 /* The original VkFormat provided by the client. This may not match any
3582 * of the actual surface formats.
3585 const struct anv_format
*format
;
3587 VkImageAspectFlags aspects
;
3590 uint32_t array_size
;
3591 uint32_t samples
; /**< VkImageCreateInfo::samples */
3593 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3594 VkImageUsageFlags stencil_usage
;
3595 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3596 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3598 /** True if this is needs to be bound to an appropriately tiled BO.
3600 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3601 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3602 * we require a dedicated allocation so that we can know to allocate a
3605 bool needs_set_tiling
;
3608 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3609 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3611 uint64_t drm_format_mod
;
3616 /* Whether the image is made of several underlying buffer objects rather a
3617 * single one with different offsets.
3621 /* Image was created with external format. */
3622 bool external_format
;
3627 * For each foo, anv_image::planes[x].surface is valid if and only if
3628 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3629 * to figure the number associated with a given aspect.
3631 * The hardware requires that the depth buffer and stencil buffer be
3632 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3633 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3634 * allocate the depth and stencil buffers as separate surfaces in the same
3639 * -----------------------
3641 * ----------------------- |
3642 * | shadow surface0 | |
3643 * ----------------------- | Plane 0
3644 * | aux surface0 | |
3645 * ----------------------- |
3646 * | fast clear colors0 | \|/
3647 * -----------------------
3649 * ----------------------- |
3650 * | shadow surface1 | |
3651 * ----------------------- | Plane 1
3652 * | aux surface1 | |
3653 * ----------------------- |
3654 * | fast clear colors1 | \|/
3655 * -----------------------
3658 * -----------------------
3662 * Offset of the entire plane (whenever the image is disjoint this is
3670 struct anv_surface surface
;
3673 * A surface which shadows the main surface and may have different
3674 * tiling. This is used for sampling using a tiling that isn't supported
3675 * for other operations.
3677 struct anv_surface shadow_surface
;
3680 * The base aux usage for this image. For color images, this can be
3681 * either CCS_E or CCS_D depending on whether or not we can reliably
3682 * leave CCS on all the time.
3684 enum isl_aux_usage aux_usage
;
3686 struct anv_surface aux_surface
;
3689 * Offset of the fast clear state (used to compute the
3690 * fast_clear_state_offset of the following planes).
3692 uint32_t fast_clear_state_offset
;
3695 * BO associated with this plane, set when bound.
3697 struct anv_address address
;
3700 * When destroying the image, also free the bo.
3706 /* The ordering of this enum is important */
3707 enum anv_fast_clear_type
{
3708 /** Image does not have/support any fast-clear blocks */
3709 ANV_FAST_CLEAR_NONE
= 0,
3710 /** Image has/supports fast-clear but only to the default value */
3711 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3712 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3713 ANV_FAST_CLEAR_ANY
= 2,
3716 /* Returns the number of auxiliary buffer levels attached to an image. */
3717 static inline uint8_t
3718 anv_image_aux_levels(const struct anv_image
* const image
,
3719 VkImageAspectFlagBits aspect
)
3721 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3722 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
3725 /* The Gen12 CCS aux surface is represented with only one level. */
3726 return image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3727 image
->planes
[plane
].surface
.isl
.levels
:
3728 image
->planes
[plane
].aux_surface
.isl
.levels
;
3731 /* Returns the number of auxiliary buffer layers attached to an image. */
3732 static inline uint32_t
3733 anv_image_aux_layers(const struct anv_image
* const image
,
3734 VkImageAspectFlagBits aspect
,
3735 const uint8_t miplevel
)
3739 /* The miplevel must exist in the main buffer. */
3740 assert(miplevel
< image
->levels
);
3742 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3743 /* There are no layers with auxiliary data because the miplevel has no
3748 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3750 /* The Gen12 CCS aux surface is represented with only one layer. */
3751 const struct isl_extent4d
*aux_logical_level0_px
=
3752 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3753 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3754 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3756 return MAX2(aux_logical_level0_px
->array_len
,
3757 aux_logical_level0_px
->depth
>> miplevel
);
3761 static inline struct anv_address
3762 anv_image_get_clear_color_addr(UNUSED
const struct anv_device
*device
,
3763 const struct anv_image
*image
,
3764 VkImageAspectFlagBits aspect
)
3766 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3768 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3769 return anv_address_add(image
->planes
[plane
].address
,
3770 image
->planes
[plane
].fast_clear_state_offset
);
3773 static inline struct anv_address
3774 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3775 const struct anv_image
*image
,
3776 VkImageAspectFlagBits aspect
)
3778 struct anv_address addr
=
3779 anv_image_get_clear_color_addr(device
, image
, aspect
);
3781 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3782 device
->isl_dev
.ss
.clear_color_state_size
:
3783 device
->isl_dev
.ss
.clear_value_size
;
3784 return anv_address_add(addr
, clear_color_state_size
);
3787 static inline struct anv_address
3788 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3789 const struct anv_image
*image
,
3790 VkImageAspectFlagBits aspect
,
3791 uint32_t level
, uint32_t array_layer
)
3793 assert(level
< anv_image_aux_levels(image
, aspect
));
3794 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3795 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3796 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3798 struct anv_address addr
=
3799 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3800 addr
.offset
+= 4; /* Go past the fast clear type */
3802 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3803 for (uint32_t l
= 0; l
< level
; l
++)
3804 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3806 addr
.offset
+= level
* image
->array_size
* 4;
3808 addr
.offset
+= array_layer
* 4;
3810 assert(addr
.offset
<
3811 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3815 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3817 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3818 const struct anv_image
*image
)
3820 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3823 /* For Gen8-11, there are some restrictions around sampling from HiZ.
3824 * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
3827 * "If this field is set to AUX_HIZ, Number of Multisamples must
3828 * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
3830 if (image
->type
== VK_IMAGE_TYPE_3D
)
3833 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3834 * struct. There's documentation which suggests that this feature actually
3835 * reduces performance on BDW, but it has only been observed to help so
3836 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3837 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3839 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3842 return image
->samples
== 1;
3846 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3847 const struct anv_image
*image
,
3850 return device
->info
.has_aux_map
&&
3851 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3855 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3856 const struct anv_image
*image
,
3857 VkImageAspectFlagBits aspect
,
3858 enum isl_aux_usage aux_usage
,
3860 uint32_t base_layer
,
3861 uint32_t layer_count
);
3864 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3865 const struct anv_image
*image
,
3866 VkImageAspectFlagBits aspect
,
3867 enum isl_aux_usage aux_usage
,
3868 enum isl_format format
, struct isl_swizzle swizzle
,
3869 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3870 VkRect2D area
, union isl_color_value clear_color
);
3872 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3873 const struct anv_image
*image
,
3874 VkImageAspectFlags aspects
,
3875 enum isl_aux_usage depth_aux_usage
,
3877 uint32_t base_layer
, uint32_t layer_count
,
3879 float depth_value
, uint8_t stencil_value
);
3881 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3882 const struct anv_image
*src_image
,
3883 enum isl_aux_usage src_aux_usage
,
3884 uint32_t src_level
, uint32_t src_base_layer
,
3885 const struct anv_image
*dst_image
,
3886 enum isl_aux_usage dst_aux_usage
,
3887 uint32_t dst_level
, uint32_t dst_base_layer
,
3888 VkImageAspectFlagBits aspect
,
3889 uint32_t src_x
, uint32_t src_y
,
3890 uint32_t dst_x
, uint32_t dst_y
,
3891 uint32_t width
, uint32_t height
,
3892 uint32_t layer_count
,
3893 enum blorp_filter filter
);
3895 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3896 const struct anv_image
*image
,
3897 VkImageAspectFlagBits aspect
, uint32_t level
,
3898 uint32_t base_layer
, uint32_t layer_count
,
3899 enum isl_aux_op hiz_op
);
3901 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3902 const struct anv_image
*image
,
3903 VkImageAspectFlags aspects
,
3905 uint32_t base_layer
, uint32_t layer_count
,
3906 VkRect2D area
, uint8_t stencil_value
);
3908 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3909 const struct anv_image
*image
,
3910 enum isl_format format
, struct isl_swizzle swizzle
,
3911 VkImageAspectFlagBits aspect
,
3912 uint32_t base_layer
, uint32_t layer_count
,
3913 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3916 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3917 const struct anv_image
*image
,
3918 enum isl_format format
, struct isl_swizzle swizzle
,
3919 VkImageAspectFlagBits aspect
, uint32_t level
,
3920 uint32_t base_layer
, uint32_t layer_count
,
3921 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3925 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3926 const struct anv_image
*image
,
3927 VkImageAspectFlagBits aspect
,
3928 uint32_t base_level
, uint32_t level_count
,
3929 uint32_t base_layer
, uint32_t layer_count
);
3932 anv_layout_to_aux_state(const struct gen_device_info
* const devinfo
,
3933 const struct anv_image
*image
,
3934 const VkImageAspectFlagBits aspect
,
3935 const VkImageLayout layout
);
3938 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3939 const struct anv_image
*image
,
3940 const VkImageAspectFlagBits aspect
,
3941 const VkImageUsageFlagBits usage
,
3942 const VkImageLayout layout
);
3944 enum anv_fast_clear_type
3945 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3946 const struct anv_image
* const image
,
3947 const VkImageAspectFlagBits aspect
,
3948 const VkImageLayout layout
);
3950 /* This is defined as a macro so that it works for both
3951 * VkImageSubresourceRange and VkImageSubresourceLayers
3953 #define anv_get_layerCount(_image, _range) \
3954 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3955 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3957 static inline uint32_t
3958 anv_get_levelCount(const struct anv_image
*image
,
3959 const VkImageSubresourceRange
*range
)
3961 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3962 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3965 static inline VkImageAspectFlags
3966 anv_image_expand_aspects(const struct anv_image
*image
,
3967 VkImageAspectFlags aspects
)
3969 /* If the underlying image has color plane aspects and
3970 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3971 * the underlying image. */
3972 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3973 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3974 return image
->aspects
;
3980 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3981 VkImageAspectFlags aspects2
)
3983 if (aspects1
== aspects2
)
3986 /* Only 1 color aspects are compatibles. */
3987 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3988 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3989 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3995 struct anv_image_view
{
3996 struct vk_object_base base
;
3998 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
4000 VkImageAspectFlags aspect_mask
;
4002 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
4006 uint32_t image_plane
;
4008 struct isl_view isl
;
4011 * RENDER_SURFACE_STATE when using image as a sampler surface with an
4012 * image layout of SHADER_READ_ONLY_OPTIMAL or
4013 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
4015 struct anv_surface_state optimal_sampler_surface_state
;
4018 * RENDER_SURFACE_STATE when using image as a sampler surface with an
4019 * image layout of GENERAL.
4021 struct anv_surface_state general_sampler_surface_state
;
4024 * RENDER_SURFACE_STATE when using image as a storage image. Separate
4025 * states for write-only and readable, using the real format for
4026 * write-only and the lowered format for readable.
4028 struct anv_surface_state storage_surface_state
;
4029 struct anv_surface_state writeonly_storage_surface_state
;
4031 struct brw_image_param storage_image_param
;
4035 enum anv_image_view_state_flags
{
4036 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
4037 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
4040 void anv_image_fill_surface_state(struct anv_device
*device
,
4041 const struct anv_image
*image
,
4042 VkImageAspectFlagBits aspect
,
4043 const struct isl_view
*view
,
4044 isl_surf_usage_flags_t view_usage
,
4045 enum isl_aux_usage aux_usage
,
4046 const union isl_color_value
*clear_color
,
4047 enum anv_image_view_state_flags flags
,
4048 struct anv_surface_state
*state_inout
,
4049 struct brw_image_param
*image_param_out
);
4051 struct anv_image_create_info
{
4052 const VkImageCreateInfo
*vk_info
;
4054 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
4055 isl_tiling_flags_t isl_tiling_flags
;
4057 /** These flags will be added to any derived from VkImageCreateInfo. */
4058 isl_surf_usage_flags_t isl_extra_usage_flags
;
4061 bool external_format
;
4064 VkResult
anv_image_create(VkDevice _device
,
4065 const struct anv_image_create_info
*info
,
4066 const VkAllocationCallbacks
* alloc
,
4070 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
4072 static inline VkExtent3D
4073 anv_sanitize_image_extent(const VkImageType imageType
,
4074 const VkExtent3D imageExtent
)
4076 switch (imageType
) {
4077 case VK_IMAGE_TYPE_1D
:
4078 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
4079 case VK_IMAGE_TYPE_2D
:
4080 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
4081 case VK_IMAGE_TYPE_3D
:
4084 unreachable("invalid image type");
4088 static inline VkOffset3D
4089 anv_sanitize_image_offset(const VkImageType imageType
,
4090 const VkOffset3D imageOffset
)
4092 switch (imageType
) {
4093 case VK_IMAGE_TYPE_1D
:
4094 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
4095 case VK_IMAGE_TYPE_2D
:
4096 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
4097 case VK_IMAGE_TYPE_3D
:
4100 unreachable("invalid image type");
4104 VkFormatFeatureFlags
4105 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
4107 const struct anv_format
*anv_format
,
4108 VkImageTiling vk_tiling
);
4110 void anv_fill_buffer_surface_state(struct anv_device
*device
,
4111 struct anv_state state
,
4112 enum isl_format format
,
4113 struct anv_address address
,
4114 uint32_t range
, uint32_t stride
);
4117 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
4118 const struct anv_attachment_state
*att_state
,
4119 const struct anv_image_view
*iview
)
4121 const struct isl_format_layout
*view_fmtl
=
4122 isl_format_get_layout(iview
->planes
[0].isl
.format
);
4124 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
4125 if (view_fmtl->channels.c.bits) \
4126 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
4128 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
4129 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
4130 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
4131 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
4133 #undef COPY_CLEAR_COLOR_CHANNEL
4137 /* Haswell border color is a bit of a disaster. Float and unorm formats use a
4138 * straightforward 32-bit float color in the first 64 bytes. Instead of using
4139 * a nice float/integer union like Gen8+, Haswell specifies the integer border
4140 * color as a separate entry /after/ the float color. The layout of this entry
4141 * also depends on the format's bpp (with extra hacks for RG32), and overlaps.
4143 * Since we don't know the format/bpp, we can't make any of the border colors
4144 * containing '1' work for all formats, as it would be in the wrong place for
4145 * some of them. We opt to make 32-bit integers work as this seems like the
4146 * most common option. Fortunately, transparent black works regardless, as
4147 * all zeroes is the same in every bit-size.
4149 struct hsw_border_color
{
4153 uint32_t _pad1
[108];
4156 struct gen8_border_color
{
4161 /* Pad out to 64 bytes */
4165 struct anv_ycbcr_conversion
{
4166 struct vk_object_base base
;
4168 const struct anv_format
* format
;
4169 VkSamplerYcbcrModelConversion ycbcr_model
;
4170 VkSamplerYcbcrRange ycbcr_range
;
4171 VkComponentSwizzle mapping
[4];
4172 VkChromaLocation chroma_offsets
[2];
4173 VkFilter chroma_filter
;
4174 bool chroma_reconstruction
;
4177 struct anv_sampler
{
4178 struct vk_object_base base
;
4180 uint32_t state
[3][4];
4182 struct anv_ycbcr_conversion
*conversion
;
4184 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
4185 * and with a 32-byte stride for use as bindless samplers.
4187 struct anv_state bindless_state
;
4189 struct anv_state custom_border_color
;
4192 struct anv_framebuffer
{
4193 struct vk_object_base base
;
4199 uint32_t attachment_count
;
4200 struct anv_image_view
* attachments
[0];
4203 struct anv_subpass_attachment
{
4204 VkImageUsageFlagBits usage
;
4205 uint32_t attachment
;
4206 VkImageLayout layout
;
4208 /* Used only with attachment containing stencil data. */
4209 VkImageLayout stencil_layout
;
4212 struct anv_subpass
{
4213 uint32_t attachment_count
;
4216 * A pointer to all attachment references used in this subpass.
4217 * Only valid if ::attachment_count > 0.
4219 struct anv_subpass_attachment
* attachments
;
4220 uint32_t input_count
;
4221 struct anv_subpass_attachment
* input_attachments
;
4222 uint32_t color_count
;
4223 struct anv_subpass_attachment
* color_attachments
;
4224 struct anv_subpass_attachment
* resolve_attachments
;
4226 struct anv_subpass_attachment
* depth_stencil_attachment
;
4227 struct anv_subpass_attachment
* ds_resolve_attachment
;
4228 VkResolveModeFlagBitsKHR depth_resolve_mode
;
4229 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
4233 /** Subpass has a depth/stencil self-dependency */
4234 bool has_ds_self_dep
;
4236 /** Subpass has at least one color resolve attachment */
4237 bool has_color_resolve
;
4240 static inline unsigned
4241 anv_subpass_view_count(const struct anv_subpass
*subpass
)
4243 return MAX2(1, util_bitcount(subpass
->view_mask
));
4246 struct anv_render_pass_attachment
{
4247 /* TODO: Consider using VkAttachmentDescription instead of storing each of
4248 * its members individually.
4252 VkImageUsageFlags usage
;
4253 VkAttachmentLoadOp load_op
;
4254 VkAttachmentStoreOp store_op
;
4255 VkAttachmentLoadOp stencil_load_op
;
4256 VkImageLayout initial_layout
;
4257 VkImageLayout final_layout
;
4258 VkImageLayout first_subpass_layout
;
4260 VkImageLayout stencil_initial_layout
;
4261 VkImageLayout stencil_final_layout
;
4263 /* The subpass id in which the attachment will be used last. */
4264 uint32_t last_subpass_idx
;
4267 struct anv_render_pass
{
4268 struct vk_object_base base
;
4270 uint32_t attachment_count
;
4271 uint32_t subpass_count
;
4272 /* An array of subpass_count+1 flushes, one per subpass boundary */
4273 enum anv_pipe_bits
* subpass_flushes
;
4274 struct anv_render_pass_attachment
* attachments
;
4275 struct anv_subpass subpasses
[0];
4278 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
4280 #define OA_SNAPSHOT_SIZE (256)
4281 #define ANV_KHR_PERF_QUERY_SIZE (ALIGN(sizeof(uint64_t), 64) + 2 * OA_SNAPSHOT_SIZE)
4283 struct anv_query_pool
{
4284 struct vk_object_base base
;
4287 VkQueryPipelineStatisticFlags pipeline_statistics
;
4288 /** Stride between slots, in bytes */
4290 /** Number of slots in this query pool */
4294 /* Perf queries : */
4295 struct anv_bo reset_bo
;
4296 uint32_t n_counters
;
4297 struct gen_perf_counter_pass
*counter_pass
;
4299 struct gen_perf_query_info
**pass_query
;
4302 static inline uint32_t khr_perf_query_preamble_offset(struct anv_query_pool
*pool
,
4305 return pass
* ANV_KHR_PERF_QUERY_SIZE
+ 8;
4308 int anv_get_instance_entrypoint_index(const char *name
);
4309 int anv_get_device_entrypoint_index(const char *name
);
4310 int anv_get_physical_device_entrypoint_index(const char *name
);
4312 const char *anv_get_instance_entry_name(int index
);
4313 const char *anv_get_physical_device_entry_name(int index
);
4314 const char *anv_get_device_entry_name(int index
);
4317 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
4318 const struct anv_instance_extension_table
*instance
);
4320 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4321 const struct anv_instance_extension_table
*instance
);
4323 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4324 const struct anv_instance_extension_table
*instance
,
4325 const struct anv_device_extension_table
*device
);
4327 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
4330 void anv_dump_image_to_ppm(struct anv_device
*device
,
4331 struct anv_image
*image
, unsigned miplevel
,
4332 unsigned array_layer
, VkImageAspectFlagBits aspect
,
4333 const char *filename
);
4335 enum anv_dump_action
{
4336 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
4339 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
4340 void anv_dump_finish(void);
4342 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
4344 static inline uint32_t
4345 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
4347 /* This function must be called from within a subpass. */
4348 assert(cmd_state
->pass
&& cmd_state
->subpass
);
4350 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
4352 /* The id of this subpass shouldn't exceed the number of subpasses in this
4353 * render pass minus 1.
4355 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
4359 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
4360 void anv_device_perf_init(struct anv_device
*device
);
4361 void anv_perf_write_pass_results(struct gen_perf_config
*perf
,
4362 struct anv_query_pool
*pool
, uint32_t pass
,
4363 const struct gen_perf_query_result
*accumulated_results
,
4364 union VkPerformanceCounterResultKHR
*results
);
4366 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4367 VK_FROM_HANDLE(__anv_type, __name, __handle)
4369 VK_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, base
, VkCommandBuffer
,
4370 VK_OBJECT_TYPE_COMMAND_BUFFER
)
4371 VK_DEFINE_HANDLE_CASTS(anv_device
, vk
.base
, VkDevice
, VK_OBJECT_TYPE_DEVICE
)
4372 VK_DEFINE_HANDLE_CASTS(anv_instance
, base
, VkInstance
, VK_OBJECT_TYPE_INSTANCE
)
4373 VK_DEFINE_HANDLE_CASTS(anv_physical_device
, base
, VkPhysicalDevice
,
4374 VK_OBJECT_TYPE_PHYSICAL_DEVICE
)
4375 VK_DEFINE_HANDLE_CASTS(anv_queue
, base
, VkQueue
, VK_OBJECT_TYPE_QUEUE
)
4377 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, base
, VkCommandPool
,
4378 VK_OBJECT_TYPE_COMMAND_POOL
)
4379 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, base
, VkBuffer
,
4380 VK_OBJECT_TYPE_BUFFER
)
4381 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, base
, VkBufferView
,
4382 VK_OBJECT_TYPE_BUFFER_VIEW
)
4383 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, base
, VkDescriptorPool
,
4384 VK_OBJECT_TYPE_DESCRIPTOR_POOL
)
4385 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, base
, VkDescriptorSet
,
4386 VK_OBJECT_TYPE_DESCRIPTOR_SET
)
4387 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, base
,
4388 VkDescriptorSetLayout
,
4389 VK_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT
)
4390 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, base
,
4391 VkDescriptorUpdateTemplate
,
4392 VK_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE
)
4393 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, base
, VkDeviceMemory
,
4394 VK_OBJECT_TYPE_DEVICE_MEMORY
)
4395 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, base
, VkFence
, VK_OBJECT_TYPE_FENCE
)
4396 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, base
, VkEvent
, VK_OBJECT_TYPE_EVENT
)
4397 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, base
, VkFramebuffer
,
4398 VK_OBJECT_TYPE_FRAMEBUFFER
)
4399 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, base
, VkImage
, VK_OBJECT_TYPE_IMAGE
)
4400 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, base
, VkImageView
,
4401 VK_OBJECT_TYPE_IMAGE_VIEW
);
4402 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, base
, VkPipelineCache
,
4403 VK_OBJECT_TYPE_PIPELINE_CACHE
)
4404 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, base
, VkPipeline
,
4405 VK_OBJECT_TYPE_PIPELINE
)
4406 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, base
, VkPipelineLayout
,
4407 VK_OBJECT_TYPE_PIPELINE_LAYOUT
)
4408 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, base
, VkQueryPool
,
4409 VK_OBJECT_TYPE_QUERY_POOL
)
4410 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, base
, VkRenderPass
,
4411 VK_OBJECT_TYPE_RENDER_PASS
)
4412 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, base
, VkSampler
,
4413 VK_OBJECT_TYPE_SAMPLER
)
4414 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, base
, VkSemaphore
,
4415 VK_OBJECT_TYPE_SEMAPHORE
)
4416 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, base
, VkShaderModule
,
4417 VK_OBJECT_TYPE_SHADER_MODULE
)
4418 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, base
,
4419 VkSamplerYcbcrConversion
,
4420 VK_OBJECT_TYPE_SAMPLER_YCBCR_CONVERSION
)
4422 /* Gen-specific function declarations */
4424 # include "anv_genX.h"
4426 # define genX(x) gen7_##x
4427 # include "anv_genX.h"
4429 # define genX(x) gen75_##x
4430 # include "anv_genX.h"
4432 # define genX(x) gen8_##x
4433 # include "anv_genX.h"
4435 # define genX(x) gen9_##x
4436 # include "anv_genX.h"
4438 # define genX(x) gen10_##x
4439 # include "anv_genX.h"
4441 # define genX(x) gen11_##x
4442 # include "anv_genX.h"
4444 # define genX(x) gen12_##x
4445 # include "anv_genX.h"
4449 #endif /* ANV_PRIVATE_H */