2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
38 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #include "brw_device_info.h"
44 #include "brw_compiler.h"
45 #include "util/macros.h"
46 #include "util/list.h"
48 /* Pre-declarations needed for WSI entrypoints */
51 typedef struct xcb_connection_t xcb_connection_t
;
52 typedef uint32_t xcb_visualid_t
;
53 typedef uint32_t xcb_window_t
;
57 #include <vulkan/vulkan.h>
58 #include <vulkan/vulkan_intel.h>
59 #include <vulkan/vk_icd.h>
61 #include "anv_entrypoints.h"
62 #include "brw_context.h"
72 #define MAX_VIEWPORTS 16
73 #define MAX_SCISSORS 16
74 #define MAX_PUSH_CONSTANTS_SIZE 128
75 #define MAX_DYNAMIC_BUFFERS 16
77 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
79 #define anv_noreturn __attribute__((__noreturn__))
80 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
82 #define MIN(a, b) ((a) < (b) ? (a) : (b))
83 #define MAX(a, b) ((a) > (b) ? (a) : (b))
85 static inline uint32_t
86 align_u32(uint32_t v
, uint32_t a
)
88 assert(a
!= 0 && a
== (a
& -a
));
89 return (v
+ a
- 1) & ~(a
- 1);
92 static inline uint64_t
93 align_u64(uint64_t v
, uint64_t a
)
95 assert(a
!= 0 && a
== (a
& -a
));
96 return (v
+ a
- 1) & ~(a
- 1);
100 align_i32(int32_t v
, int32_t a
)
102 assert(a
!= 0 && a
== (a
& -a
));
103 return (v
+ a
- 1) & ~(a
- 1);
106 /** Alignment must be a power of 2. */
108 anv_is_aligned(uintmax_t n
, uintmax_t a
)
110 assert(a
== (a
& -a
));
111 return (n
& (a
- 1)) == 0;
114 static inline uint32_t
115 anv_minify(uint32_t n
, uint32_t levels
)
117 if (unlikely(n
== 0))
120 return MAX(n
>> levels
, 1);
124 anv_clamp_f(float f
, float min
, float max
)
137 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
139 if (*inout_mask
& clear_mask
) {
140 *inout_mask
&= ~clear_mask
;
147 #define for_each_bit(b, dword) \
148 for (uint32_t __dword = (dword); \
149 (b) = __builtin_ffs(__dword) - 1, __dword; \
150 __dword &= ~(1 << (b)))
152 #define typed_memcpy(dest, src, count) ({ \
153 static_assert(sizeof(*src) == sizeof(*dest), ""); \
154 memcpy((dest), (src), (count) * sizeof(*(src))); \
157 #define zero(x) (memset(&(x), 0, sizeof(x)))
159 /* Define no kernel as 1, since that's an illegal offset for a kernel */
163 VkStructureType sType
;
167 /* Whenever we generate an error, pass it through this function. Useful for
168 * debugging, where we can break on it. Only call at error site, not when
169 * propagating errors. Might be useful to plug in a stack trace here.
172 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
175 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
176 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
178 #define vk_error(error) error
179 #define vk_errorf(error, format, ...) error
182 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
183 anv_printflike(3, 4);
184 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
185 void anv_loge_v(const char *format
, va_list va
);
188 * Print a FINISHME message, including its source location.
190 #define anv_finishme(format, ...) \
191 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
193 /* A non-fatal assert. Useful for debugging. */
195 #define anv_assert(x) ({ \
196 if (unlikely(!(x))) \
197 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
200 #define anv_assert(x)
204 * If a block of code is annotated with anv_validate, then the block runs only
208 #define anv_validate if (1)
210 #define anv_validate if (0)
213 void anv_abortf(const char *format
, ...) anv_noreturn
anv_printflike(1, 2);
214 void anv_abortfv(const char *format
, va_list va
) anv_noreturn
;
216 #define stub_return(v) \
218 anv_finishme("stub %s", __func__); \
224 anv_finishme("stub %s", __func__); \
229 * A dynamically growable, circular buffer. Elements are added at head and
230 * removed from tail. head and tail are free-running uint32_t indices and we
231 * only compute the modulo with size when accessing the array. This way,
232 * number of bytes in the queue is always head - tail, even in case of
239 uint32_t element_size
;
244 int anv_vector_init(struct anv_vector
*queue
, uint32_t element_size
, uint32_t size
);
245 void *anv_vector_add(struct anv_vector
*queue
);
246 void *anv_vector_remove(struct anv_vector
*queue
);
249 anv_vector_length(struct anv_vector
*queue
)
251 return (queue
->head
- queue
->tail
) / queue
->element_size
;
255 anv_vector_head(struct anv_vector
*vector
)
257 assert(vector
->tail
< vector
->head
);
258 return (void *)((char *)vector
->data
+
259 ((vector
->head
- vector
->element_size
) &
260 (vector
->size
- 1)));
264 anv_vector_tail(struct anv_vector
*vector
)
266 return (void *)((char *)vector
->data
+ (vector
->tail
& (vector
->size
- 1)));
270 anv_vector_finish(struct anv_vector
*queue
)
275 #define anv_vector_foreach(elem, queue) \
276 static_assert(__builtin_types_compatible_p(__typeof__(queue), struct anv_vector *), ""); \
277 for (uint32_t __anv_vector_offset = (queue)->tail; \
278 elem = (queue)->data + (__anv_vector_offset & ((queue)->size - 1)), __anv_vector_offset < (queue)->head; \
279 __anv_vector_offset += (queue)->element_size)
284 /* Index into the current validation list. This is used by the
285 * validation list building alrogithm to track which buffers are already
286 * in the validation list so that we can ensure uniqueness.
290 /* Last known offset. This value is provided by the kernel when we
291 * execbuf and is used as the presumed offset for the next bunch of
299 /* We need to set the WRITE flag on winsys bos so GEM will know we're
300 * writing to them and synchronize uses on other rings (eg if the display
301 * server uses the blitter ring).
306 /* Represents a lock-free linked list of "free" things. This is used by
307 * both the block pool and the state pools. Unfortunately, in order to
308 * solve the ABA problem, we can't use a single uint32_t head.
310 union anv_free_list
{
314 /* A simple count that is incremented every time the head changes. */
320 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
322 struct anv_block_state
{
332 struct anv_block_pool
{
333 struct anv_device
*device
;
337 /* The offset from the start of the bo to the "center" of the block
338 * pool. Pointers to allocated blocks are given by
339 * bo.map + center_bo_offset + offsets.
341 uint32_t center_bo_offset
;
343 /* Current memory map of the block pool. This pointer may or may not
344 * point to the actual beginning of the block pool memory. If
345 * anv_block_pool_alloc_back has ever been called, then this pointer
346 * will point to the "center" position of the buffer and all offsets
347 * (negative or positive) given out by the block pool alloc functions
348 * will be valid relative to this pointer.
350 * In particular, map == bo.map + center_offset
356 * Array of mmaps and gem handles owned by the block pool, reclaimed when
357 * the block pool is destroyed.
359 struct anv_vector mmap_cleanups
;
363 union anv_free_list free_list
;
364 struct anv_block_state state
;
366 union anv_free_list back_free_list
;
367 struct anv_block_state back_state
;
370 /* Block pools are backed by a fixed-size 2GB memfd */
371 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
373 /* The center of the block pool is also the middle of the memfd. This may
374 * change in the future if we decide differently for some reason.
376 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
378 static inline uint32_t
379 anv_block_pool_size(struct anv_block_pool
*pool
)
381 return pool
->state
.end
+ pool
->back_state
.end
;
390 struct anv_fixed_size_state_pool
{
392 union anv_free_list free_list
;
393 struct anv_block_state block
;
396 #define ANV_MIN_STATE_SIZE_LOG2 6
397 #define ANV_MAX_STATE_SIZE_LOG2 10
399 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2)
401 struct anv_state_pool
{
402 struct anv_block_pool
*block_pool
;
403 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
406 struct anv_state_stream_block
;
408 struct anv_state_stream
{
409 struct anv_block_pool
*block_pool
;
411 /* The current working block */
412 struct anv_state_stream_block
*block
;
414 /* Offset at which the current block starts */
416 /* Offset at which to allocate the next state */
418 /* Offset at which the current block ends */
422 #define CACHELINE_SIZE 64
423 #define CACHELINE_MASK 63
426 anv_clflush_range(void *start
, size_t size
)
428 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
429 void *end
= start
+ size
;
431 __builtin_ia32_mfence();
433 __builtin_ia32_clflush(p
);
439 anv_state_clflush(struct anv_state state
)
441 anv_clflush_range(state
.map
, state
.alloc_size
);
444 void anv_block_pool_init(struct anv_block_pool
*pool
,
445 struct anv_device
*device
, uint32_t block_size
);
446 void anv_block_pool_finish(struct anv_block_pool
*pool
);
447 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
);
448 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
);
449 void anv_block_pool_free(struct anv_block_pool
*pool
, int32_t offset
);
450 void anv_state_pool_init(struct anv_state_pool
*pool
,
451 struct anv_block_pool
*block_pool
);
452 void anv_state_pool_finish(struct anv_state_pool
*pool
);
453 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
454 size_t state_size
, size_t alignment
);
455 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
456 void anv_state_stream_init(struct anv_state_stream
*stream
,
457 struct anv_block_pool
*block_pool
);
458 void anv_state_stream_finish(struct anv_state_stream
*stream
);
459 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
460 uint32_t size
, uint32_t alignment
);
463 * Implements a pool of re-usable BOs. The interface is identical to that
464 * of block_pool except that each block is its own BO.
467 struct anv_device
*device
;
472 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
473 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
474 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
476 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
478 struct anv_scratch_pool
{
479 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
480 struct anv_bo bos
[16][MESA_SHADER_STAGES
];
483 void anv_scratch_pool_init(struct anv_device
*device
,
484 struct anv_scratch_pool
*pool
);
485 void anv_scratch_pool_finish(struct anv_device
*device
,
486 struct anv_scratch_pool
*pool
);
487 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
488 struct anv_scratch_pool
*pool
,
489 gl_shader_stage stage
,
490 unsigned per_thread_scratch
);
492 void *anv_resolve_entrypoint(uint32_t index
);
494 extern struct anv_dispatch_table dtable
;
496 #define ANV_CALL(func) ({ \
497 if (dtable.func == NULL) { \
498 size_t idx = offsetof(struct anv_dispatch_table, func) / sizeof(void *); \
499 dtable.entrypoints[idx] = anv_resolve_entrypoint(idx); \
505 anv_alloc(const VkAllocationCallbacks
*alloc
,
506 size_t size
, size_t align
,
507 VkSystemAllocationScope scope
)
509 return alloc
->pfnAllocation(alloc
->pUserData
, size
, align
, scope
);
513 anv_realloc(const VkAllocationCallbacks
*alloc
,
514 void *ptr
, size_t size
, size_t align
,
515 VkSystemAllocationScope scope
)
517 return alloc
->pfnReallocation(alloc
->pUserData
, ptr
, size
, align
, scope
);
521 anv_free(const VkAllocationCallbacks
*alloc
, void *data
)
523 alloc
->pfnFree(alloc
->pUserData
, data
);
527 anv_alloc2(const VkAllocationCallbacks
*parent_alloc
,
528 const VkAllocationCallbacks
*alloc
,
529 size_t size
, size_t align
,
530 VkSystemAllocationScope scope
)
533 return anv_alloc(alloc
, size
, align
, scope
);
535 return anv_alloc(parent_alloc
, size
, align
, scope
);
539 anv_free2(const VkAllocationCallbacks
*parent_alloc
,
540 const VkAllocationCallbacks
*alloc
,
544 anv_free(alloc
, data
);
546 anv_free(parent_alloc
, data
);
549 struct anv_wsi_interaface
;
551 #define VK_ICD_WSI_PLATFORM_MAX 5
553 struct anv_physical_device
{
554 VK_LOADER_DATA _loader_data
;
556 struct anv_instance
* instance
;
560 const struct brw_device_info
* info
;
561 uint64_t aperture_size
;
562 struct brw_compiler
* compiler
;
563 struct isl_device isl_dev
;
564 int cmd_parser_version
;
566 struct anv_wsi_interface
* wsi
[VK_ICD_WSI_PLATFORM_MAX
];
569 struct anv_instance
{
570 VK_LOADER_DATA _loader_data
;
572 VkAllocationCallbacks alloc
;
575 int physicalDeviceCount
;
576 struct anv_physical_device physicalDevice
;
579 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
580 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
582 struct anv_meta_state
{
583 VkAllocationCallbacks alloc
;
586 * Use array element `i` for images with `2^i` samples.
590 * Pipeline N is used to clear color attachment N of the current
593 * HACK: We use one pipeline per color attachment to work around the
594 * compiler's inability to dynamically set the render target index of
595 * the render target write message.
597 struct anv_pipeline
*color_pipelines
[MAX_RTS
];
599 struct anv_pipeline
*depth_only_pipeline
;
600 struct anv_pipeline
*stencil_only_pipeline
;
601 struct anv_pipeline
*depthstencil_pipeline
;
602 } clear
[1 + MAX_SAMPLES_LOG2
];
605 VkRenderPass render_pass
;
607 /** Pipeline that blits from a 1D image. */
608 VkPipeline pipeline_1d_src
;
610 /** Pipeline that blits from a 2D image. */
611 VkPipeline pipeline_2d_src
;
613 /** Pipeline that blits from a 3D image. */
614 VkPipeline pipeline_3d_src
;
616 VkPipelineLayout pipeline_layout
;
617 VkDescriptorSetLayout ds_layout
;
621 VkRenderPass render_pass
;
623 VkPipelineLayout img_p_layout
;
624 VkDescriptorSetLayout img_ds_layout
;
625 VkPipelineLayout buf_p_layout
;
626 VkDescriptorSetLayout buf_ds_layout
;
628 /* Pipelines indexed by source and destination type. See the
629 * blit2d_src_type and blit2d_dst_type enums in anv_meta_blit2d.c to
630 * see what these mean.
632 VkPipeline pipelines
[2][3];
636 /** Pipeline [i] resolves an image with 2^(i+1) samples. */
637 VkPipeline pipelines
[MAX_SAMPLES_LOG2
];
640 VkPipelineLayout pipeline_layout
;
641 VkDescriptorSetLayout ds_layout
;
646 VK_LOADER_DATA _loader_data
;
648 struct anv_device
* device
;
650 struct anv_state_pool
* pool
;
653 struct anv_pipeline_cache
{
654 struct anv_device
* device
;
655 struct anv_state_stream program_stream
;
656 pthread_mutex_t mutex
;
660 uint32_t kernel_count
;
661 uint32_t * hash_table
;
664 struct anv_pipeline_bind_map
;
666 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
667 struct anv_device
*device
);
668 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
669 uint32_t anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
670 const unsigned char *sha1
,
671 const struct brw_stage_prog_data
**prog_data
,
672 struct anv_pipeline_bind_map
*map
);
673 uint32_t anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
674 const unsigned char *sha1
,
677 const struct brw_stage_prog_data
**prog_data
,
678 size_t prog_data_size
,
679 struct anv_pipeline_bind_map
*map
);
682 VK_LOADER_DATA _loader_data
;
684 VkAllocationCallbacks alloc
;
686 struct anv_instance
* instance
;
688 struct brw_device_info info
;
689 struct isl_device isl_dev
;
692 bool can_chain_batches
;
693 bool robust_buffer_access
;
695 struct anv_bo_pool batch_bo_pool
;
697 struct anv_block_pool dynamic_state_block_pool
;
698 struct anv_state_pool dynamic_state_pool
;
700 struct anv_block_pool instruction_block_pool
;
701 struct anv_pipeline_cache default_pipeline_cache
;
703 struct anv_block_pool surface_state_block_pool
;
704 struct anv_state_pool surface_state_pool
;
706 struct anv_bo workaround_bo
;
708 struct anv_meta_state meta_state
;
710 struct anv_state border_colors
;
712 struct anv_queue queue
;
714 struct anv_scratch_pool scratch_pool
;
716 uint32_t default_mocs
;
718 pthread_mutex_t mutex
;
721 void anv_device_get_cache_uuid(void *uuid
);
724 void* anv_gem_mmap(struct anv_device
*device
,
725 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
726 void anv_gem_munmap(void *p
, uint64_t size
);
727 uint32_t anv_gem_create(struct anv_device
*device
, size_t size
);
728 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
729 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
730 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
731 int anv_gem_execbuffer(struct anv_device
*device
,
732 struct drm_i915_gem_execbuffer2
*execbuf
);
733 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
734 uint32_t stride
, uint32_t tiling
);
735 int anv_gem_create_context(struct anv_device
*device
);
736 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
737 int anv_gem_get_param(int fd
, uint32_t param
);
738 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
739 int anv_gem_get_aperture(int fd
, uint64_t *size
);
740 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
741 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
742 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
743 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
744 uint32_t read_domains
, uint32_t write_domain
);
746 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
748 struct anv_reloc_list
{
751 struct drm_i915_gem_relocation_entry
* relocs
;
752 struct anv_bo
** reloc_bos
;
755 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
756 const VkAllocationCallbacks
*alloc
);
757 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
758 const VkAllocationCallbacks
*alloc
);
760 uint64_t anv_reloc_list_add(struct anv_reloc_list
*list
,
761 const VkAllocationCallbacks
*alloc
,
762 uint32_t offset
, struct anv_bo
*target_bo
,
765 struct anv_batch_bo
{
766 /* Link in the anv_cmd_buffer.owned_batch_bos list */
767 struct list_head link
;
771 /* Bytes actually consumed in this batch BO */
774 /* Last seen surface state block pool bo offset */
775 uint32_t last_ss_pool_bo_offset
;
777 struct anv_reloc_list relocs
;
781 const VkAllocationCallbacks
* alloc
;
787 struct anv_reloc_list
* relocs
;
789 /* This callback is called (with the associated user data) in the event
790 * that the batch runs out of space.
792 VkResult (*extend_cb
)(struct anv_batch
*, void *);
796 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
797 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
798 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
799 void *location
, struct anv_bo
*bo
, uint32_t offset
);
800 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
801 struct anv_batch
*batch
);
808 #define __gen_address_type struct anv_address
809 #define __gen_user_data struct anv_batch
811 static inline uint64_t
812 __gen_combine_address(struct anv_batch
*batch
, void *location
,
813 const struct anv_address address
, uint32_t delta
)
815 if (address
.bo
== NULL
) {
816 return address
.offset
+ delta
;
818 assert(batch
->start
<= location
&& location
< batch
->end
);
820 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
824 /* Wrapper macros needed to work around preprocessor argument issues. In
825 * particular, arguments don't get pre-evaluated if they are concatenated.
826 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
827 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
828 * We can work around this easily enough with these helpers.
830 #define __anv_cmd_length(cmd) cmd ## _length
831 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
832 #define __anv_cmd_header(cmd) cmd ## _header
833 #define __anv_cmd_pack(cmd) cmd ## _pack
834 #define __anv_reg_num(reg) reg ## _num
836 #define anv_pack_struct(dst, struc, ...) do { \
837 struct struc __template = { \
840 __anv_cmd_pack(struc)(NULL, dst, &__template); \
841 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
844 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
845 void *__dst = anv_batch_emit_dwords(batch, n); \
846 struct cmd __template = { \
847 __anv_cmd_header(cmd), \
848 .DWordLength = n - __anv_cmd_length_bias(cmd), \
851 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
855 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
859 static_assert(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1), "mismatch merge"); \
860 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
861 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
862 dw[i] = (dwords0)[i] | (dwords1)[i]; \
863 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
866 #define anv_batch_emit(batch, cmd, name) \
867 for (struct cmd name = { __anv_cmd_header(cmd) }, \
868 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
869 __builtin_expect(_dst != NULL, 1); \
870 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
871 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
875 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
876 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
877 struct anv_state __state = \
878 anv_state_pool_alloc((pool), __size, align); \
879 struct cmd __template = { \
882 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
883 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
884 if (!(pool)->block_pool->device->info.has_llc) \
885 anv_state_clflush(__state); \
889 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
890 .GraphicsDataTypeGFDT = 0, \
891 .LLCCacheabilityControlLLCCC = 0, \
892 .L3CacheabilityControlL3CC = 1, \
895 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
896 .LLCeLLCCacheabilityControlLLCCC = 0, \
897 .L3CacheabilityControlL3CC = 1, \
900 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
901 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
902 .TargetCache = L3DefertoPATforLLCeLLCselection, \
906 /* Skylake: MOCS is now an index into an array of 62 different caching
907 * configurations programmed by the kernel.
910 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
911 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
912 .IndextoMOCSTables = 2 \
915 #define GEN9_MOCS_PTE { \
916 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
917 .IndextoMOCSTables = 1 \
920 struct anv_device_memory
{
923 VkDeviceSize map_size
;
928 * Header for Vertex URB Entry (VUE)
930 struct anv_vue_header
{
932 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
933 uint32_t ViewportIndex
;
937 struct anv_descriptor_set_binding_layout
{
939 /* The type of the descriptors in this binding */
940 VkDescriptorType type
;
943 /* Number of array elements in this binding */
946 /* Index into the flattend descriptor set */
947 uint16_t descriptor_index
;
949 /* Index into the dynamic state array for a dynamic buffer */
950 int16_t dynamic_offset_index
;
952 /* Index into the descriptor set buffer views */
953 int16_t buffer_index
;
956 /* Index into the binding table for the associated surface */
957 int16_t surface_index
;
959 /* Index into the sampler table for the associated sampler */
960 int16_t sampler_index
;
962 /* Index into the image table for the associated image */
964 } stage
[MESA_SHADER_STAGES
];
966 /* Immutable samplers (or NULL if no immutable samplers) */
967 struct anv_sampler
**immutable_samplers
;
970 struct anv_descriptor_set_layout
{
971 /* Number of bindings in this descriptor set */
972 uint16_t binding_count
;
974 /* Total size of the descriptor set with room for all array entries */
977 /* Shader stages affected by this descriptor set */
978 uint16_t shader_stages
;
980 /* Number of buffers in this descriptor set */
981 uint16_t buffer_count
;
983 /* Number of dynamic offsets used by this descriptor set */
984 uint16_t dynamic_offset_count
;
986 /* Bindings in this descriptor set */
987 struct anv_descriptor_set_binding_layout binding
[0];
990 struct anv_descriptor
{
991 VkDescriptorType type
;
995 struct anv_image_view
*image_view
;
996 struct anv_sampler
*sampler
;
999 struct anv_buffer_view
*buffer_view
;
1003 struct anv_descriptor_set
{
1004 const struct anv_descriptor_set_layout
*layout
;
1006 uint32_t buffer_count
;
1007 struct anv_buffer_view
*buffer_views
;
1008 struct anv_descriptor descriptors
[0];
1011 struct anv_descriptor_pool
{
1016 struct anv_state_stream surface_state_stream
;
1017 void *surface_state_free_list
;
1023 anv_descriptor_set_create(struct anv_device
*device
,
1024 struct anv_descriptor_pool
*pool
,
1025 const struct anv_descriptor_set_layout
*layout
,
1026 struct anv_descriptor_set
**out_set
);
1029 anv_descriptor_set_destroy(struct anv_device
*device
,
1030 struct anv_descriptor_pool
*pool
,
1031 struct anv_descriptor_set
*set
);
1033 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1035 struct anv_pipeline_binding
{
1036 /* The descriptor set this surface corresponds to. The special value of
1037 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1038 * to a color attachment and not a regular descriptor.
1042 /* Binding in the descriptor set */
1045 /* Index in the binding */
1049 struct anv_pipeline_layout
{
1051 struct anv_descriptor_set_layout
*layout
;
1052 uint32_t dynamic_offset_start
;
1058 bool has_dynamic_offsets
;
1059 } stage
[MESA_SHADER_STAGES
];
1063 struct anv_device
* device
;
1066 VkBufferUsageFlags usage
;
1068 /* Set when bound */
1070 VkDeviceSize offset
;
1073 enum anv_cmd_dirty_bits
{
1074 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1075 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1076 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1077 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1078 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1079 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1080 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1081 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1082 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1083 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1084 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1085 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1086 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1088 typedef uint32_t anv_cmd_dirty_mask_t
;
1090 enum anv_pipe_bits
{
1091 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1092 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1093 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1094 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1095 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1096 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1097 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1098 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1099 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1100 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1101 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1103 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1104 * a flush has happened but not a CS stall. The next time we do any sort
1105 * of invalidation we need to insert a CS stall at that time. Otherwise,
1106 * we would have to CS stall on every flush which could be bad.
1108 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1111 #define ANV_PIPE_FLUSH_BITS ( \
1112 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1113 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1114 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1116 #define ANV_PIPE_STALL_BITS ( \
1117 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1118 ANV_PIPE_DEPTH_STALL_BIT | \
1119 ANV_PIPE_CS_STALL_BIT)
1121 #define ANV_PIPE_INVALIDATE_BITS ( \
1122 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1123 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1124 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1125 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1126 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1127 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1129 struct anv_vertex_binding
{
1130 struct anv_buffer
* buffer
;
1131 VkDeviceSize offset
;
1134 struct anv_push_constants
{
1135 /* Current allocated size of this push constants data structure.
1136 * Because a decent chunk of it may not be used (images on SKL, for
1137 * instance), we won't actually allocate the entire structure up-front.
1141 /* Push constant data provided by the client through vkPushConstants */
1142 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1144 /* Our hardware only provides zero-based vertex and instance id so, in
1145 * order to satisfy the vulkan requirements, we may have to push one or
1146 * both of these into the shader.
1148 uint32_t base_vertex
;
1149 uint32_t base_instance
;
1151 /* Offsets and ranges for dynamically bound buffers */
1155 } dynamic
[MAX_DYNAMIC_BUFFERS
];
1157 /* Image data for image_load_store on pre-SKL */
1158 struct brw_image_param images
[MAX_IMAGES
];
1161 struct anv_dynamic_state
{
1164 VkViewport viewports
[MAX_VIEWPORTS
];
1169 VkRect2D scissors
[MAX_SCISSORS
];
1180 float blend_constants
[4];
1190 } stencil_compare_mask
;
1195 } stencil_write_mask
;
1200 } stencil_reference
;
1203 extern const struct anv_dynamic_state default_dynamic_state
;
1205 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1206 const struct anv_dynamic_state
*src
,
1207 uint32_t copy_mask
);
1210 * Attachment state when recording a renderpass instance.
1212 * The clear value is valid only if there exists a pending clear.
1214 struct anv_attachment_state
{
1215 VkImageAspectFlags pending_clear_aspects
;
1216 VkClearValue clear_value
;
1219 /** State required while building cmd buffer */
1220 struct anv_cmd_state
{
1221 /* PIPELINE_SELECT.PipelineSelection */
1222 uint32_t current_pipeline
;
1223 const struct anv_l3_config
* current_l3_config
;
1225 anv_cmd_dirty_mask_t dirty
;
1226 anv_cmd_dirty_mask_t compute_dirty
;
1227 enum anv_pipe_bits pending_pipe_bits
;
1228 uint32_t num_workgroups_offset
;
1229 struct anv_bo
*num_workgroups_bo
;
1230 VkShaderStageFlags descriptors_dirty
;
1231 VkShaderStageFlags push_constants_dirty
;
1232 uint32_t scratch_size
;
1233 struct anv_pipeline
* pipeline
;
1234 struct anv_pipeline
* compute_pipeline
;
1235 struct anv_framebuffer
* framebuffer
;
1236 struct anv_render_pass
* pass
;
1237 struct anv_subpass
* subpass
;
1238 VkRect2D render_area
;
1239 uint32_t restart_index
;
1240 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1241 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1242 VkShaderStageFlags push_constant_stages
;
1243 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1244 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1245 struct anv_state samplers
[MESA_SHADER_STAGES
];
1246 struct anv_dynamic_state dynamic
;
1250 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1251 * valid only when recording a render pass instance.
1253 struct anv_attachment_state
* attachments
;
1256 struct anv_buffer
* index_buffer
;
1257 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1258 uint32_t index_offset
;
1262 struct anv_cmd_pool
{
1263 VkAllocationCallbacks alloc
;
1264 struct list_head cmd_buffers
;
1267 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1269 enum anv_cmd_buffer_exec_mode
{
1270 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1271 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1272 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1273 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1274 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1277 struct anv_cmd_buffer
{
1278 VK_LOADER_DATA _loader_data
;
1280 struct anv_device
* device
;
1282 struct anv_cmd_pool
* pool
;
1283 struct list_head pool_link
;
1285 struct anv_batch batch
;
1287 /* Fields required for the actual chain of anv_batch_bo's.
1289 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1291 struct list_head batch_bos
;
1292 enum anv_cmd_buffer_exec_mode exec_mode
;
1294 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1295 * referenced by this command buffer
1297 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1299 struct anv_vector seen_bbos
;
1301 /* A vector of int32_t's for every block of binding tables.
1303 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1305 struct anv_vector bt_blocks
;
1307 struct anv_reloc_list surface_relocs
;
1309 /* Information needed for execbuf
1311 * These fields are generated by anv_cmd_buffer_prepare_execbuf().
1314 struct drm_i915_gem_execbuffer2 execbuf
;
1316 struct drm_i915_gem_exec_object2
* objects
;
1318 struct anv_bo
** bos
;
1320 /* Allocated length of the 'objects' and 'bos' arrays */
1321 uint32_t array_length
;
1326 /* Serial for tracking buffer completion */
1329 /* Stream objects for storing temporary data */
1330 struct anv_state_stream surface_state_stream
;
1331 struct anv_state_stream dynamic_state_stream
;
1333 VkCommandBufferUsageFlags usage_flags
;
1334 VkCommandBufferLevel level
;
1336 struct anv_cmd_state state
;
1339 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1340 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1341 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1342 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1343 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1344 struct anv_cmd_buffer
*secondary
);
1345 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1347 VkResult
anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1348 unsigned stage
, struct anv_state
*bt_state
);
1349 VkResult
anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1350 unsigned stage
, struct anv_state
*state
);
1351 uint32_t anv_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
);
1353 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1354 const void *data
, uint32_t size
, uint32_t alignment
);
1355 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1356 uint32_t *a
, uint32_t *b
,
1357 uint32_t dwords
, uint32_t alignment
);
1360 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1362 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1363 uint32_t entries
, uint32_t *state_offset
);
1365 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1367 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1368 uint32_t size
, uint32_t alignment
);
1371 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1373 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1374 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1375 bool depth_clamp_enable
);
1376 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1378 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1380 void anv_cmd_state_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1381 const VkRenderPassBeginInfo
*info
);
1383 void anv_cmd_buffer_set_subpass(struct anv_cmd_buffer
*cmd_buffer
,
1384 struct anv_subpass
*subpass
);
1387 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1388 gl_shader_stage stage
);
1390 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1392 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1393 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1395 const struct anv_image_view
*
1396 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1398 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1402 struct drm_i915_gem_execbuffer2 execbuf
;
1403 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1409 struct anv_state state
;
1414 struct anv_shader_module
{
1415 struct nir_shader
* nir
;
1417 unsigned char sha1
[20];
1422 void anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
1423 struct anv_shader_module
*module
,
1424 const char *entrypoint
,
1425 const VkSpecializationInfo
*spec_info
);
1427 static inline gl_shader_stage
1428 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1430 assert(__builtin_popcount(vk_stage
) == 1);
1431 return ffs(vk_stage
) - 1;
1434 static inline VkShaderStageFlagBits
1435 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1437 return (1 << mesa_stage
);
1440 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1442 #define anv_foreach_stage(stage, stage_bits) \
1443 for (gl_shader_stage stage, \
1444 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1445 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1446 __tmp &= ~(1 << (stage)))
1448 struct anv_pipeline_bind_map
{
1449 uint32_t surface_count
;
1450 uint32_t sampler_count
;
1451 uint32_t image_count
;
1452 uint32_t attachment_count
;
1454 struct anv_pipeline_binding
* surface_to_descriptor
;
1455 struct anv_pipeline_binding
* sampler_to_descriptor
;
1456 uint32_t * surface_to_attachment
;
1459 struct anv_pipeline
{
1460 struct anv_device
* device
;
1461 struct anv_batch batch
;
1462 uint32_t batch_data
[512];
1463 struct anv_reloc_list batch_relocs
;
1464 uint32_t dynamic_state_mask
;
1465 struct anv_dynamic_state dynamic_state
;
1467 struct anv_pipeline_layout
* layout
;
1468 struct anv_pipeline_bind_map bindings
[MESA_SHADER_STAGES
];
1471 bool needs_data_cache
;
1473 const struct brw_stage_prog_data
* prog_data
[MESA_SHADER_STAGES
];
1475 uint32_t start
[MESA_SHADER_GEOMETRY
+ 1];
1476 uint32_t size
[MESA_SHADER_GEOMETRY
+ 1];
1477 uint32_t entries
[MESA_SHADER_GEOMETRY
+ 1];
1478 const struct anv_l3_config
* l3_config
;
1479 uint32_t total_size
;
1482 VkShaderStageFlags active_stages
;
1483 struct anv_state blend_state
;
1491 uint32_t binding_stride
[MAX_VBS
];
1492 bool instancing_enable
[MAX_VBS
];
1493 bool primitive_restart
;
1496 uint32_t cs_right_mask
;
1498 bool depth_clamp_enable
;
1502 uint32_t depth_stencil_state
[3];
1508 uint32_t wm_depth_stencil
[3];
1512 uint32_t wm_depth_stencil
[4];
1516 static inline const struct brw_vs_prog_data
*
1517 get_vs_prog_data(struct anv_pipeline
*pipeline
)
1519 return (const struct brw_vs_prog_data
*) pipeline
->prog_data
[MESA_SHADER_VERTEX
];
1522 static inline const struct brw_gs_prog_data
*
1523 get_gs_prog_data(struct anv_pipeline
*pipeline
)
1525 return (const struct brw_gs_prog_data
*) pipeline
->prog_data
[MESA_SHADER_GEOMETRY
];
1528 static inline const struct brw_wm_prog_data
*
1529 get_wm_prog_data(struct anv_pipeline
*pipeline
)
1531 return (const struct brw_wm_prog_data
*) pipeline
->prog_data
[MESA_SHADER_FRAGMENT
];
1534 static inline const struct brw_cs_prog_data
*
1535 get_cs_prog_data(struct anv_pipeline
*pipeline
)
1537 return (const struct brw_cs_prog_data
*) pipeline
->prog_data
[MESA_SHADER_COMPUTE
];
1540 struct anv_graphics_pipeline_create_info
{
1542 * If non-negative, overrides the color attachment count of the pipeline's
1545 int8_t color_attachment_count
;
1553 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1554 struct anv_pipeline_cache
*cache
,
1555 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1556 const struct anv_graphics_pipeline_create_info
*extra
,
1557 const VkAllocationCallbacks
*alloc
);
1560 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1561 struct anv_pipeline_cache
*cache
,
1562 const VkComputePipelineCreateInfo
*info
,
1563 struct anv_shader_module
*module
,
1564 const char *entrypoint
,
1565 const VkSpecializationInfo
*spec_info
);
1568 anv_graphics_pipeline_create(VkDevice device
,
1569 VkPipelineCache cache
,
1570 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1571 const struct anv_graphics_pipeline_create_info
*extra
,
1572 const VkAllocationCallbacks
*alloc
,
1573 VkPipeline
*pPipeline
);
1575 struct anv_format_swizzle
{
1576 enum isl_channel_select r
:4;
1577 enum isl_channel_select g
:4;
1578 enum isl_channel_select b
:4;
1579 enum isl_channel_select a
:4;
1583 enum isl_format isl_format
:16;
1584 struct anv_format_swizzle swizzle
;
1588 anv_get_format(const struct brw_device_info
*devinfo
, VkFormat format
,
1589 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1591 static inline enum isl_format
1592 anv_get_isl_format(const struct brw_device_info
*devinfo
, VkFormat vk_format
,
1593 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1595 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1599 anv_compute_urb_partition(struct anv_pipeline
*pipeline
);
1602 anv_setup_pipeline_l3_config(struct anv_pipeline
*pipeline
);
1605 * Subsurface of an anv_image.
1607 struct anv_surface
{
1608 struct isl_surf isl
;
1611 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1618 /* The original VkFormat provided by the client. This may not match any
1619 * of the actual surface formats.
1622 VkImageAspectFlags aspects
;
1625 uint32_t array_size
;
1626 uint32_t samples
; /**< VkImageCreateInfo::samples */
1627 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1628 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1633 /* Set when bound */
1635 VkDeviceSize offset
;
1640 * For each foo, anv_image::foo_surface is valid if and only if
1641 * anv_image::aspects has a foo aspect.
1643 * The hardware requires that the depth buffer and stencil buffer be
1644 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1645 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1646 * allocate the depth and stencil buffers as separate surfaces in the same
1650 struct anv_surface color_surface
;
1653 struct anv_surface depth_surface
;
1654 struct anv_surface stencil_surface
;
1659 static inline uint32_t
1660 anv_get_layerCount(const struct anv_image
*image
,
1661 const VkImageSubresourceRange
*range
)
1663 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1664 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1667 static inline uint32_t
1668 anv_get_levelCount(const struct anv_image
*image
,
1669 const VkImageSubresourceRange
*range
)
1671 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1672 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1676 struct anv_image_view
{
1677 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
1679 uint32_t offset
; /**< Offset into bo. */
1681 VkImageAspectFlags aspect_mask
;
1683 uint32_t base_layer
;
1685 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1687 /** RENDER_SURFACE_STATE when using image as a color render target. */
1688 struct anv_state color_rt_surface_state
;
1690 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1691 struct anv_state sampler_surface_state
;
1693 /** RENDER_SURFACE_STATE when using image as a storage image. */
1694 struct anv_state storage_surface_state
;
1696 struct brw_image_param storage_image_param
;
1699 struct anv_image_create_info
{
1700 const VkImageCreateInfo
*vk_info
;
1701 isl_tiling_flags_t isl_tiling_flags
;
1705 VkResult
anv_image_create(VkDevice _device
,
1706 const struct anv_image_create_info
*info
,
1707 const VkAllocationCallbacks
* alloc
,
1710 struct anv_surface
*
1711 anv_image_get_surface_for_aspect_mask(struct anv_image
*image
,
1712 VkImageAspectFlags aspect_mask
);
1714 void anv_image_view_init(struct anv_image_view
*view
,
1715 struct anv_device
*device
,
1716 const VkImageViewCreateInfo
* pCreateInfo
,
1717 struct anv_cmd_buffer
*cmd_buffer
,
1718 VkImageUsageFlags usage_mask
);
1720 struct anv_buffer_view
{
1721 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1723 uint32_t offset
; /**< Offset into bo. */
1724 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1726 struct anv_state surface_state
;
1727 struct anv_state storage_surface_state
;
1729 struct brw_image_param storage_image_param
;
1732 void anv_buffer_view_init(struct anv_buffer_view
*view
,
1733 struct anv_device
*device
,
1734 const VkBufferViewCreateInfo
* pCreateInfo
,
1735 struct anv_cmd_buffer
*cmd_buffer
);
1738 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
1740 static inline struct VkExtent3D
1741 anv_sanitize_image_extent(const VkImageType imageType
,
1742 const struct VkExtent3D imageExtent
)
1744 switch (imageType
) {
1745 case VK_IMAGE_TYPE_1D
:
1746 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1747 case VK_IMAGE_TYPE_2D
:
1748 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1749 case VK_IMAGE_TYPE_3D
:
1752 unreachable("invalid image type");
1756 static inline struct VkOffset3D
1757 anv_sanitize_image_offset(const VkImageType imageType
,
1758 const struct VkOffset3D imageOffset
)
1760 switch (imageType
) {
1761 case VK_IMAGE_TYPE_1D
:
1762 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1763 case VK_IMAGE_TYPE_2D
:
1764 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1765 case VK_IMAGE_TYPE_3D
:
1768 unreachable("invalid image type");
1773 void anv_fill_buffer_surface_state(struct anv_device
*device
,
1774 struct anv_state state
,
1775 enum isl_format format
,
1776 uint32_t offset
, uint32_t range
,
1779 void anv_image_view_fill_image_param(struct anv_device
*device
,
1780 struct anv_image_view
*view
,
1781 struct brw_image_param
*param
);
1782 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
1783 struct anv_buffer_view
*view
,
1784 struct brw_image_param
*param
);
1786 struct anv_sampler
{
1790 struct anv_framebuffer
{
1795 uint32_t attachment_count
;
1796 struct anv_image_view
* attachments
[0];
1799 struct anv_subpass
{
1800 uint32_t input_count
;
1801 uint32_t * input_attachments
;
1802 uint32_t color_count
;
1803 uint32_t * color_attachments
;
1804 uint32_t * resolve_attachments
;
1805 uint32_t depth_stencil_attachment
;
1807 /** Subpass has at least one resolve attachment */
1811 struct anv_render_pass_attachment
{
1814 VkAttachmentLoadOp load_op
;
1815 VkAttachmentStoreOp store_op
;
1816 VkAttachmentLoadOp stencil_load_op
;
1819 struct anv_render_pass
{
1820 uint32_t attachment_count
;
1821 uint32_t subpass_count
;
1822 uint32_t * subpass_attachments
;
1823 struct anv_render_pass_attachment
* attachments
;
1824 struct anv_subpass subpasses
[0];
1827 extern struct anv_render_pass anv_meta_dummy_renderpass
;
1829 struct anv_query_pool_slot
{
1835 struct anv_query_pool
{
1841 VkResult
anv_device_init_meta(struct anv_device
*device
);
1842 void anv_device_finish_meta(struct anv_device
*device
);
1844 void *anv_lookup_entrypoint(const char *name
);
1846 void anv_dump_image_to_ppm(struct anv_device
*device
,
1847 struct anv_image
*image
, unsigned miplevel
,
1848 unsigned array_layer
, VkImageAspectFlagBits aspect
,
1849 const char *filename
);
1851 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1853 static inline struct __anv_type * \
1854 __anv_type ## _from_handle(__VkType _handle) \
1856 return (struct __anv_type *) _handle; \
1859 static inline __VkType \
1860 __anv_type ## _to_handle(struct __anv_type *_obj) \
1862 return (__VkType) _obj; \
1865 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1867 static inline struct __anv_type * \
1868 __anv_type ## _from_handle(__VkType _handle) \
1870 return (struct __anv_type *)(uintptr_t) _handle; \
1873 static inline __VkType \
1874 __anv_type ## _to_handle(struct __anv_type *_obj) \
1876 return (__VkType)(uintptr_t) _obj; \
1879 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1880 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1882 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
1883 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
1884 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
1885 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
1886 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
1888 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
1889 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
1890 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
1891 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
1892 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
1893 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
1894 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
1895 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
1896 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
1897 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
1898 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
1899 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
1900 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
1901 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
1902 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
1903 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
1904 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
1905 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
1906 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
1908 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1910 static inline const __VkType * \
1911 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1913 return (const __VkType *) __anv_obj; \
1916 #define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1917 const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name)
1919 ANV_DEFINE_STRUCT_CASTS(anv_common
, VkMemoryBarrier
)
1920 ANV_DEFINE_STRUCT_CASTS(anv_common
, VkBufferMemoryBarrier
)
1921 ANV_DEFINE_STRUCT_CASTS(anv_common
, VkImageMemoryBarrier
)
1923 /* Gen-specific function declarations */
1925 # include "anv_genX.h"
1927 # define genX(x) gen7_##x
1928 # include "anv_genX.h"
1930 # define genX(x) gen75_##x
1931 # include "anv_genX.h"
1933 # define genX(x) gen8_##x
1934 # include "anv_genX.h"
1936 # define genX(x) gen9_##x
1937 # include "anv_genX.h"