2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/bitset.h"
53 #include "util/macros.h"
54 #include "util/hash_table.h"
55 #include "util/list.h"
56 #include "util/sparse_array.h"
57 #include "util/u_atomic.h"
58 #include "util/u_vector.h"
59 #include "util/u_math.h"
61 #include "util/xmlconfig.h"
63 #include "vk_debug_report.h"
65 /* Pre-declarations needed for WSI entrypoints */
68 typedef struct xcb_connection_t xcb_connection_t
;
69 typedef uint32_t xcb_visualid_t
;
70 typedef uint32_t xcb_window_t
;
73 struct anv_buffer_view
;
74 struct anv_image_view
;
77 struct gen_aux_map_context
;
79 struct gen_perf_config
;
81 #include <vulkan/vulkan.h>
82 #include <vulkan/vulkan_intel.h>
83 #include <vulkan/vk_icd.h>
85 #include "anv_android.h"
86 #include "anv_entrypoints.h"
87 #include "anv_extensions.h"
90 #include "dev/gen_debug.h"
91 #include "common/intel_log.h"
92 #include "wsi_common.h"
94 /* anv Virtual Memory Layout
95 * =========================
97 * When the anv driver is determining the virtual graphics addresses of memory
98 * objects itself using the softpin mechanism, the following memory ranges
101 * Three special considerations to notice:
103 * (1) the dynamic state pool is located within the same 4 GiB as the low
104 * heap. This is to work around a VF cache issue described in a comment in
105 * anv_physical_device_init_heaps.
107 * (2) the binding table pool is located at lower addresses than the surface
108 * state pool, within a 4 GiB range. This allows surface state base addresses
109 * to cover both binding tables (16 bit offsets) and surface states (32 bit
112 * (3) the last 4 GiB of the address space is withheld from the high
113 * heap. Various hardware units will read past the end of an object for
114 * various reasons. This healthy margin prevents reads from wrapping around
117 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
118 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
119 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
120 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
121 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
122 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
123 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
124 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
125 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
126 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
127 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
129 #define LOW_HEAP_SIZE \
130 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
131 #define DYNAMIC_STATE_POOL_SIZE \
132 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
133 #define BINDING_TABLE_POOL_SIZE \
134 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
135 #define SURFACE_STATE_POOL_SIZE \
136 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
137 #define INSTRUCTION_STATE_POOL_SIZE \
138 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
140 /* Allowing different clear colors requires us to perform a depth resolve at
141 * the end of certain render passes. This is because while slow clears store
142 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
143 * See the PRMs for examples describing when additional resolves would be
144 * necessary. To enable fast clears without requiring extra resolves, we set
145 * the clear value to a globally-defined one. We could allow different values
146 * if the user doesn't expect coherent data during or after a render passes
147 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
148 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
149 * 1.0f seems to be the only value used. The only application that doesn't set
150 * this value does so through the usage of an seemingly uninitialized clear
153 #define ANV_HZ_FC_VAL 1.0f
156 #define MAX_XFB_BUFFERS 4
157 #define MAX_XFB_STREAMS 4
160 #define MAX_VIEWPORTS 16
161 #define MAX_SCISSORS 16
162 #define MAX_PUSH_CONSTANTS_SIZE 128
163 #define MAX_DYNAMIC_BUFFERS 16
164 #define MAX_IMAGES 64
165 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
166 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
167 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
169 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
171 * "The surface state model is used when a Binding Table Index (specified
172 * in the message descriptor) of less than 240 is specified. In this model,
173 * the Binding Table Index is used to index into the binding table, and the
174 * binding table entry contains a pointer to the SURFACE_STATE."
176 * Binding table values above 240 are used for various things in the hardware
177 * such as stateless, stateless with incoherent cache, SLM, and bindless.
179 #define MAX_BINDING_TABLE_SIZE 240
181 /* The kernel relocation API has a limitation of a 32-bit delta value
182 * applied to the address before it is written which, in spite of it being
183 * unsigned, is treated as signed . Because of the way that this maps to
184 * the Vulkan API, we cannot handle an offset into a buffer that does not
185 * fit into a signed 32 bits. The only mechanism we have for dealing with
186 * this at the moment is to limit all VkDeviceMemory objects to a maximum
187 * of 2GB each. The Vulkan spec allows us to do this:
189 * "Some platforms may have a limit on the maximum size of a single
190 * allocation. For example, certain systems may fail to create
191 * allocations with a size greater than or equal to 4GB. Such a limit is
192 * implementation-dependent, and if such a failure occurs then the error
193 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
195 * We don't use vk_error here because it's not an error so much as an
196 * indication to the application that the allocation is too large.
198 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
200 #define ANV_SVGS_VB_INDEX MAX_VBS
201 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
203 /* We reserve this MI ALU register for the purpose of handling predication.
204 * Other code which uses the MI ALU should leave it alone.
206 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
208 /* For gen12 we set the streamout buffers using 4 separate commands
209 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
210 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
211 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
212 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
213 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
214 * 3DSTATE_SO_BUFFER_INDEX_0.
216 #define SO_BUFFER_INDEX_0_CMD 0x60
217 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
219 static inline uint32_t
220 align_down_npot_u32(uint32_t v
, uint32_t a
)
225 static inline uint32_t
226 align_u32(uint32_t v
, uint32_t a
)
228 assert(a
!= 0 && a
== (a
& -a
));
229 return (v
+ a
- 1) & ~(a
- 1);
232 static inline uint64_t
233 align_u64(uint64_t v
, uint64_t a
)
235 assert(a
!= 0 && a
== (a
& -a
));
236 return (v
+ a
- 1) & ~(a
- 1);
239 static inline int32_t
240 align_i32(int32_t v
, int32_t a
)
242 assert(a
!= 0 && a
== (a
& -a
));
243 return (v
+ a
- 1) & ~(a
- 1);
246 /** Alignment must be a power of 2. */
248 anv_is_aligned(uintmax_t n
, uintmax_t a
)
250 assert(a
== (a
& -a
));
251 return (n
& (a
- 1)) == 0;
254 static inline uint32_t
255 anv_minify(uint32_t n
, uint32_t levels
)
257 if (unlikely(n
== 0))
260 return MAX2(n
>> levels
, 1);
264 anv_clamp_f(float f
, float min
, float max
)
277 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
279 if (*inout_mask
& clear_mask
) {
280 *inout_mask
&= ~clear_mask
;
287 static inline union isl_color_value
288 vk_to_isl_color(VkClearColorValue color
)
290 return (union isl_color_value
) {
300 #define for_each_bit(b, dword) \
301 for (uint32_t __dword = (dword); \
302 (b) = __builtin_ffs(__dword) - 1, __dword; \
303 __dword &= ~(1 << (b)))
305 #define typed_memcpy(dest, src, count) ({ \
306 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
307 memcpy((dest), (src), (count) * sizeof(*(src))); \
310 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
311 * to be added here in order to utilize mapping in debug/error/perf macros.
313 #define REPORT_OBJECT_TYPE(o) \
314 __builtin_choose_expr ( \
315 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
316 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
317 __builtin_choose_expr ( \
318 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
319 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
320 __builtin_choose_expr ( \
321 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
322 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
323 __builtin_choose_expr ( \
324 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
325 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
326 __builtin_choose_expr ( \
327 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
328 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
329 __builtin_choose_expr ( \
330 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
331 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
332 __builtin_choose_expr ( \
333 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
334 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
335 __builtin_choose_expr ( \
336 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
337 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
338 __builtin_choose_expr ( \
339 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
340 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), void*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
407 /* The void expression results in a compile-time error \
408 when assigning the result to something. */ \
409 (void)0)))))))))))))))))))))))))))))))
411 /* Whenever we generate an error, pass it through this function. Useful for
412 * debugging, where we can break on it. Only call at error site, not when
413 * propagating errors. Might be useful to plug in a stack trace here.
416 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
417 VkDebugReportObjectTypeEXT type
, VkResult error
,
418 const char *file
, int line
, const char *format
,
421 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
422 VkDebugReportObjectTypeEXT type
, VkResult error
,
423 const char *file
, int line
, const char *format
, ...)
424 anv_printflike(7, 8);
427 #define vk_error(error) __vk_errorf(NULL, NULL,\
428 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
429 error, __FILE__, __LINE__, NULL)
430 #define vk_errorv(instance, obj, error, format, args)\
431 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
432 __FILE__, __LINE__, format, args)
433 #define vk_errorf(instance, obj, error, format, ...)\
434 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
435 __FILE__, __LINE__, format, ## __VA_ARGS__)
437 #define vk_error(error) error
438 #define vk_errorf(instance, obj, error, format, ...) error
442 * Warn on ignored extension structs.
444 * The Vulkan spec requires us to ignore unsupported or unknown structs in
445 * a pNext chain. In debug mode, emitting warnings for ignored structs may
446 * help us discover structs that we should not have ignored.
449 * From the Vulkan 1.0.38 spec:
451 * Any component of the implementation (the loader, any enabled layers,
452 * and drivers) must skip over, without processing (other than reading the
453 * sType and pNext members) any chained structures with sType values not
454 * defined by extensions supported by that component.
456 #define anv_debug_ignored_stype(sType) \
457 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
459 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
460 VkDebugReportObjectTypeEXT type
, const char *file
,
461 int line
, const char *format
, ...)
462 anv_printflike(6, 7);
463 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
464 void anv_loge_v(const char *format
, va_list va
);
467 * Print a FINISHME message, including its source location.
469 #define anv_finishme(format, ...) \
471 static bool reported = false; \
473 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
480 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
482 #define anv_perf_warn(instance, obj, format, ...) \
484 static bool reported = false; \
485 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
486 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
487 format, ##__VA_ARGS__); \
492 /* A non-fatal assert. Useful for debugging. */
494 #define anv_assert(x) ({ \
495 if (unlikely(!(x))) \
496 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
499 #define anv_assert(x)
502 /* A multi-pointer allocator
504 * When copying data structures from the user (such as a render pass), it's
505 * common to need to allocate data for a bunch of different things. Instead
506 * of doing several allocations and having to handle all of the error checking
507 * that entails, it can be easier to do a single allocation. This struct
508 * helps facilitate that. The intended usage looks like this:
511 * anv_multialloc_add(&ma, &main_ptr, 1);
512 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
513 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
515 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
516 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
518 struct anv_multialloc
{
526 #define ANV_MULTIALLOC_INIT \
527 ((struct anv_multialloc) { 0, })
529 #define ANV_MULTIALLOC(_name) \
530 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
532 __attribute__((always_inline
))
534 _anv_multialloc_add(struct anv_multialloc
*ma
,
535 void **ptr
, size_t size
, size_t align
)
537 size_t offset
= align_u64(ma
->size
, align
);
538 ma
->size
= offset
+ size
;
539 ma
->align
= MAX2(ma
->align
, align
);
541 /* Store the offset in the pointer. */
542 *ptr
= (void *)(uintptr_t)offset
;
544 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
545 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
548 #define anv_multialloc_add_size(_ma, _ptr, _size) \
549 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
551 #define anv_multialloc_add(_ma, _ptr, _count) \
552 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
554 __attribute__((always_inline
))
556 anv_multialloc_alloc(struct anv_multialloc
*ma
,
557 const VkAllocationCallbacks
*alloc
,
558 VkSystemAllocationScope scope
)
560 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
564 /* Fill out each of the pointers with their final value.
566 * for (uint32_t i = 0; i < ma->ptr_count; i++)
567 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
569 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
570 * constant, GCC is incapable of figuring this out and unrolling the loop
571 * so we have to give it a little help.
573 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
574 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
575 if ((_i) < ma->ptr_count) \
576 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
577 _ANV_MULTIALLOC_UPDATE_POINTER(0);
578 _ANV_MULTIALLOC_UPDATE_POINTER(1);
579 _ANV_MULTIALLOC_UPDATE_POINTER(2);
580 _ANV_MULTIALLOC_UPDATE_POINTER(3);
581 _ANV_MULTIALLOC_UPDATE_POINTER(4);
582 _ANV_MULTIALLOC_UPDATE_POINTER(5);
583 _ANV_MULTIALLOC_UPDATE_POINTER(6);
584 _ANV_MULTIALLOC_UPDATE_POINTER(7);
585 #undef _ANV_MULTIALLOC_UPDATE_POINTER
590 __attribute__((always_inline
))
592 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
593 const VkAllocationCallbacks
*parent_alloc
,
594 const VkAllocationCallbacks
*alloc
,
595 VkSystemAllocationScope scope
)
597 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
605 /* Index into the current validation list. This is used by the
606 * validation list building alrogithm to track which buffers are already
607 * in the validation list so that we can ensure uniqueness.
611 /* Index for use with util_sparse_array_free_list */
614 /* Last known offset. This value is provided by the kernel when we
615 * execbuf and is used as the presumed offset for the next bunch of
622 /* Map for internally mapped BOs.
624 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
628 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
631 /** True if this BO may be shared with other processes */
634 /** True if this BO is a wrapper
636 * When set to true, none of the fields in this BO are meaningful except
637 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
638 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
639 * is set in the physical device.
643 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
644 bool has_fixed_address
:1;
646 /** True if this BO wraps a host pointer */
647 bool from_host_ptr
:1;
650 static inline struct anv_bo
*
651 anv_bo_unwrap(struct anv_bo
*bo
)
653 while (bo
->is_wrapper
)
658 /* Represents a lock-free linked list of "free" things. This is used by
659 * both the block pool and the state pools. Unfortunately, in order to
660 * solve the ABA problem, we can't use a single uint32_t head.
662 union anv_free_list
{
666 /* A simple count that is incremented every time the head changes. */
669 /* Make sure it's aligned to 64 bits. This will make atomic operations
670 * faster on 32 bit platforms.
672 uint64_t u64
__attribute__ ((aligned (8)));
675 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
677 struct anv_block_state
{
683 /* Make sure it's aligned to 64 bits. This will make atomic operations
684 * faster on 32 bit platforms.
686 uint64_t u64
__attribute__ ((aligned (8)));
690 #define anv_block_pool_foreach_bo(bo, pool) \
691 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
692 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
695 #define ANV_MAX_BLOCK_POOL_BOS 20
697 struct anv_block_pool
{
698 struct anv_device
*device
;
701 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
702 * around the actual BO so that we grow the pool after the wrapper BO has
703 * been put in a relocation list. This is only used in the non-softpin
706 struct anv_bo wrapper_bo
;
708 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
714 /* The address where the start of the pool is pinned. The various bos that
715 * are created as the pool grows will have addresses in the range
716 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
718 uint64_t start_address
;
720 /* The offset from the start of the bo to the "center" of the block
721 * pool. Pointers to allocated blocks are given by
722 * bo.map + center_bo_offset + offsets.
724 uint32_t center_bo_offset
;
726 /* Current memory map of the block pool. This pointer may or may not
727 * point to the actual beginning of the block pool memory. If
728 * anv_block_pool_alloc_back has ever been called, then this pointer
729 * will point to the "center" position of the buffer and all offsets
730 * (negative or positive) given out by the block pool alloc functions
731 * will be valid relative to this pointer.
733 * In particular, map == bo.map + center_offset
735 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
736 * since it will handle the softpin case as well, where this points to NULL.
742 * Array of mmaps and gem handles owned by the block pool, reclaimed when
743 * the block pool is destroyed.
745 struct u_vector mmap_cleanups
;
747 struct anv_block_state state
;
749 struct anv_block_state back_state
;
752 /* Block pools are backed by a fixed-size 1GB memfd */
753 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
755 /* The center of the block pool is also the middle of the memfd. This may
756 * change in the future if we decide differently for some reason.
758 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
760 static inline uint32_t
761 anv_block_pool_size(struct anv_block_pool
*pool
)
763 return pool
->state
.end
+ pool
->back_state
.end
;
773 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
775 struct anv_fixed_size_state_pool
{
776 union anv_free_list free_list
;
777 struct anv_block_state block
;
780 #define ANV_MIN_STATE_SIZE_LOG2 6
781 #define ANV_MAX_STATE_SIZE_LOG2 21
783 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
785 struct anv_free_entry
{
787 struct anv_state state
;
790 struct anv_state_table
{
791 struct anv_device
*device
;
793 struct anv_free_entry
*map
;
795 struct anv_block_state state
;
796 struct u_vector cleanups
;
799 struct anv_state_pool
{
800 struct anv_block_pool block_pool
;
802 struct anv_state_table table
;
804 /* The size of blocks which will be allocated from the block pool */
807 /** Free list for "back" allocations */
808 union anv_free_list back_alloc_free_list
;
810 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
813 struct anv_state_stream_block
;
815 struct anv_state_stream
{
816 struct anv_state_pool
*state_pool
;
818 /* The size of blocks to allocate from the state pool */
821 /* Current block we're allocating from */
822 struct anv_state block
;
824 /* Offset into the current block at which to allocate the next state */
827 /* List of all blocks allocated from this pool */
828 struct anv_state_stream_block
*block_list
;
831 /* The block_pool functions exported for testing only. The block pool should
832 * only be used via a state pool (see below).
834 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
835 struct anv_device
*device
,
836 uint64_t start_address
,
837 uint32_t initial_size
);
838 void anv_block_pool_finish(struct anv_block_pool
*pool
);
839 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
840 uint32_t block_size
, uint32_t *padding
);
841 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
842 uint32_t block_size
);
843 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
845 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
846 struct anv_device
*device
,
847 uint64_t start_address
,
848 uint32_t block_size
);
849 void anv_state_pool_finish(struct anv_state_pool
*pool
);
850 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
851 uint32_t state_size
, uint32_t alignment
);
852 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
853 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
854 void anv_state_stream_init(struct anv_state_stream
*stream
,
855 struct anv_state_pool
*state_pool
,
856 uint32_t block_size
);
857 void anv_state_stream_finish(struct anv_state_stream
*stream
);
858 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
859 uint32_t size
, uint32_t alignment
);
861 VkResult
anv_state_table_init(struct anv_state_table
*table
,
862 struct anv_device
*device
,
863 uint32_t initial_entries
);
864 void anv_state_table_finish(struct anv_state_table
*table
);
865 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
867 void anv_free_list_push(union anv_free_list
*list
,
868 struct anv_state_table
*table
,
869 uint32_t idx
, uint32_t count
);
870 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
871 struct anv_state_table
*table
);
874 static inline struct anv_state
*
875 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
877 return &table
->map
[idx
].state
;
880 * Implements a pool of re-usable BOs. The interface is identical to that
881 * of block_pool except that each block is its own BO.
884 struct anv_device
*device
;
888 struct util_sparse_array_free_list free_list
[16];
891 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
893 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
894 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
895 struct anv_bo
**bo_out
);
896 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
898 struct anv_scratch_pool
{
899 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
900 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
903 void anv_scratch_pool_init(struct anv_device
*device
,
904 struct anv_scratch_pool
*pool
);
905 void anv_scratch_pool_finish(struct anv_device
*device
,
906 struct anv_scratch_pool
*pool
);
907 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
908 struct anv_scratch_pool
*pool
,
909 gl_shader_stage stage
,
910 unsigned per_thread_scratch
);
912 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
913 struct anv_bo_cache
{
914 struct util_sparse_array bo_map
;
915 pthread_mutex_t mutex
;
918 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
919 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
921 struct anv_memory_type
{
922 /* Standard bits passed on to the client */
923 VkMemoryPropertyFlags propertyFlags
;
926 /* Driver-internal book-keeping */
927 VkBufferUsageFlags valid_buffer_usage
;
930 struct anv_memory_heap
{
931 /* Standard bits passed on to the client */
933 VkMemoryHeapFlags flags
;
935 /* Driver-internal book-keeping */
938 bool supports_48bit_addresses
;
942 struct anv_physical_device
{
943 VK_LOADER_DATA _loader_data
;
945 struct anv_instance
* instance
;
956 struct gen_device_info info
;
957 /** Amount of "GPU memory" we want to advertise
959 * Clearly, this value is bogus since Intel is a UMA architecture. On
960 * gen7 platforms, we are limited by GTT size unless we want to implement
961 * fine-grained tracking and GTT splitting. On Broadwell and above we are
962 * practically unlimited. However, we will never report more than 3/4 of
963 * the total system ram to try and avoid running out of RAM.
965 bool supports_48bit_addresses
;
966 struct brw_compiler
* compiler
;
967 struct isl_device isl_dev
;
968 struct gen_perf_config
* perf
;
969 int cmd_parser_version
;
971 bool has_exec_capture
;
974 bool has_syncobj_wait
;
975 bool has_context_priority
;
977 bool has_context_isolation
;
978 bool has_mem_available
;
979 bool always_use_bindless
;
981 /** True if we can access buffers using A64 messages */
982 bool has_a64_buffer_access
;
983 /** True if we can use bindless access for images */
984 bool has_bindless_images
;
985 /** True if we can use bindless access for samplers */
986 bool has_bindless_samplers
;
988 struct anv_device_extension_table supported_extensions
;
989 struct anv_physical_device_dispatch_table dispatch
;
992 uint32_t subslice_total
;
996 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
998 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1001 uint8_t driver_build_sha1
[20];
1002 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1003 uint8_t driver_uuid
[VK_UUID_SIZE
];
1004 uint8_t device_uuid
[VK_UUID_SIZE
];
1006 struct disk_cache
* disk_cache
;
1008 struct wsi_device wsi_device
;
1013 struct anv_app_info
{
1014 const char* app_name
;
1015 uint32_t app_version
;
1016 const char* engine_name
;
1017 uint32_t engine_version
;
1018 uint32_t api_version
;
1021 struct anv_instance
{
1022 VK_LOADER_DATA _loader_data
;
1024 VkAllocationCallbacks alloc
;
1026 struct anv_app_info app_info
;
1028 struct anv_instance_extension_table enabled_extensions
;
1029 struct anv_instance_dispatch_table dispatch
;
1030 struct anv_device_dispatch_table device_dispatch
;
1032 int physicalDeviceCount
;
1033 struct anv_physical_device physicalDevice
;
1035 bool pipeline_cache_enabled
;
1037 struct vk_debug_report_instance debug_report_callbacks
;
1039 struct driOptionCache dri_options
;
1040 struct driOptionCache available_dri_options
;
1043 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1044 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1046 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1047 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1051 VK_LOADER_DATA _loader_data
;
1053 struct anv_device
* device
;
1055 VkDeviceQueueCreateFlags flags
;
1058 struct anv_pipeline_cache
{
1059 struct anv_device
* device
;
1060 pthread_mutex_t mutex
;
1062 struct hash_table
* nir_cache
;
1064 struct hash_table
* cache
;
1067 struct nir_xfb_info
;
1068 struct anv_pipeline_bind_map
;
1070 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1071 struct anv_device
*device
,
1072 bool cache_enabled
);
1073 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1075 struct anv_shader_bin
*
1076 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1077 const void *key
, uint32_t key_size
);
1078 struct anv_shader_bin
*
1079 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1080 const void *key_data
, uint32_t key_size
,
1081 const void *kernel_data
, uint32_t kernel_size
,
1082 const void *constant_data
,
1083 uint32_t constant_data_size
,
1084 const struct brw_stage_prog_data
*prog_data
,
1085 uint32_t prog_data_size
,
1086 const struct brw_compile_stats
*stats
,
1088 const struct nir_xfb_info
*xfb_info
,
1089 const struct anv_pipeline_bind_map
*bind_map
);
1091 struct anv_shader_bin
*
1092 anv_device_search_for_kernel(struct anv_device
*device
,
1093 struct anv_pipeline_cache
*cache
,
1094 const void *key_data
, uint32_t key_size
,
1095 bool *user_cache_bit
);
1097 struct anv_shader_bin
*
1098 anv_device_upload_kernel(struct anv_device
*device
,
1099 struct anv_pipeline_cache
*cache
,
1100 const void *key_data
, uint32_t key_size
,
1101 const void *kernel_data
, uint32_t kernel_size
,
1102 const void *constant_data
,
1103 uint32_t constant_data_size
,
1104 const struct brw_stage_prog_data
*prog_data
,
1105 uint32_t prog_data_size
,
1106 const struct brw_compile_stats
*stats
,
1108 const struct nir_xfb_info
*xfb_info
,
1109 const struct anv_pipeline_bind_map
*bind_map
);
1112 struct nir_shader_compiler_options
;
1115 anv_device_search_for_nir(struct anv_device
*device
,
1116 struct anv_pipeline_cache
*cache
,
1117 const struct nir_shader_compiler_options
*nir_options
,
1118 unsigned char sha1_key
[20],
1122 anv_device_upload_nir(struct anv_device
*device
,
1123 struct anv_pipeline_cache
*cache
,
1124 const struct nir_shader
*nir
,
1125 unsigned char sha1_key
[20]);
1128 VK_LOADER_DATA _loader_data
;
1130 VkAllocationCallbacks alloc
;
1132 struct anv_instance
* instance
;
1133 uint32_t chipset_id
;
1135 struct gen_device_info info
;
1136 struct isl_device isl_dev
;
1139 bool can_chain_batches
;
1140 bool robust_buffer_access
;
1141 struct anv_device_extension_table enabled_extensions
;
1142 struct anv_device_dispatch_table dispatch
;
1144 pthread_mutex_t vma_mutex
;
1145 struct util_vma_heap vma_lo
;
1146 struct util_vma_heap vma_hi
;
1147 uint64_t vma_lo_available
;
1148 uint64_t vma_hi_available
;
1150 /** List of all anv_device_memory objects */
1151 struct list_head memory_objects
;
1153 struct anv_bo_pool batch_bo_pool
;
1155 struct anv_bo_cache bo_cache
;
1157 struct anv_state_pool dynamic_state_pool
;
1158 struct anv_state_pool instruction_state_pool
;
1159 struct anv_state_pool binding_table_pool
;
1160 struct anv_state_pool surface_state_pool
;
1162 struct anv_bo
* workaround_bo
;
1163 struct anv_bo
* trivial_batch_bo
;
1164 struct anv_bo
* hiz_clear_bo
;
1166 struct anv_pipeline_cache default_pipeline_cache
;
1167 struct blorp_context blorp
;
1169 struct anv_state border_colors
;
1171 struct anv_state slice_hash
;
1173 struct anv_queue queue
;
1175 struct anv_scratch_pool scratch_pool
;
1177 uint32_t default_mocs
;
1178 uint32_t external_mocs
;
1180 pthread_mutex_t mutex
;
1181 pthread_cond_t queue_submit
;
1184 struct gen_batch_decode_ctx decoder_ctx
;
1186 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1187 * the cmd_buffer's list.
1189 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1191 int perf_fd
; /* -1 if no opened */
1192 uint64_t perf_metric
; /* 0 if unset */
1194 struct gen_aux_map_context
*aux_map_ctx
;
1197 static inline struct anv_state_pool
*
1198 anv_binding_table_pool(struct anv_device
*device
)
1200 if (device
->instance
->physicalDevice
.use_softpin
)
1201 return &device
->binding_table_pool
;
1203 return &device
->surface_state_pool
;
1206 static inline struct anv_state
1207 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1208 if (device
->instance
->physicalDevice
.use_softpin
)
1209 return anv_state_pool_alloc(&device
->binding_table_pool
,
1210 device
->binding_table_pool
.block_size
, 0);
1212 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1216 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1217 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1220 static inline uint32_t
1221 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1223 if (bo
->is_external
)
1224 return device
->external_mocs
;
1226 return device
->default_mocs
;
1229 void anv_device_init_blorp(struct anv_device
*device
);
1230 void anv_device_finish_blorp(struct anv_device
*device
);
1232 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1233 const char *file
, int line
,
1234 const char *msg
, ...)
1235 anv_printflike(4, 5);
1236 #define anv_device_set_lost(dev, ...) \
1237 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1240 anv_device_is_lost(struct anv_device
*device
)
1242 return unlikely(device
->_lost
);
1245 VkResult
anv_device_execbuf(struct anv_device
*device
,
1246 struct drm_i915_gem_execbuffer2
*execbuf
,
1247 struct anv_bo
**execbuf_bos
);
1248 VkResult
anv_device_query_status(struct anv_device
*device
);
1251 enum anv_bo_alloc_flags
{
1252 /** Specifies that the BO must have a 32-bit address
1254 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1256 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1258 /** Specifies that the BO may be shared externally */
1259 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1261 /** Specifies that the BO should be mapped */
1262 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1264 /** Specifies that the BO should be snooped so we get coherency */
1265 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1267 /** Specifies that the BO should be captured in error states */
1268 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1270 /** Specifies that the BO will have an address assigned by the caller */
1271 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1273 /** Enables implicit synchronization on the BO
1275 * This is the opposite of EXEC_OBJECT_ASYNC.
1277 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1279 /** Enables implicit synchronization on the BO
1281 * This is equivalent to EXEC_OBJECT_WRITE.
1283 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1286 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1287 enum anv_bo_alloc_flags alloc_flags
,
1288 struct anv_bo
**bo
);
1289 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1290 void *host_ptr
, uint32_t size
,
1291 enum anv_bo_alloc_flags alloc_flags
,
1292 struct anv_bo
**bo_out
);
1293 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1294 enum anv_bo_alloc_flags alloc_flags
,
1295 struct anv_bo
**bo
);
1296 VkResult
anv_device_export_bo(struct anv_device
*device
,
1297 struct anv_bo
*bo
, int *fd_out
);
1298 void anv_device_release_bo(struct anv_device
*device
,
1301 static inline struct anv_bo
*
1302 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1304 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1307 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1308 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1311 void* anv_gem_mmap(struct anv_device
*device
,
1312 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1313 void anv_gem_munmap(void *p
, uint64_t size
);
1314 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1315 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1316 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1317 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1318 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1319 int anv_gem_execbuffer(struct anv_device
*device
,
1320 struct drm_i915_gem_execbuffer2
*execbuf
);
1321 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1322 uint32_t stride
, uint32_t tiling
);
1323 int anv_gem_create_context(struct anv_device
*device
);
1324 bool anv_gem_has_context_priority(int fd
);
1325 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1326 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1328 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1330 int anv_gem_get_param(int fd
, uint32_t param
);
1331 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1332 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1333 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1334 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1335 uint32_t *active
, uint32_t *pending
);
1336 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1337 int anv_gem_reg_read(struct anv_device
*device
,
1338 uint32_t offset
, uint64_t *result
);
1339 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1340 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1341 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1342 uint32_t read_domains
, uint32_t write_domain
);
1343 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1344 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1345 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1346 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1347 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1348 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1350 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1351 uint32_t handle
, int fd
);
1352 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1353 bool anv_gem_supports_syncobj_wait(int fd
);
1354 int anv_gem_syncobj_wait(struct anv_device
*device
,
1355 uint32_t *handles
, uint32_t num_handles
,
1356 int64_t abs_timeout_ns
, bool wait_all
);
1358 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1359 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1361 struct anv_reloc_list
{
1362 uint32_t num_relocs
;
1363 uint32_t array_length
;
1364 struct drm_i915_gem_relocation_entry
* relocs
;
1365 struct anv_bo
** reloc_bos
;
1370 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1371 const VkAllocationCallbacks
*alloc
);
1372 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1373 const VkAllocationCallbacks
*alloc
);
1375 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1376 const VkAllocationCallbacks
*alloc
,
1377 uint32_t offset
, struct anv_bo
*target_bo
,
1378 uint32_t delta
, uint64_t *address_u64_out
);
1380 struct anv_batch_bo
{
1381 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1382 struct list_head link
;
1386 /* Bytes actually consumed in this batch BO */
1389 struct anv_reloc_list relocs
;
1393 const VkAllocationCallbacks
* alloc
;
1399 struct anv_reloc_list
* relocs
;
1401 /* This callback is called (with the associated user data) in the event
1402 * that the batch runs out of space.
1404 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1408 * Current error status of the command buffer. Used to track inconsistent
1409 * or incomplete command buffer states that are the consequence of run-time
1410 * errors such as out of memory scenarios. We want to track this in the
1411 * batch because the command buffer object is not visible to some parts
1417 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1418 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1419 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1420 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1421 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1422 struct anv_batch
*batch
);
1424 static inline VkResult
1425 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1427 assert(error
!= VK_SUCCESS
);
1428 if (batch
->status
== VK_SUCCESS
)
1429 batch
->status
= error
;
1430 return batch
->status
;
1434 anv_batch_has_error(struct anv_batch
*batch
)
1436 return batch
->status
!= VK_SUCCESS
;
1439 struct anv_address
{
1444 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1447 anv_address_is_null(struct anv_address addr
)
1449 return addr
.bo
== NULL
&& addr
.offset
== 0;
1452 static inline uint64_t
1453 anv_address_physical(struct anv_address addr
)
1455 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1456 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1458 return gen_canonical_address(addr
.offset
);
1461 static inline struct anv_address
1462 anv_address_add(struct anv_address addr
, uint64_t offset
)
1464 addr
.offset
+= offset
;
1469 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1471 unsigned reloc_size
= 0;
1472 if (device
->info
.gen
>= 8) {
1473 reloc_size
= sizeof(uint64_t);
1474 *(uint64_t *)p
= gen_canonical_address(v
);
1476 reloc_size
= sizeof(uint32_t);
1480 if (flush
&& !device
->info
.has_llc
)
1481 gen_flush_range(p
, reloc_size
);
1484 static inline uint64_t
1485 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1486 const struct anv_address address
, uint32_t delta
)
1488 if (address
.bo
== NULL
) {
1489 return address
.offset
+ delta
;
1491 assert(batch
->start
<= location
&& location
< batch
->end
);
1493 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1497 #define __gen_address_type struct anv_address
1498 #define __gen_user_data struct anv_batch
1499 #define __gen_combine_address _anv_combine_address
1501 /* Wrapper macros needed to work around preprocessor argument issues. In
1502 * particular, arguments don't get pre-evaluated if they are concatenated.
1503 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1504 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1505 * We can work around this easily enough with these helpers.
1507 #define __anv_cmd_length(cmd) cmd ## _length
1508 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1509 #define __anv_cmd_header(cmd) cmd ## _header
1510 #define __anv_cmd_pack(cmd) cmd ## _pack
1511 #define __anv_reg_num(reg) reg ## _num
1513 #define anv_pack_struct(dst, struc, ...) do { \
1514 struct struc __template = { \
1517 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1518 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1521 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1522 void *__dst = anv_batch_emit_dwords(batch, n); \
1524 struct cmd __template = { \
1525 __anv_cmd_header(cmd), \
1526 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1529 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1534 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1538 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1539 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1542 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1543 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1544 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1547 #define anv_batch_emit(batch, cmd, name) \
1548 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1549 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1550 __builtin_expect(_dst != NULL, 1); \
1551 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1552 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1556 /* MEMORY_OBJECT_CONTROL_STATE:
1557 * .GraphicsDataTypeGFDT = 0,
1558 * .LLCCacheabilityControlLLCCC = 0,
1559 * .L3CacheabilityControlL3CC = 1,
1563 /* MEMORY_OBJECT_CONTROL_STATE:
1564 * .LLCeLLCCacheabilityControlLLCCC = 0,
1565 * .L3CacheabilityControlL3CC = 1,
1567 #define GEN75_MOCS 1
1569 /* MEMORY_OBJECT_CONTROL_STATE:
1570 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1571 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1572 * .AgeforQUADLRU = 0
1574 #define GEN8_MOCS 0x78
1576 /* MEMORY_OBJECT_CONTROL_STATE:
1577 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1578 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1579 * .AgeforQUADLRU = 0
1581 #define GEN8_EXTERNAL_MOCS 0x18
1583 /* Skylake: MOCS is now an index into an array of 62 different caching
1584 * configurations programmed by the kernel.
1587 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1588 #define GEN9_MOCS (2 << 1)
1590 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1591 #define GEN9_EXTERNAL_MOCS (1 << 1)
1593 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1594 #define GEN10_MOCS GEN9_MOCS
1595 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1597 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1598 #define GEN11_MOCS GEN9_MOCS
1599 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1601 /* TigerLake MOCS */
1602 #define GEN12_MOCS GEN9_MOCS
1603 /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
1604 #define GEN12_EXTERNAL_MOCS (3 << 1)
1606 struct anv_device_memory
{
1607 struct list_head link
;
1610 struct anv_memory_type
* type
;
1611 VkDeviceSize map_size
;
1614 /* If set, we are holding reference to AHardwareBuffer
1615 * which we must release when memory is freed.
1617 struct AHardwareBuffer
* ahw
;
1619 /* If set, this memory comes from a host pointer. */
1624 * Header for Vertex URB Entry (VUE)
1626 struct anv_vue_header
{
1628 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1629 uint32_t ViewportIndex
;
1633 /** Struct representing a sampled image descriptor
1635 * This descriptor layout is used for sampled images, bare sampler, and
1636 * combined image/sampler descriptors.
1638 struct anv_sampled_image_descriptor
{
1639 /** Bindless image handle
1641 * This is expected to already be shifted such that the 20-bit
1642 * SURFACE_STATE table index is in the top 20 bits.
1646 /** Bindless sampler handle
1648 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1649 * to the dynamic state base address.
1654 struct anv_texture_swizzle_descriptor
{
1657 * See also nir_intrinsic_channel_select_intel
1661 /** Unused padding to ensure the struct is a multiple of 64 bits */
1665 /** Struct representing a storage image descriptor */
1666 struct anv_storage_image_descriptor
{
1667 /** Bindless image handles
1669 * These are expected to already be shifted such that the 20-bit
1670 * SURFACE_STATE table index is in the top 20 bits.
1672 uint32_t read_write
;
1673 uint32_t write_only
;
1676 /** Struct representing a address/range descriptor
1678 * The fields of this struct correspond directly to the data layout of
1679 * nir_address_format_64bit_bounded_global addresses. The last field is the
1680 * offset in the NIR address so it must be zero so that when you load the
1681 * descriptor you get a pointer to the start of the range.
1683 struct anv_address_range_descriptor
{
1689 enum anv_descriptor_data
{
1690 /** The descriptor contains a BTI reference to a surface state */
1691 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1692 /** The descriptor contains a BTI reference to a sampler state */
1693 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1694 /** The descriptor contains an actual buffer view */
1695 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1696 /** The descriptor contains auxiliary image layout data */
1697 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1698 /** The descriptor contains auxiliary image layout data */
1699 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1700 /** anv_address_range_descriptor with a buffer address and range */
1701 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1702 /** Bindless surface handle */
1703 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1704 /** Storage image handles */
1705 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1706 /** Storage image handles */
1707 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1710 struct anv_descriptor_set_binding_layout
{
1712 /* The type of the descriptors in this binding */
1713 VkDescriptorType type
;
1716 /* Flags provided when this binding was created */
1717 VkDescriptorBindingFlagsEXT flags
;
1719 /* Bitfield representing the type of data this descriptor contains */
1720 enum anv_descriptor_data data
;
1722 /* Maximum number of YCbCr texture/sampler planes */
1723 uint8_t max_plane_count
;
1725 /* Number of array elements in this binding (or size in bytes for inline
1728 uint16_t array_size
;
1730 /* Index into the flattend descriptor set */
1731 uint16_t descriptor_index
;
1733 /* Index into the dynamic state array for a dynamic buffer */
1734 int16_t dynamic_offset_index
;
1736 /* Index into the descriptor set buffer views */
1737 int16_t buffer_view_index
;
1739 /* Offset into the descriptor buffer where this descriptor lives */
1740 uint32_t descriptor_offset
;
1742 /* Immutable samplers (or NULL if no immutable samplers) */
1743 struct anv_sampler
**immutable_samplers
;
1746 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1748 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1749 VkDescriptorType type
);
1751 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1752 const struct anv_descriptor_set_binding_layout
*binding
,
1755 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1756 const struct anv_descriptor_set_binding_layout
*binding
,
1759 struct anv_descriptor_set_layout
{
1760 /* Descriptor set layouts can be destroyed at almost any time */
1763 /* Number of bindings in this descriptor set */
1764 uint16_t binding_count
;
1766 /* Total size of the descriptor set with room for all array entries */
1769 /* Shader stages affected by this descriptor set */
1770 uint16_t shader_stages
;
1772 /* Number of buffer views in this descriptor set */
1773 uint16_t buffer_view_count
;
1775 /* Number of dynamic offsets used by this descriptor set */
1776 uint16_t dynamic_offset_count
;
1778 /* Size of the descriptor buffer for this descriptor set */
1779 uint32_t descriptor_buffer_size
;
1781 /* Bindings in this descriptor set */
1782 struct anv_descriptor_set_binding_layout binding
[0];
1786 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1788 assert(layout
&& layout
->ref_cnt
>= 1);
1789 p_atomic_inc(&layout
->ref_cnt
);
1793 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1794 struct anv_descriptor_set_layout
*layout
)
1796 assert(layout
&& layout
->ref_cnt
>= 1);
1797 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1798 vk_free(&device
->alloc
, layout
);
1801 struct anv_descriptor
{
1802 VkDescriptorType type
;
1806 VkImageLayout layout
;
1807 struct anv_image_view
*image_view
;
1808 struct anv_sampler
*sampler
;
1812 struct anv_buffer
*buffer
;
1817 struct anv_buffer_view
*buffer_view
;
1821 struct anv_descriptor_set
{
1822 struct anv_descriptor_pool
*pool
;
1823 struct anv_descriptor_set_layout
*layout
;
1826 /* State relative to anv_descriptor_pool::bo */
1827 struct anv_state desc_mem
;
1828 /* Surface state for the descriptor buffer */
1829 struct anv_state desc_surface_state
;
1831 uint32_t buffer_view_count
;
1832 struct anv_buffer_view
*buffer_views
;
1834 /* Link to descriptor pool's desc_sets list . */
1835 struct list_head pool_link
;
1837 struct anv_descriptor descriptors
[0];
1840 struct anv_buffer_view
{
1841 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1842 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1844 struct anv_address address
;
1846 struct anv_state surface_state
;
1847 struct anv_state storage_surface_state
;
1848 struct anv_state writeonly_storage_surface_state
;
1850 struct brw_image_param storage_image_param
;
1853 struct anv_push_descriptor_set
{
1854 struct anv_descriptor_set set
;
1856 /* Put this field right behind anv_descriptor_set so it fills up the
1857 * descriptors[0] field. */
1858 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1860 /** True if the descriptor set buffer has been referenced by a draw or
1863 bool set_used_on_gpu
;
1865 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1868 struct anv_descriptor_pool
{
1874 struct util_vma_heap bo_heap
;
1876 struct anv_state_stream surface_state_stream
;
1877 void *surface_state_free_list
;
1879 struct list_head desc_sets
;
1884 enum anv_descriptor_template_entry_type
{
1885 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1886 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1887 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1890 struct anv_descriptor_template_entry
{
1891 /* The type of descriptor in this entry */
1892 VkDescriptorType type
;
1894 /* Binding in the descriptor set */
1897 /* Offset at which to write into the descriptor set binding */
1898 uint32_t array_element
;
1900 /* Number of elements to write into the descriptor set binding */
1901 uint32_t array_count
;
1903 /* Offset into the user provided data */
1906 /* Stride between elements into the user provided data */
1910 struct anv_descriptor_update_template
{
1911 VkPipelineBindPoint bind_point
;
1913 /* The descriptor set this template corresponds to. This value is only
1914 * valid if the template was created with the templateType
1915 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1919 /* Number of entries in this template */
1920 uint32_t entry_count
;
1922 /* Entries of the template */
1923 struct anv_descriptor_template_entry entries
[0];
1927 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1930 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1931 struct anv_descriptor_set
*set
,
1932 const VkDescriptorImageInfo
* const info
,
1933 VkDescriptorType type
,
1938 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1939 struct anv_descriptor_set
*set
,
1940 VkDescriptorType type
,
1941 struct anv_buffer_view
*buffer_view
,
1946 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1947 struct anv_descriptor_set
*set
,
1948 struct anv_state_stream
*alloc_stream
,
1949 VkDescriptorType type
,
1950 struct anv_buffer
*buffer
,
1953 VkDeviceSize offset
,
1954 VkDeviceSize range
);
1956 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1957 struct anv_descriptor_set
*set
,
1964 anv_descriptor_set_write_template(struct anv_device
*device
,
1965 struct anv_descriptor_set
*set
,
1966 struct anv_state_stream
*alloc_stream
,
1967 const struct anv_descriptor_update_template
*template,
1971 anv_descriptor_set_create(struct anv_device
*device
,
1972 struct anv_descriptor_pool
*pool
,
1973 struct anv_descriptor_set_layout
*layout
,
1974 struct anv_descriptor_set
**out_set
);
1977 anv_descriptor_set_destroy(struct anv_device
*device
,
1978 struct anv_descriptor_pool
*pool
,
1979 struct anv_descriptor_set
*set
);
1981 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
1982 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
1983 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1984 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1986 struct anv_pipeline_binding
{
1987 /* The descriptor set this surface corresponds to. The special value of
1988 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1989 * to a color attachment and not a regular descriptor.
1993 /* Binding in the descriptor set */
1996 /* Index in the binding */
1999 /* Plane in the binding index */
2002 /* Input attachment index (relative to the subpass) */
2003 uint8_t input_attachment_index
;
2005 /* For a storage image, whether it is write-only */
2009 struct anv_pipeline_layout
{
2011 struct anv_descriptor_set_layout
*layout
;
2012 uint32_t dynamic_offset_start
;
2017 unsigned char sha1
[20];
2021 struct anv_device
* device
;
2024 VkBufferUsageFlags usage
;
2026 /* Set when bound */
2027 struct anv_address address
;
2030 static inline uint64_t
2031 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2033 assert(offset
<= buffer
->size
);
2034 if (range
== VK_WHOLE_SIZE
) {
2035 return buffer
->size
- offset
;
2037 assert(range
+ offset
>= range
);
2038 assert(range
+ offset
<= buffer
->size
);
2043 enum anv_cmd_dirty_bits
{
2044 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2045 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2046 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2047 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2048 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2049 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2050 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2051 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2052 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2053 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2054 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2055 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2056 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2057 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2059 typedef uint32_t anv_cmd_dirty_mask_t
;
2061 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2062 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2063 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2064 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2065 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2066 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2067 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2068 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2069 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2070 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2071 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2073 static inline enum anv_cmd_dirty_bits
2074 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2077 case VK_DYNAMIC_STATE_VIEWPORT
:
2078 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2079 case VK_DYNAMIC_STATE_SCISSOR
:
2080 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2081 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2082 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2083 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2084 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2085 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2086 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2087 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2088 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2089 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2090 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2091 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2092 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2093 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2094 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2095 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2096 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2098 assert(!"Unsupported dynamic state");
2104 enum anv_pipe_bits
{
2105 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2106 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2107 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2108 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2109 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2110 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2111 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2112 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2113 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2114 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2115 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2116 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2118 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2119 * a flush has happened but not a CS stall. The next time we do any sort
2120 * of invalidation we need to insert a CS stall at that time. Otherwise,
2121 * we would have to CS stall on every flush which could be bad.
2123 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2125 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2126 * target operations related to transfer commands with VkBuffer as
2127 * destination are ongoing. Some operations like copies on the command
2128 * streamer might need to be aware of this to trigger the appropriate stall
2129 * before they can proceed with the copy.
2131 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2134 #define ANV_PIPE_FLUSH_BITS ( \
2135 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2136 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2137 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2138 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2140 #define ANV_PIPE_STALL_BITS ( \
2141 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2142 ANV_PIPE_DEPTH_STALL_BIT | \
2143 ANV_PIPE_CS_STALL_BIT)
2145 #define ANV_PIPE_INVALIDATE_BITS ( \
2146 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2147 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2148 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2149 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2150 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2151 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2153 static inline enum anv_pipe_bits
2154 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2156 enum anv_pipe_bits pipe_bits
= 0;
2159 for_each_bit(b
, flags
) {
2160 switch ((VkAccessFlagBits
)(1 << b
)) {
2161 case VK_ACCESS_SHADER_WRITE_BIT
:
2162 /* We're transitioning a buffer that was previously used as write
2163 * destination through the data port. To make its content available
2164 * to future operations, flush the data cache.
2166 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2168 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2169 /* We're transitioning a buffer that was previously used as render
2170 * target. To make its content available to future operations, flush
2171 * the render target cache.
2173 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2175 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2176 /* We're transitioning a buffer that was previously used as depth
2177 * buffer. To make its content available to future operations, flush
2180 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2182 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2183 /* We're transitioning a buffer that was previously used as a
2184 * transfer write destination. Generic write operations include color
2185 * & depth operations as well as buffer operations like :
2186 * - vkCmdClearColorImage()
2187 * - vkCmdClearDepthStencilImage()
2188 * - vkCmdBlitImage()
2189 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2191 * Most of these operations are implemented using Blorp which writes
2192 * through the render target, so flush that cache to make it visible
2193 * to future operations. And for depth related operations we also
2194 * need to flush the depth cache.
2196 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2197 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2199 case VK_ACCESS_MEMORY_WRITE_BIT
:
2200 /* We're transitioning a buffer for generic write operations. Flush
2203 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2206 break; /* Nothing to do */
2213 static inline enum anv_pipe_bits
2214 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2216 enum anv_pipe_bits pipe_bits
= 0;
2219 for_each_bit(b
, flags
) {
2220 switch ((VkAccessFlagBits
)(1 << b
)) {
2221 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2222 /* Indirect draw commands take a buffer as input that we're going to
2223 * read from the command streamer to load some of the HW registers
2224 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2225 * command streamer stall so that all the cache flushes have
2226 * completed before the command streamer loads from memory.
2228 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2229 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2230 * through a vertex buffer, so invalidate that cache.
2232 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2233 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2234 * UBO from the buffer, so we need to invalidate constant cache.
2236 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2238 case VK_ACCESS_INDEX_READ_BIT
:
2239 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2240 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2241 * commands, so we invalidate the VF cache to make sure there is no
2242 * stale data when we start rendering.
2244 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2246 case VK_ACCESS_UNIFORM_READ_BIT
:
2247 /* We transitioning a buffer to be used as uniform data. Because
2248 * uniform is accessed through the data port & sampler, we need to
2249 * invalidate the texture cache (sampler) & constant cache (data
2250 * port) to avoid stale data.
2252 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2253 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2255 case VK_ACCESS_SHADER_READ_BIT
:
2256 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2257 case VK_ACCESS_TRANSFER_READ_BIT
:
2258 /* Transitioning a buffer to be read through the sampler, so
2259 * invalidate the texture cache, we don't want any stale data.
2261 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2263 case VK_ACCESS_MEMORY_READ_BIT
:
2264 /* Transitioning a buffer for generic read, invalidate all the
2267 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2269 case VK_ACCESS_MEMORY_WRITE_BIT
:
2270 /* Generic write, make sure all previously written things land in
2273 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2275 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2276 /* Transitioning a buffer for conditional rendering. We'll load the
2277 * content of this buffer into HW registers using the command
2278 * streamer, so we need to stall the command streamer to make sure
2279 * any in-flight flush operations have completed.
2281 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2284 break; /* Nothing to do */
2291 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2292 VK_IMAGE_ASPECT_COLOR_BIT | \
2293 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2294 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2295 VK_IMAGE_ASPECT_PLANE_2_BIT)
2296 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2297 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2298 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2299 VK_IMAGE_ASPECT_PLANE_2_BIT)
2301 struct anv_vertex_binding
{
2302 struct anv_buffer
* buffer
;
2303 VkDeviceSize offset
;
2306 struct anv_xfb_binding
{
2307 struct anv_buffer
* buffer
;
2308 VkDeviceSize offset
;
2312 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
2313 #define ANV_PARAM_IS_PUSH(param) ((uint32_t)(param) >> 16 == 1)
2314 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2316 #define ANV_PARAM_DYN_OFFSET(offset) ((2 << 16) | (uint32_t)(offset))
2317 #define ANV_PARAM_IS_DYN_OFFSET(param) ((uint32_t)(param) >> 16 == 2)
2318 #define ANV_PARAM_DYN_OFFSET_IDX(param) ((param) & 0xffff)
2320 struct anv_push_constants
{
2321 /* Push constant data provided by the client through vkPushConstants */
2322 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2324 /* Used for vkCmdDispatchBase */
2325 uint32_t base_work_group_id
[3];
2328 struct anv_dynamic_state
{
2331 VkViewport viewports
[MAX_VIEWPORTS
];
2336 VkRect2D scissors
[MAX_SCISSORS
];
2347 float blend_constants
[4];
2357 } stencil_compare_mask
;
2362 } stencil_write_mask
;
2367 } stencil_reference
;
2375 extern const struct anv_dynamic_state default_dynamic_state
;
2377 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2378 const struct anv_dynamic_state
*src
,
2379 uint32_t copy_mask
);
2381 struct anv_surface_state
{
2382 struct anv_state state
;
2383 /** Address of the surface referred to by this state
2385 * This address is relative to the start of the BO.
2387 struct anv_address address
;
2388 /* Address of the aux surface, if any
2390 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2392 * With the exception of gen8, the bottom 12 bits of this address' offset
2393 * include extra aux information.
2395 struct anv_address aux_address
;
2396 /* Address of the clear color, if any
2398 * This address is relative to the start of the BO.
2400 struct anv_address clear_address
;
2404 * Attachment state when recording a renderpass instance.
2406 * The clear value is valid only if there exists a pending clear.
2408 struct anv_attachment_state
{
2409 enum isl_aux_usage aux_usage
;
2410 enum isl_aux_usage input_aux_usage
;
2411 struct anv_surface_state color
;
2412 struct anv_surface_state input
;
2414 VkImageLayout current_layout
;
2415 VkImageAspectFlags pending_clear_aspects
;
2416 VkImageAspectFlags pending_load_aspects
;
2418 VkClearValue clear_value
;
2419 bool clear_color_is_zero_one
;
2420 bool clear_color_is_zero
;
2422 /* When multiview is active, attachments with a renderpass clear
2423 * operation have their respective layers cleared on the first
2424 * subpass that uses them, and only in that subpass. We keep track
2425 * of this using a bitfield to indicate which layers of an attachment
2426 * have not been cleared yet when multiview is active.
2428 uint32_t pending_clear_views
;
2429 struct anv_image_view
* image_view
;
2432 /** State tracking for particular pipeline bind point
2434 * This struct is the base struct for anv_cmd_graphics_state and
2435 * anv_cmd_compute_state. These are used to track state which is bound to a
2436 * particular type of pipeline. Generic state that applies per-stage such as
2437 * binding table offsets and push constants is tracked generically with a
2438 * per-stage array in anv_cmd_state.
2440 struct anv_cmd_pipeline_state
{
2441 struct anv_pipeline
*pipeline
;
2442 struct anv_pipeline_layout
*layout
;
2444 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2445 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2447 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2450 /** State tracking for graphics pipeline
2452 * This has anv_cmd_pipeline_state as a base struct to track things which get
2453 * bound to a graphics pipeline. Along with general pipeline bind point state
2454 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2455 * state which is graphics-specific.
2457 struct anv_cmd_graphics_state
{
2458 struct anv_cmd_pipeline_state base
;
2460 anv_cmd_dirty_mask_t dirty
;
2463 struct anv_dynamic_state dynamic
;
2466 struct anv_buffer
*index_buffer
;
2467 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2468 uint32_t index_offset
;
2472 /** State tracking for compute pipeline
2474 * This has anv_cmd_pipeline_state as a base struct to track things which get
2475 * bound to a compute pipeline. Along with general pipeline bind point state
2476 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2477 * state which is compute-specific.
2479 struct anv_cmd_compute_state
{
2480 struct anv_cmd_pipeline_state base
;
2482 bool pipeline_dirty
;
2484 struct anv_address num_workgroups
;
2487 /** State required while building cmd buffer */
2488 struct anv_cmd_state
{
2489 /* PIPELINE_SELECT.PipelineSelection */
2490 uint32_t current_pipeline
;
2491 const struct gen_l3_config
* current_l3_config
;
2492 uint32_t last_aux_map_state
;
2494 struct anv_cmd_graphics_state gfx
;
2495 struct anv_cmd_compute_state compute
;
2497 enum anv_pipe_bits pending_pipe_bits
;
2498 VkShaderStageFlags descriptors_dirty
;
2499 VkShaderStageFlags push_constants_dirty
;
2501 struct anv_framebuffer
* framebuffer
;
2502 struct anv_render_pass
* pass
;
2503 struct anv_subpass
* subpass
;
2504 VkRect2D render_area
;
2505 uint32_t restart_index
;
2506 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2508 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2509 VkShaderStageFlags push_constant_stages
;
2510 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2511 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2512 struct anv_state samplers
[MESA_SHADER_STAGES
];
2515 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2516 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2517 * and before invoking the secondary in ExecuteCommands.
2519 bool pma_fix_enabled
;
2522 * Whether or not we know for certain that HiZ is enabled for the current
2523 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2524 * enabled or not, this will be false.
2528 bool conditional_render_enabled
;
2531 * Last rendering scale argument provided to
2532 * genX(cmd_buffer_emit_hashing_mode)().
2534 unsigned current_hash_scale
;
2537 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2538 * valid only when recording a render pass instance.
2540 struct anv_attachment_state
* attachments
;
2543 * Surface states for color render targets. These are stored in a single
2544 * flat array. For depth-stencil attachments, the surface state is simply
2547 struct anv_state render_pass_states
;
2550 * A null surface state of the right size to match the framebuffer. This
2551 * is one of the states in render_pass_states.
2553 struct anv_state null_surface_state
;
2556 struct anv_cmd_pool
{
2557 VkAllocationCallbacks alloc
;
2558 struct list_head cmd_buffers
;
2561 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2563 enum anv_cmd_buffer_exec_mode
{
2564 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2565 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2566 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2567 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2568 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2571 struct anv_cmd_buffer
{
2572 VK_LOADER_DATA _loader_data
;
2574 struct anv_device
* device
;
2576 struct anv_cmd_pool
* pool
;
2577 struct list_head pool_link
;
2579 struct anv_batch batch
;
2581 /* Fields required for the actual chain of anv_batch_bo's.
2583 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2585 struct list_head batch_bos
;
2586 enum anv_cmd_buffer_exec_mode exec_mode
;
2588 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2589 * referenced by this command buffer
2591 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2593 struct u_vector seen_bbos
;
2595 /* A vector of int32_t's for every block of binding tables.
2597 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2599 struct u_vector bt_block_states
;
2602 struct anv_reloc_list surface_relocs
;
2603 /** Last seen surface state block pool center bo offset */
2604 uint32_t last_ss_pool_center
;
2606 /* Serial for tracking buffer completion */
2609 /* Stream objects for storing temporary data */
2610 struct anv_state_stream surface_state_stream
;
2611 struct anv_state_stream dynamic_state_stream
;
2613 VkCommandBufferUsageFlags usage_flags
;
2614 VkCommandBufferLevel level
;
2616 struct anv_cmd_state state
;
2618 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2619 uint64_t intel_perf_marker
;
2622 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2623 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2624 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2625 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2626 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2627 struct anv_cmd_buffer
*secondary
);
2628 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2629 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2630 struct anv_cmd_buffer
*cmd_buffer
,
2631 const VkSemaphore
*in_semaphores
,
2632 uint32_t num_in_semaphores
,
2633 const VkSemaphore
*out_semaphores
,
2634 uint32_t num_out_semaphores
,
2637 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2639 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2640 const void *data
, uint32_t size
, uint32_t alignment
);
2641 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2642 uint32_t *a
, uint32_t *b
,
2643 uint32_t dwords
, uint32_t alignment
);
2646 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2648 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2649 uint32_t entries
, uint32_t *state_offset
);
2651 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2653 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2654 uint32_t size
, uint32_t alignment
);
2657 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2659 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2660 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2661 bool depth_clamp_enable
);
2662 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2664 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2665 struct anv_render_pass
*pass
,
2666 struct anv_framebuffer
*framebuffer
,
2667 const VkClearValue
*clear_values
);
2669 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2672 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2673 gl_shader_stage stage
);
2675 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2677 const struct anv_image_view
*
2678 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2681 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2682 uint32_t num_entries
,
2683 uint32_t *state_offset
,
2684 struct anv_state
*bt_state
);
2686 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2688 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2690 enum anv_fence_type
{
2691 ANV_FENCE_TYPE_NONE
= 0,
2693 ANV_FENCE_TYPE_SYNCOBJ
,
2697 enum anv_bo_fence_state
{
2698 /** Indicates that this is a new (or newly reset fence) */
2699 ANV_BO_FENCE_STATE_RESET
,
2701 /** Indicates that this fence has been submitted to the GPU but is still
2702 * (as far as we know) in use by the GPU.
2704 ANV_BO_FENCE_STATE_SUBMITTED
,
2706 ANV_BO_FENCE_STATE_SIGNALED
,
2709 struct anv_fence_impl
{
2710 enum anv_fence_type type
;
2713 /** Fence implementation for BO fences
2715 * These fences use a BO and a set of CPU-tracked state flags. The BO
2716 * is added to the object list of the last execbuf call in a QueueSubmit
2717 * and is marked EXEC_WRITE. The state flags track when the BO has been
2718 * submitted to the kernel. We need to do this because Vulkan lets you
2719 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2720 * will say it's idle in this case.
2724 enum anv_bo_fence_state state
;
2727 /** DRM syncobj handle for syncobj-based fences */
2731 struct wsi_fence
*fence_wsi
;
2736 /* Permanent fence state. Every fence has some form of permanent state
2737 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2738 * cross-process fences) or it could just be a dummy for use internally.
2740 struct anv_fence_impl permanent
;
2742 /* Temporary fence state. A fence *may* have temporary state. That state
2743 * is added to the fence by an import operation and is reset back to
2744 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2745 * state cannot be signaled because the fence must already be signaled
2746 * before the temporary state can be exported from the fence in the other
2747 * process and imported here.
2749 struct anv_fence_impl temporary
;
2754 struct anv_state state
;
2757 enum anv_semaphore_type
{
2758 ANV_SEMAPHORE_TYPE_NONE
= 0,
2759 ANV_SEMAPHORE_TYPE_DUMMY
,
2760 ANV_SEMAPHORE_TYPE_BO
,
2761 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2762 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2765 struct anv_semaphore_impl
{
2766 enum anv_semaphore_type type
;
2769 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2770 * This BO will be added to the object list on any execbuf2 calls for
2771 * which this semaphore is used as a wait or signal fence. When used as
2772 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2776 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2777 * If the semaphore is in the unsignaled state due to either just being
2778 * created or because it has been used for a wait, fd will be -1.
2782 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2783 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2784 * import so we don't need to bother with a userspace cache.
2790 struct anv_semaphore
{
2791 /* Permanent semaphore state. Every semaphore has some form of permanent
2792 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2793 * (for cross-process semaphores0 or it could just be a dummy for use
2796 struct anv_semaphore_impl permanent
;
2798 /* Temporary semaphore state. A semaphore *may* have temporary state.
2799 * That state is added to the semaphore by an import operation and is reset
2800 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2801 * semaphore with temporary state cannot be signaled because the semaphore
2802 * must already be signaled before the temporary state can be exported from
2803 * the semaphore in the other process and imported here.
2805 struct anv_semaphore_impl temporary
;
2808 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2809 struct anv_semaphore
*semaphore
);
2811 struct anv_shader_module
{
2812 unsigned char sha1
[20];
2817 static inline gl_shader_stage
2818 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2820 assert(__builtin_popcount(vk_stage
) == 1);
2821 return ffs(vk_stage
) - 1;
2824 static inline VkShaderStageFlagBits
2825 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2827 return (1 << mesa_stage
);
2830 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2832 #define anv_foreach_stage(stage, stage_bits) \
2833 for (gl_shader_stage stage, \
2834 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2835 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2836 __tmp &= ~(1 << (stage)))
2838 struct anv_pipeline_bind_map
{
2839 uint32_t surface_count
;
2840 uint32_t sampler_count
;
2842 struct anv_pipeline_binding
* surface_to_descriptor
;
2843 struct anv_pipeline_binding
* sampler_to_descriptor
;
2846 struct anv_shader_bin_key
{
2851 struct anv_shader_bin
{
2854 const struct anv_shader_bin_key
*key
;
2856 struct anv_state kernel
;
2857 uint32_t kernel_size
;
2859 struct anv_state constant_data
;
2860 uint32_t constant_data_size
;
2862 const struct brw_stage_prog_data
*prog_data
;
2863 uint32_t prog_data_size
;
2865 struct brw_compile_stats stats
[3];
2868 struct nir_xfb_info
*xfb_info
;
2870 struct anv_pipeline_bind_map bind_map
;
2873 struct anv_shader_bin
*
2874 anv_shader_bin_create(struct anv_device
*device
,
2875 const void *key
, uint32_t key_size
,
2876 const void *kernel
, uint32_t kernel_size
,
2877 const void *constant_data
, uint32_t constant_data_size
,
2878 const struct brw_stage_prog_data
*prog_data
,
2879 uint32_t prog_data_size
, const void *prog_data_param
,
2880 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
2881 const struct nir_xfb_info
*xfb_info
,
2882 const struct anv_pipeline_bind_map
*bind_map
);
2885 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2888 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2890 assert(shader
&& shader
->ref_cnt
>= 1);
2891 p_atomic_inc(&shader
->ref_cnt
);
2895 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2897 assert(shader
&& shader
->ref_cnt
>= 1);
2898 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2899 anv_shader_bin_destroy(device
, shader
);
2902 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
2903 #define MAX_PIPELINE_EXECUTABLES 7
2905 struct anv_pipeline_executable
{
2906 gl_shader_stage stage
;
2908 struct brw_compile_stats stats
;
2914 struct anv_pipeline
{
2915 struct anv_device
* device
;
2916 struct anv_batch batch
;
2917 uint32_t batch_data
[512];
2918 struct anv_reloc_list batch_relocs
;
2919 anv_cmd_dirty_mask_t dynamic_state_mask
;
2920 struct anv_dynamic_state dynamic_state
;
2924 VkPipelineCreateFlags flags
;
2925 struct anv_subpass
* subpass
;
2927 bool needs_data_cache
;
2929 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2931 uint32_t num_executables
;
2932 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
2935 const struct gen_l3_config
* l3_config
;
2936 uint32_t total_size
;
2939 VkShaderStageFlags active_stages
;
2940 struct anv_state blend_state
;
2943 struct anv_pipeline_vertex_binding
{
2946 uint32_t instance_divisor
;
2951 bool primitive_restart
;
2954 uint32_t cs_right_mask
;
2957 bool depth_test_enable
;
2958 bool writes_stencil
;
2959 bool stencil_test_enable
;
2960 bool depth_clamp_enable
;
2961 bool depth_clip_enable
;
2962 bool sample_shading_enable
;
2964 bool depth_bounds_test_enable
;
2968 uint32_t depth_stencil_state
[3];
2974 uint32_t wm_depth_stencil
[3];
2978 uint32_t wm_depth_stencil
[4];
2981 uint32_t interface_descriptor_data
[8];
2985 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2986 gl_shader_stage stage
)
2988 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2991 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2992 static inline const struct brw_##prefix##_prog_data * \
2993 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2995 if (anv_pipeline_has_stage(pipeline, stage)) { \
2996 return (const struct brw_##prefix##_prog_data *) \
2997 pipeline->shaders[stage]->prog_data; \
3003 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3004 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3005 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3006 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3007 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3008 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
3010 static inline const struct brw_vue_prog_data
*
3011 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
3013 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3014 return &get_gs_prog_data(pipeline
)->base
;
3015 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3016 return &get_tes_prog_data(pipeline
)->base
;
3018 return &get_vs_prog_data(pipeline
)->base
;
3022 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
3023 struct anv_pipeline_cache
*cache
,
3024 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3025 const VkAllocationCallbacks
*alloc
);
3028 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
3029 struct anv_pipeline_cache
*cache
,
3030 const VkComputePipelineCreateInfo
*info
,
3031 const struct anv_shader_module
*module
,
3032 const char *entrypoint
,
3033 const VkSpecializationInfo
*spec_info
);
3035 struct anv_format_plane
{
3036 enum isl_format isl_format
:16;
3037 struct isl_swizzle swizzle
;
3039 /* Whether this plane contains chroma channels */
3042 /* For downscaling of YUV planes */
3043 uint8_t denominator_scales
[2];
3045 /* How to map sampled ycbcr planes to a single 4 component element. */
3046 struct isl_swizzle ycbcr_swizzle
;
3048 /* What aspect is associated to this plane */
3049 VkImageAspectFlags aspect
;
3054 struct anv_format_plane planes
[3];
3060 static inline uint32_t
3061 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3062 VkImageAspectFlags aspect_mask
)
3064 switch (aspect_mask
) {
3065 case VK_IMAGE_ASPECT_COLOR_BIT
:
3066 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3067 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3069 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3070 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3073 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3075 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3078 /* Purposefully assert with depth/stencil aspects. */
3079 unreachable("invalid image aspect");
3083 static inline VkImageAspectFlags
3084 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3087 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3088 if (util_bitcount(image_aspects
) > 1)
3089 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3090 return VK_IMAGE_ASPECT_COLOR_BIT
;
3092 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3093 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3094 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3095 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3098 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3099 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3101 const struct anv_format
*
3102 anv_get_format(VkFormat format
);
3104 static inline uint32_t
3105 anv_get_format_planes(VkFormat vk_format
)
3107 const struct anv_format
*format
= anv_get_format(vk_format
);
3109 return format
!= NULL
? format
->n_planes
: 0;
3112 struct anv_format_plane
3113 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3114 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3116 static inline enum isl_format
3117 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3118 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3120 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3123 static inline struct isl_swizzle
3124 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3126 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3127 * RGB as RGBA for texturing
3129 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3130 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3132 /* But it doesn't matter what we render to that channel */
3133 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3139 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3142 * Subsurface of an anv_image.
3144 struct anv_surface
{
3145 /** Valid only if isl_surf::size_B > 0. */
3146 struct isl_surf isl
;
3149 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3155 VkImageType type
; /**< VkImageCreateInfo::imageType */
3156 /* The original VkFormat provided by the client. This may not match any
3157 * of the actual surface formats.
3160 const struct anv_format
*format
;
3162 VkImageAspectFlags aspects
;
3165 uint32_t array_size
;
3166 uint32_t samples
; /**< VkImageCreateInfo::samples */
3168 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3169 VkImageUsageFlags stencil_usage
;
3170 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3171 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3173 /** True if this is needs to be bound to an appropriately tiled BO.
3175 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3176 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3177 * we require a dedicated allocation so that we can know to allocate a
3180 bool needs_set_tiling
;
3183 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3184 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3186 uint64_t drm_format_mod
;
3191 /* Whether the image is made of several underlying buffer objects rather a
3192 * single one with different offsets.
3196 /* All the formats that can be used when creating views of this image
3197 * are CCS_E compatible.
3199 bool ccs_e_compatible
;
3201 /* Image was created with external format. */
3202 bool external_format
;
3207 * For each foo, anv_image::planes[x].surface is valid if and only if
3208 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3209 * to figure the number associated with a given aspect.
3211 * The hardware requires that the depth buffer and stencil buffer be
3212 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3213 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3214 * allocate the depth and stencil buffers as separate surfaces in the same
3219 * -----------------------
3221 * ----------------------- |
3222 * | shadow surface0 | |
3223 * ----------------------- | Plane 0
3224 * | aux surface0 | |
3225 * ----------------------- |
3226 * | fast clear colors0 | \|/
3227 * -----------------------
3229 * ----------------------- |
3230 * | shadow surface1 | |
3231 * ----------------------- | Plane 1
3232 * | aux surface1 | |
3233 * ----------------------- |
3234 * | fast clear colors1 | \|/
3235 * -----------------------
3238 * -----------------------
3242 * Offset of the entire plane (whenever the image is disjoint this is
3250 struct anv_surface surface
;
3253 * A surface which shadows the main surface and may have different
3254 * tiling. This is used for sampling using a tiling that isn't supported
3255 * for other operations.
3257 struct anv_surface shadow_surface
;
3260 * For color images, this is the aux usage for this image when not used
3261 * as a color attachment.
3263 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3264 * image has a HiZ buffer.
3266 enum isl_aux_usage aux_usage
;
3268 struct anv_surface aux_surface
;
3271 * Offset of the fast clear state (used to compute the
3272 * fast_clear_state_offset of the following planes).
3274 uint32_t fast_clear_state_offset
;
3277 * BO associated with this plane, set when bound.
3279 struct anv_address address
;
3282 * Address of the main surface used to fill the aux map table. This is
3283 * used at destruction of the image since the Vulkan spec does not
3284 * guarantee that the address.bo field we still be valid at destruction.
3286 uint64_t aux_map_surface_address
;
3289 * When destroying the image, also free the bo.
3295 /* The ordering of this enum is important */
3296 enum anv_fast_clear_type
{
3297 /** Image does not have/support any fast-clear blocks */
3298 ANV_FAST_CLEAR_NONE
= 0,
3299 /** Image has/supports fast-clear but only to the default value */
3300 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3301 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3302 ANV_FAST_CLEAR_ANY
= 2,
3305 /* Returns the number of auxiliary buffer levels attached to an image. */
3306 static inline uint8_t
3307 anv_image_aux_levels(const struct anv_image
* const image
,
3308 VkImageAspectFlagBits aspect
)
3310 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3312 /* The Gen12 CCS aux surface is represented with only one level. */
3313 const uint8_t aux_logical_levels
=
3314 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3315 image
->planes
[plane
].surface
.isl
.levels
:
3316 image
->planes
[plane
].aux_surface
.isl
.levels
;
3318 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3319 aux_logical_levels
: 0;
3322 /* Returns the number of auxiliary buffer layers attached to an image. */
3323 static inline uint32_t
3324 anv_image_aux_layers(const struct anv_image
* const image
,
3325 VkImageAspectFlagBits aspect
,
3326 const uint8_t miplevel
)
3330 /* The miplevel must exist in the main buffer. */
3331 assert(miplevel
< image
->levels
);
3333 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3334 /* There are no layers with auxiliary data because the miplevel has no
3339 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3341 /* The Gen12 CCS aux surface is represented with only one layer. */
3342 const struct isl_extent4d
*aux_logical_level0_px
=
3343 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3344 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3345 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3347 return MAX2(aux_logical_level0_px
->array_len
,
3348 aux_logical_level0_px
->depth
>> miplevel
);
3352 static inline struct anv_address
3353 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3354 const struct anv_image
*image
,
3355 VkImageAspectFlagBits aspect
)
3357 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3359 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3360 return anv_address_add(image
->planes
[plane
].address
,
3361 image
->planes
[plane
].fast_clear_state_offset
);
3364 static inline struct anv_address
3365 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3366 const struct anv_image
*image
,
3367 VkImageAspectFlagBits aspect
)
3369 struct anv_address addr
=
3370 anv_image_get_clear_color_addr(device
, image
, aspect
);
3372 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3373 device
->isl_dev
.ss
.clear_color_state_size
:
3374 device
->isl_dev
.ss
.clear_value_size
;
3375 return anv_address_add(addr
, clear_color_state_size
);
3378 static inline struct anv_address
3379 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3380 const struct anv_image
*image
,
3381 VkImageAspectFlagBits aspect
,
3382 uint32_t level
, uint32_t array_layer
)
3384 assert(level
< anv_image_aux_levels(image
, aspect
));
3385 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3386 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3387 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3389 struct anv_address addr
=
3390 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3391 addr
.offset
+= 4; /* Go past the fast clear type */
3393 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3394 for (uint32_t l
= 0; l
< level
; l
++)
3395 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3397 addr
.offset
+= level
* image
->array_size
* 4;
3399 addr
.offset
+= array_layer
* 4;
3401 assert(addr
.offset
<
3402 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3406 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3408 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3409 const struct anv_image
*image
)
3411 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3414 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3415 * struct. There's documentation which suggests that this feature actually
3416 * reduces performance on BDW, but it has only been observed to help so
3417 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3418 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3420 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3423 return image
->samples
== 1;
3427 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3428 const struct anv_image
*image
,
3431 return device
->info
.has_aux_map
&&
3432 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3436 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3437 const struct anv_image
*image
,
3438 VkImageAspectFlagBits aspect
,
3439 enum isl_aux_usage aux_usage
,
3441 uint32_t base_layer
,
3442 uint32_t layer_count
);
3445 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3446 const struct anv_image
*image
,
3447 VkImageAspectFlagBits aspect
,
3448 enum isl_aux_usage aux_usage
,
3449 enum isl_format format
, struct isl_swizzle swizzle
,
3450 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3451 VkRect2D area
, union isl_color_value clear_color
);
3453 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3454 const struct anv_image
*image
,
3455 VkImageAspectFlags aspects
,
3456 enum isl_aux_usage depth_aux_usage
,
3458 uint32_t base_layer
, uint32_t layer_count
,
3460 float depth_value
, uint8_t stencil_value
);
3462 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3463 const struct anv_image
*src_image
,
3464 enum isl_aux_usage src_aux_usage
,
3465 uint32_t src_level
, uint32_t src_base_layer
,
3466 const struct anv_image
*dst_image
,
3467 enum isl_aux_usage dst_aux_usage
,
3468 uint32_t dst_level
, uint32_t dst_base_layer
,
3469 VkImageAspectFlagBits aspect
,
3470 uint32_t src_x
, uint32_t src_y
,
3471 uint32_t dst_x
, uint32_t dst_y
,
3472 uint32_t width
, uint32_t height
,
3473 uint32_t layer_count
,
3474 enum blorp_filter filter
);
3476 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3477 const struct anv_image
*image
,
3478 VkImageAspectFlagBits aspect
, uint32_t level
,
3479 uint32_t base_layer
, uint32_t layer_count
,
3480 enum isl_aux_op hiz_op
);
3482 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3483 const struct anv_image
*image
,
3484 VkImageAspectFlags aspects
,
3486 uint32_t base_layer
, uint32_t layer_count
,
3487 VkRect2D area
, uint8_t stencil_value
);
3489 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3490 const struct anv_image
*image
,
3491 enum isl_format format
,
3492 VkImageAspectFlagBits aspect
,
3493 uint32_t base_layer
, uint32_t layer_count
,
3494 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3497 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3498 const struct anv_image
*image
,
3499 enum isl_format format
,
3500 VkImageAspectFlagBits aspect
, uint32_t level
,
3501 uint32_t base_layer
, uint32_t layer_count
,
3502 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3506 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3507 const struct anv_image
*image
,
3508 VkImageAspectFlagBits aspect
,
3509 uint32_t base_level
, uint32_t level_count
,
3510 uint32_t base_layer
, uint32_t layer_count
);
3513 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3514 const struct anv_image
*image
,
3515 const VkImageAspectFlagBits aspect
,
3516 const VkImageLayout layout
);
3518 enum anv_fast_clear_type
3519 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3520 const struct anv_image
* const image
,
3521 const VkImageAspectFlagBits aspect
,
3522 const VkImageLayout layout
);
3524 /* This is defined as a macro so that it works for both
3525 * VkImageSubresourceRange and VkImageSubresourceLayers
3527 #define anv_get_layerCount(_image, _range) \
3528 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3529 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3531 static inline uint32_t
3532 anv_get_levelCount(const struct anv_image
*image
,
3533 const VkImageSubresourceRange
*range
)
3535 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3536 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3539 static inline VkImageAspectFlags
3540 anv_image_expand_aspects(const struct anv_image
*image
,
3541 VkImageAspectFlags aspects
)
3543 /* If the underlying image has color plane aspects and
3544 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3545 * the underlying image. */
3546 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3547 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3548 return image
->aspects
;
3554 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3555 VkImageAspectFlags aspects2
)
3557 if (aspects1
== aspects2
)
3560 /* Only 1 color aspects are compatibles. */
3561 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3562 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3563 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3569 struct anv_image_view
{
3570 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3572 VkImageAspectFlags aspect_mask
;
3574 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3578 uint32_t image_plane
;
3580 struct isl_view isl
;
3583 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3584 * image layout of SHADER_READ_ONLY_OPTIMAL or
3585 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3587 struct anv_surface_state optimal_sampler_surface_state
;
3590 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3591 * image layout of GENERAL.
3593 struct anv_surface_state general_sampler_surface_state
;
3596 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3597 * states for write-only and readable, using the real format for
3598 * write-only and the lowered format for readable.
3600 struct anv_surface_state storage_surface_state
;
3601 struct anv_surface_state writeonly_storage_surface_state
;
3603 struct brw_image_param storage_image_param
;
3607 enum anv_image_view_state_flags
{
3608 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3609 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3612 void anv_image_fill_surface_state(struct anv_device
*device
,
3613 const struct anv_image
*image
,
3614 VkImageAspectFlagBits aspect
,
3615 const struct isl_view
*view
,
3616 isl_surf_usage_flags_t view_usage
,
3617 enum isl_aux_usage aux_usage
,
3618 const union isl_color_value
*clear_color
,
3619 enum anv_image_view_state_flags flags
,
3620 struct anv_surface_state
*state_inout
,
3621 struct brw_image_param
*image_param_out
);
3623 struct anv_image_create_info
{
3624 const VkImageCreateInfo
*vk_info
;
3626 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3627 isl_tiling_flags_t isl_tiling_flags
;
3629 /** These flags will be added to any derived from VkImageCreateInfo. */
3630 isl_surf_usage_flags_t isl_extra_usage_flags
;
3633 bool external_format
;
3636 VkResult
anv_image_create(VkDevice _device
,
3637 const struct anv_image_create_info
*info
,
3638 const VkAllocationCallbacks
* alloc
,
3641 const struct anv_surface
*
3642 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3643 VkImageAspectFlags aspect_mask
);
3646 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3648 static inline struct VkExtent3D
3649 anv_sanitize_image_extent(const VkImageType imageType
,
3650 const struct VkExtent3D imageExtent
)
3652 switch (imageType
) {
3653 case VK_IMAGE_TYPE_1D
:
3654 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3655 case VK_IMAGE_TYPE_2D
:
3656 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3657 case VK_IMAGE_TYPE_3D
:
3660 unreachable("invalid image type");
3664 static inline struct VkOffset3D
3665 anv_sanitize_image_offset(const VkImageType imageType
,
3666 const struct VkOffset3D imageOffset
)
3668 switch (imageType
) {
3669 case VK_IMAGE_TYPE_1D
:
3670 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3671 case VK_IMAGE_TYPE_2D
:
3672 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3673 case VK_IMAGE_TYPE_3D
:
3676 unreachable("invalid image type");
3680 VkFormatFeatureFlags
3681 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3683 const struct anv_format
*anv_format
,
3684 VkImageTiling vk_tiling
);
3686 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3687 struct anv_state state
,
3688 enum isl_format format
,
3689 struct anv_address address
,
3690 uint32_t range
, uint32_t stride
);
3693 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3694 const struct anv_attachment_state
*att_state
,
3695 const struct anv_image_view
*iview
)
3697 const struct isl_format_layout
*view_fmtl
=
3698 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3700 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3701 if (view_fmtl->channels.c.bits) \
3702 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3704 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3705 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3706 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3707 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3709 #undef COPY_CLEAR_COLOR_CHANNEL
3713 struct anv_ycbcr_conversion
{
3714 const struct anv_format
* format
;
3715 VkSamplerYcbcrModelConversion ycbcr_model
;
3716 VkSamplerYcbcrRange ycbcr_range
;
3717 VkComponentSwizzle mapping
[4];
3718 VkChromaLocation chroma_offsets
[2];
3719 VkFilter chroma_filter
;
3720 bool chroma_reconstruction
;
3723 struct anv_sampler
{
3724 uint32_t state
[3][4];
3726 struct anv_ycbcr_conversion
*conversion
;
3728 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3729 * and with a 32-byte stride for use as bindless samplers.
3731 struct anv_state bindless_state
;
3734 struct anv_framebuffer
{
3739 uint32_t attachment_count
;
3740 struct anv_image_view
* attachments
[0];
3743 struct anv_subpass_attachment
{
3744 VkImageUsageFlagBits usage
;
3745 uint32_t attachment
;
3746 VkImageLayout layout
;
3749 struct anv_subpass
{
3750 uint32_t attachment_count
;
3753 * A pointer to all attachment references used in this subpass.
3754 * Only valid if ::attachment_count > 0.
3756 struct anv_subpass_attachment
* attachments
;
3757 uint32_t input_count
;
3758 struct anv_subpass_attachment
* input_attachments
;
3759 uint32_t color_count
;
3760 struct anv_subpass_attachment
* color_attachments
;
3761 struct anv_subpass_attachment
* resolve_attachments
;
3763 struct anv_subpass_attachment
* depth_stencil_attachment
;
3764 struct anv_subpass_attachment
* ds_resolve_attachment
;
3765 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3766 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3770 /** Subpass has a depth/stencil self-dependency */
3771 bool has_ds_self_dep
;
3773 /** Subpass has at least one color resolve attachment */
3774 bool has_color_resolve
;
3777 static inline unsigned
3778 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3780 return MAX2(1, util_bitcount(subpass
->view_mask
));
3783 struct anv_render_pass_attachment
{
3784 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3785 * its members individually.
3789 VkImageUsageFlags usage
;
3790 VkAttachmentLoadOp load_op
;
3791 VkAttachmentStoreOp store_op
;
3792 VkAttachmentLoadOp stencil_load_op
;
3793 VkImageLayout initial_layout
;
3794 VkImageLayout final_layout
;
3795 VkImageLayout first_subpass_layout
;
3797 /* The subpass id in which the attachment will be used last. */
3798 uint32_t last_subpass_idx
;
3801 struct anv_render_pass
{
3802 uint32_t attachment_count
;
3803 uint32_t subpass_count
;
3804 /* An array of subpass_count+1 flushes, one per subpass boundary */
3805 enum anv_pipe_bits
* subpass_flushes
;
3806 struct anv_render_pass_attachment
* attachments
;
3807 struct anv_subpass subpasses
[0];
3810 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3812 struct anv_query_pool
{
3814 VkQueryPipelineStatisticFlags pipeline_statistics
;
3815 /** Stride between slots, in bytes */
3817 /** Number of slots in this query pool */
3822 int anv_get_instance_entrypoint_index(const char *name
);
3823 int anv_get_device_entrypoint_index(const char *name
);
3824 int anv_get_physical_device_entrypoint_index(const char *name
);
3826 const char *anv_get_instance_entry_name(int index
);
3827 const char *anv_get_physical_device_entry_name(int index
);
3828 const char *anv_get_device_entry_name(int index
);
3831 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3832 const struct anv_instance_extension_table
*instance
);
3834 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3835 const struct anv_instance_extension_table
*instance
);
3837 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3838 const struct anv_instance_extension_table
*instance
,
3839 const struct anv_device_extension_table
*device
);
3841 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3844 void anv_dump_image_to_ppm(struct anv_device
*device
,
3845 struct anv_image
*image
, unsigned miplevel
,
3846 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3847 const char *filename
);
3849 enum anv_dump_action
{
3850 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3853 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3854 void anv_dump_finish(void);
3856 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
3858 static inline uint32_t
3859 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3861 /* This function must be called from within a subpass. */
3862 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3864 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3866 /* The id of this subpass shouldn't exceed the number of subpasses in this
3867 * render pass minus 1.
3869 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3873 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
3874 void anv_device_perf_init(struct anv_device
*device
);
3876 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3878 static inline struct __anv_type * \
3879 __anv_type ## _from_handle(__VkType _handle) \
3881 return (struct __anv_type *) _handle; \
3884 static inline __VkType \
3885 __anv_type ## _to_handle(struct __anv_type *_obj) \
3887 return (__VkType) _obj; \
3890 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3892 static inline struct __anv_type * \
3893 __anv_type ## _from_handle(__VkType _handle) \
3895 return (struct __anv_type *)(uintptr_t) _handle; \
3898 static inline __VkType \
3899 __anv_type ## _to_handle(struct __anv_type *_obj) \
3901 return (__VkType)(uintptr_t) _obj; \
3904 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3905 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3907 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3908 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3909 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3910 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3911 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3913 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3914 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3915 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3916 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3917 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3918 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3919 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3920 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3921 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3922 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3923 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3924 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3925 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3926 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3927 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3928 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3929 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3930 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3931 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3932 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3933 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3934 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3935 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3937 /* Gen-specific function declarations */
3939 # include "anv_genX.h"
3941 # define genX(x) gen7_##x
3942 # include "anv_genX.h"
3944 # define genX(x) gen75_##x
3945 # include "anv_genX.h"
3947 # define genX(x) gen8_##x
3948 # include "anv_genX.h"
3950 # define genX(x) gen9_##x
3951 # include "anv_genX.h"
3953 # define genX(x) gen10_##x
3954 # include "anv_genX.h"
3956 # define genX(x) gen11_##x
3957 # include "anv_genX.h"
3959 # define genX(x) gen12_##x
3960 # include "anv_genX.h"
3964 #endif /* ANV_PRIVATE_H */