2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/macros.h"
53 #include "util/hash_table.h"
54 #include "util/list.h"
56 #include "util/u_atomic.h"
57 #include "util/u_vector.h"
58 #include "util/u_math.h"
61 #include "vk_debug_report.h"
63 /* Pre-declarations needed for WSI entrypoints */
66 typedef struct xcb_connection_t xcb_connection_t
;
67 typedef uint32_t xcb_visualid_t
;
68 typedef uint32_t xcb_window_t
;
71 struct anv_buffer_view
;
72 struct anv_image_view
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vk_icd.h>
81 #include "anv_android.h"
82 #include "anv_entrypoints.h"
83 #include "anv_extensions.h"
86 #include "common/gen_debug.h"
87 #include "common/intel_log.h"
88 #include "wsi_common.h"
90 /* anv Virtual Memory Layout
91 * =========================
93 * When the anv driver is determining the virtual graphics addresses of memory
94 * objects itself using the softpin mechanism, the following memory ranges
97 * Three special considerations to notice:
99 * (1) the dynamic state pool is located within the same 4 GiB as the low
100 * heap. This is to work around a VF cache issue described in a comment in
101 * anv_physical_device_init_heaps.
103 * (2) the binding table pool is located at lower addresses than the surface
104 * state pool, within a 4 GiB range. This allows surface state base addresses
105 * to cover both binding tables (16 bit offsets) and surface states (32 bit
108 * (3) the last 4 GiB of the address space is withheld from the high
109 * heap. Various hardware units will read past the end of an object for
110 * various reasons. This healthy margin prevents reads from wrapping around
113 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
114 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
115 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
116 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
117 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
118 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
119 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
120 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
121 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
122 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
123 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
124 #define HIGH_HEAP_MAX_ADDRESS 0xfffeffffffffULL
126 #define LOW_HEAP_SIZE \
127 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
128 #define HIGH_HEAP_SIZE \
129 (HIGH_HEAP_MAX_ADDRESS - HIGH_HEAP_MIN_ADDRESS + 1)
130 #define DYNAMIC_STATE_POOL_SIZE \
131 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
132 #define BINDING_TABLE_POOL_SIZE \
133 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
134 #define SURFACE_STATE_POOL_SIZE \
135 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
136 #define INSTRUCTION_STATE_POOL_SIZE \
137 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
139 /* Allowing different clear colors requires us to perform a depth resolve at
140 * the end of certain render passes. This is because while slow clears store
141 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
142 * See the PRMs for examples describing when additional resolves would be
143 * necessary. To enable fast clears without requiring extra resolves, we set
144 * the clear value to a globally-defined one. We could allow different values
145 * if the user doesn't expect coherent data during or after a render passes
146 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
147 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
148 * 1.0f seems to be the only value used. The only application that doesn't set
149 * this value does so through the usage of an seemingly uninitialized clear
152 #define ANV_HZ_FC_VAL 1.0f
155 #define MAX_XFB_BUFFERS 4
156 #define MAX_XFB_STREAMS 4
159 #define MAX_VIEWPORTS 16
160 #define MAX_SCISSORS 16
161 #define MAX_PUSH_CONSTANTS_SIZE 128
162 #define MAX_DYNAMIC_BUFFERS 16
163 #define MAX_IMAGES 64
164 #define MAX_GEN8_IMAGES 8
165 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
166 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
167 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
169 /* The kernel relocation API has a limitation of a 32-bit delta value
170 * applied to the address before it is written which, in spite of it being
171 * unsigned, is treated as signed . Because of the way that this maps to
172 * the Vulkan API, we cannot handle an offset into a buffer that does not
173 * fit into a signed 32 bits. The only mechanism we have for dealing with
174 * this at the moment is to limit all VkDeviceMemory objects to a maximum
175 * of 2GB each. The Vulkan spec allows us to do this:
177 * "Some platforms may have a limit on the maximum size of a single
178 * allocation. For example, certain systems may fail to create
179 * allocations with a size greater than or equal to 4GB. Such a limit is
180 * implementation-dependent, and if such a failure occurs then the error
181 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
183 * We don't use vk_error here because it's not an error so much as an
184 * indication to the application that the allocation is too large.
186 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
188 #define ANV_SVGS_VB_INDEX MAX_VBS
189 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
191 /* We reserve this MI ALU register for the purpose of handling predication.
192 * Other code which uses the MI ALU should leave it alone.
194 #define ANV_PREDICATE_RESULT_REG MI_ALU_REG15
196 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
198 static inline uint32_t
199 align_down_npot_u32(uint32_t v
, uint32_t a
)
204 static inline uint32_t
205 align_u32(uint32_t v
, uint32_t a
)
207 assert(a
!= 0 && a
== (a
& -a
));
208 return (v
+ a
- 1) & ~(a
- 1);
211 static inline uint64_t
212 align_u64(uint64_t v
, uint64_t a
)
214 assert(a
!= 0 && a
== (a
& -a
));
215 return (v
+ a
- 1) & ~(a
- 1);
218 static inline int32_t
219 align_i32(int32_t v
, int32_t a
)
221 assert(a
!= 0 && a
== (a
& -a
));
222 return (v
+ a
- 1) & ~(a
- 1);
225 /** Alignment must be a power of 2. */
227 anv_is_aligned(uintmax_t n
, uintmax_t a
)
229 assert(a
== (a
& -a
));
230 return (n
& (a
- 1)) == 0;
233 static inline uint32_t
234 anv_minify(uint32_t n
, uint32_t levels
)
236 if (unlikely(n
== 0))
239 return MAX2(n
>> levels
, 1);
243 anv_clamp_f(float f
, float min
, float max
)
256 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
258 if (*inout_mask
& clear_mask
) {
259 *inout_mask
&= ~clear_mask
;
266 static inline union isl_color_value
267 vk_to_isl_color(VkClearColorValue color
)
269 return (union isl_color_value
) {
279 #define for_each_bit(b, dword) \
280 for (uint32_t __dword = (dword); \
281 (b) = __builtin_ffs(__dword) - 1, __dword; \
282 __dword &= ~(1 << (b)))
284 #define typed_memcpy(dest, src, count) ({ \
285 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
286 memcpy((dest), (src), (count) * sizeof(*(src))); \
289 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
290 * to be added here in order to utilize mapping in debug/error/perf macros.
292 #define REPORT_OBJECT_TYPE(o) \
293 __builtin_choose_expr ( \
294 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
295 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
296 __builtin_choose_expr ( \
297 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
298 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
299 __builtin_choose_expr ( \
300 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
301 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
302 __builtin_choose_expr ( \
303 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
304 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
305 __builtin_choose_expr ( \
306 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
307 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
308 __builtin_choose_expr ( \
309 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
310 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
311 __builtin_choose_expr ( \
312 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
313 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
314 __builtin_choose_expr ( \
315 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
316 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
317 __builtin_choose_expr ( \
318 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
319 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
320 __builtin_choose_expr ( \
321 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
322 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
323 __builtin_choose_expr ( \
324 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
325 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
326 __builtin_choose_expr ( \
327 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
328 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
329 __builtin_choose_expr ( \
330 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
331 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
332 __builtin_choose_expr ( \
333 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
334 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
335 __builtin_choose_expr ( \
336 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
337 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
338 __builtin_choose_expr ( \
339 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
340 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), void*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
386 /* The void expression results in a compile-time error \
387 when assigning the result to something. */ \
388 (void)0)))))))))))))))))))))))))))))))
390 /* Whenever we generate an error, pass it through this function. Useful for
391 * debugging, where we can break on it. Only call at error site, not when
392 * propagating errors. Might be useful to plug in a stack trace here.
395 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
396 VkDebugReportObjectTypeEXT type
, VkResult error
,
397 const char *file
, int line
, const char *format
,
400 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
401 VkDebugReportObjectTypeEXT type
, VkResult error
,
402 const char *file
, int line
, const char *format
, ...);
405 #define vk_error(error) __vk_errorf(NULL, NULL,\
406 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
407 error, __FILE__, __LINE__, NULL)
408 #define vk_errorv(instance, obj, error, format, args)\
409 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
410 __FILE__, __LINE__, format, args)
411 #define vk_errorf(instance, obj, error, format, ...)\
412 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
413 __FILE__, __LINE__, format, ## __VA_ARGS__)
415 #define vk_error(error) error
416 #define vk_errorf(instance, obj, error, format, ...) error
420 * Warn on ignored extension structs.
422 * The Vulkan spec requires us to ignore unsupported or unknown structs in
423 * a pNext chain. In debug mode, emitting warnings for ignored structs may
424 * help us discover structs that we should not have ignored.
427 * From the Vulkan 1.0.38 spec:
429 * Any component of the implementation (the loader, any enabled layers,
430 * and drivers) must skip over, without processing (other than reading the
431 * sType and pNext members) any chained structures with sType values not
432 * defined by extensions supported by that component.
434 #define anv_debug_ignored_stype(sType) \
435 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
437 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
438 VkDebugReportObjectTypeEXT type
, const char *file
,
439 int line
, const char *format
, ...)
440 anv_printflike(6, 7);
441 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
442 void anv_loge_v(const char *format
, va_list va
);
445 * Print a FINISHME message, including its source location.
447 #define anv_finishme(format, ...) \
449 static bool reported = false; \
451 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
458 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
460 #define anv_perf_warn(instance, obj, format, ...) \
462 static bool reported = false; \
463 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
464 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
465 format, ##__VA_ARGS__); \
470 /* A non-fatal assert. Useful for debugging. */
472 #define anv_assert(x) ({ \
473 if (unlikely(!(x))) \
474 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
477 #define anv_assert(x)
480 /* A multi-pointer allocator
482 * When copying data structures from the user (such as a render pass), it's
483 * common to need to allocate data for a bunch of different things. Instead
484 * of doing several allocations and having to handle all of the error checking
485 * that entails, it can be easier to do a single allocation. This struct
486 * helps facilitate that. The intended usage looks like this:
489 * anv_multialloc_add(&ma, &main_ptr, 1);
490 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
491 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
493 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
494 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
496 struct anv_multialloc
{
504 #define ANV_MULTIALLOC_INIT \
505 ((struct anv_multialloc) { 0, })
507 #define ANV_MULTIALLOC(_name) \
508 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
510 __attribute__((always_inline
))
512 _anv_multialloc_add(struct anv_multialloc
*ma
,
513 void **ptr
, size_t size
, size_t align
)
515 size_t offset
= align_u64(ma
->size
, align
);
516 ma
->size
= offset
+ size
;
517 ma
->align
= MAX2(ma
->align
, align
);
519 /* Store the offset in the pointer. */
520 *ptr
= (void *)(uintptr_t)offset
;
522 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
523 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
526 #define anv_multialloc_add_size(_ma, _ptr, _size) \
527 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
529 #define anv_multialloc_add(_ma, _ptr, _count) \
530 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
532 __attribute__((always_inline
))
534 anv_multialloc_alloc(struct anv_multialloc
*ma
,
535 const VkAllocationCallbacks
*alloc
,
536 VkSystemAllocationScope scope
)
538 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
542 /* Fill out each of the pointers with their final value.
544 * for (uint32_t i = 0; i < ma->ptr_count; i++)
545 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
547 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
548 * constant, GCC is incapable of figuring this out and unrolling the loop
549 * so we have to give it a little help.
551 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
552 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
553 if ((_i) < ma->ptr_count) \
554 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
555 _ANV_MULTIALLOC_UPDATE_POINTER(0);
556 _ANV_MULTIALLOC_UPDATE_POINTER(1);
557 _ANV_MULTIALLOC_UPDATE_POINTER(2);
558 _ANV_MULTIALLOC_UPDATE_POINTER(3);
559 _ANV_MULTIALLOC_UPDATE_POINTER(4);
560 _ANV_MULTIALLOC_UPDATE_POINTER(5);
561 _ANV_MULTIALLOC_UPDATE_POINTER(6);
562 _ANV_MULTIALLOC_UPDATE_POINTER(7);
563 #undef _ANV_MULTIALLOC_UPDATE_POINTER
568 __attribute__((always_inline
))
570 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
571 const VkAllocationCallbacks
*parent_alloc
,
572 const VkAllocationCallbacks
*alloc
,
573 VkSystemAllocationScope scope
)
575 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
578 /* Extra ANV-defined BO flags which won't be passed to the kernel */
579 #define ANV_BO_EXTERNAL (1ull << 31)
580 #define ANV_BO_FLAG_MASK (1ull << 31)
585 /* Index into the current validation list. This is used by the
586 * validation list building alrogithm to track which buffers are already
587 * in the validation list so that we can ensure uniqueness.
591 /* Last known offset. This value is provided by the kernel when we
592 * execbuf and is used as the presumed offset for the next bunch of
600 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
605 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
607 bo
->gem_handle
= gem_handle
;
615 /* Represents a lock-free linked list of "free" things. This is used by
616 * both the block pool and the state pools. Unfortunately, in order to
617 * solve the ABA problem, we can't use a single uint32_t head.
619 union anv_free_list
{
623 /* A simple count that is incremented every time the head changes. */
629 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
631 struct anv_block_state
{
641 #define anv_block_pool_foreach_bo(bo, pool) \
642 for (bo = (pool)->bos; bo != &(pool)->bos[(pool)->nbos]; bo++)
644 #define ANV_MAX_BLOCK_POOL_BOS 20
646 struct anv_block_pool
{
647 struct anv_device
*device
;
651 struct anv_bo bos
[ANV_MAX_BLOCK_POOL_BOS
];
657 /* The address where the start of the pool is pinned. The various bos that
658 * are created as the pool grows will have addresses in the range
659 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
661 uint64_t start_address
;
663 /* The offset from the start of the bo to the "center" of the block
664 * pool. Pointers to allocated blocks are given by
665 * bo.map + center_bo_offset + offsets.
667 uint32_t center_bo_offset
;
669 /* Current memory map of the block pool. This pointer may or may not
670 * point to the actual beginning of the block pool memory. If
671 * anv_block_pool_alloc_back has ever been called, then this pointer
672 * will point to the "center" position of the buffer and all offsets
673 * (negative or positive) given out by the block pool alloc functions
674 * will be valid relative to this pointer.
676 * In particular, map == bo.map + center_offset
678 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
679 * since it will handle the softpin case as well, where this points to NULL.
685 * Array of mmaps and gem handles owned by the block pool, reclaimed when
686 * the block pool is destroyed.
688 struct u_vector mmap_cleanups
;
690 struct anv_block_state state
;
692 struct anv_block_state back_state
;
695 /* Block pools are backed by a fixed-size 1GB memfd */
696 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
698 /* The center of the block pool is also the middle of the memfd. This may
699 * change in the future if we decide differently for some reason.
701 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
703 static inline uint32_t
704 anv_block_pool_size(struct anv_block_pool
*pool
)
706 return pool
->state
.end
+ pool
->back_state
.end
;
716 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
718 struct anv_fixed_size_state_pool
{
719 union anv_free_list free_list
;
720 struct anv_block_state block
;
723 #define ANV_MIN_STATE_SIZE_LOG2 6
724 #define ANV_MAX_STATE_SIZE_LOG2 20
726 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
728 struct anv_free_entry
{
730 struct anv_state state
;
733 struct anv_state_table
{
734 struct anv_device
*device
;
736 struct anv_free_entry
*map
;
738 struct anv_block_state state
;
739 struct u_vector mmap_cleanups
;
742 struct anv_state_pool
{
743 struct anv_block_pool block_pool
;
745 struct anv_state_table table
;
747 /* The size of blocks which will be allocated from the block pool */
750 /** Free list for "back" allocations */
751 union anv_free_list back_alloc_free_list
;
753 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
756 struct anv_state_stream_block
;
758 struct anv_state_stream
{
759 struct anv_state_pool
*state_pool
;
761 /* The size of blocks to allocate from the state pool */
764 /* Current block we're allocating from */
765 struct anv_state block
;
767 /* Offset into the current block at which to allocate the next state */
770 /* List of all blocks allocated from this pool */
771 struct anv_state_stream_block
*block_list
;
774 /* The block_pool functions exported for testing only. The block pool should
775 * only be used via a state pool (see below).
777 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
778 struct anv_device
*device
,
779 uint64_t start_address
,
780 uint32_t initial_size
,
782 void anv_block_pool_finish(struct anv_block_pool
*pool
);
783 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
784 uint32_t block_size
, uint32_t *padding
);
785 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
786 uint32_t block_size
);
787 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
789 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
790 struct anv_device
*device
,
791 uint64_t start_address
,
794 void anv_state_pool_finish(struct anv_state_pool
*pool
);
795 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
796 uint32_t state_size
, uint32_t alignment
);
797 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
798 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
799 void anv_state_stream_init(struct anv_state_stream
*stream
,
800 struct anv_state_pool
*state_pool
,
801 uint32_t block_size
);
802 void anv_state_stream_finish(struct anv_state_stream
*stream
);
803 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
804 uint32_t size
, uint32_t alignment
);
806 VkResult
anv_state_table_init(struct anv_state_table
*table
,
807 struct anv_device
*device
,
808 uint32_t initial_entries
);
809 void anv_state_table_finish(struct anv_state_table
*table
);
810 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
812 void anv_free_list_push(union anv_free_list
*list
,
813 struct anv_state_table
*table
,
814 uint32_t idx
, uint32_t count
);
815 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
816 struct anv_state_table
*table
);
819 static inline struct anv_state
*
820 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
822 return &table
->map
[idx
].state
;
825 * Implements a pool of re-usable BOs. The interface is identical to that
826 * of block_pool except that each block is its own BO.
829 struct anv_device
*device
;
836 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
838 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
839 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
841 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
843 struct anv_scratch_bo
{
848 struct anv_scratch_pool
{
849 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
850 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
853 void anv_scratch_pool_init(struct anv_device
*device
,
854 struct anv_scratch_pool
*pool
);
855 void anv_scratch_pool_finish(struct anv_device
*device
,
856 struct anv_scratch_pool
*pool
);
857 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
858 struct anv_scratch_pool
*pool
,
859 gl_shader_stage stage
,
860 unsigned per_thread_scratch
);
862 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
863 struct anv_bo_cache
{
864 struct hash_table
*bo_map
;
865 pthread_mutex_t mutex
;
868 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
869 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
870 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
871 struct anv_bo_cache
*cache
,
872 uint64_t size
, uint64_t bo_flags
,
874 VkResult
anv_bo_cache_import(struct anv_device
*device
,
875 struct anv_bo_cache
*cache
,
876 int fd
, uint64_t bo_flags
,
878 VkResult
anv_bo_cache_export(struct anv_device
*device
,
879 struct anv_bo_cache
*cache
,
880 struct anv_bo
*bo_in
, int *fd_out
);
881 void anv_bo_cache_release(struct anv_device
*device
,
882 struct anv_bo_cache
*cache
,
885 struct anv_memory_type
{
886 /* Standard bits passed on to the client */
887 VkMemoryPropertyFlags propertyFlags
;
890 /* Driver-internal book-keeping */
891 VkBufferUsageFlags valid_buffer_usage
;
894 struct anv_memory_heap
{
895 /* Standard bits passed on to the client */
897 VkMemoryHeapFlags flags
;
899 /* Driver-internal book-keeping */
900 bool supports_48bit_addresses
;
903 struct anv_physical_device
{
904 VK_LOADER_DATA _loader_data
;
906 struct anv_instance
* instance
;
917 struct gen_device_info info
;
918 /** Amount of "GPU memory" we want to advertise
920 * Clearly, this value is bogus since Intel is a UMA architecture. On
921 * gen7 platforms, we are limited by GTT size unless we want to implement
922 * fine-grained tracking and GTT splitting. On Broadwell and above we are
923 * practically unlimited. However, we will never report more than 3/4 of
924 * the total system ram to try and avoid running out of RAM.
926 bool supports_48bit_addresses
;
927 struct brw_compiler
* compiler
;
928 struct isl_device isl_dev
;
929 int cmd_parser_version
;
931 bool has_exec_capture
;
934 bool has_syncobj_wait
;
935 bool has_context_priority
;
937 bool has_context_isolation
;
939 struct anv_device_extension_table supported_extensions
;
942 uint32_t subslice_total
;
946 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
948 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
951 uint8_t driver_build_sha1
[20];
952 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
953 uint8_t driver_uuid
[VK_UUID_SIZE
];
954 uint8_t device_uuid
[VK_UUID_SIZE
];
956 struct disk_cache
* disk_cache
;
958 struct wsi_device wsi_device
;
963 struct anv_app_info
{
964 const char* app_name
;
965 uint32_t app_version
;
966 const char* engine_name
;
967 uint32_t engine_version
;
968 uint32_t api_version
;
971 struct anv_instance
{
972 VK_LOADER_DATA _loader_data
;
974 VkAllocationCallbacks alloc
;
976 struct anv_app_info app_info
;
978 struct anv_instance_extension_table enabled_extensions
;
979 struct anv_instance_dispatch_table dispatch
;
980 struct anv_device_dispatch_table device_dispatch
;
982 int physicalDeviceCount
;
983 struct anv_physical_device physicalDevice
;
985 bool pipeline_cache_enabled
;
987 struct vk_debug_report_instance debug_report_callbacks
;
990 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
991 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
993 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
994 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
998 VK_LOADER_DATA _loader_data
;
1000 struct anv_device
* device
;
1002 VkDeviceQueueCreateFlags flags
;
1005 struct anv_pipeline_cache
{
1006 struct anv_device
* device
;
1007 pthread_mutex_t mutex
;
1009 struct hash_table
* nir_cache
;
1011 struct hash_table
* cache
;
1014 struct nir_xfb_info
;
1015 struct anv_pipeline_bind_map
;
1017 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1018 struct anv_device
*device
,
1019 bool cache_enabled
);
1020 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1022 struct anv_shader_bin
*
1023 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1024 const void *key
, uint32_t key_size
);
1025 struct anv_shader_bin
*
1026 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1027 const void *key_data
, uint32_t key_size
,
1028 const void *kernel_data
, uint32_t kernel_size
,
1029 const void *constant_data
,
1030 uint32_t constant_data_size
,
1031 const struct brw_stage_prog_data
*prog_data
,
1032 uint32_t prog_data_size
,
1033 const struct nir_xfb_info
*xfb_info
,
1034 const struct anv_pipeline_bind_map
*bind_map
);
1036 struct anv_shader_bin
*
1037 anv_device_search_for_kernel(struct anv_device
*device
,
1038 struct anv_pipeline_cache
*cache
,
1039 const void *key_data
, uint32_t key_size
);
1041 struct anv_shader_bin
*
1042 anv_device_upload_kernel(struct anv_device
*device
,
1043 struct anv_pipeline_cache
*cache
,
1044 const void *key_data
, uint32_t key_size
,
1045 const void *kernel_data
, uint32_t kernel_size
,
1046 const void *constant_data
,
1047 uint32_t constant_data_size
,
1048 const struct brw_stage_prog_data
*prog_data
,
1049 uint32_t prog_data_size
,
1050 const struct nir_xfb_info
*xfb_info
,
1051 const struct anv_pipeline_bind_map
*bind_map
);
1054 struct nir_shader_compiler_options
;
1057 anv_device_search_for_nir(struct anv_device
*device
,
1058 struct anv_pipeline_cache
*cache
,
1059 const struct nir_shader_compiler_options
*nir_options
,
1060 unsigned char sha1_key
[20],
1064 anv_device_upload_nir(struct anv_device
*device
,
1065 struct anv_pipeline_cache
*cache
,
1066 const struct nir_shader
*nir
,
1067 unsigned char sha1_key
[20]);
1070 VK_LOADER_DATA _loader_data
;
1072 VkAllocationCallbacks alloc
;
1074 struct anv_instance
* instance
;
1075 uint32_t chipset_id
;
1077 struct gen_device_info info
;
1078 struct isl_device isl_dev
;
1081 bool can_chain_batches
;
1082 bool robust_buffer_access
;
1083 struct anv_device_extension_table enabled_extensions
;
1084 struct anv_device_dispatch_table dispatch
;
1086 pthread_mutex_t vma_mutex
;
1087 struct util_vma_heap vma_lo
;
1088 struct util_vma_heap vma_hi
;
1089 uint64_t vma_lo_available
;
1090 uint64_t vma_hi_available
;
1092 struct anv_bo_pool batch_bo_pool
;
1094 struct anv_bo_cache bo_cache
;
1096 struct anv_state_pool dynamic_state_pool
;
1097 struct anv_state_pool instruction_state_pool
;
1098 struct anv_state_pool binding_table_pool
;
1099 struct anv_state_pool surface_state_pool
;
1101 struct anv_bo workaround_bo
;
1102 struct anv_bo trivial_batch_bo
;
1103 struct anv_bo hiz_clear_bo
;
1105 /* Set of pointers to anv_buffer objects for all pinned buffers. Pinned
1106 * buffers are always resident because they could be used at any time via
1107 * VK_EXT_buffer_device_address.
1109 struct set
* pinned_buffers
;
1111 struct anv_pipeline_cache default_pipeline_cache
;
1112 struct blorp_context blorp
;
1114 struct anv_state border_colors
;
1116 struct anv_queue queue
;
1118 struct anv_scratch_pool scratch_pool
;
1120 uint32_t default_mocs
;
1121 uint32_t external_mocs
;
1123 pthread_mutex_t mutex
;
1124 pthread_cond_t queue_submit
;
1127 struct gen_batch_decode_ctx decoder_ctx
;
1129 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1130 * the cmd_buffer's list.
1132 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1135 static inline struct anv_state_pool
*
1136 anv_binding_table_pool(struct anv_device
*device
)
1138 if (device
->instance
->physicalDevice
.use_softpin
)
1139 return &device
->binding_table_pool
;
1141 return &device
->surface_state_pool
;
1144 static inline struct anv_state
1145 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1146 if (device
->instance
->physicalDevice
.use_softpin
)
1147 return anv_state_pool_alloc(&device
->binding_table_pool
,
1148 device
->binding_table_pool
.block_size
, 0);
1150 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1154 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1155 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1158 static inline uint32_t
1159 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1161 if (bo
->flags
& ANV_BO_EXTERNAL
)
1162 return device
->external_mocs
;
1164 return device
->default_mocs
;
1167 void anv_device_init_blorp(struct anv_device
*device
);
1168 void anv_device_finish_blorp(struct anv_device
*device
);
1170 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1171 const char *file
, int line
,
1172 const char *msg
, ...);
1173 #define anv_device_set_lost(dev, ...) \
1174 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1177 anv_device_is_lost(struct anv_device
*device
)
1179 return unlikely(device
->_lost
);
1182 VkResult
anv_device_execbuf(struct anv_device
*device
,
1183 struct drm_i915_gem_execbuffer2
*execbuf
,
1184 struct anv_bo
**execbuf_bos
);
1185 VkResult
anv_device_query_status(struct anv_device
*device
);
1186 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1187 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1190 void* anv_gem_mmap(struct anv_device
*device
,
1191 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1192 void anv_gem_munmap(void *p
, uint64_t size
);
1193 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1194 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1195 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1196 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1197 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1198 int anv_gem_execbuffer(struct anv_device
*device
,
1199 struct drm_i915_gem_execbuffer2
*execbuf
);
1200 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1201 uint32_t stride
, uint32_t tiling
);
1202 int anv_gem_create_context(struct anv_device
*device
);
1203 bool anv_gem_has_context_priority(int fd
);
1204 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1205 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1207 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1209 int anv_gem_get_param(int fd
, uint32_t param
);
1210 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1211 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1212 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1213 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1214 uint32_t *active
, uint32_t *pending
);
1215 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1216 int anv_gem_reg_read(struct anv_device
*device
,
1217 uint32_t offset
, uint64_t *result
);
1218 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1219 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1220 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1221 uint32_t read_domains
, uint32_t write_domain
);
1222 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1223 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1224 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1225 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1226 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1227 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1229 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1230 uint32_t handle
, int fd
);
1231 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1232 bool anv_gem_supports_syncobj_wait(int fd
);
1233 int anv_gem_syncobj_wait(struct anv_device
*device
,
1234 uint32_t *handles
, uint32_t num_handles
,
1235 int64_t abs_timeout_ns
, bool wait_all
);
1237 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1238 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1240 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1242 struct anv_reloc_list
{
1243 uint32_t num_relocs
;
1244 uint32_t array_length
;
1245 struct drm_i915_gem_relocation_entry
* relocs
;
1246 struct anv_bo
** reloc_bos
;
1250 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1251 const VkAllocationCallbacks
*alloc
);
1252 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1253 const VkAllocationCallbacks
*alloc
);
1255 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1256 const VkAllocationCallbacks
*alloc
,
1257 uint32_t offset
, struct anv_bo
*target_bo
,
1260 struct anv_batch_bo
{
1261 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1262 struct list_head link
;
1266 /* Bytes actually consumed in this batch BO */
1269 struct anv_reloc_list relocs
;
1273 const VkAllocationCallbacks
* alloc
;
1279 struct anv_reloc_list
* relocs
;
1281 /* This callback is called (with the associated user data) in the event
1282 * that the batch runs out of space.
1284 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1288 * Current error status of the command buffer. Used to track inconsistent
1289 * or incomplete command buffer states that are the consequence of run-time
1290 * errors such as out of memory scenarios. We want to track this in the
1291 * batch because the command buffer object is not visible to some parts
1297 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1298 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1299 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1300 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1301 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1302 struct anv_batch
*batch
);
1304 static inline VkResult
1305 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1307 assert(error
!= VK_SUCCESS
);
1308 if (batch
->status
== VK_SUCCESS
)
1309 batch
->status
= error
;
1310 return batch
->status
;
1314 anv_batch_has_error(struct anv_batch
*batch
)
1316 return batch
->status
!= VK_SUCCESS
;
1319 struct anv_address
{
1324 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1327 anv_address_is_null(struct anv_address addr
)
1329 return addr
.bo
== NULL
&& addr
.offset
== 0;
1332 static inline uint64_t
1333 anv_address_physical(struct anv_address addr
)
1335 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1336 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1338 return gen_canonical_address(addr
.offset
);
1341 static inline struct anv_address
1342 anv_address_add(struct anv_address addr
, uint64_t offset
)
1344 addr
.offset
+= offset
;
1349 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1351 unsigned reloc_size
= 0;
1352 if (device
->info
.gen
>= 8) {
1353 reloc_size
= sizeof(uint64_t);
1354 *(uint64_t *)p
= gen_canonical_address(v
);
1356 reloc_size
= sizeof(uint32_t);
1360 if (flush
&& !device
->info
.has_llc
)
1361 gen_flush_range(p
, reloc_size
);
1364 static inline uint64_t
1365 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1366 const struct anv_address address
, uint32_t delta
)
1368 if (address
.bo
== NULL
) {
1369 return address
.offset
+ delta
;
1371 assert(batch
->start
<= location
&& location
< batch
->end
);
1373 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1377 #define __gen_address_type struct anv_address
1378 #define __gen_user_data struct anv_batch
1379 #define __gen_combine_address _anv_combine_address
1381 /* Wrapper macros needed to work around preprocessor argument issues. In
1382 * particular, arguments don't get pre-evaluated if they are concatenated.
1383 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1384 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1385 * We can work around this easily enough with these helpers.
1387 #define __anv_cmd_length(cmd) cmd ## _length
1388 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1389 #define __anv_cmd_header(cmd) cmd ## _header
1390 #define __anv_cmd_pack(cmd) cmd ## _pack
1391 #define __anv_reg_num(reg) reg ## _num
1393 #define anv_pack_struct(dst, struc, ...) do { \
1394 struct struc __template = { \
1397 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1398 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1401 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1402 void *__dst = anv_batch_emit_dwords(batch, n); \
1404 struct cmd __template = { \
1405 __anv_cmd_header(cmd), \
1406 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1409 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1414 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1418 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1419 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1422 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1423 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1424 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1427 #define anv_batch_emit(batch, cmd, name) \
1428 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1429 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1430 __builtin_expect(_dst != NULL, 1); \
1431 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1432 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1436 /* MEMORY_OBJECT_CONTROL_STATE:
1437 * .GraphicsDataTypeGFDT = 0,
1438 * .LLCCacheabilityControlLLCCC = 0,
1439 * .L3CacheabilityControlL3CC = 1,
1443 /* MEMORY_OBJECT_CONTROL_STATE:
1444 * .LLCeLLCCacheabilityControlLLCCC = 0,
1445 * .L3CacheabilityControlL3CC = 1,
1447 #define GEN75_MOCS 1
1449 /* MEMORY_OBJECT_CONTROL_STATE:
1450 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1451 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1452 * .AgeforQUADLRU = 0
1454 #define GEN8_MOCS 0x78
1456 /* MEMORY_OBJECT_CONTROL_STATE:
1457 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1458 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1459 * .AgeforQUADLRU = 0
1461 #define GEN8_EXTERNAL_MOCS 0x18
1463 /* Skylake: MOCS is now an index into an array of 62 different caching
1464 * configurations programmed by the kernel.
1467 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1468 #define GEN9_MOCS (2 << 1)
1470 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1471 #define GEN9_EXTERNAL_MOCS (1 << 1)
1473 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1474 #define GEN10_MOCS GEN9_MOCS
1475 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1477 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1478 #define GEN11_MOCS GEN9_MOCS
1479 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1481 struct anv_device_memory
{
1483 struct anv_memory_type
* type
;
1484 VkDeviceSize map_size
;
1487 /* If set, we are holding reference to AHardwareBuffer
1488 * which we must release when memory is freed.
1490 struct AHardwareBuffer
* ahw
;
1494 * Header for Vertex URB Entry (VUE)
1496 struct anv_vue_header
{
1498 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1499 uint32_t ViewportIndex
;
1503 enum anv_descriptor_data
{
1504 /** The descriptor contains a BTI reference to a surface state */
1505 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1506 /** The descriptor contains a BTI reference to a sampler state */
1507 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1508 /** The descriptor contains an actual buffer view */
1509 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1510 /** The descriptor contains auxiliary image layout data */
1511 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1512 /** The descriptor contains auxiliary image layout data */
1513 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1516 struct anv_descriptor_set_binding_layout
{
1518 /* The type of the descriptors in this binding */
1519 VkDescriptorType type
;
1522 /* Bitfield representing the type of data this descriptor contains */
1523 enum anv_descriptor_data data
;
1525 /* Number of array elements in this binding (or size in bytes for inline
1528 uint16_t array_size
;
1530 /* Index into the flattend descriptor set */
1531 uint16_t descriptor_index
;
1533 /* Index into the dynamic state array for a dynamic buffer */
1534 int16_t dynamic_offset_index
;
1536 /* Index into the descriptor set buffer views */
1537 int16_t buffer_view_index
;
1539 /* Offset into the descriptor buffer where this descriptor lives */
1540 uint32_t descriptor_offset
;
1542 /* Immutable samplers (or NULL if no immutable samplers) */
1543 struct anv_sampler
**immutable_samplers
;
1546 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1548 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1549 VkDescriptorType type
);
1551 struct anv_descriptor_set_layout
{
1552 /* Descriptor set layouts can be destroyed at almost any time */
1555 /* Number of bindings in this descriptor set */
1556 uint16_t binding_count
;
1558 /* Total size of the descriptor set with room for all array entries */
1561 /* Shader stages affected by this descriptor set */
1562 uint16_t shader_stages
;
1564 /* Number of buffer views in this descriptor set */
1565 uint16_t buffer_view_count
;
1567 /* Number of dynamic offsets used by this descriptor set */
1568 uint16_t dynamic_offset_count
;
1570 /* Size of the descriptor buffer for this descriptor set */
1571 uint32_t descriptor_buffer_size
;
1573 /* Bindings in this descriptor set */
1574 struct anv_descriptor_set_binding_layout binding
[0];
1578 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1580 assert(layout
&& layout
->ref_cnt
>= 1);
1581 p_atomic_inc(&layout
->ref_cnt
);
1585 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1586 struct anv_descriptor_set_layout
*layout
)
1588 assert(layout
&& layout
->ref_cnt
>= 1);
1589 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1590 vk_free(&device
->alloc
, layout
);
1593 struct anv_descriptor
{
1594 VkDescriptorType type
;
1598 VkImageLayout layout
;
1599 struct anv_image_view
*image_view
;
1600 struct anv_sampler
*sampler
;
1604 struct anv_buffer
*buffer
;
1609 struct anv_buffer_view
*buffer_view
;
1613 struct anv_descriptor_set
{
1614 struct anv_descriptor_pool
*pool
;
1615 struct anv_descriptor_set_layout
*layout
;
1618 /* State relative to anv_descriptor_pool::bo */
1619 struct anv_state desc_mem
;
1620 /* Surface state for the descriptor buffer */
1621 struct anv_state desc_surface_state
;
1623 uint32_t buffer_view_count
;
1624 struct anv_buffer_view
*buffer_views
;
1625 struct anv_descriptor descriptors
[0];
1628 struct anv_buffer_view
{
1629 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1630 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1632 struct anv_address address
;
1634 struct anv_state surface_state
;
1635 struct anv_state storage_surface_state
;
1636 struct anv_state writeonly_storage_surface_state
;
1638 struct brw_image_param storage_image_param
;
1641 struct anv_push_descriptor_set
{
1642 struct anv_descriptor_set set
;
1644 /* Put this field right behind anv_descriptor_set so it fills up the
1645 * descriptors[0] field. */
1646 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1648 /** True if the descriptor set buffer has been referenced by a draw or
1651 bool set_used_on_gpu
;
1653 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1656 struct anv_descriptor_pool
{
1662 struct util_vma_heap bo_heap
;
1664 struct anv_state_stream surface_state_stream
;
1665 void *surface_state_free_list
;
1670 enum anv_descriptor_template_entry_type
{
1671 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1672 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1673 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1676 struct anv_descriptor_template_entry
{
1677 /* The type of descriptor in this entry */
1678 VkDescriptorType type
;
1680 /* Binding in the descriptor set */
1683 /* Offset at which to write into the descriptor set binding */
1684 uint32_t array_element
;
1686 /* Number of elements to write into the descriptor set binding */
1687 uint32_t array_count
;
1689 /* Offset into the user provided data */
1692 /* Stride between elements into the user provided data */
1696 struct anv_descriptor_update_template
{
1697 VkPipelineBindPoint bind_point
;
1699 /* The descriptor set this template corresponds to. This value is only
1700 * valid if the template was created with the templateType
1701 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1705 /* Number of entries in this template */
1706 uint32_t entry_count
;
1708 /* Entries of the template */
1709 struct anv_descriptor_template_entry entries
[0];
1713 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1716 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1717 struct anv_descriptor_set
*set
,
1718 const VkDescriptorImageInfo
* const info
,
1719 VkDescriptorType type
,
1724 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1725 struct anv_descriptor_set
*set
,
1726 VkDescriptorType type
,
1727 struct anv_buffer_view
*buffer_view
,
1732 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1733 struct anv_descriptor_set
*set
,
1734 struct anv_state_stream
*alloc_stream
,
1735 VkDescriptorType type
,
1736 struct anv_buffer
*buffer
,
1739 VkDeviceSize offset
,
1740 VkDeviceSize range
);
1742 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1743 struct anv_descriptor_set
*set
,
1750 anv_descriptor_set_write_template(struct anv_device
*device
,
1751 struct anv_descriptor_set
*set
,
1752 struct anv_state_stream
*alloc_stream
,
1753 const struct anv_descriptor_update_template
*template,
1757 anv_descriptor_set_create(struct anv_device
*device
,
1758 struct anv_descriptor_pool
*pool
,
1759 struct anv_descriptor_set_layout
*layout
,
1760 struct anv_descriptor_set
**out_set
);
1763 anv_descriptor_set_destroy(struct anv_device
*device
,
1764 struct anv_descriptor_pool
*pool
,
1765 struct anv_descriptor_set
*set
);
1767 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
1768 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
1769 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1770 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1772 struct anv_pipeline_binding
{
1773 /* The descriptor set this surface corresponds to. The special value of
1774 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1775 * to a color attachment and not a regular descriptor.
1779 /* Binding in the descriptor set */
1782 /* Index in the binding */
1785 /* Plane in the binding index */
1788 /* Input attachment index (relative to the subpass) */
1789 uint8_t input_attachment_index
;
1791 /* For a storage image, whether it is write-only */
1795 struct anv_pipeline_layout
{
1797 struct anv_descriptor_set_layout
*layout
;
1798 uint32_t dynamic_offset_start
;
1803 unsigned char sha1
[20];
1807 struct anv_device
* device
;
1810 VkBufferUsageFlags usage
;
1812 /* Set when bound */
1813 struct anv_address address
;
1816 static inline uint64_t
1817 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1819 assert(offset
<= buffer
->size
);
1820 if (range
== VK_WHOLE_SIZE
) {
1821 return buffer
->size
- offset
;
1823 assert(range
+ offset
>= range
);
1824 assert(range
+ offset
<= buffer
->size
);
1829 enum anv_cmd_dirty_bits
{
1830 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1831 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1832 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1833 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1834 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1835 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1836 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1837 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1838 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1839 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1840 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1841 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1842 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1843 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
1845 typedef uint32_t anv_cmd_dirty_mask_t
;
1847 enum anv_pipe_bits
{
1848 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1849 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1850 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1851 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1852 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1853 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1854 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1855 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1856 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1857 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1858 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1860 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1861 * a flush has happened but not a CS stall. The next time we do any sort
1862 * of invalidation we need to insert a CS stall at that time. Otherwise,
1863 * we would have to CS stall on every flush which could be bad.
1865 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1867 /* This bit does not exist directly in PIPE_CONTROL. It means that render
1868 * target operations related to transfer commands with VkBuffer as
1869 * destination are ongoing. Some operations like copies on the command
1870 * streamer might need to be aware of this to trigger the appropriate stall
1871 * before they can proceed with the copy.
1873 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
1876 #define ANV_PIPE_FLUSH_BITS ( \
1877 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1878 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1879 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1881 #define ANV_PIPE_STALL_BITS ( \
1882 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1883 ANV_PIPE_DEPTH_STALL_BIT | \
1884 ANV_PIPE_CS_STALL_BIT)
1886 #define ANV_PIPE_INVALIDATE_BITS ( \
1887 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1888 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1889 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1890 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1891 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1892 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1894 static inline enum anv_pipe_bits
1895 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1897 enum anv_pipe_bits pipe_bits
= 0;
1900 for_each_bit(b
, flags
) {
1901 switch ((VkAccessFlagBits
)(1 << b
)) {
1902 case VK_ACCESS_SHADER_WRITE_BIT
:
1903 /* We're transitioning a buffer that was previously used as write
1904 * destination through the data port. To make its content available
1905 * to future operations, flush the data cache.
1907 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1909 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1910 /* We're transitioning a buffer that was previously used as render
1911 * target. To make its content available to future operations, flush
1912 * the render target cache.
1914 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1916 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1917 /* We're transitioning a buffer that was previously used as depth
1918 * buffer. To make its content available to future operations, flush
1921 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1923 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1924 /* We're transitioning a buffer that was previously used as a
1925 * transfer write destination. Generic write operations include color
1926 * & depth operations as well as buffer operations like :
1927 * - vkCmdClearColorImage()
1928 * - vkCmdClearDepthStencilImage()
1929 * - vkCmdBlitImage()
1930 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
1932 * Most of these operations are implemented using Blorp which writes
1933 * through the render target, so flush that cache to make it visible
1934 * to future operations. And for depth related operations we also
1935 * need to flush the depth cache.
1937 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1938 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1940 case VK_ACCESS_MEMORY_WRITE_BIT
:
1941 /* We're transitioning a buffer for generic write operations. Flush
1944 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
1947 break; /* Nothing to do */
1954 static inline enum anv_pipe_bits
1955 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1957 enum anv_pipe_bits pipe_bits
= 0;
1960 for_each_bit(b
, flags
) {
1961 switch ((VkAccessFlagBits
)(1 << b
)) {
1962 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1963 /* Indirect draw commands take a buffer as input that we're going to
1964 * read from the command streamer to load some of the HW registers
1965 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
1966 * command streamer stall so that all the cache flushes have
1967 * completed before the command streamer loads from memory.
1969 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1970 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
1971 * through a vertex buffer, so invalidate that cache.
1973 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1974 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
1975 * UBO from the buffer, so we need to invalidate constant cache.
1977 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1979 case VK_ACCESS_INDEX_READ_BIT
:
1980 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1981 /* We transitioning a buffer to be used for as input for vkCmdDraw*
1982 * commands, so we invalidate the VF cache to make sure there is no
1983 * stale data when we start rendering.
1985 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1987 case VK_ACCESS_UNIFORM_READ_BIT
:
1988 /* We transitioning a buffer to be used as uniform data. Because
1989 * uniform is accessed through the data port & sampler, we need to
1990 * invalidate the texture cache (sampler) & constant cache (data
1991 * port) to avoid stale data.
1993 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1994 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1996 case VK_ACCESS_SHADER_READ_BIT
:
1997 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1998 case VK_ACCESS_TRANSFER_READ_BIT
:
1999 /* Transitioning a buffer to be read through the sampler, so
2000 * invalidate the texture cache, we don't want any stale data.
2002 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2004 case VK_ACCESS_MEMORY_READ_BIT
:
2005 /* Transitioning a buffer for generic read, invalidate all the
2008 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2010 case VK_ACCESS_MEMORY_WRITE_BIT
:
2011 /* Generic write, make sure all previously written things land in
2014 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2016 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2017 /* Transitioning a buffer for conditional rendering. We'll load the
2018 * content of this buffer into HW registers using the command
2019 * streamer, so we need to stall the command streamer to make sure
2020 * any in-flight flush operations have completed.
2022 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2025 break; /* Nothing to do */
2032 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2033 VK_IMAGE_ASPECT_COLOR_BIT | \
2034 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2035 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2036 VK_IMAGE_ASPECT_PLANE_2_BIT)
2037 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2038 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2039 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2040 VK_IMAGE_ASPECT_PLANE_2_BIT)
2042 struct anv_vertex_binding
{
2043 struct anv_buffer
* buffer
;
2044 VkDeviceSize offset
;
2047 struct anv_xfb_binding
{
2048 struct anv_buffer
* buffer
;
2049 VkDeviceSize offset
;
2053 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
2054 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2056 struct anv_push_constants
{
2057 /* Current allocated size of this push constants data structure.
2058 * Because a decent chunk of it may not be used (images on SKL, for
2059 * instance), we won't actually allocate the entire structure up-front.
2063 /* Push constant data provided by the client through vkPushConstants */
2064 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2066 /* Used for vkCmdDispatchBase */
2067 uint32_t base_work_group_id
[3];
2069 /* Image data for image_load_store on pre-SKL */
2070 struct brw_image_param images
[MAX_GEN8_IMAGES
];
2073 struct anv_dynamic_state
{
2076 VkViewport viewports
[MAX_VIEWPORTS
];
2081 VkRect2D scissors
[MAX_SCISSORS
];
2092 float blend_constants
[4];
2102 } stencil_compare_mask
;
2107 } stencil_write_mask
;
2112 } stencil_reference
;
2115 extern const struct anv_dynamic_state default_dynamic_state
;
2117 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2118 const struct anv_dynamic_state
*src
,
2119 uint32_t copy_mask
);
2121 struct anv_surface_state
{
2122 struct anv_state state
;
2123 /** Address of the surface referred to by this state
2125 * This address is relative to the start of the BO.
2127 struct anv_address address
;
2128 /* Address of the aux surface, if any
2130 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2132 * With the exception of gen8, the bottom 12 bits of this address' offset
2133 * include extra aux information.
2135 struct anv_address aux_address
;
2136 /* Address of the clear color, if any
2138 * This address is relative to the start of the BO.
2140 struct anv_address clear_address
;
2144 * Attachment state when recording a renderpass instance.
2146 * The clear value is valid only if there exists a pending clear.
2148 struct anv_attachment_state
{
2149 enum isl_aux_usage aux_usage
;
2150 enum isl_aux_usage input_aux_usage
;
2151 struct anv_surface_state color
;
2152 struct anv_surface_state input
;
2154 VkImageLayout current_layout
;
2155 VkImageAspectFlags pending_clear_aspects
;
2156 VkImageAspectFlags pending_load_aspects
;
2158 VkClearValue clear_value
;
2159 bool clear_color_is_zero_one
;
2160 bool clear_color_is_zero
;
2162 /* When multiview is active, attachments with a renderpass clear
2163 * operation have their respective layers cleared on the first
2164 * subpass that uses them, and only in that subpass. We keep track
2165 * of this using a bitfield to indicate which layers of an attachment
2166 * have not been cleared yet when multiview is active.
2168 uint32_t pending_clear_views
;
2171 /** State tracking for particular pipeline bind point
2173 * This struct is the base struct for anv_cmd_graphics_state and
2174 * anv_cmd_compute_state. These are used to track state which is bound to a
2175 * particular type of pipeline. Generic state that applies per-stage such as
2176 * binding table offsets and push constants is tracked generically with a
2177 * per-stage array in anv_cmd_state.
2179 struct anv_cmd_pipeline_state
{
2180 struct anv_pipeline
*pipeline
;
2181 struct anv_pipeline_layout
*layout
;
2183 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2184 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2186 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2189 /** State tracking for graphics pipeline
2191 * This has anv_cmd_pipeline_state as a base struct to track things which get
2192 * bound to a graphics pipeline. Along with general pipeline bind point state
2193 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2194 * state which is graphics-specific.
2196 struct anv_cmd_graphics_state
{
2197 struct anv_cmd_pipeline_state base
;
2199 anv_cmd_dirty_mask_t dirty
;
2202 struct anv_dynamic_state dynamic
;
2205 struct anv_buffer
*index_buffer
;
2206 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2207 uint32_t index_offset
;
2211 /** State tracking for compute pipeline
2213 * This has anv_cmd_pipeline_state as a base struct to track things which get
2214 * bound to a compute pipeline. Along with general pipeline bind point state
2215 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2216 * state which is compute-specific.
2218 struct anv_cmd_compute_state
{
2219 struct anv_cmd_pipeline_state base
;
2221 bool pipeline_dirty
;
2223 struct anv_address num_workgroups
;
2226 /** State required while building cmd buffer */
2227 struct anv_cmd_state
{
2228 /* PIPELINE_SELECT.PipelineSelection */
2229 uint32_t current_pipeline
;
2230 const struct gen_l3_config
* current_l3_config
;
2232 struct anv_cmd_graphics_state gfx
;
2233 struct anv_cmd_compute_state compute
;
2235 enum anv_pipe_bits pending_pipe_bits
;
2236 VkShaderStageFlags descriptors_dirty
;
2237 VkShaderStageFlags push_constants_dirty
;
2239 struct anv_framebuffer
* framebuffer
;
2240 struct anv_render_pass
* pass
;
2241 struct anv_subpass
* subpass
;
2242 VkRect2D render_area
;
2243 uint32_t restart_index
;
2244 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2246 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2247 VkShaderStageFlags push_constant_stages
;
2248 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
2249 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2250 struct anv_state samplers
[MESA_SHADER_STAGES
];
2253 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2254 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2255 * and before invoking the secondary in ExecuteCommands.
2257 bool pma_fix_enabled
;
2260 * Whether or not we know for certain that HiZ is enabled for the current
2261 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2262 * enabled or not, this will be false.
2266 bool conditional_render_enabled
;
2269 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2270 * valid only when recording a render pass instance.
2272 struct anv_attachment_state
* attachments
;
2275 * Surface states for color render targets. These are stored in a single
2276 * flat array. For depth-stencil attachments, the surface state is simply
2279 struct anv_state render_pass_states
;
2282 * A null surface state of the right size to match the framebuffer. This
2283 * is one of the states in render_pass_states.
2285 struct anv_state null_surface_state
;
2288 struct anv_cmd_pool
{
2289 VkAllocationCallbacks alloc
;
2290 struct list_head cmd_buffers
;
2293 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2295 enum anv_cmd_buffer_exec_mode
{
2296 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2297 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2298 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2299 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2300 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2303 struct anv_cmd_buffer
{
2304 VK_LOADER_DATA _loader_data
;
2306 struct anv_device
* device
;
2308 struct anv_cmd_pool
* pool
;
2309 struct list_head pool_link
;
2311 struct anv_batch batch
;
2313 /* Fields required for the actual chain of anv_batch_bo's.
2315 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2317 struct list_head batch_bos
;
2318 enum anv_cmd_buffer_exec_mode exec_mode
;
2320 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2321 * referenced by this command buffer
2323 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2325 struct u_vector seen_bbos
;
2327 /* A vector of int32_t's for every block of binding tables.
2329 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2331 struct u_vector bt_block_states
;
2334 struct anv_reloc_list surface_relocs
;
2335 /** Last seen surface state block pool center bo offset */
2336 uint32_t last_ss_pool_center
;
2338 /* Serial for tracking buffer completion */
2341 /* Stream objects for storing temporary data */
2342 struct anv_state_stream surface_state_stream
;
2343 struct anv_state_stream dynamic_state_stream
;
2345 VkCommandBufferUsageFlags usage_flags
;
2346 VkCommandBufferLevel level
;
2348 struct anv_cmd_state state
;
2351 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2352 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2353 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2354 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2355 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2356 struct anv_cmd_buffer
*secondary
);
2357 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2358 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2359 struct anv_cmd_buffer
*cmd_buffer
,
2360 const VkSemaphore
*in_semaphores
,
2361 uint32_t num_in_semaphores
,
2362 const VkSemaphore
*out_semaphores
,
2363 uint32_t num_out_semaphores
,
2366 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2369 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
2370 gl_shader_stage stage
, uint32_t size
);
2371 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
2372 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
2373 (offsetof(struct anv_push_constants, field) + \
2374 sizeof(cmd_buffer->state.push_constants[0]->field)))
2376 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2377 const void *data
, uint32_t size
, uint32_t alignment
);
2378 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2379 uint32_t *a
, uint32_t *b
,
2380 uint32_t dwords
, uint32_t alignment
);
2383 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2385 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2386 uint32_t entries
, uint32_t *state_offset
);
2388 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2390 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2391 uint32_t size
, uint32_t alignment
);
2394 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2396 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2397 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2398 bool depth_clamp_enable
);
2399 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2401 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2402 struct anv_render_pass
*pass
,
2403 struct anv_framebuffer
*framebuffer
,
2404 const VkClearValue
*clear_values
);
2406 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2409 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2410 gl_shader_stage stage
);
2412 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2414 const struct anv_image_view
*
2415 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2418 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2419 uint32_t num_entries
,
2420 uint32_t *state_offset
,
2421 struct anv_state
*bt_state
);
2423 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2425 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2427 enum anv_fence_type
{
2428 ANV_FENCE_TYPE_NONE
= 0,
2430 ANV_FENCE_TYPE_SYNCOBJ
,
2434 enum anv_bo_fence_state
{
2435 /** Indicates that this is a new (or newly reset fence) */
2436 ANV_BO_FENCE_STATE_RESET
,
2438 /** Indicates that this fence has been submitted to the GPU but is still
2439 * (as far as we know) in use by the GPU.
2441 ANV_BO_FENCE_STATE_SUBMITTED
,
2443 ANV_BO_FENCE_STATE_SIGNALED
,
2446 struct anv_fence_impl
{
2447 enum anv_fence_type type
;
2450 /** Fence implementation for BO fences
2452 * These fences use a BO and a set of CPU-tracked state flags. The BO
2453 * is added to the object list of the last execbuf call in a QueueSubmit
2454 * and is marked EXEC_WRITE. The state flags track when the BO has been
2455 * submitted to the kernel. We need to do this because Vulkan lets you
2456 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2457 * will say it's idle in this case.
2461 enum anv_bo_fence_state state
;
2464 /** DRM syncobj handle for syncobj-based fences */
2468 struct wsi_fence
*fence_wsi
;
2473 /* Permanent fence state. Every fence has some form of permanent state
2474 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2475 * cross-process fences) or it could just be a dummy for use internally.
2477 struct anv_fence_impl permanent
;
2479 /* Temporary fence state. A fence *may* have temporary state. That state
2480 * is added to the fence by an import operation and is reset back to
2481 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2482 * state cannot be signaled because the fence must already be signaled
2483 * before the temporary state can be exported from the fence in the other
2484 * process and imported here.
2486 struct anv_fence_impl temporary
;
2491 struct anv_state state
;
2494 enum anv_semaphore_type
{
2495 ANV_SEMAPHORE_TYPE_NONE
= 0,
2496 ANV_SEMAPHORE_TYPE_DUMMY
,
2497 ANV_SEMAPHORE_TYPE_BO
,
2498 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2499 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2502 struct anv_semaphore_impl
{
2503 enum anv_semaphore_type type
;
2506 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2507 * This BO will be added to the object list on any execbuf2 calls for
2508 * which this semaphore is used as a wait or signal fence. When used as
2509 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2513 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2514 * If the semaphore is in the unsignaled state due to either just being
2515 * created or because it has been used for a wait, fd will be -1.
2519 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2520 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2521 * import so we don't need to bother with a userspace cache.
2527 struct anv_semaphore
{
2528 /* Permanent semaphore state. Every semaphore has some form of permanent
2529 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2530 * (for cross-process semaphores0 or it could just be a dummy for use
2533 struct anv_semaphore_impl permanent
;
2535 /* Temporary semaphore state. A semaphore *may* have temporary state.
2536 * That state is added to the semaphore by an import operation and is reset
2537 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2538 * semaphore with temporary state cannot be signaled because the semaphore
2539 * must already be signaled before the temporary state can be exported from
2540 * the semaphore in the other process and imported here.
2542 struct anv_semaphore_impl temporary
;
2545 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2546 struct anv_semaphore
*semaphore
);
2548 struct anv_shader_module
{
2549 unsigned char sha1
[20];
2554 static inline gl_shader_stage
2555 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2557 assert(__builtin_popcount(vk_stage
) == 1);
2558 return ffs(vk_stage
) - 1;
2561 static inline VkShaderStageFlagBits
2562 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2564 return (1 << mesa_stage
);
2567 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2569 #define anv_foreach_stage(stage, stage_bits) \
2570 for (gl_shader_stage stage, \
2571 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2572 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2573 __tmp &= ~(1 << (stage)))
2575 struct anv_pipeline_bind_map
{
2576 uint32_t surface_count
;
2577 uint32_t sampler_count
;
2578 uint32_t image_param_count
;
2580 struct anv_pipeline_binding
* surface_to_descriptor
;
2581 struct anv_pipeline_binding
* sampler_to_descriptor
;
2584 struct anv_shader_bin_key
{
2589 struct anv_shader_bin
{
2592 const struct anv_shader_bin_key
*key
;
2594 struct anv_state kernel
;
2595 uint32_t kernel_size
;
2597 struct anv_state constant_data
;
2598 uint32_t constant_data_size
;
2600 const struct brw_stage_prog_data
*prog_data
;
2601 uint32_t prog_data_size
;
2603 struct nir_xfb_info
*xfb_info
;
2605 struct anv_pipeline_bind_map bind_map
;
2608 struct anv_shader_bin
*
2609 anv_shader_bin_create(struct anv_device
*device
,
2610 const void *key
, uint32_t key_size
,
2611 const void *kernel
, uint32_t kernel_size
,
2612 const void *constant_data
, uint32_t constant_data_size
,
2613 const struct brw_stage_prog_data
*prog_data
,
2614 uint32_t prog_data_size
, const void *prog_data_param
,
2615 const struct nir_xfb_info
*xfb_info
,
2616 const struct anv_pipeline_bind_map
*bind_map
);
2619 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2622 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2624 assert(shader
&& shader
->ref_cnt
>= 1);
2625 p_atomic_inc(&shader
->ref_cnt
);
2629 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2631 assert(shader
&& shader
->ref_cnt
>= 1);
2632 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2633 anv_shader_bin_destroy(device
, shader
);
2636 struct anv_pipeline
{
2637 struct anv_device
* device
;
2638 struct anv_batch batch
;
2639 uint32_t batch_data
[512];
2640 struct anv_reloc_list batch_relocs
;
2641 uint32_t dynamic_state_mask
;
2642 struct anv_dynamic_state dynamic_state
;
2644 struct anv_subpass
* subpass
;
2646 bool needs_data_cache
;
2648 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2651 const struct gen_l3_config
* l3_config
;
2652 uint32_t total_size
;
2655 VkShaderStageFlags active_stages
;
2656 struct anv_state blend_state
;
2659 struct anv_pipeline_vertex_binding
{
2662 uint32_t instance_divisor
;
2667 bool primitive_restart
;
2670 uint32_t cs_right_mask
;
2673 bool depth_test_enable
;
2674 bool writes_stencil
;
2675 bool stencil_test_enable
;
2676 bool depth_clamp_enable
;
2677 bool depth_clip_enable
;
2678 bool sample_shading_enable
;
2683 uint32_t depth_stencil_state
[3];
2689 uint32_t wm_depth_stencil
[3];
2693 uint32_t wm_depth_stencil
[4];
2696 uint32_t interface_descriptor_data
[8];
2700 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2701 gl_shader_stage stage
)
2703 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2706 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2707 static inline const struct brw_##prefix##_prog_data * \
2708 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2710 if (anv_pipeline_has_stage(pipeline, stage)) { \
2711 return (const struct brw_##prefix##_prog_data *) \
2712 pipeline->shaders[stage]->prog_data; \
2718 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2719 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2720 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2721 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2722 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2723 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2725 static inline const struct brw_vue_prog_data
*
2726 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2728 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2729 return &get_gs_prog_data(pipeline
)->base
;
2730 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2731 return &get_tes_prog_data(pipeline
)->base
;
2733 return &get_vs_prog_data(pipeline
)->base
;
2737 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2738 struct anv_pipeline_cache
*cache
,
2739 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2740 const VkAllocationCallbacks
*alloc
);
2743 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2744 struct anv_pipeline_cache
*cache
,
2745 const VkComputePipelineCreateInfo
*info
,
2746 const struct anv_shader_module
*module
,
2747 const char *entrypoint
,
2748 const VkSpecializationInfo
*spec_info
);
2750 struct anv_format_plane
{
2751 enum isl_format isl_format
:16;
2752 struct isl_swizzle swizzle
;
2754 /* Whether this plane contains chroma channels */
2757 /* For downscaling of YUV planes */
2758 uint8_t denominator_scales
[2];
2760 /* How to map sampled ycbcr planes to a single 4 component element. */
2761 struct isl_swizzle ycbcr_swizzle
;
2763 /* What aspect is associated to this plane */
2764 VkImageAspectFlags aspect
;
2769 struct anv_format_plane planes
[3];
2775 static inline uint32_t
2776 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2777 VkImageAspectFlags aspect_mask
)
2779 switch (aspect_mask
) {
2780 case VK_IMAGE_ASPECT_COLOR_BIT
:
2781 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2782 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2784 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2785 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2788 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2790 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2793 /* Purposefully assert with depth/stencil aspects. */
2794 unreachable("invalid image aspect");
2798 static inline VkImageAspectFlags
2799 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
2802 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2803 if (util_bitcount(image_aspects
) > 1)
2804 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
2805 return VK_IMAGE_ASPECT_COLOR_BIT
;
2807 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
2808 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
2809 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
2810 return VK_IMAGE_ASPECT_STENCIL_BIT
;
2813 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2814 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2816 const struct anv_format
*
2817 anv_get_format(VkFormat format
);
2819 static inline uint32_t
2820 anv_get_format_planes(VkFormat vk_format
)
2822 const struct anv_format
*format
= anv_get_format(vk_format
);
2824 return format
!= NULL
? format
->n_planes
: 0;
2827 struct anv_format_plane
2828 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2829 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
2831 static inline enum isl_format
2832 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2833 VkImageAspectFlags aspect
, VkImageTiling tiling
)
2835 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
2838 static inline struct isl_swizzle
2839 anv_swizzle_for_render(struct isl_swizzle swizzle
)
2841 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2842 * RGB as RGBA for texturing
2844 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
2845 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
2847 /* But it doesn't matter what we render to that channel */
2848 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
2854 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
2857 * Subsurface of an anv_image.
2859 struct anv_surface
{
2860 /** Valid only if isl_surf::size_B > 0. */
2861 struct isl_surf isl
;
2864 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2871 /* The original VkFormat provided by the client. This may not match any
2872 * of the actual surface formats.
2875 const struct anv_format
*format
;
2877 VkImageAspectFlags aspects
;
2880 uint32_t array_size
;
2881 uint32_t samples
; /**< VkImageCreateInfo::samples */
2883 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2884 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
2885 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2887 /** True if this is needs to be bound to an appropriately tiled BO.
2889 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2890 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2891 * we require a dedicated allocation so that we can know to allocate a
2894 bool needs_set_tiling
;
2897 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2898 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2900 uint64_t drm_format_mod
;
2905 /* Whether the image is made of several underlying buffer objects rather a
2906 * single one with different offsets.
2910 /* All the formats that can be used when creating views of this image
2911 * are CCS_E compatible.
2913 bool ccs_e_compatible
;
2915 /* Image was created with external format. */
2916 bool external_format
;
2921 * For each foo, anv_image::planes[x].surface is valid if and only if
2922 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2923 * to figure the number associated with a given aspect.
2925 * The hardware requires that the depth buffer and stencil buffer be
2926 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2927 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2928 * allocate the depth and stencil buffers as separate surfaces in the same
2933 * -----------------------
2935 * ----------------------- |
2936 * | shadow surface0 | |
2937 * ----------------------- | Plane 0
2938 * | aux surface0 | |
2939 * ----------------------- |
2940 * | fast clear colors0 | \|/
2941 * -----------------------
2943 * ----------------------- |
2944 * | shadow surface1 | |
2945 * ----------------------- | Plane 1
2946 * | aux surface1 | |
2947 * ----------------------- |
2948 * | fast clear colors1 | \|/
2949 * -----------------------
2952 * -----------------------
2956 * Offset of the entire plane (whenever the image is disjoint this is
2964 struct anv_surface surface
;
2967 * A surface which shadows the main surface and may have different
2968 * tiling. This is used for sampling using a tiling that isn't supported
2969 * for other operations.
2971 struct anv_surface shadow_surface
;
2974 * For color images, this is the aux usage for this image when not used
2975 * as a color attachment.
2977 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2978 * image has a HiZ buffer.
2980 enum isl_aux_usage aux_usage
;
2982 struct anv_surface aux_surface
;
2985 * Offset of the fast clear state (used to compute the
2986 * fast_clear_state_offset of the following planes).
2988 uint32_t fast_clear_state_offset
;
2991 * BO associated with this plane, set when bound.
2993 struct anv_address address
;
2996 * When destroying the image, also free the bo.
3002 /* The ordering of this enum is important */
3003 enum anv_fast_clear_type
{
3004 /** Image does not have/support any fast-clear blocks */
3005 ANV_FAST_CLEAR_NONE
= 0,
3006 /** Image has/supports fast-clear but only to the default value */
3007 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3008 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3009 ANV_FAST_CLEAR_ANY
= 2,
3012 /* Returns the number of auxiliary buffer levels attached to an image. */
3013 static inline uint8_t
3014 anv_image_aux_levels(const struct anv_image
* const image
,
3015 VkImageAspectFlagBits aspect
)
3017 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3018 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3019 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
3022 /* Returns the number of auxiliary buffer layers attached to an image. */
3023 static inline uint32_t
3024 anv_image_aux_layers(const struct anv_image
* const image
,
3025 VkImageAspectFlagBits aspect
,
3026 const uint8_t miplevel
)
3030 /* The miplevel must exist in the main buffer. */
3031 assert(miplevel
< image
->levels
);
3033 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3034 /* There are no layers with auxiliary data because the miplevel has no
3039 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3040 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
3041 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
3045 static inline struct anv_address
3046 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3047 const struct anv_image
*image
,
3048 VkImageAspectFlagBits aspect
)
3050 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3052 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3053 return anv_address_add(image
->planes
[plane
].address
,
3054 image
->planes
[plane
].fast_clear_state_offset
);
3057 static inline struct anv_address
3058 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3059 const struct anv_image
*image
,
3060 VkImageAspectFlagBits aspect
)
3062 struct anv_address addr
=
3063 anv_image_get_clear_color_addr(device
, image
, aspect
);
3065 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3066 device
->isl_dev
.ss
.clear_color_state_size
:
3067 device
->isl_dev
.ss
.clear_value_size
;
3068 return anv_address_add(addr
, clear_color_state_size
);
3071 static inline struct anv_address
3072 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3073 const struct anv_image
*image
,
3074 VkImageAspectFlagBits aspect
,
3075 uint32_t level
, uint32_t array_layer
)
3077 assert(level
< anv_image_aux_levels(image
, aspect
));
3078 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3079 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3080 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3082 struct anv_address addr
=
3083 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3084 addr
.offset
+= 4; /* Go past the fast clear type */
3086 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3087 for (uint32_t l
= 0; l
< level
; l
++)
3088 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3090 addr
.offset
+= level
* image
->array_size
* 4;
3092 addr
.offset
+= array_layer
* 4;
3097 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3099 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3100 const struct anv_image
*image
)
3102 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3105 if (devinfo
->gen
< 8)
3108 return image
->samples
== 1;
3112 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3113 const struct anv_image
*image
,
3114 VkImageAspectFlagBits aspect
,
3115 enum isl_aux_usage aux_usage
,
3117 uint32_t base_layer
,
3118 uint32_t layer_count
);
3121 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3122 const struct anv_image
*image
,
3123 VkImageAspectFlagBits aspect
,
3124 enum isl_aux_usage aux_usage
,
3125 enum isl_format format
, struct isl_swizzle swizzle
,
3126 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3127 VkRect2D area
, union isl_color_value clear_color
);
3129 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3130 const struct anv_image
*image
,
3131 VkImageAspectFlags aspects
,
3132 enum isl_aux_usage depth_aux_usage
,
3134 uint32_t base_layer
, uint32_t layer_count
,
3136 float depth_value
, uint8_t stencil_value
);
3138 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3139 const struct anv_image
*src_image
,
3140 enum isl_aux_usage src_aux_usage
,
3141 uint32_t src_level
, uint32_t src_base_layer
,
3142 const struct anv_image
*dst_image
,
3143 enum isl_aux_usage dst_aux_usage
,
3144 uint32_t dst_level
, uint32_t dst_base_layer
,
3145 VkImageAspectFlagBits aspect
,
3146 uint32_t src_x
, uint32_t src_y
,
3147 uint32_t dst_x
, uint32_t dst_y
,
3148 uint32_t width
, uint32_t height
,
3149 uint32_t layer_count
,
3150 enum blorp_filter filter
);
3152 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3153 const struct anv_image
*image
,
3154 VkImageAspectFlagBits aspect
, uint32_t level
,
3155 uint32_t base_layer
, uint32_t layer_count
,
3156 enum isl_aux_op hiz_op
);
3158 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3159 const struct anv_image
*image
,
3160 VkImageAspectFlags aspects
,
3162 uint32_t base_layer
, uint32_t layer_count
,
3163 VkRect2D area
, uint8_t stencil_value
);
3165 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3166 const struct anv_image
*image
,
3167 enum isl_format format
,
3168 VkImageAspectFlagBits aspect
,
3169 uint32_t base_layer
, uint32_t layer_count
,
3170 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3173 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3174 const struct anv_image
*image
,
3175 enum isl_format format
,
3176 VkImageAspectFlagBits aspect
, uint32_t level
,
3177 uint32_t base_layer
, uint32_t layer_count
,
3178 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3182 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3183 const struct anv_image
*image
,
3184 uint32_t base_level
, uint32_t level_count
,
3185 uint32_t base_layer
, uint32_t layer_count
);
3188 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3189 const struct anv_image
*image
,
3190 const VkImageAspectFlagBits aspect
,
3191 const VkImageLayout layout
);
3193 enum anv_fast_clear_type
3194 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3195 const struct anv_image
* const image
,
3196 const VkImageAspectFlagBits aspect
,
3197 const VkImageLayout layout
);
3199 /* This is defined as a macro so that it works for both
3200 * VkImageSubresourceRange and VkImageSubresourceLayers
3202 #define anv_get_layerCount(_image, _range) \
3203 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3204 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3206 static inline uint32_t
3207 anv_get_levelCount(const struct anv_image
*image
,
3208 const VkImageSubresourceRange
*range
)
3210 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3211 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3214 static inline VkImageAspectFlags
3215 anv_image_expand_aspects(const struct anv_image
*image
,
3216 VkImageAspectFlags aspects
)
3218 /* If the underlying image has color plane aspects and
3219 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3220 * the underlying image. */
3221 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3222 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3223 return image
->aspects
;
3229 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3230 VkImageAspectFlags aspects2
)
3232 if (aspects1
== aspects2
)
3235 /* Only 1 color aspects are compatibles. */
3236 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3237 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3238 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3244 struct anv_image_view
{
3245 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3247 VkImageAspectFlags aspect_mask
;
3249 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3253 uint32_t image_plane
;
3255 struct isl_view isl
;
3258 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3259 * image layout of SHADER_READ_ONLY_OPTIMAL or
3260 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3262 struct anv_surface_state optimal_sampler_surface_state
;
3265 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3266 * image layout of GENERAL.
3268 struct anv_surface_state general_sampler_surface_state
;
3271 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3272 * states for write-only and readable, using the real format for
3273 * write-only and the lowered format for readable.
3275 struct anv_surface_state storage_surface_state
;
3276 struct anv_surface_state writeonly_storage_surface_state
;
3278 struct brw_image_param storage_image_param
;
3282 enum anv_image_view_state_flags
{
3283 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3284 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3287 void anv_image_fill_surface_state(struct anv_device
*device
,
3288 const struct anv_image
*image
,
3289 VkImageAspectFlagBits aspect
,
3290 const struct isl_view
*view
,
3291 isl_surf_usage_flags_t view_usage
,
3292 enum isl_aux_usage aux_usage
,
3293 const union isl_color_value
*clear_color
,
3294 enum anv_image_view_state_flags flags
,
3295 struct anv_surface_state
*state_inout
,
3296 struct brw_image_param
*image_param_out
);
3298 struct anv_image_create_info
{
3299 const VkImageCreateInfo
*vk_info
;
3301 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3302 isl_tiling_flags_t isl_tiling_flags
;
3304 /** These flags will be added to any derived from VkImageCreateInfo. */
3305 isl_surf_usage_flags_t isl_extra_usage_flags
;
3308 bool external_format
;
3311 VkResult
anv_image_create(VkDevice _device
,
3312 const struct anv_image_create_info
*info
,
3313 const VkAllocationCallbacks
* alloc
,
3316 const struct anv_surface
*
3317 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3318 VkImageAspectFlags aspect_mask
);
3321 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3323 static inline struct VkExtent3D
3324 anv_sanitize_image_extent(const VkImageType imageType
,
3325 const struct VkExtent3D imageExtent
)
3327 switch (imageType
) {
3328 case VK_IMAGE_TYPE_1D
:
3329 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3330 case VK_IMAGE_TYPE_2D
:
3331 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3332 case VK_IMAGE_TYPE_3D
:
3335 unreachable("invalid image type");
3339 static inline struct VkOffset3D
3340 anv_sanitize_image_offset(const VkImageType imageType
,
3341 const struct VkOffset3D imageOffset
)
3343 switch (imageType
) {
3344 case VK_IMAGE_TYPE_1D
:
3345 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3346 case VK_IMAGE_TYPE_2D
:
3347 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3348 case VK_IMAGE_TYPE_3D
:
3351 unreachable("invalid image type");
3355 VkFormatFeatureFlags
3356 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3358 const struct anv_format
*anv_format
,
3359 VkImageTiling vk_tiling
);
3361 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3362 struct anv_state state
,
3363 enum isl_format format
,
3364 struct anv_address address
,
3365 uint32_t range
, uint32_t stride
);
3368 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3369 const struct anv_attachment_state
*att_state
,
3370 const struct anv_image_view
*iview
)
3372 const struct isl_format_layout
*view_fmtl
=
3373 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3375 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3376 if (view_fmtl->channels.c.bits) \
3377 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3379 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3380 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3381 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3382 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3384 #undef COPY_CLEAR_COLOR_CHANNEL
3388 struct anv_ycbcr_conversion
{
3389 const struct anv_format
* format
;
3390 VkSamplerYcbcrModelConversion ycbcr_model
;
3391 VkSamplerYcbcrRange ycbcr_range
;
3392 VkComponentSwizzle mapping
[4];
3393 VkChromaLocation chroma_offsets
[2];
3394 VkFilter chroma_filter
;
3395 bool chroma_reconstruction
;
3398 struct anv_sampler
{
3399 uint32_t state
[3][4];
3401 struct anv_ycbcr_conversion
*conversion
;
3404 struct anv_framebuffer
{
3409 uint32_t attachment_count
;
3410 struct anv_image_view
* attachments
[0];
3413 struct anv_subpass_attachment
{
3414 VkImageUsageFlagBits usage
;
3415 uint32_t attachment
;
3416 VkImageLayout layout
;
3419 struct anv_subpass
{
3420 uint32_t attachment_count
;
3423 * A pointer to all attachment references used in this subpass.
3424 * Only valid if ::attachment_count > 0.
3426 struct anv_subpass_attachment
* attachments
;
3427 uint32_t input_count
;
3428 struct anv_subpass_attachment
* input_attachments
;
3429 uint32_t color_count
;
3430 struct anv_subpass_attachment
* color_attachments
;
3431 struct anv_subpass_attachment
* resolve_attachments
;
3433 struct anv_subpass_attachment
* depth_stencil_attachment
;
3434 struct anv_subpass_attachment
* ds_resolve_attachment
;
3435 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3436 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3440 /** Subpass has a depth/stencil self-dependency */
3441 bool has_ds_self_dep
;
3443 /** Subpass has at least one color resolve attachment */
3444 bool has_color_resolve
;
3447 static inline unsigned
3448 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3450 return MAX2(1, util_bitcount(subpass
->view_mask
));
3453 struct anv_render_pass_attachment
{
3454 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3455 * its members individually.
3459 VkImageUsageFlags usage
;
3460 VkAttachmentLoadOp load_op
;
3461 VkAttachmentStoreOp store_op
;
3462 VkAttachmentLoadOp stencil_load_op
;
3463 VkImageLayout initial_layout
;
3464 VkImageLayout final_layout
;
3465 VkImageLayout first_subpass_layout
;
3467 /* The subpass id in which the attachment will be used last. */
3468 uint32_t last_subpass_idx
;
3471 struct anv_render_pass
{
3472 uint32_t attachment_count
;
3473 uint32_t subpass_count
;
3474 /* An array of subpass_count+1 flushes, one per subpass boundary */
3475 enum anv_pipe_bits
* subpass_flushes
;
3476 struct anv_render_pass_attachment
* attachments
;
3477 struct anv_subpass subpasses
[0];
3480 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3482 struct anv_query_pool
{
3484 VkQueryPipelineStatisticFlags pipeline_statistics
;
3485 /** Stride between slots, in bytes */
3487 /** Number of slots in this query pool */
3492 int anv_get_instance_entrypoint_index(const char *name
);
3493 int anv_get_device_entrypoint_index(const char *name
);
3496 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3497 const struct anv_instance_extension_table
*instance
);
3500 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3501 const struct anv_instance_extension_table
*instance
,
3502 const struct anv_device_extension_table
*device
);
3504 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3507 void anv_dump_image_to_ppm(struct anv_device
*device
,
3508 struct anv_image
*image
, unsigned miplevel
,
3509 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3510 const char *filename
);
3512 enum anv_dump_action
{
3513 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3516 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3517 void anv_dump_finish(void);
3519 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
3520 struct anv_framebuffer
*fb
);
3522 static inline uint32_t
3523 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3525 /* This function must be called from within a subpass. */
3526 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3528 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3530 /* The id of this subpass shouldn't exceed the number of subpasses in this
3531 * render pass minus 1.
3533 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3537 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3539 static inline struct __anv_type * \
3540 __anv_type ## _from_handle(__VkType _handle) \
3542 return (struct __anv_type *) _handle; \
3545 static inline __VkType \
3546 __anv_type ## _to_handle(struct __anv_type *_obj) \
3548 return (__VkType) _obj; \
3551 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3553 static inline struct __anv_type * \
3554 __anv_type ## _from_handle(__VkType _handle) \
3556 return (struct __anv_type *)(uintptr_t) _handle; \
3559 static inline __VkType \
3560 __anv_type ## _to_handle(struct __anv_type *_obj) \
3562 return (__VkType)(uintptr_t) _obj; \
3565 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3566 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3568 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3569 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3570 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3571 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3572 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3574 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3575 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3576 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3577 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3578 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3579 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3580 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3581 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3582 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3583 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3584 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3585 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3586 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3587 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3588 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3589 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3590 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3591 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3592 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3593 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3594 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3595 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3596 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3598 /* Gen-specific function declarations */
3600 # include "anv_genX.h"
3602 # define genX(x) gen7_##x
3603 # include "anv_genX.h"
3605 # define genX(x) gen75_##x
3606 # include "anv_genX.h"
3608 # define genX(x) gen8_##x
3609 # include "anv_genX.h"
3611 # define genX(x) gen9_##x
3612 # include "anv_genX.h"
3614 # define genX(x) gen10_##x
3615 # include "anv_genX.h"
3617 # define genX(x) gen11_##x
3618 # include "anv_genX.h"
3622 #endif /* ANV_PRIVATE_H */