7a963c8fb6957777943af5b729cb3e52dc5c494c
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49
50 /* Pre-declarations needed for WSI entrypoints */
51 struct wl_surface;
52 struct wl_display;
53 typedef struct xcb_connection_t xcb_connection_t;
54 typedef uint32_t xcb_visualid_t;
55 typedef uint32_t xcb_window_t;
56
57 struct gen_l3_config;
58
59 #include <vulkan/vulkan.h>
60 #include <vulkan/vulkan_intel.h>
61 #include <vulkan/vk_icd.h>
62
63 #include "anv_entrypoints.h"
64 #include "brw_context.h"
65 #include "isl/isl.h"
66
67 #ifdef __cplusplus
68 extern "C" {
69 #endif
70
71 #define MAX_VBS 32
72 #define MAX_SETS 8
73 #define MAX_RTS 8
74 #define MAX_VIEWPORTS 16
75 #define MAX_SCISSORS 16
76 #define MAX_PUSH_CONSTANTS_SIZE 128
77 #define MAX_DYNAMIC_BUFFERS 16
78 #define MAX_IMAGES 8
79 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
80
81 #define anv_noreturn __attribute__((__noreturn__))
82 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
83
84 #define MIN(a, b) ((a) < (b) ? (a) : (b))
85 #define MAX(a, b) ((a) > (b) ? (a) : (b))
86
87 static inline uint32_t
88 align_down_npot_u32(uint32_t v, uint32_t a)
89 {
90 return v - (v % a);
91 }
92
93 static inline uint32_t
94 align_u32(uint32_t v, uint32_t a)
95 {
96 assert(a != 0 && a == (a & -a));
97 return (v + a - 1) & ~(a - 1);
98 }
99
100 static inline uint64_t
101 align_u64(uint64_t v, uint64_t a)
102 {
103 assert(a != 0 && a == (a & -a));
104 return (v + a - 1) & ~(a - 1);
105 }
106
107 static inline int32_t
108 align_i32(int32_t v, int32_t a)
109 {
110 assert(a != 0 && a == (a & -a));
111 return (v + a - 1) & ~(a - 1);
112 }
113
114 /** Alignment must be a power of 2. */
115 static inline bool
116 anv_is_aligned(uintmax_t n, uintmax_t a)
117 {
118 assert(a == (a & -a));
119 return (n & (a - 1)) == 0;
120 }
121
122 static inline uint32_t
123 anv_minify(uint32_t n, uint32_t levels)
124 {
125 if (unlikely(n == 0))
126 return 0;
127 else
128 return MAX(n >> levels, 1);
129 }
130
131 static inline float
132 anv_clamp_f(float f, float min, float max)
133 {
134 assert(min < max);
135
136 if (f > max)
137 return max;
138 else if (f < min)
139 return min;
140 else
141 return f;
142 }
143
144 static inline bool
145 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
146 {
147 if (*inout_mask & clear_mask) {
148 *inout_mask &= ~clear_mask;
149 return true;
150 } else {
151 return false;
152 }
153 }
154
155 #define for_each_bit(b, dword) \
156 for (uint32_t __dword = (dword); \
157 (b) = __builtin_ffs(__dword) - 1, __dword; \
158 __dword &= ~(1 << (b)))
159
160 #define typed_memcpy(dest, src, count) ({ \
161 static_assert(sizeof(*src) == sizeof(*dest), ""); \
162 memcpy((dest), (src), (count) * sizeof(*(src))); \
163 })
164
165 #define zero(x) (memset(&(x), 0, sizeof(x)))
166
167 /* Define no kernel as 1, since that's an illegal offset for a kernel */
168 #define NO_KERNEL 1
169
170 struct anv_common {
171 VkStructureType sType;
172 const void* pNext;
173 };
174
175 /* Whenever we generate an error, pass it through this function. Useful for
176 * debugging, where we can break on it. Only call at error site, not when
177 * propagating errors. Might be useful to plug in a stack trace here.
178 */
179
180 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
181
182 #ifdef DEBUG
183 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
184 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
185 #else
186 #define vk_error(error) error
187 #define vk_errorf(error, format, ...) error
188 #endif
189
190 void __anv_finishme(const char *file, int line, const char *format, ...)
191 anv_printflike(3, 4);
192 void anv_loge(const char *format, ...) anv_printflike(1, 2);
193 void anv_loge_v(const char *format, va_list va);
194
195 /**
196 * Print a FINISHME message, including its source location.
197 */
198 #define anv_finishme(format, ...) \
199 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
200
201 /* A non-fatal assert. Useful for debugging. */
202 #ifdef DEBUG
203 #define anv_assert(x) ({ \
204 if (unlikely(!(x))) \
205 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
206 })
207 #else
208 #define anv_assert(x)
209 #endif
210
211 /**
212 * If a block of code is annotated with anv_validate, then the block runs only
213 * in debug builds.
214 */
215 #ifdef DEBUG
216 #define anv_validate if (1)
217 #else
218 #define anv_validate if (0)
219 #endif
220
221 void anv_abortf(const char *format, ...) anv_noreturn anv_printflike(1, 2);
222 void anv_abortfv(const char *format, va_list va) anv_noreturn;
223
224 #define stub_return(v) \
225 do { \
226 anv_finishme("stub %s", __func__); \
227 return (v); \
228 } while (0)
229
230 #define stub() \
231 do { \
232 anv_finishme("stub %s", __func__); \
233 return; \
234 } while (0)
235
236 /**
237 * A dynamically growable, circular buffer. Elements are added at head and
238 * removed from tail. head and tail are free-running uint32_t indices and we
239 * only compute the modulo with size when accessing the array. This way,
240 * number of bytes in the queue is always head - tail, even in case of
241 * wraparound.
242 */
243
244 struct anv_vector {
245 uint32_t head;
246 uint32_t tail;
247 uint32_t element_size;
248 uint32_t size;
249 void *data;
250 };
251
252 int anv_vector_init(struct anv_vector *queue, uint32_t element_size, uint32_t size);
253 void *anv_vector_add(struct anv_vector *queue);
254 void *anv_vector_remove(struct anv_vector *queue);
255
256 static inline int
257 anv_vector_length(struct anv_vector *queue)
258 {
259 return (queue->head - queue->tail) / queue->element_size;
260 }
261
262 static inline void *
263 anv_vector_head(struct anv_vector *vector)
264 {
265 assert(vector->tail < vector->head);
266 return (void *)((char *)vector->data +
267 ((vector->head - vector->element_size) &
268 (vector->size - 1)));
269 }
270
271 static inline void *
272 anv_vector_tail(struct anv_vector *vector)
273 {
274 return (void *)((char *)vector->data + (vector->tail & (vector->size - 1)));
275 }
276
277 static inline void
278 anv_vector_finish(struct anv_vector *queue)
279 {
280 free(queue->data);
281 }
282
283 #define anv_vector_foreach(elem, queue) \
284 static_assert(__builtin_types_compatible_p(__typeof__(queue), struct anv_vector *), ""); \
285 for (uint32_t __anv_vector_offset = (queue)->tail; \
286 elem = (queue)->data + (__anv_vector_offset & ((queue)->size - 1)), __anv_vector_offset < (queue)->head; \
287 __anv_vector_offset += (queue)->element_size)
288
289 struct anv_bo {
290 uint32_t gem_handle;
291
292 /* Index into the current validation list. This is used by the
293 * validation list building alrogithm to track which buffers are already
294 * in the validation list so that we can ensure uniqueness.
295 */
296 uint32_t index;
297
298 /* Last known offset. This value is provided by the kernel when we
299 * execbuf and is used as the presumed offset for the next bunch of
300 * relocations.
301 */
302 uint64_t offset;
303
304 uint64_t size;
305 void *map;
306
307 /* We need to set the WRITE flag on winsys bos so GEM will know we're
308 * writing to them and synchronize uses on other rings (eg if the display
309 * server uses the blitter ring).
310 */
311 bool is_winsys_bo;
312 };
313
314 /* Represents a lock-free linked list of "free" things. This is used by
315 * both the block pool and the state pools. Unfortunately, in order to
316 * solve the ABA problem, we can't use a single uint32_t head.
317 */
318 union anv_free_list {
319 struct {
320 int32_t offset;
321
322 /* A simple count that is incremented every time the head changes. */
323 uint32_t count;
324 };
325 uint64_t u64;
326 };
327
328 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
329
330 struct anv_block_state {
331 union {
332 struct {
333 uint32_t next;
334 uint32_t end;
335 };
336 uint64_t u64;
337 };
338 };
339
340 struct anv_block_pool {
341 struct anv_device *device;
342
343 struct anv_bo bo;
344
345 /* The offset from the start of the bo to the "center" of the block
346 * pool. Pointers to allocated blocks are given by
347 * bo.map + center_bo_offset + offsets.
348 */
349 uint32_t center_bo_offset;
350
351 /* Current memory map of the block pool. This pointer may or may not
352 * point to the actual beginning of the block pool memory. If
353 * anv_block_pool_alloc_back has ever been called, then this pointer
354 * will point to the "center" position of the buffer and all offsets
355 * (negative or positive) given out by the block pool alloc functions
356 * will be valid relative to this pointer.
357 *
358 * In particular, map == bo.map + center_offset
359 */
360 void *map;
361 int fd;
362
363 /**
364 * Array of mmaps and gem handles owned by the block pool, reclaimed when
365 * the block pool is destroyed.
366 */
367 struct anv_vector mmap_cleanups;
368
369 uint32_t block_size;
370
371 union anv_free_list free_list;
372 struct anv_block_state state;
373
374 union anv_free_list back_free_list;
375 struct anv_block_state back_state;
376 };
377
378 /* Block pools are backed by a fixed-size 2GB memfd */
379 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
380
381 /* The center of the block pool is also the middle of the memfd. This may
382 * change in the future if we decide differently for some reason.
383 */
384 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
385
386 static inline uint32_t
387 anv_block_pool_size(struct anv_block_pool *pool)
388 {
389 return pool->state.end + pool->back_state.end;
390 }
391
392 struct anv_state {
393 int32_t offset;
394 uint32_t alloc_size;
395 void *map;
396 };
397
398 struct anv_fixed_size_state_pool {
399 size_t state_size;
400 union anv_free_list free_list;
401 struct anv_block_state block;
402 };
403
404 #define ANV_MIN_STATE_SIZE_LOG2 6
405 #define ANV_MAX_STATE_SIZE_LOG2 17
406
407 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
408
409 struct anv_state_pool {
410 struct anv_block_pool *block_pool;
411 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
412 };
413
414 struct anv_state_stream_block;
415
416 struct anv_state_stream {
417 struct anv_block_pool *block_pool;
418
419 /* The current working block */
420 struct anv_state_stream_block *block;
421
422 /* Offset at which the current block starts */
423 uint32_t start;
424 /* Offset at which to allocate the next state */
425 uint32_t next;
426 /* Offset at which the current block ends */
427 uint32_t end;
428 };
429
430 #define CACHELINE_SIZE 64
431 #define CACHELINE_MASK 63
432
433 static inline void
434 anv_clflush_range(void *start, size_t size)
435 {
436 void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
437 void *end = start + size;
438
439 __builtin_ia32_mfence();
440 while (p < end) {
441 __builtin_ia32_clflush(p);
442 p += CACHELINE_SIZE;
443 }
444 }
445
446 static void inline
447 anv_state_clflush(struct anv_state state)
448 {
449 anv_clflush_range(state.map, state.alloc_size);
450 }
451
452 void anv_block_pool_init(struct anv_block_pool *pool,
453 struct anv_device *device, uint32_t block_size);
454 void anv_block_pool_finish(struct anv_block_pool *pool);
455 int32_t anv_block_pool_alloc(struct anv_block_pool *pool);
456 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool);
457 void anv_block_pool_free(struct anv_block_pool *pool, int32_t offset);
458 void anv_state_pool_init(struct anv_state_pool *pool,
459 struct anv_block_pool *block_pool);
460 void anv_state_pool_finish(struct anv_state_pool *pool);
461 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
462 size_t state_size, size_t alignment);
463 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
464 void anv_state_stream_init(struct anv_state_stream *stream,
465 struct anv_block_pool *block_pool);
466 void anv_state_stream_finish(struct anv_state_stream *stream);
467 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
468 uint32_t size, uint32_t alignment);
469
470 /**
471 * Implements a pool of re-usable BOs. The interface is identical to that
472 * of block_pool except that each block is its own BO.
473 */
474 struct anv_bo_pool {
475 struct anv_device *device;
476
477 void *free_list[16];
478 };
479
480 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
481 void anv_bo_pool_finish(struct anv_bo_pool *pool);
482 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
483 uint32_t size);
484 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
485
486 struct anv_scratch_pool {
487 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
488 struct anv_bo bos[16][MESA_SHADER_STAGES];
489 };
490
491 void anv_scratch_pool_init(struct anv_device *device,
492 struct anv_scratch_pool *pool);
493 void anv_scratch_pool_finish(struct anv_device *device,
494 struct anv_scratch_pool *pool);
495 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
496 struct anv_scratch_pool *pool,
497 gl_shader_stage stage,
498 unsigned per_thread_scratch);
499
500 void *anv_resolve_entrypoint(uint32_t index);
501
502 extern struct anv_dispatch_table dtable;
503
504 #define ANV_CALL(func) ({ \
505 if (dtable.func == NULL) { \
506 size_t idx = offsetof(struct anv_dispatch_table, func) / sizeof(void *); \
507 dtable.entrypoints[idx] = anv_resolve_entrypoint(idx); \
508 } \
509 dtable.func; \
510 })
511
512 static inline void *
513 anv_alloc(const VkAllocationCallbacks *alloc,
514 size_t size, size_t align,
515 VkSystemAllocationScope scope)
516 {
517 return alloc->pfnAllocation(alloc->pUserData, size, align, scope);
518 }
519
520 static inline void *
521 anv_realloc(const VkAllocationCallbacks *alloc,
522 void *ptr, size_t size, size_t align,
523 VkSystemAllocationScope scope)
524 {
525 return alloc->pfnReallocation(alloc->pUserData, ptr, size, align, scope);
526 }
527
528 static inline void
529 anv_free(const VkAllocationCallbacks *alloc, void *data)
530 {
531 alloc->pfnFree(alloc->pUserData, data);
532 }
533
534 static inline void *
535 anv_alloc2(const VkAllocationCallbacks *parent_alloc,
536 const VkAllocationCallbacks *alloc,
537 size_t size, size_t align,
538 VkSystemAllocationScope scope)
539 {
540 if (alloc)
541 return anv_alloc(alloc, size, align, scope);
542 else
543 return anv_alloc(parent_alloc, size, align, scope);
544 }
545
546 static inline void
547 anv_free2(const VkAllocationCallbacks *parent_alloc,
548 const VkAllocationCallbacks *alloc,
549 void *data)
550 {
551 if (alloc)
552 anv_free(alloc, data);
553 else
554 anv_free(parent_alloc, data);
555 }
556
557 struct anv_wsi_interaface;
558
559 #define VK_ICD_WSI_PLATFORM_MAX 5
560
561 struct anv_physical_device {
562 VK_LOADER_DATA _loader_data;
563
564 struct anv_instance * instance;
565 uint32_t chipset_id;
566 char path[20];
567 const char * name;
568 struct gen_device_info info;
569 uint64_t aperture_size;
570 struct brw_compiler * compiler;
571 struct isl_device isl_dev;
572 int cmd_parser_version;
573
574 uint32_t eu_total;
575 uint32_t subslice_total;
576
577 struct anv_wsi_interface * wsi[VK_ICD_WSI_PLATFORM_MAX];
578 };
579
580 struct anv_instance {
581 VK_LOADER_DATA _loader_data;
582
583 VkAllocationCallbacks alloc;
584
585 uint32_t apiVersion;
586 int physicalDeviceCount;
587 struct anv_physical_device physicalDevice;
588 };
589
590 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
591 void anv_finish_wsi(struct anv_physical_device *physical_device);
592
593 struct anv_queue {
594 VK_LOADER_DATA _loader_data;
595
596 struct anv_device * device;
597
598 struct anv_state_pool * pool;
599 };
600
601 struct anv_pipeline_cache {
602 struct anv_device * device;
603 pthread_mutex_t mutex;
604
605 struct hash_table * cache;
606 };
607
608 struct anv_pipeline_bind_map;
609
610 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
611 struct anv_device *device,
612 bool cache_enabled);
613 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
614
615 struct anv_shader_bin *
616 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
617 const void *key, uint32_t key_size);
618 struct anv_shader_bin *
619 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
620 const void *key_data, uint32_t key_size,
621 const void *kernel_data, uint32_t kernel_size,
622 const void *prog_data, uint32_t prog_data_size,
623 const struct anv_pipeline_bind_map *bind_map);
624
625 struct anv_device {
626 VK_LOADER_DATA _loader_data;
627
628 VkAllocationCallbacks alloc;
629
630 struct anv_instance * instance;
631 uint32_t chipset_id;
632 struct gen_device_info info;
633 struct isl_device isl_dev;
634 int context_id;
635 int fd;
636 bool can_chain_batches;
637 bool robust_buffer_access;
638
639 struct anv_bo_pool batch_bo_pool;
640
641 struct anv_block_pool dynamic_state_block_pool;
642 struct anv_state_pool dynamic_state_pool;
643
644 struct anv_block_pool instruction_block_pool;
645 struct anv_state_pool instruction_state_pool;
646
647 struct anv_block_pool surface_state_block_pool;
648 struct anv_state_pool surface_state_pool;
649
650 struct anv_bo workaround_bo;
651
652 struct anv_pipeline_cache blorp_shader_cache;
653 struct blorp_context blorp;
654
655 struct anv_state border_colors;
656
657 struct anv_queue queue;
658
659 struct anv_scratch_pool scratch_pool;
660
661 uint32_t default_mocs;
662
663 pthread_mutex_t mutex;
664 };
665
666 void anv_device_get_cache_uuid(void *uuid);
667
668 void anv_device_init_blorp(struct anv_device *device);
669 void anv_device_finish_blorp(struct anv_device *device);
670
671 void* anv_gem_mmap(struct anv_device *device,
672 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
673 void anv_gem_munmap(void *p, uint64_t size);
674 uint32_t anv_gem_create(struct anv_device *device, size_t size);
675 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
676 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
677 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
678 int anv_gem_execbuffer(struct anv_device *device,
679 struct drm_i915_gem_execbuffer2 *execbuf);
680 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
681 uint32_t stride, uint32_t tiling);
682 int anv_gem_create_context(struct anv_device *device);
683 int anv_gem_destroy_context(struct anv_device *device, int context);
684 int anv_gem_get_param(int fd, uint32_t param);
685 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
686 int anv_gem_get_aperture(int fd, uint64_t *size);
687 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
688 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
689 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
690 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
691 uint32_t read_domains, uint32_t write_domain);
692
693 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
694
695 struct anv_reloc_list {
696 size_t num_relocs;
697 size_t array_length;
698 struct drm_i915_gem_relocation_entry * relocs;
699 struct anv_bo ** reloc_bos;
700 };
701
702 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
703 const VkAllocationCallbacks *alloc);
704 void anv_reloc_list_finish(struct anv_reloc_list *list,
705 const VkAllocationCallbacks *alloc);
706
707 uint64_t anv_reloc_list_add(struct anv_reloc_list *list,
708 const VkAllocationCallbacks *alloc,
709 uint32_t offset, struct anv_bo *target_bo,
710 uint32_t delta);
711
712 struct anv_batch_bo {
713 /* Link in the anv_cmd_buffer.owned_batch_bos list */
714 struct list_head link;
715
716 struct anv_bo bo;
717
718 /* Bytes actually consumed in this batch BO */
719 size_t length;
720
721 /* Last seen surface state block pool bo offset */
722 uint32_t last_ss_pool_bo_offset;
723
724 struct anv_reloc_list relocs;
725 };
726
727 struct anv_batch {
728 const VkAllocationCallbacks * alloc;
729
730 void * start;
731 void * end;
732 void * next;
733
734 struct anv_reloc_list * relocs;
735
736 /* This callback is called (with the associated user data) in the event
737 * that the batch runs out of space.
738 */
739 VkResult (*extend_cb)(struct anv_batch *, void *);
740 void * user_data;
741 };
742
743 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
744 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
745 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
746 void *location, struct anv_bo *bo, uint32_t offset);
747 VkResult anv_device_submit_simple_batch(struct anv_device *device,
748 struct anv_batch *batch);
749
750 struct anv_address {
751 struct anv_bo *bo;
752 uint32_t offset;
753 };
754
755 static inline uint64_t
756 _anv_combine_address(struct anv_batch *batch, void *location,
757 const struct anv_address address, uint32_t delta)
758 {
759 if (address.bo == NULL) {
760 return address.offset + delta;
761 } else {
762 assert(batch->start <= location && location < batch->end);
763
764 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
765 }
766 }
767
768 #define __gen_address_type struct anv_address
769 #define __gen_user_data struct anv_batch
770 #define __gen_combine_address _anv_combine_address
771
772 /* Wrapper macros needed to work around preprocessor argument issues. In
773 * particular, arguments don't get pre-evaluated if they are concatenated.
774 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
775 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
776 * We can work around this easily enough with these helpers.
777 */
778 #define __anv_cmd_length(cmd) cmd ## _length
779 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
780 #define __anv_cmd_header(cmd) cmd ## _header
781 #define __anv_cmd_pack(cmd) cmd ## _pack
782 #define __anv_reg_num(reg) reg ## _num
783
784 #define anv_pack_struct(dst, struc, ...) do { \
785 struct struc __template = { \
786 __VA_ARGS__ \
787 }; \
788 __anv_cmd_pack(struc)(NULL, dst, &__template); \
789 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
790 } while (0)
791
792 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
793 void *__dst = anv_batch_emit_dwords(batch, n); \
794 struct cmd __template = { \
795 __anv_cmd_header(cmd), \
796 .DWordLength = n - __anv_cmd_length_bias(cmd), \
797 __VA_ARGS__ \
798 }; \
799 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
800 __dst; \
801 })
802
803 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
804 do { \
805 uint32_t *dw; \
806 \
807 static_assert(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1), "mismatch merge"); \
808 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
809 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
810 dw[i] = (dwords0)[i] | (dwords1)[i]; \
811 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
812 } while (0)
813
814 #define anv_batch_emit(batch, cmd, name) \
815 for (struct cmd name = { __anv_cmd_header(cmd) }, \
816 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
817 __builtin_expect(_dst != NULL, 1); \
818 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
819 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
820 _dst = NULL; \
821 }))
822
823 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
824 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
825 struct anv_state __state = \
826 anv_state_pool_alloc((pool), __size, align); \
827 struct cmd __template = { \
828 __VA_ARGS__ \
829 }; \
830 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
831 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
832 if (!(pool)->block_pool->device->info.has_llc) \
833 anv_state_clflush(__state); \
834 __state; \
835 })
836
837 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
838 .GraphicsDataTypeGFDT = 0, \
839 .LLCCacheabilityControlLLCCC = 0, \
840 .L3CacheabilityControlL3CC = 1, \
841 }
842
843 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
844 .LLCeLLCCacheabilityControlLLCCC = 0, \
845 .L3CacheabilityControlL3CC = 1, \
846 }
847
848 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
849 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
850 .TargetCache = L3DefertoPATforLLCeLLCselection, \
851 .AgeforQUADLRU = 0 \
852 }
853
854 /* Skylake: MOCS is now an index into an array of 62 different caching
855 * configurations programmed by the kernel.
856 */
857
858 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
859 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
860 .IndextoMOCSTables = 2 \
861 }
862
863 #define GEN9_MOCS_PTE { \
864 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
865 .IndextoMOCSTables = 1 \
866 }
867
868 struct anv_device_memory {
869 struct anv_bo bo;
870 uint32_t type_index;
871 VkDeviceSize map_size;
872 void * map;
873 };
874
875 /**
876 * Header for Vertex URB Entry (VUE)
877 */
878 struct anv_vue_header {
879 uint32_t Reserved;
880 uint32_t RTAIndex; /* RenderTargetArrayIndex */
881 uint32_t ViewportIndex;
882 float PointWidth;
883 };
884
885 struct anv_descriptor_set_binding_layout {
886 #ifndef NDEBUG
887 /* The type of the descriptors in this binding */
888 VkDescriptorType type;
889 #endif
890
891 /* Number of array elements in this binding */
892 uint16_t array_size;
893
894 /* Index into the flattend descriptor set */
895 uint16_t descriptor_index;
896
897 /* Index into the dynamic state array for a dynamic buffer */
898 int16_t dynamic_offset_index;
899
900 /* Index into the descriptor set buffer views */
901 int16_t buffer_index;
902
903 struct {
904 /* Index into the binding table for the associated surface */
905 int16_t surface_index;
906
907 /* Index into the sampler table for the associated sampler */
908 int16_t sampler_index;
909
910 /* Index into the image table for the associated image */
911 int16_t image_index;
912 } stage[MESA_SHADER_STAGES];
913
914 /* Immutable samplers (or NULL if no immutable samplers) */
915 struct anv_sampler **immutable_samplers;
916 };
917
918 struct anv_descriptor_set_layout {
919 /* Number of bindings in this descriptor set */
920 uint16_t binding_count;
921
922 /* Total size of the descriptor set with room for all array entries */
923 uint16_t size;
924
925 /* Shader stages affected by this descriptor set */
926 uint16_t shader_stages;
927
928 /* Number of buffers in this descriptor set */
929 uint16_t buffer_count;
930
931 /* Number of dynamic offsets used by this descriptor set */
932 uint16_t dynamic_offset_count;
933
934 /* Bindings in this descriptor set */
935 struct anv_descriptor_set_binding_layout binding[0];
936 };
937
938 struct anv_descriptor {
939 VkDescriptorType type;
940
941 union {
942 struct {
943 struct anv_image_view *image_view;
944 struct anv_sampler *sampler;
945 };
946
947 struct anv_buffer_view *buffer_view;
948 };
949 };
950
951 struct anv_descriptor_set {
952 const struct anv_descriptor_set_layout *layout;
953 uint32_t size;
954 uint32_t buffer_count;
955 struct anv_buffer_view *buffer_views;
956 struct anv_descriptor descriptors[0];
957 };
958
959 struct anv_descriptor_pool {
960 uint32_t size;
961 uint32_t next;
962 uint32_t free_list;
963
964 struct anv_state_stream surface_state_stream;
965 void *surface_state_free_list;
966
967 char data[0];
968 };
969
970 VkResult
971 anv_descriptor_set_create(struct anv_device *device,
972 struct anv_descriptor_pool *pool,
973 const struct anv_descriptor_set_layout *layout,
974 struct anv_descriptor_set **out_set);
975
976 void
977 anv_descriptor_set_destroy(struct anv_device *device,
978 struct anv_descriptor_pool *pool,
979 struct anv_descriptor_set *set);
980
981 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
982
983 struct anv_pipeline_binding {
984 /* The descriptor set this surface corresponds to. The special value of
985 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
986 * to a color attachment and not a regular descriptor.
987 */
988 uint8_t set;
989
990 /* Binding in the descriptor set */
991 uint8_t binding;
992
993 /* Index in the binding */
994 uint8_t index;
995 };
996
997 struct anv_pipeline_layout {
998 struct {
999 struct anv_descriptor_set_layout *layout;
1000 uint32_t dynamic_offset_start;
1001 } set[MAX_SETS];
1002
1003 uint32_t num_sets;
1004
1005 struct {
1006 bool has_dynamic_offsets;
1007 } stage[MESA_SHADER_STAGES];
1008
1009 unsigned char sha1[20];
1010 };
1011
1012 struct anv_buffer {
1013 struct anv_device * device;
1014 VkDeviceSize size;
1015
1016 VkBufferUsageFlags usage;
1017
1018 /* Set when bound */
1019 struct anv_bo * bo;
1020 VkDeviceSize offset;
1021 };
1022
1023 enum anv_cmd_dirty_bits {
1024 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1025 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1026 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1027 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1028 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1029 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1030 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1031 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1032 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1033 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1034 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1035 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1036 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1037 };
1038 typedef uint32_t anv_cmd_dirty_mask_t;
1039
1040 enum anv_pipe_bits {
1041 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1042 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1043 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1044 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1045 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1046 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1047 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1048 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1049 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1050 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1051 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1052
1053 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1054 * a flush has happened but not a CS stall. The next time we do any sort
1055 * of invalidation we need to insert a CS stall at that time. Otherwise,
1056 * we would have to CS stall on every flush which could be bad.
1057 */
1058 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1059 };
1060
1061 #define ANV_PIPE_FLUSH_BITS ( \
1062 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1063 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1064 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1065
1066 #define ANV_PIPE_STALL_BITS ( \
1067 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1068 ANV_PIPE_DEPTH_STALL_BIT | \
1069 ANV_PIPE_CS_STALL_BIT)
1070
1071 #define ANV_PIPE_INVALIDATE_BITS ( \
1072 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1073 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1074 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1075 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1076 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1077 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1078
1079 struct anv_vertex_binding {
1080 struct anv_buffer * buffer;
1081 VkDeviceSize offset;
1082 };
1083
1084 struct anv_push_constants {
1085 /* Current allocated size of this push constants data structure.
1086 * Because a decent chunk of it may not be used (images on SKL, for
1087 * instance), we won't actually allocate the entire structure up-front.
1088 */
1089 uint32_t size;
1090
1091 /* Push constant data provided by the client through vkPushConstants */
1092 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1093
1094 /* Our hardware only provides zero-based vertex and instance id so, in
1095 * order to satisfy the vulkan requirements, we may have to push one or
1096 * both of these into the shader.
1097 */
1098 uint32_t base_vertex;
1099 uint32_t base_instance;
1100
1101 /* Offsets and ranges for dynamically bound buffers */
1102 struct {
1103 uint32_t offset;
1104 uint32_t range;
1105 } dynamic[MAX_DYNAMIC_BUFFERS];
1106
1107 /* Image data for image_load_store on pre-SKL */
1108 struct brw_image_param images[MAX_IMAGES];
1109 };
1110
1111 struct anv_dynamic_state {
1112 struct {
1113 uint32_t count;
1114 VkViewport viewports[MAX_VIEWPORTS];
1115 } viewport;
1116
1117 struct {
1118 uint32_t count;
1119 VkRect2D scissors[MAX_SCISSORS];
1120 } scissor;
1121
1122 float line_width;
1123
1124 struct {
1125 float bias;
1126 float clamp;
1127 float slope;
1128 } depth_bias;
1129
1130 float blend_constants[4];
1131
1132 struct {
1133 float min;
1134 float max;
1135 } depth_bounds;
1136
1137 struct {
1138 uint32_t front;
1139 uint32_t back;
1140 } stencil_compare_mask;
1141
1142 struct {
1143 uint32_t front;
1144 uint32_t back;
1145 } stencil_write_mask;
1146
1147 struct {
1148 uint32_t front;
1149 uint32_t back;
1150 } stencil_reference;
1151 };
1152
1153 extern const struct anv_dynamic_state default_dynamic_state;
1154
1155 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1156 const struct anv_dynamic_state *src,
1157 uint32_t copy_mask);
1158
1159 /**
1160 * Attachment state when recording a renderpass instance.
1161 *
1162 * The clear value is valid only if there exists a pending clear.
1163 */
1164 struct anv_attachment_state {
1165 VkImageAspectFlags pending_clear_aspects;
1166 VkClearValue clear_value;
1167 };
1168
1169 /** State required while building cmd buffer */
1170 struct anv_cmd_state {
1171 /* PIPELINE_SELECT.PipelineSelection */
1172 uint32_t current_pipeline;
1173 const struct gen_l3_config * current_l3_config;
1174 uint32_t vb_dirty;
1175 anv_cmd_dirty_mask_t dirty;
1176 anv_cmd_dirty_mask_t compute_dirty;
1177 enum anv_pipe_bits pending_pipe_bits;
1178 uint32_t num_workgroups_offset;
1179 struct anv_bo *num_workgroups_bo;
1180 VkShaderStageFlags descriptors_dirty;
1181 VkShaderStageFlags push_constants_dirty;
1182 uint32_t scratch_size;
1183 struct anv_pipeline * pipeline;
1184 struct anv_pipeline * compute_pipeline;
1185 struct anv_framebuffer * framebuffer;
1186 struct anv_render_pass * pass;
1187 struct anv_subpass * subpass;
1188 VkRect2D render_area;
1189 uint32_t restart_index;
1190 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1191 struct anv_descriptor_set * descriptors[MAX_SETS];
1192 VkShaderStageFlags push_constant_stages;
1193 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1194 struct anv_state binding_tables[MESA_SHADER_STAGES];
1195 struct anv_state samplers[MESA_SHADER_STAGES];
1196 struct anv_dynamic_state dynamic;
1197 bool need_query_wa;
1198
1199 /**
1200 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1201 * valid only when recording a render pass instance.
1202 */
1203 struct anv_attachment_state * attachments;
1204
1205 struct {
1206 struct anv_buffer * index_buffer;
1207 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1208 uint32_t index_offset;
1209 } gen7;
1210 };
1211
1212 struct anv_cmd_pool {
1213 VkAllocationCallbacks alloc;
1214 struct list_head cmd_buffers;
1215 };
1216
1217 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1218
1219 enum anv_cmd_buffer_exec_mode {
1220 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1221 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1222 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1223 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1224 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1225 };
1226
1227 struct anv_cmd_buffer {
1228 VK_LOADER_DATA _loader_data;
1229
1230 struct anv_device * device;
1231
1232 struct anv_cmd_pool * pool;
1233 struct list_head pool_link;
1234
1235 struct anv_batch batch;
1236
1237 /* Fields required for the actual chain of anv_batch_bo's.
1238 *
1239 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1240 */
1241 struct list_head batch_bos;
1242 enum anv_cmd_buffer_exec_mode exec_mode;
1243
1244 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1245 * referenced by this command buffer
1246 *
1247 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1248 */
1249 struct anv_vector seen_bbos;
1250
1251 /* A vector of int32_t's for every block of binding tables.
1252 *
1253 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1254 */
1255 struct anv_vector bt_blocks;
1256 uint32_t bt_next;
1257 struct anv_reloc_list surface_relocs;
1258
1259 /* Information needed for execbuf
1260 *
1261 * These fields are generated by anv_cmd_buffer_prepare_execbuf().
1262 */
1263 struct {
1264 struct drm_i915_gem_execbuffer2 execbuf;
1265
1266 struct drm_i915_gem_exec_object2 * objects;
1267 uint32_t bo_count;
1268 struct anv_bo ** bos;
1269
1270 /* Allocated length of the 'objects' and 'bos' arrays */
1271 uint32_t array_length;
1272
1273 bool need_reloc;
1274 } execbuf2;
1275
1276 /* Serial for tracking buffer completion */
1277 uint32_t serial;
1278
1279 /* Stream objects for storing temporary data */
1280 struct anv_state_stream surface_state_stream;
1281 struct anv_state_stream dynamic_state_stream;
1282
1283 VkCommandBufferUsageFlags usage_flags;
1284 VkCommandBufferLevel level;
1285
1286 struct anv_cmd_state state;
1287 };
1288
1289 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1290 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1291 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1292 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1293 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1294 struct anv_cmd_buffer *secondary);
1295 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1296
1297 VkResult anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
1298 unsigned stage, struct anv_state *bt_state);
1299 VkResult anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
1300 unsigned stage, struct anv_state *state);
1301 uint32_t anv_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer);
1302
1303 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1304 const void *data, uint32_t size, uint32_t alignment);
1305 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1306 uint32_t *a, uint32_t *b,
1307 uint32_t dwords, uint32_t alignment);
1308
1309 struct anv_address
1310 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1311 struct anv_state
1312 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1313 uint32_t entries, uint32_t *state_offset);
1314 struct anv_state
1315 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1316 struct anv_state
1317 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1318 uint32_t size, uint32_t alignment);
1319
1320 VkResult
1321 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1322
1323 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1324 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1325 bool depth_clamp_enable);
1326 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1327
1328 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1329
1330 void anv_cmd_state_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1331 const VkRenderPassBeginInfo *info);
1332
1333 struct anv_state
1334 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1335 gl_shader_stage stage);
1336 struct anv_state
1337 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1338
1339 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1340 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1341
1342 const struct anv_image_view *
1343 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1344
1345 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1346
1347 struct anv_fence {
1348 struct anv_bo bo;
1349 struct drm_i915_gem_execbuffer2 execbuf;
1350 struct drm_i915_gem_exec_object2 exec2_objects[1];
1351 bool ready;
1352 };
1353
1354 struct anv_event {
1355 uint64_t semaphore;
1356 struct anv_state state;
1357 };
1358
1359 struct nir_shader;
1360
1361 struct anv_shader_module {
1362 struct nir_shader * nir;
1363
1364 unsigned char sha1[20];
1365 uint32_t size;
1366 char data[0];
1367 };
1368
1369 void anv_hash_shader(unsigned char *hash, const void *key, size_t key_size,
1370 struct anv_shader_module *module,
1371 const char *entrypoint,
1372 const struct anv_pipeline_layout *pipeline_layout,
1373 const VkSpecializationInfo *spec_info);
1374
1375 static inline gl_shader_stage
1376 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1377 {
1378 assert(__builtin_popcount(vk_stage) == 1);
1379 return ffs(vk_stage) - 1;
1380 }
1381
1382 static inline VkShaderStageFlagBits
1383 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1384 {
1385 return (1 << mesa_stage);
1386 }
1387
1388 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1389
1390 #define anv_foreach_stage(stage, stage_bits) \
1391 for (gl_shader_stage stage, \
1392 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1393 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1394 __tmp &= ~(1 << (stage)))
1395
1396 struct anv_pipeline_bind_map {
1397 uint32_t surface_count;
1398 uint32_t sampler_count;
1399 uint32_t image_count;
1400
1401 struct anv_pipeline_binding * surface_to_descriptor;
1402 struct anv_pipeline_binding * sampler_to_descriptor;
1403 };
1404
1405 struct anv_shader_bin {
1406 uint32_t ref_cnt;
1407
1408 struct anv_state kernel;
1409 uint32_t kernel_size;
1410
1411 struct anv_pipeline_bind_map bind_map;
1412
1413 uint32_t prog_data_size;
1414
1415 /* Prog data follows, then the key, both aligned to 8-bytes */
1416 };
1417
1418 struct anv_shader_bin *
1419 anv_shader_bin_create(struct anv_device *device,
1420 const void *key, uint32_t key_size,
1421 const void *kernel, uint32_t kernel_size,
1422 const void *prog_data, uint32_t prog_data_size,
1423 const struct anv_pipeline_bind_map *bind_map);
1424
1425 void
1426 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
1427
1428 static inline void
1429 anv_shader_bin_ref(struct anv_shader_bin *shader)
1430 {
1431 assert(shader->ref_cnt >= 1);
1432 __sync_fetch_and_add(&shader->ref_cnt, 1);
1433 }
1434
1435 static inline void
1436 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
1437 {
1438 assert(shader->ref_cnt >= 1);
1439 if (__sync_fetch_and_add(&shader->ref_cnt, -1) == 1)
1440 anv_shader_bin_destroy(device, shader);
1441 }
1442
1443 static inline const struct brw_stage_prog_data *
1444 anv_shader_bin_get_prog_data(const struct anv_shader_bin *shader)
1445 {
1446 const void *data = shader;
1447 data += align_u32(sizeof(struct anv_shader_bin), 8);
1448 return data;
1449 }
1450
1451 struct anv_pipeline {
1452 struct anv_device * device;
1453 struct anv_batch batch;
1454 uint32_t batch_data[512];
1455 struct anv_reloc_list batch_relocs;
1456 uint32_t dynamic_state_mask;
1457 struct anv_dynamic_state dynamic_state;
1458
1459 struct anv_pipeline_layout * layout;
1460
1461 bool use_repclear;
1462 bool needs_data_cache;
1463
1464 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
1465
1466 struct {
1467 const struct gen_l3_config * l3_config;
1468 uint32_t total_size;
1469 } urb;
1470
1471 VkShaderStageFlags active_stages;
1472 struct anv_state blend_state;
1473 uint32_t vs_simd8;
1474 uint32_t vs_vec4;
1475 uint32_t ps_ksp0;
1476 uint32_t gs_kernel;
1477 uint32_t cs_simd;
1478
1479 uint32_t vb_used;
1480 uint32_t binding_stride[MAX_VBS];
1481 bool instancing_enable[MAX_VBS];
1482 bool primitive_restart;
1483 uint32_t topology;
1484
1485 uint32_t cs_right_mask;
1486
1487 bool depth_clamp_enable;
1488
1489 struct {
1490 uint32_t sf[7];
1491 uint32_t depth_stencil_state[3];
1492 } gen7;
1493
1494 struct {
1495 uint32_t sf[4];
1496 uint32_t raster[5];
1497 uint32_t wm_depth_stencil[3];
1498 } gen8;
1499
1500 struct {
1501 uint32_t wm_depth_stencil[4];
1502 } gen9;
1503 };
1504
1505 static inline bool
1506 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
1507 gl_shader_stage stage)
1508 {
1509 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
1510 }
1511
1512 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1513 static inline const struct brw_##prefix##_prog_data * \
1514 get_##prefix##_prog_data(struct anv_pipeline *pipeline) \
1515 { \
1516 if (anv_pipeline_has_stage(pipeline, stage)) { \
1517 return (const struct brw_##prefix##_prog_data *) \
1518 anv_shader_bin_get_prog_data(pipeline->shaders[stage]); \
1519 } else { \
1520 return NULL; \
1521 } \
1522 }
1523
1524 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
1525 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
1526 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
1527 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
1528
1529 struct anv_graphics_pipeline_create_info {
1530 /**
1531 * If non-negative, overrides the color attachment count of the pipeline's
1532 * subpass.
1533 */
1534 int8_t color_attachment_count;
1535
1536 bool use_repclear;
1537 bool disable_vs;
1538 bool use_rectlist;
1539 };
1540
1541 VkResult
1542 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
1543 struct anv_pipeline_cache *cache,
1544 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1545 const struct anv_graphics_pipeline_create_info *extra,
1546 const VkAllocationCallbacks *alloc);
1547
1548 VkResult
1549 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1550 struct anv_pipeline_cache *cache,
1551 const VkComputePipelineCreateInfo *info,
1552 struct anv_shader_module *module,
1553 const char *entrypoint,
1554 const VkSpecializationInfo *spec_info);
1555
1556 VkResult
1557 anv_graphics_pipeline_create(VkDevice device,
1558 VkPipelineCache cache,
1559 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1560 const struct anv_graphics_pipeline_create_info *extra,
1561 const VkAllocationCallbacks *alloc,
1562 VkPipeline *pPipeline);
1563
1564 struct anv_format {
1565 enum isl_format isl_format:16;
1566 struct isl_swizzle swizzle;
1567 };
1568
1569 struct anv_format
1570 anv_get_format(const struct gen_device_info *devinfo, VkFormat format,
1571 VkImageAspectFlags aspect, VkImageTiling tiling);
1572
1573 static inline enum isl_format
1574 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
1575 VkImageAspectFlags aspect, VkImageTiling tiling)
1576 {
1577 return anv_get_format(devinfo, vk_format, aspect, tiling).isl_format;
1578 }
1579
1580 void
1581 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
1582
1583 /**
1584 * Subsurface of an anv_image.
1585 */
1586 struct anv_surface {
1587 /** Valid only if isl_surf::size > 0. */
1588 struct isl_surf isl;
1589
1590 /**
1591 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1592 */
1593 uint32_t offset;
1594 };
1595
1596 struct anv_image {
1597 VkImageType type;
1598 /* The original VkFormat provided by the client. This may not match any
1599 * of the actual surface formats.
1600 */
1601 VkFormat vk_format;
1602 VkImageAspectFlags aspects;
1603 VkExtent3D extent;
1604 uint32_t levels;
1605 uint32_t array_size;
1606 uint32_t samples; /**< VkImageCreateInfo::samples */
1607 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1608 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1609
1610 VkDeviceSize size;
1611 uint32_t alignment;
1612
1613 /* Set when bound */
1614 struct anv_bo *bo;
1615 VkDeviceSize offset;
1616
1617 /**
1618 * Image subsurfaces
1619 *
1620 * For each foo, anv_image::foo_surface is valid if and only if
1621 * anv_image::aspects has a foo aspect.
1622 *
1623 * The hardware requires that the depth buffer and stencil buffer be
1624 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1625 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1626 * allocate the depth and stencil buffers as separate surfaces in the same
1627 * bo.
1628 */
1629 union {
1630 struct anv_surface color_surface;
1631
1632 struct {
1633 struct anv_surface depth_surface;
1634 struct anv_surface hiz_surface;
1635 struct anv_surface stencil_surface;
1636 };
1637 };
1638 };
1639
1640 static inline uint32_t
1641 anv_get_layerCount(const struct anv_image *image,
1642 const VkImageSubresourceRange *range)
1643 {
1644 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1645 image->array_size - range->baseArrayLayer : range->layerCount;
1646 }
1647
1648 static inline uint32_t
1649 anv_get_levelCount(const struct anv_image *image,
1650 const VkImageSubresourceRange *range)
1651 {
1652 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1653 image->levels - range->baseMipLevel : range->levelCount;
1654 }
1655
1656
1657 struct anv_image_view {
1658 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
1659 struct anv_bo *bo;
1660 uint32_t offset; /**< Offset into bo. */
1661
1662 struct isl_view isl;
1663
1664 VkImageAspectFlags aspect_mask;
1665 VkFormat vk_format;
1666 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1667
1668 /** RENDER_SURFACE_STATE when using image as a color render target. */
1669 struct anv_state color_rt_surface_state;
1670
1671 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1672 struct anv_state sampler_surface_state;
1673
1674 /** RENDER_SURFACE_STATE when using image as a storage image. */
1675 struct anv_state storage_surface_state;
1676
1677 struct brw_image_param storage_image_param;
1678 };
1679
1680 struct anv_image_create_info {
1681 const VkImageCreateInfo *vk_info;
1682
1683 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1684 isl_tiling_flags_t isl_tiling_flags;
1685
1686 uint32_t stride;
1687 };
1688
1689 VkResult anv_image_create(VkDevice _device,
1690 const struct anv_image_create_info *info,
1691 const VkAllocationCallbacks* alloc,
1692 VkImage *pImage);
1693
1694 const struct anv_surface *
1695 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
1696 VkImageAspectFlags aspect_mask);
1697
1698 static inline bool
1699 anv_image_has_hiz(const struct anv_image *image)
1700 {
1701 /* We must check the aspect because anv_image::hiz_surface belongs to
1702 * a union.
1703 */
1704 return (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1705 image->hiz_surface.isl.size > 0;
1706 }
1707
1708 void anv_image_view_init(struct anv_image_view *view,
1709 struct anv_device *device,
1710 const VkImageViewCreateInfo* pCreateInfo,
1711 struct anv_cmd_buffer *cmd_buffer,
1712 VkImageUsageFlags usage_mask);
1713
1714 struct anv_buffer_view {
1715 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1716 struct anv_bo *bo;
1717 uint32_t offset; /**< Offset into bo. */
1718 uint64_t range; /**< VkBufferViewCreateInfo::range */
1719
1720 struct anv_state surface_state;
1721 struct anv_state storage_surface_state;
1722
1723 struct brw_image_param storage_image_param;
1724 };
1725
1726 void anv_buffer_view_init(struct anv_buffer_view *view,
1727 struct anv_device *device,
1728 const VkBufferViewCreateInfo* pCreateInfo,
1729 struct anv_cmd_buffer *cmd_buffer);
1730
1731 enum isl_format
1732 anv_isl_format_for_descriptor_type(VkDescriptorType type);
1733
1734 static inline struct VkExtent3D
1735 anv_sanitize_image_extent(const VkImageType imageType,
1736 const struct VkExtent3D imageExtent)
1737 {
1738 switch (imageType) {
1739 case VK_IMAGE_TYPE_1D:
1740 return (VkExtent3D) { imageExtent.width, 1, 1 };
1741 case VK_IMAGE_TYPE_2D:
1742 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1743 case VK_IMAGE_TYPE_3D:
1744 return imageExtent;
1745 default:
1746 unreachable("invalid image type");
1747 }
1748 }
1749
1750 static inline struct VkOffset3D
1751 anv_sanitize_image_offset(const VkImageType imageType,
1752 const struct VkOffset3D imageOffset)
1753 {
1754 switch (imageType) {
1755 case VK_IMAGE_TYPE_1D:
1756 return (VkOffset3D) { imageOffset.x, 0, 0 };
1757 case VK_IMAGE_TYPE_2D:
1758 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1759 case VK_IMAGE_TYPE_3D:
1760 return imageOffset;
1761 default:
1762 unreachable("invalid image type");
1763 }
1764 }
1765
1766
1767 void anv_fill_buffer_surface_state(struct anv_device *device,
1768 struct anv_state state,
1769 enum isl_format format,
1770 uint32_t offset, uint32_t range,
1771 uint32_t stride);
1772
1773 void anv_image_view_fill_image_param(struct anv_device *device,
1774 struct anv_image_view *view,
1775 struct brw_image_param *param);
1776 void anv_buffer_view_fill_image_param(struct anv_device *device,
1777 struct anv_buffer_view *view,
1778 struct brw_image_param *param);
1779
1780 struct anv_sampler {
1781 uint32_t state[4];
1782 };
1783
1784 struct anv_framebuffer {
1785 uint32_t width;
1786 uint32_t height;
1787 uint32_t layers;
1788
1789 uint32_t attachment_count;
1790 struct anv_image_view * attachments[0];
1791 };
1792
1793 struct anv_subpass {
1794 uint32_t input_count;
1795 uint32_t * input_attachments;
1796 uint32_t color_count;
1797 uint32_t * color_attachments;
1798 uint32_t * resolve_attachments;
1799 uint32_t depth_stencil_attachment;
1800
1801 /** Subpass has at least one resolve attachment */
1802 bool has_resolve;
1803 };
1804
1805 struct anv_render_pass_attachment {
1806 VkFormat format;
1807 uint32_t samples;
1808 VkAttachmentLoadOp load_op;
1809 VkAttachmentStoreOp store_op;
1810 VkAttachmentLoadOp stencil_load_op;
1811 };
1812
1813 struct anv_render_pass {
1814 uint32_t attachment_count;
1815 uint32_t subpass_count;
1816 uint32_t * subpass_attachments;
1817 struct anv_render_pass_attachment * attachments;
1818 struct anv_subpass subpasses[0];
1819 };
1820
1821 struct anv_query_pool_slot {
1822 uint64_t begin;
1823 uint64_t end;
1824 uint64_t available;
1825 };
1826
1827 struct anv_query_pool {
1828 VkQueryType type;
1829 uint32_t slots;
1830 struct anv_bo bo;
1831 };
1832
1833 void *anv_lookup_entrypoint(const char *name);
1834
1835 void anv_dump_image_to_ppm(struct anv_device *device,
1836 struct anv_image *image, unsigned miplevel,
1837 unsigned array_layer, VkImageAspectFlagBits aspect,
1838 const char *filename);
1839
1840 enum anv_dump_action {
1841 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
1842 };
1843
1844 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
1845 void anv_dump_finish(void);
1846
1847 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
1848 struct anv_framebuffer *fb);
1849
1850 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1851 \
1852 static inline struct __anv_type * \
1853 __anv_type ## _from_handle(__VkType _handle) \
1854 { \
1855 return (struct __anv_type *) _handle; \
1856 } \
1857 \
1858 static inline __VkType \
1859 __anv_type ## _to_handle(struct __anv_type *_obj) \
1860 { \
1861 return (__VkType) _obj; \
1862 }
1863
1864 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1865 \
1866 static inline struct __anv_type * \
1867 __anv_type ## _from_handle(__VkType _handle) \
1868 { \
1869 return (struct __anv_type *)(uintptr_t) _handle; \
1870 } \
1871 \
1872 static inline __VkType \
1873 __anv_type ## _to_handle(struct __anv_type *_obj) \
1874 { \
1875 return (__VkType)(uintptr_t) _obj; \
1876 }
1877
1878 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1879 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1880
1881 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
1882 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
1883 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
1884 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
1885 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
1886
1887 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
1888 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
1889 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
1890 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
1891 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
1892 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
1893 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
1894 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
1895 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
1896 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
1897 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
1898 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
1899 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
1900 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
1901 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
1902 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
1903 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
1904 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
1905 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
1906
1907 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1908 \
1909 static inline const __VkType * \
1910 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1911 { \
1912 return (const __VkType *) __anv_obj; \
1913 }
1914
1915 #define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1916 const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name)
1917
1918 ANV_DEFINE_STRUCT_CASTS(anv_common, VkMemoryBarrier)
1919 ANV_DEFINE_STRUCT_CASTS(anv_common, VkBufferMemoryBarrier)
1920 ANV_DEFINE_STRUCT_CASTS(anv_common, VkImageMemoryBarrier)
1921
1922 /* Gen-specific function declarations */
1923 #ifdef genX
1924 # include "anv_genX.h"
1925 #else
1926 # define genX(x) gen7_##x
1927 # include "anv_genX.h"
1928 # undef genX
1929 # define genX(x) gen75_##x
1930 # include "anv_genX.h"
1931 # undef genX
1932 # define genX(x) gen8_##x
1933 # include "anv_genX.h"
1934 # undef genX
1935 # define genX(x) gen9_##x
1936 # include "anv_genX.h"
1937 # undef genX
1938 #endif
1939
1940 #ifdef __cplusplus
1941 }
1942 #endif
1943
1944 #endif /* ANV_PRIVATE_H */