2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
51 /* Pre-declarations needed for WSI entrypoints */
54 typedef struct xcb_connection_t xcb_connection_t
;
55 typedef uint32_t xcb_visualid_t
;
56 typedef uint32_t xcb_window_t
;
60 #include <vulkan/vulkan.h>
61 #include <vulkan/vulkan_intel.h>
62 #include <vulkan/vk_icd.h>
64 #include "anv_entrypoints.h"
65 #include "brw_context.h"
75 #define MAX_VIEWPORTS 16
76 #define MAX_SCISSORS 16
77 #define MAX_PUSH_CONSTANTS_SIZE 128
78 #define MAX_DYNAMIC_BUFFERS 16
80 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
82 #define anv_noreturn __attribute__((__noreturn__))
83 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
85 static inline uint32_t
86 align_down_npot_u32(uint32_t v
, uint32_t a
)
91 static inline uint32_t
92 align_u32(uint32_t v
, uint32_t a
)
94 assert(a
!= 0 && a
== (a
& -a
));
95 return (v
+ a
- 1) & ~(a
- 1);
98 static inline uint64_t
99 align_u64(uint64_t v
, uint64_t a
)
101 assert(a
!= 0 && a
== (a
& -a
));
102 return (v
+ a
- 1) & ~(a
- 1);
105 static inline int32_t
106 align_i32(int32_t v
, int32_t a
)
108 assert(a
!= 0 && a
== (a
& -a
));
109 return (v
+ a
- 1) & ~(a
- 1);
112 /** Alignment must be a power of 2. */
114 anv_is_aligned(uintmax_t n
, uintmax_t a
)
116 assert(a
== (a
& -a
));
117 return (n
& (a
- 1)) == 0;
120 static inline uint32_t
121 anv_minify(uint32_t n
, uint32_t levels
)
123 if (unlikely(n
== 0))
126 return MAX2(n
>> levels
, 1);
130 anv_clamp_f(float f
, float min
, float max
)
143 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
145 if (*inout_mask
& clear_mask
) {
146 *inout_mask
&= ~clear_mask
;
153 #define for_each_bit(b, dword) \
154 for (uint32_t __dword = (dword); \
155 (b) = __builtin_ffs(__dword) - 1, __dword; \
156 __dword &= ~(1 << (b)))
158 #define typed_memcpy(dest, src, count) ({ \
159 static_assert(sizeof(*src) == sizeof(*dest), ""); \
160 memcpy((dest), (src), (count) * sizeof(*(src))); \
163 #define zero(x) (memset(&(x), 0, sizeof(x)))
165 /* Define no kernel as 1, since that's an illegal offset for a kernel */
169 VkStructureType sType
;
173 /* Whenever we generate an error, pass it through this function. Useful for
174 * debugging, where we can break on it. Only call at error site, not when
175 * propagating errors. Might be useful to plug in a stack trace here.
178 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
181 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
182 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
184 #define vk_error(error) error
185 #define vk_errorf(error, format, ...) error
188 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
189 anv_printflike(3, 4);
190 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
191 void anv_loge_v(const char *format
, va_list va
);
194 * Print a FINISHME message, including its source location.
196 #define anv_finishme(format, ...) \
197 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
199 /* A non-fatal assert. Useful for debugging. */
201 #define anv_assert(x) ({ \
202 if (unlikely(!(x))) \
203 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
206 #define anv_assert(x)
210 * If a block of code is annotated with anv_validate, then the block runs only
214 #define anv_validate if (1)
216 #define anv_validate if (0)
219 void anv_abortf(const char *format
, ...) anv_noreturn
anv_printflike(1, 2);
220 void anv_abortfv(const char *format
, va_list va
) anv_noreturn
;
222 #define stub_return(v) \
224 anv_finishme("stub %s", __func__); \
230 anv_finishme("stub %s", __func__); \
235 * A dynamically growable, circular buffer. Elements are added at head and
236 * removed from tail. head and tail are free-running uint32_t indices and we
237 * only compute the modulo with size when accessing the array. This way,
238 * number of bytes in the queue is always head - tail, even in case of
245 /* Index into the current validation list. This is used by the
246 * validation list building alrogithm to track which buffers are already
247 * in the validation list so that we can ensure uniqueness.
251 /* Last known offset. This value is provided by the kernel when we
252 * execbuf and is used as the presumed offset for the next bunch of
260 /* We need to set the WRITE flag on winsys bos so GEM will know we're
261 * writing to them and synchronize uses on other rings (eg if the display
262 * server uses the blitter ring).
267 /* Represents a lock-free linked list of "free" things. This is used by
268 * both the block pool and the state pools. Unfortunately, in order to
269 * solve the ABA problem, we can't use a single uint32_t head.
271 union anv_free_list
{
275 /* A simple count that is incremented every time the head changes. */
281 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
283 struct anv_block_state
{
293 struct anv_block_pool
{
294 struct anv_device
*device
;
298 /* The offset from the start of the bo to the "center" of the block
299 * pool. Pointers to allocated blocks are given by
300 * bo.map + center_bo_offset + offsets.
302 uint32_t center_bo_offset
;
304 /* Current memory map of the block pool. This pointer may or may not
305 * point to the actual beginning of the block pool memory. If
306 * anv_block_pool_alloc_back has ever been called, then this pointer
307 * will point to the "center" position of the buffer and all offsets
308 * (negative or positive) given out by the block pool alloc functions
309 * will be valid relative to this pointer.
311 * In particular, map == bo.map + center_offset
317 * Array of mmaps and gem handles owned by the block pool, reclaimed when
318 * the block pool is destroyed.
320 struct u_vector mmap_cleanups
;
324 union anv_free_list free_list
;
325 struct anv_block_state state
;
327 union anv_free_list back_free_list
;
328 struct anv_block_state back_state
;
331 /* Block pools are backed by a fixed-size 2GB memfd */
332 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
334 /* The center of the block pool is also the middle of the memfd. This may
335 * change in the future if we decide differently for some reason.
337 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
339 static inline uint32_t
340 anv_block_pool_size(struct anv_block_pool
*pool
)
342 return pool
->state
.end
+ pool
->back_state
.end
;
351 struct anv_fixed_size_state_pool
{
353 union anv_free_list free_list
;
354 struct anv_block_state block
;
357 #define ANV_MIN_STATE_SIZE_LOG2 6
358 #define ANV_MAX_STATE_SIZE_LOG2 17
360 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
362 struct anv_state_pool
{
363 struct anv_block_pool
*block_pool
;
364 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
367 struct anv_state_stream_block
;
369 struct anv_state_stream
{
370 struct anv_block_pool
*block_pool
;
372 /* The current working block */
373 struct anv_state_stream_block
*block
;
375 /* Offset at which the current block starts */
377 /* Offset at which to allocate the next state */
379 /* Offset at which the current block ends */
383 #define CACHELINE_SIZE 64
384 #define CACHELINE_MASK 63
387 anv_clflush_range(void *start
, size_t size
)
389 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
390 void *end
= start
+ size
;
392 __builtin_ia32_mfence();
394 __builtin_ia32_clflush(p
);
400 anv_state_clflush(struct anv_state state
)
402 anv_clflush_range(state
.map
, state
.alloc_size
);
405 void anv_block_pool_init(struct anv_block_pool
*pool
,
406 struct anv_device
*device
, uint32_t block_size
);
407 void anv_block_pool_finish(struct anv_block_pool
*pool
);
408 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
);
409 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
);
410 void anv_block_pool_free(struct anv_block_pool
*pool
, int32_t offset
);
411 void anv_state_pool_init(struct anv_state_pool
*pool
,
412 struct anv_block_pool
*block_pool
);
413 void anv_state_pool_finish(struct anv_state_pool
*pool
);
414 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
415 size_t state_size
, size_t alignment
);
416 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
417 void anv_state_stream_init(struct anv_state_stream
*stream
,
418 struct anv_block_pool
*block_pool
);
419 void anv_state_stream_finish(struct anv_state_stream
*stream
);
420 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
421 uint32_t size
, uint32_t alignment
);
424 * Implements a pool of re-usable BOs. The interface is identical to that
425 * of block_pool except that each block is its own BO.
428 struct anv_device
*device
;
433 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
434 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
435 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
437 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
439 struct anv_scratch_pool
{
440 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
441 struct anv_bo bos
[16][MESA_SHADER_STAGES
];
444 void anv_scratch_pool_init(struct anv_device
*device
,
445 struct anv_scratch_pool
*pool
);
446 void anv_scratch_pool_finish(struct anv_device
*device
,
447 struct anv_scratch_pool
*pool
);
448 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
449 struct anv_scratch_pool
*pool
,
450 gl_shader_stage stage
,
451 unsigned per_thread_scratch
);
453 extern struct anv_dispatch_table dtable
;
456 anv_alloc(const VkAllocationCallbacks
*alloc
,
457 size_t size
, size_t align
,
458 VkSystemAllocationScope scope
)
460 return alloc
->pfnAllocation(alloc
->pUserData
, size
, align
, scope
);
464 anv_realloc(const VkAllocationCallbacks
*alloc
,
465 void *ptr
, size_t size
, size_t align
,
466 VkSystemAllocationScope scope
)
468 return alloc
->pfnReallocation(alloc
->pUserData
, ptr
, size
, align
, scope
);
472 anv_free(const VkAllocationCallbacks
*alloc
, void *data
)
474 alloc
->pfnFree(alloc
->pUserData
, data
);
478 anv_alloc2(const VkAllocationCallbacks
*parent_alloc
,
479 const VkAllocationCallbacks
*alloc
,
480 size_t size
, size_t align
,
481 VkSystemAllocationScope scope
)
484 return anv_alloc(alloc
, size
, align
, scope
);
486 return anv_alloc(parent_alloc
, size
, align
, scope
);
490 anv_free2(const VkAllocationCallbacks
*parent_alloc
,
491 const VkAllocationCallbacks
*alloc
,
495 anv_free(alloc
, data
);
497 anv_free(parent_alloc
, data
);
500 struct anv_wsi_interaface
;
502 #define VK_ICD_WSI_PLATFORM_MAX 5
504 struct anv_physical_device
{
505 VK_LOADER_DATA _loader_data
;
507 struct anv_instance
* instance
;
511 struct gen_device_info info
;
512 uint64_t aperture_size
;
513 struct brw_compiler
* compiler
;
514 struct isl_device isl_dev
;
515 int cmd_parser_version
;
518 uint32_t subslice_total
;
520 struct anv_wsi_interface
* wsi
[VK_ICD_WSI_PLATFORM_MAX
];
523 struct anv_instance
{
524 VK_LOADER_DATA _loader_data
;
526 VkAllocationCallbacks alloc
;
529 int physicalDeviceCount
;
530 struct anv_physical_device physicalDevice
;
533 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
534 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
537 VK_LOADER_DATA _loader_data
;
539 struct anv_device
* device
;
541 struct anv_state_pool
* pool
;
544 struct anv_pipeline_cache
{
545 struct anv_device
* device
;
546 pthread_mutex_t mutex
;
548 struct hash_table
* cache
;
551 struct anv_pipeline_bind_map
;
553 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
554 struct anv_device
*device
,
556 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
558 struct anv_shader_bin
*
559 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
560 const void *key
, uint32_t key_size
);
561 struct anv_shader_bin
*
562 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
563 const void *key_data
, uint32_t key_size
,
564 const void *kernel_data
, uint32_t kernel_size
,
565 const void *prog_data
, uint32_t prog_data_size
,
566 const struct anv_pipeline_bind_map
*bind_map
);
569 VK_LOADER_DATA _loader_data
;
571 VkAllocationCallbacks alloc
;
573 struct anv_instance
* instance
;
575 struct gen_device_info info
;
576 struct isl_device isl_dev
;
579 bool can_chain_batches
;
580 bool robust_buffer_access
;
582 struct anv_bo_pool batch_bo_pool
;
584 struct anv_block_pool dynamic_state_block_pool
;
585 struct anv_state_pool dynamic_state_pool
;
587 struct anv_block_pool instruction_block_pool
;
588 struct anv_state_pool instruction_state_pool
;
590 struct anv_block_pool surface_state_block_pool
;
591 struct anv_state_pool surface_state_pool
;
593 struct anv_bo workaround_bo
;
595 struct anv_pipeline_cache blorp_shader_cache
;
596 struct blorp_context blorp
;
598 struct anv_state border_colors
;
600 struct anv_queue queue
;
602 struct anv_scratch_pool scratch_pool
;
604 uint32_t default_mocs
;
606 pthread_mutex_t mutex
;
609 void anv_device_get_cache_uuid(void *uuid
);
611 void anv_device_init_blorp(struct anv_device
*device
);
612 void anv_device_finish_blorp(struct anv_device
*device
);
614 void* anv_gem_mmap(struct anv_device
*device
,
615 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
616 void anv_gem_munmap(void *p
, uint64_t size
);
617 uint32_t anv_gem_create(struct anv_device
*device
, size_t size
);
618 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
619 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
620 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
621 int anv_gem_execbuffer(struct anv_device
*device
,
622 struct drm_i915_gem_execbuffer2
*execbuf
);
623 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
624 uint32_t stride
, uint32_t tiling
);
625 int anv_gem_create_context(struct anv_device
*device
);
626 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
627 int anv_gem_get_param(int fd
, uint32_t param
);
628 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
629 int anv_gem_get_aperture(int fd
, uint64_t *size
);
630 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
631 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
632 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
633 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
634 uint32_t read_domains
, uint32_t write_domain
);
636 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
638 struct anv_reloc_list
{
641 struct drm_i915_gem_relocation_entry
* relocs
;
642 struct anv_bo
** reloc_bos
;
645 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
646 const VkAllocationCallbacks
*alloc
);
647 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
648 const VkAllocationCallbacks
*alloc
);
650 uint64_t anv_reloc_list_add(struct anv_reloc_list
*list
,
651 const VkAllocationCallbacks
*alloc
,
652 uint32_t offset
, struct anv_bo
*target_bo
,
655 struct anv_batch_bo
{
656 /* Link in the anv_cmd_buffer.owned_batch_bos list */
657 struct list_head link
;
661 /* Bytes actually consumed in this batch BO */
664 /* Last seen surface state block pool bo offset */
665 uint32_t last_ss_pool_bo_offset
;
667 struct anv_reloc_list relocs
;
671 const VkAllocationCallbacks
* alloc
;
677 struct anv_reloc_list
* relocs
;
679 /* This callback is called (with the associated user data) in the event
680 * that the batch runs out of space.
682 VkResult (*extend_cb
)(struct anv_batch
*, void *);
686 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
687 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
688 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
689 void *location
, struct anv_bo
*bo
, uint32_t offset
);
690 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
691 struct anv_batch
*batch
);
698 static inline uint64_t
699 _anv_combine_address(struct anv_batch
*batch
, void *location
,
700 const struct anv_address address
, uint32_t delta
)
702 if (address
.bo
== NULL
) {
703 return address
.offset
+ delta
;
705 assert(batch
->start
<= location
&& location
< batch
->end
);
707 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
711 #define __gen_address_type struct anv_address
712 #define __gen_user_data struct anv_batch
713 #define __gen_combine_address _anv_combine_address
715 /* Wrapper macros needed to work around preprocessor argument issues. In
716 * particular, arguments don't get pre-evaluated if they are concatenated.
717 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
718 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
719 * We can work around this easily enough with these helpers.
721 #define __anv_cmd_length(cmd) cmd ## _length
722 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
723 #define __anv_cmd_header(cmd) cmd ## _header
724 #define __anv_cmd_pack(cmd) cmd ## _pack
725 #define __anv_reg_num(reg) reg ## _num
727 #define anv_pack_struct(dst, struc, ...) do { \
728 struct struc __template = { \
731 __anv_cmd_pack(struc)(NULL, dst, &__template); \
732 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
735 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
736 void *__dst = anv_batch_emit_dwords(batch, n); \
737 struct cmd __template = { \
738 __anv_cmd_header(cmd), \
739 .DWordLength = n - __anv_cmd_length_bias(cmd), \
742 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
746 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
750 static_assert(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1), "mismatch merge"); \
751 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
752 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
753 dw[i] = (dwords0)[i] | (dwords1)[i]; \
754 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
757 #define anv_batch_emit(batch, cmd, name) \
758 for (struct cmd name = { __anv_cmd_header(cmd) }, \
759 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
760 __builtin_expect(_dst != NULL, 1); \
761 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
762 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
766 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
767 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
768 struct anv_state __state = \
769 anv_state_pool_alloc((pool), __size, align); \
770 struct cmd __template = { \
773 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
774 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
775 if (!(pool)->block_pool->device->info.has_llc) \
776 anv_state_clflush(__state); \
780 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
781 .GraphicsDataTypeGFDT = 0, \
782 .LLCCacheabilityControlLLCCC = 0, \
783 .L3CacheabilityControlL3CC = 1, \
786 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
787 .LLCeLLCCacheabilityControlLLCCC = 0, \
788 .L3CacheabilityControlL3CC = 1, \
791 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
792 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
793 .TargetCache = L3DefertoPATforLLCeLLCselection, \
797 /* Skylake: MOCS is now an index into an array of 62 different caching
798 * configurations programmed by the kernel.
801 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
802 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
803 .IndextoMOCSTables = 2 \
806 #define GEN9_MOCS_PTE { \
807 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
808 .IndextoMOCSTables = 1 \
811 struct anv_device_memory
{
814 VkDeviceSize map_size
;
819 * Header for Vertex URB Entry (VUE)
821 struct anv_vue_header
{
823 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
824 uint32_t ViewportIndex
;
828 struct anv_descriptor_set_binding_layout
{
830 /* The type of the descriptors in this binding */
831 VkDescriptorType type
;
834 /* Number of array elements in this binding */
837 /* Index into the flattend descriptor set */
838 uint16_t descriptor_index
;
840 /* Index into the dynamic state array for a dynamic buffer */
841 int16_t dynamic_offset_index
;
843 /* Index into the descriptor set buffer views */
844 int16_t buffer_index
;
847 /* Index into the binding table for the associated surface */
848 int16_t surface_index
;
850 /* Index into the sampler table for the associated sampler */
851 int16_t sampler_index
;
853 /* Index into the image table for the associated image */
855 } stage
[MESA_SHADER_STAGES
];
857 /* Immutable samplers (or NULL if no immutable samplers) */
858 struct anv_sampler
**immutable_samplers
;
861 struct anv_descriptor_set_layout
{
862 /* Number of bindings in this descriptor set */
863 uint16_t binding_count
;
865 /* Total size of the descriptor set with room for all array entries */
868 /* Shader stages affected by this descriptor set */
869 uint16_t shader_stages
;
871 /* Number of buffers in this descriptor set */
872 uint16_t buffer_count
;
874 /* Number of dynamic offsets used by this descriptor set */
875 uint16_t dynamic_offset_count
;
877 /* Bindings in this descriptor set */
878 struct anv_descriptor_set_binding_layout binding
[0];
881 struct anv_descriptor
{
882 VkDescriptorType type
;
886 struct anv_image_view
*image_view
;
887 struct anv_sampler
*sampler
;
890 struct anv_buffer_view
*buffer_view
;
894 struct anv_descriptor_set
{
895 const struct anv_descriptor_set_layout
*layout
;
897 uint32_t buffer_count
;
898 struct anv_buffer_view
*buffer_views
;
899 struct anv_descriptor descriptors
[0];
902 struct anv_descriptor_pool
{
907 struct anv_state_stream surface_state_stream
;
908 void *surface_state_free_list
;
914 anv_descriptor_set_create(struct anv_device
*device
,
915 struct anv_descriptor_pool
*pool
,
916 const struct anv_descriptor_set_layout
*layout
,
917 struct anv_descriptor_set
**out_set
);
920 anv_descriptor_set_destroy(struct anv_device
*device
,
921 struct anv_descriptor_pool
*pool
,
922 struct anv_descriptor_set
*set
);
924 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
926 struct anv_pipeline_binding
{
927 /* The descriptor set this surface corresponds to. The special value of
928 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
929 * to a color attachment and not a regular descriptor.
933 /* Binding in the descriptor set */
936 /* Index in the binding */
940 struct anv_pipeline_layout
{
942 struct anv_descriptor_set_layout
*layout
;
943 uint32_t dynamic_offset_start
;
949 bool has_dynamic_offsets
;
950 } stage
[MESA_SHADER_STAGES
];
952 unsigned char sha1
[20];
956 struct anv_device
* device
;
959 VkBufferUsageFlags usage
;
966 enum anv_cmd_dirty_bits
{
967 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
968 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
969 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
970 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
971 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
972 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
973 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
974 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
975 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
976 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
977 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
978 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
979 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
981 typedef uint32_t anv_cmd_dirty_mask_t
;
984 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
985 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
986 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
987 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
988 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
989 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
990 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
991 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
992 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
993 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
994 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
996 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
997 * a flush has happened but not a CS stall. The next time we do any sort
998 * of invalidation we need to insert a CS stall at that time. Otherwise,
999 * we would have to CS stall on every flush which could be bad.
1001 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1004 #define ANV_PIPE_FLUSH_BITS ( \
1005 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1006 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1007 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1009 #define ANV_PIPE_STALL_BITS ( \
1010 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1011 ANV_PIPE_DEPTH_STALL_BIT | \
1012 ANV_PIPE_CS_STALL_BIT)
1014 #define ANV_PIPE_INVALIDATE_BITS ( \
1015 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1016 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1017 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1018 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1019 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1020 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1022 struct anv_vertex_binding
{
1023 struct anv_buffer
* buffer
;
1024 VkDeviceSize offset
;
1027 struct anv_push_constants
{
1028 /* Current allocated size of this push constants data structure.
1029 * Because a decent chunk of it may not be used (images on SKL, for
1030 * instance), we won't actually allocate the entire structure up-front.
1034 /* Push constant data provided by the client through vkPushConstants */
1035 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1037 /* Our hardware only provides zero-based vertex and instance id so, in
1038 * order to satisfy the vulkan requirements, we may have to push one or
1039 * both of these into the shader.
1041 uint32_t base_vertex
;
1042 uint32_t base_instance
;
1044 /* Offsets and ranges for dynamically bound buffers */
1048 } dynamic
[MAX_DYNAMIC_BUFFERS
];
1050 /* Image data for image_load_store on pre-SKL */
1051 struct brw_image_param images
[MAX_IMAGES
];
1054 struct anv_dynamic_state
{
1057 VkViewport viewports
[MAX_VIEWPORTS
];
1062 VkRect2D scissors
[MAX_SCISSORS
];
1073 float blend_constants
[4];
1083 } stencil_compare_mask
;
1088 } stencil_write_mask
;
1093 } stencil_reference
;
1096 extern const struct anv_dynamic_state default_dynamic_state
;
1098 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1099 const struct anv_dynamic_state
*src
,
1100 uint32_t copy_mask
);
1103 * Attachment state when recording a renderpass instance.
1105 * The clear value is valid only if there exists a pending clear.
1107 struct anv_attachment_state
{
1108 VkImageAspectFlags pending_clear_aspects
;
1109 VkClearValue clear_value
;
1112 /** State required while building cmd buffer */
1113 struct anv_cmd_state
{
1114 /* PIPELINE_SELECT.PipelineSelection */
1115 uint32_t current_pipeline
;
1116 const struct gen_l3_config
* current_l3_config
;
1118 anv_cmd_dirty_mask_t dirty
;
1119 anv_cmd_dirty_mask_t compute_dirty
;
1120 enum anv_pipe_bits pending_pipe_bits
;
1121 uint32_t num_workgroups_offset
;
1122 struct anv_bo
*num_workgroups_bo
;
1123 VkShaderStageFlags descriptors_dirty
;
1124 VkShaderStageFlags push_constants_dirty
;
1125 uint32_t scratch_size
;
1126 struct anv_pipeline
* pipeline
;
1127 struct anv_pipeline
* compute_pipeline
;
1128 struct anv_framebuffer
* framebuffer
;
1129 struct anv_render_pass
* pass
;
1130 struct anv_subpass
* subpass
;
1131 VkRect2D render_area
;
1132 uint32_t restart_index
;
1133 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1134 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1135 VkShaderStageFlags push_constant_stages
;
1136 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1137 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1138 struct anv_state samplers
[MESA_SHADER_STAGES
];
1139 struct anv_dynamic_state dynamic
;
1143 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1144 * valid only when recording a render pass instance.
1146 struct anv_attachment_state
* attachments
;
1149 struct anv_buffer
* index_buffer
;
1150 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1151 uint32_t index_offset
;
1155 struct anv_cmd_pool
{
1156 VkAllocationCallbacks alloc
;
1157 struct list_head cmd_buffers
;
1160 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1162 enum anv_cmd_buffer_exec_mode
{
1163 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1164 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1165 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1166 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1167 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1170 struct anv_cmd_buffer
{
1171 VK_LOADER_DATA _loader_data
;
1173 struct anv_device
* device
;
1175 struct anv_cmd_pool
* pool
;
1176 struct list_head pool_link
;
1178 struct anv_batch batch
;
1180 /* Fields required for the actual chain of anv_batch_bo's.
1182 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1184 struct list_head batch_bos
;
1185 enum anv_cmd_buffer_exec_mode exec_mode
;
1187 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1188 * referenced by this command buffer
1190 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1192 struct u_vector seen_bbos
;
1194 /* A vector of int32_t's for every block of binding tables.
1196 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1198 struct u_vector bt_blocks
;
1200 struct anv_reloc_list surface_relocs
;
1202 /* Information needed for execbuf
1204 * These fields are generated by anv_cmd_buffer_prepare_execbuf().
1207 struct drm_i915_gem_execbuffer2 execbuf
;
1209 struct drm_i915_gem_exec_object2
* objects
;
1211 struct anv_bo
** bos
;
1213 /* Allocated length of the 'objects' and 'bos' arrays */
1214 uint32_t array_length
;
1219 /* Serial for tracking buffer completion */
1222 /* Stream objects for storing temporary data */
1223 struct anv_state_stream surface_state_stream
;
1224 struct anv_state_stream dynamic_state_stream
;
1226 VkCommandBufferUsageFlags usage_flags
;
1227 VkCommandBufferLevel level
;
1229 struct anv_cmd_state state
;
1232 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1233 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1234 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1235 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1236 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1237 struct anv_cmd_buffer
*secondary
);
1238 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1240 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1243 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1244 gl_shader_stage stage
, uint32_t size
);
1245 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1246 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1247 (offsetof(struct anv_push_constants, field) + \
1248 sizeof(cmd_buffer->state.push_constants[0]->field)))
1250 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1251 const void *data
, uint32_t size
, uint32_t alignment
);
1252 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1253 uint32_t *a
, uint32_t *b
,
1254 uint32_t dwords
, uint32_t alignment
);
1257 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1259 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1260 uint32_t entries
, uint32_t *state_offset
);
1262 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1264 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1265 uint32_t size
, uint32_t alignment
);
1268 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1270 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1271 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1272 bool depth_clamp_enable
);
1273 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1275 void anv_cmd_state_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1276 const VkRenderPassBeginInfo
*info
);
1279 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1280 gl_shader_stage stage
);
1282 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1284 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1285 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1287 const struct anv_image_view
*
1288 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1290 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1294 struct drm_i915_gem_execbuffer2 execbuf
;
1295 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1301 struct anv_state state
;
1304 struct anv_shader_module
{
1305 unsigned char sha1
[20];
1310 void anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
1311 struct anv_shader_module
*module
,
1312 const char *entrypoint
,
1313 const struct anv_pipeline_layout
*pipeline_layout
,
1314 const VkSpecializationInfo
*spec_info
);
1316 static inline gl_shader_stage
1317 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1319 assert(__builtin_popcount(vk_stage
) == 1);
1320 return ffs(vk_stage
) - 1;
1323 static inline VkShaderStageFlagBits
1324 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1326 return (1 << mesa_stage
);
1329 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1331 #define anv_foreach_stage(stage, stage_bits) \
1332 for (gl_shader_stage stage, \
1333 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1334 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1335 __tmp &= ~(1 << (stage)))
1337 struct anv_pipeline_bind_map
{
1338 uint32_t surface_count
;
1339 uint32_t sampler_count
;
1340 uint32_t image_count
;
1342 struct anv_pipeline_binding
* surface_to_descriptor
;
1343 struct anv_pipeline_binding
* sampler_to_descriptor
;
1346 struct anv_shader_bin
{
1349 struct anv_state kernel
;
1350 uint32_t kernel_size
;
1352 struct anv_pipeline_bind_map bind_map
;
1354 uint32_t prog_data_size
;
1356 /* Prog data follows, then the key, both aligned to 8-bytes */
1359 struct anv_shader_bin
*
1360 anv_shader_bin_create(struct anv_device
*device
,
1361 const void *key
, uint32_t key_size
,
1362 const void *kernel
, uint32_t kernel_size
,
1363 const void *prog_data
, uint32_t prog_data_size
,
1364 const struct anv_pipeline_bind_map
*bind_map
);
1367 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1370 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1372 assert(shader
->ref_cnt
>= 1);
1373 __sync_fetch_and_add(&shader
->ref_cnt
, 1);
1377 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1379 assert(shader
->ref_cnt
>= 1);
1380 if (__sync_fetch_and_add(&shader
->ref_cnt
, -1) == 1)
1381 anv_shader_bin_destroy(device
, shader
);
1384 static inline const struct brw_stage_prog_data
*
1385 anv_shader_bin_get_prog_data(const struct anv_shader_bin
*shader
)
1387 const void *data
= shader
;
1388 data
+= align_u32(sizeof(struct anv_shader_bin
), 8);
1392 struct anv_pipeline
{
1393 struct anv_device
* device
;
1394 struct anv_batch batch
;
1395 uint32_t batch_data
[512];
1396 struct anv_reloc_list batch_relocs
;
1397 uint32_t dynamic_state_mask
;
1398 struct anv_dynamic_state dynamic_state
;
1400 struct anv_pipeline_layout
* layout
;
1402 bool needs_data_cache
;
1404 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1407 const struct gen_l3_config
* l3_config
;
1408 uint32_t total_size
;
1411 VkShaderStageFlags active_stages
;
1412 struct anv_state blend_state
;
1420 uint32_t binding_stride
[MAX_VBS
];
1421 bool instancing_enable
[MAX_VBS
];
1422 bool primitive_restart
;
1425 uint32_t cs_right_mask
;
1427 bool depth_clamp_enable
;
1431 uint32_t depth_stencil_state
[3];
1437 uint32_t wm_depth_stencil
[3];
1441 uint32_t wm_depth_stencil
[4];
1446 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1447 gl_shader_stage stage
)
1449 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1452 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1453 static inline const struct brw_##prefix##_prog_data * \
1454 get_##prefix##_prog_data(struct anv_pipeline *pipeline) \
1456 if (anv_pipeline_has_stage(pipeline, stage)) { \
1457 return (const struct brw_##prefix##_prog_data *) \
1458 anv_shader_bin_get_prog_data(pipeline->shaders[stage]); \
1464 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1465 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1466 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1467 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1470 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1471 struct anv_pipeline_cache
*cache
,
1472 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1473 const VkAllocationCallbacks
*alloc
);
1476 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1477 struct anv_pipeline_cache
*cache
,
1478 const VkComputePipelineCreateInfo
*info
,
1479 struct anv_shader_module
*module
,
1480 const char *entrypoint
,
1481 const VkSpecializationInfo
*spec_info
);
1484 enum isl_format isl_format
:16;
1485 struct isl_swizzle swizzle
;
1489 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1490 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1492 static inline enum isl_format
1493 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1494 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1496 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1500 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
1503 * Subsurface of an anv_image.
1505 struct anv_surface
{
1506 /** Valid only if isl_surf::size > 0. */
1507 struct isl_surf isl
;
1510 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1517 /* The original VkFormat provided by the client. This may not match any
1518 * of the actual surface formats.
1521 VkImageAspectFlags aspects
;
1524 uint32_t array_size
;
1525 uint32_t samples
; /**< VkImageCreateInfo::samples */
1526 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1527 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1532 /* Set when bound */
1534 VkDeviceSize offset
;
1539 * For each foo, anv_image::foo_surface is valid if and only if
1540 * anv_image::aspects has a foo aspect.
1542 * The hardware requires that the depth buffer and stencil buffer be
1543 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1544 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1545 * allocate the depth and stencil buffers as separate surfaces in the same
1549 struct anv_surface color_surface
;
1552 struct anv_surface depth_surface
;
1553 struct anv_surface hiz_surface
;
1554 struct anv_surface stencil_surface
;
1559 static inline uint32_t
1560 anv_get_layerCount(const struct anv_image
*image
,
1561 const VkImageSubresourceRange
*range
)
1563 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1564 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1567 static inline uint32_t
1568 anv_get_levelCount(const struct anv_image
*image
,
1569 const VkImageSubresourceRange
*range
)
1571 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1572 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1576 struct anv_image_view
{
1577 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
1579 uint32_t offset
; /**< Offset into bo. */
1581 struct isl_view isl
;
1583 VkImageAspectFlags aspect_mask
;
1585 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1587 /** RENDER_SURFACE_STATE when using image as a color render target. */
1588 struct anv_state color_rt_surface_state
;
1590 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1591 struct anv_state sampler_surface_state
;
1593 /** RENDER_SURFACE_STATE when using image as a storage image. */
1594 struct anv_state storage_surface_state
;
1596 struct brw_image_param storage_image_param
;
1599 struct anv_image_create_info
{
1600 const VkImageCreateInfo
*vk_info
;
1602 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1603 isl_tiling_flags_t isl_tiling_flags
;
1608 VkResult
anv_image_create(VkDevice _device
,
1609 const struct anv_image_create_info
*info
,
1610 const VkAllocationCallbacks
* alloc
,
1613 const struct anv_surface
*
1614 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1615 VkImageAspectFlags aspect_mask
);
1618 anv_image_has_hiz(const struct anv_image
*image
)
1620 /* We must check the aspect because anv_image::hiz_surface belongs to
1623 return (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1624 image
->hiz_surface
.isl
.size
> 0;
1627 struct anv_buffer_view
{
1628 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1630 uint32_t offset
; /**< Offset into bo. */
1631 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1633 struct anv_state surface_state
;
1634 struct anv_state storage_surface_state
;
1636 struct brw_image_param storage_image_param
;
1640 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
1642 static inline struct VkExtent3D
1643 anv_sanitize_image_extent(const VkImageType imageType
,
1644 const struct VkExtent3D imageExtent
)
1646 switch (imageType
) {
1647 case VK_IMAGE_TYPE_1D
:
1648 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1649 case VK_IMAGE_TYPE_2D
:
1650 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1651 case VK_IMAGE_TYPE_3D
:
1654 unreachable("invalid image type");
1658 static inline struct VkOffset3D
1659 anv_sanitize_image_offset(const VkImageType imageType
,
1660 const struct VkOffset3D imageOffset
)
1662 switch (imageType
) {
1663 case VK_IMAGE_TYPE_1D
:
1664 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1665 case VK_IMAGE_TYPE_2D
:
1666 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1667 case VK_IMAGE_TYPE_3D
:
1670 unreachable("invalid image type");
1675 void anv_fill_buffer_surface_state(struct anv_device
*device
,
1676 struct anv_state state
,
1677 enum isl_format format
,
1678 uint32_t offset
, uint32_t range
,
1681 void anv_image_view_fill_image_param(struct anv_device
*device
,
1682 struct anv_image_view
*view
,
1683 struct brw_image_param
*param
);
1684 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
1685 struct anv_buffer_view
*view
,
1686 struct brw_image_param
*param
);
1688 struct anv_sampler
{
1692 struct anv_framebuffer
{
1697 uint32_t attachment_count
;
1698 struct anv_image_view
* attachments
[0];
1701 struct anv_subpass
{
1702 uint32_t input_count
;
1703 uint32_t * input_attachments
;
1704 uint32_t color_count
;
1705 uint32_t * color_attachments
;
1706 uint32_t * resolve_attachments
;
1707 uint32_t depth_stencil_attachment
;
1709 /** Subpass has at least one resolve attachment */
1713 struct anv_render_pass_attachment
{
1716 VkAttachmentLoadOp load_op
;
1717 VkAttachmentStoreOp store_op
;
1718 VkAttachmentLoadOp stencil_load_op
;
1721 struct anv_render_pass
{
1722 uint32_t attachment_count
;
1723 uint32_t subpass_count
;
1724 uint32_t * subpass_attachments
;
1725 struct anv_render_pass_attachment
* attachments
;
1726 struct anv_subpass subpasses
[0];
1729 struct anv_query_pool_slot
{
1735 struct anv_query_pool
{
1741 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
1744 void anv_dump_image_to_ppm(struct anv_device
*device
,
1745 struct anv_image
*image
, unsigned miplevel
,
1746 unsigned array_layer
, VkImageAspectFlagBits aspect
,
1747 const char *filename
);
1749 enum anv_dump_action
{
1750 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
1753 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
1754 void anv_dump_finish(void);
1756 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
1757 struct anv_framebuffer
*fb
);
1759 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1761 static inline struct __anv_type * \
1762 __anv_type ## _from_handle(__VkType _handle) \
1764 return (struct __anv_type *) _handle; \
1767 static inline __VkType \
1768 __anv_type ## _to_handle(struct __anv_type *_obj) \
1770 return (__VkType) _obj; \
1773 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1775 static inline struct __anv_type * \
1776 __anv_type ## _from_handle(__VkType _handle) \
1778 return (struct __anv_type *)(uintptr_t) _handle; \
1781 static inline __VkType \
1782 __anv_type ## _to_handle(struct __anv_type *_obj) \
1784 return (__VkType)(uintptr_t) _obj; \
1787 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1788 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1790 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
1791 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
1792 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
1793 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
1794 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
1796 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
1797 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
1798 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
1799 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
1800 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
1801 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
1802 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
1803 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
1804 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
1805 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
1806 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
1807 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
1808 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
1809 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
1810 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
1811 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
1812 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
1813 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
1814 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
1816 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1818 static inline const __VkType * \
1819 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1821 return (const __VkType *) __anv_obj; \
1824 #define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1825 const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name)
1827 ANV_DEFINE_STRUCT_CASTS(anv_common
, VkMemoryBarrier
)
1828 ANV_DEFINE_STRUCT_CASTS(anv_common
, VkBufferMemoryBarrier
)
1829 ANV_DEFINE_STRUCT_CASTS(anv_common
, VkImageMemoryBarrier
)
1831 /* Gen-specific function declarations */
1833 # include "anv_genX.h"
1835 # define genX(x) gen7_##x
1836 # include "anv_genX.h"
1838 # define genX(x) gen75_##x
1839 # include "anv_genX.h"
1841 # define genX(x) gen8_##x
1842 # include "anv_genX.h"
1844 # define genX(x) gen9_##x
1845 # include "anv_genX.h"
1853 #endif /* ANV_PRIVATE_H */