2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
54 /* Pre-declarations needed for WSI entrypoints */
57 typedef struct xcb_connection_t xcb_connection_t
;
58 typedef uint32_t xcb_visualid_t
;
59 typedef uint32_t xcb_window_t
;
62 struct anv_buffer_view
;
63 struct anv_image_view
;
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
71 #include "anv_entrypoints.h"
74 #include "common/gen_debug.h"
75 #include "wsi_common.h"
77 /* Allowing different clear colors requires us to perform a depth resolve at
78 * the end of certain render passes. This is because while slow clears store
79 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
80 * See the PRMs for examples describing when additional resolves would be
81 * necessary. To enable fast clears without requiring extra resolves, we set
82 * the clear value to a globally-defined one. We could allow different values
83 * if the user doesn't expect coherent data during or after a render passes
84 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
85 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
86 * 1.0f seems to be the only value used. The only application that doesn't set
87 * this value does so through the usage of an seemingly uninitialized clear
90 #define ANV_HZ_FC_VAL 1.0f
95 #define MAX_VIEWPORTS 16
96 #define MAX_SCISSORS 16
97 #define MAX_PUSH_CONSTANTS_SIZE 128
98 #define MAX_DYNAMIC_BUFFERS 16
100 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
102 #define ANV_SVGS_VB_INDEX MAX_VBS
103 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
105 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
107 static inline uint32_t
108 align_down_npot_u32(uint32_t v
, uint32_t a
)
113 static inline uint32_t
114 align_u32(uint32_t v
, uint32_t a
)
116 assert(a
!= 0 && a
== (a
& -a
));
117 return (v
+ a
- 1) & ~(a
- 1);
120 static inline uint64_t
121 align_u64(uint64_t v
, uint64_t a
)
123 assert(a
!= 0 && a
== (a
& -a
));
124 return (v
+ a
- 1) & ~(a
- 1);
127 static inline int32_t
128 align_i32(int32_t v
, int32_t a
)
130 assert(a
!= 0 && a
== (a
& -a
));
131 return (v
+ a
- 1) & ~(a
- 1);
134 /** Alignment must be a power of 2. */
136 anv_is_aligned(uintmax_t n
, uintmax_t a
)
138 assert(a
== (a
& -a
));
139 return (n
& (a
- 1)) == 0;
142 static inline uint32_t
143 anv_minify(uint32_t n
, uint32_t levels
)
145 if (unlikely(n
== 0))
148 return MAX2(n
>> levels
, 1);
152 anv_clamp_f(float f
, float min
, float max
)
165 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
167 if (*inout_mask
& clear_mask
) {
168 *inout_mask
&= ~clear_mask
;
175 static inline union isl_color_value
176 vk_to_isl_color(VkClearColorValue color
)
178 return (union isl_color_value
) {
188 #define for_each_bit(b, dword) \
189 for (uint32_t __dword = (dword); \
190 (b) = __builtin_ffs(__dword) - 1, __dword; \
191 __dword &= ~(1 << (b)))
193 #define typed_memcpy(dest, src, count) ({ \
194 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
195 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 /* Whenever we generate an error, pass it through this function. Useful for
199 * debugging, where we can break on it. Only call at error site, not when
200 * propagating errors. Might be useful to plug in a stack trace here.
203 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
206 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
207 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
208 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
210 #define vk_error(error) error
211 #define vk_errorf(error, format, ...) error
212 #define anv_debug(format, ...)
216 * Warn on ignored extension structs.
218 * The Vulkan spec requires us to ignore unsupported or unknown structs in
219 * a pNext chain. In debug mode, emitting warnings for ignored structs may
220 * help us discover structs that we should not have ignored.
223 * From the Vulkan 1.0.38 spec:
225 * Any component of the implementation (the loader, any enabled layers,
226 * and drivers) must skip over, without processing (other than reading the
227 * sType and pNext members) any chained structures with sType values not
228 * defined by extensions supported by that component.
230 #define anv_debug_ignored_stype(sType) \
231 anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType))
233 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
234 anv_printflike(3, 4);
235 void __anv_perf_warn(const char *file
, int line
, const char *format
, ...)
236 anv_printflike(3, 4);
237 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
238 void anv_loge_v(const char *format
, va_list va
);
241 * Print a FINISHME message, including its source location.
243 #define anv_finishme(format, ...) \
245 static bool reported = false; \
247 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
253 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
255 #define anv_perf_warn(format, ...) \
257 static bool reported = false; \
258 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
259 __anv_perf_warn(__FILE__, __LINE__, format, ##__VA_ARGS__); \
264 /* A non-fatal assert. Useful for debugging. */
266 #define anv_assert(x) ({ \
267 if (unlikely(!(x))) \
268 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
271 #define anv_assert(x)
274 /* A multi-pointer allocator
276 * When copying data structures from the user (such as a render pass), it's
277 * common to need to allocate data for a bunch of different things. Instead
278 * of doing several allocations and having to handle all of the error checking
279 * that entails, it can be easier to do a single allocation. This struct
280 * helps facilitate that. The intended usage looks like this:
283 * anv_multialloc_add(&ma, &main_ptr, 1);
284 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
285 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
287 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
288 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
290 struct anv_multialloc
{
298 #define ANV_MULTIALLOC_INIT \
299 ((struct anv_multialloc) { 0, })
301 #define ANV_MULTIALLOC(_name) \
302 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
304 __attribute__((always_inline
))
306 _anv_multialloc_add(struct anv_multialloc
*ma
,
307 void **ptr
, size_t size
, size_t align
)
309 size_t offset
= align_u64(ma
->size
, align
);
310 ma
->size
= offset
+ size
;
311 ma
->align
= MAX2(ma
->align
, align
);
313 /* Store the offset in the pointer. */
314 *ptr
= (void *)(uintptr_t)offset
;
316 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
317 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
320 #define anv_multialloc_add(_ma, _ptr, _count) \
321 _anv_multialloc_add((_ma), (void **)(_ptr), \
322 (_count) * sizeof(**(_ptr)), __alignof__(**(_ptr)))
324 __attribute__((always_inline
))
326 anv_multialloc_alloc(struct anv_multialloc
*ma
,
327 const VkAllocationCallbacks
*alloc
,
328 VkSystemAllocationScope scope
)
330 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
334 /* Fill out each of the pointers with their final value.
336 * for (uint32_t i = 0; i < ma->ptr_count; i++)
337 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
339 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
340 * constant, GCC is incapable of figuring this out and unrolling the loop
341 * so we have to give it a little help.
343 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
344 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
345 if ((_i) < ma->ptr_count) \
346 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
347 _ANV_MULTIALLOC_UPDATE_POINTER(0);
348 _ANV_MULTIALLOC_UPDATE_POINTER(1);
349 _ANV_MULTIALLOC_UPDATE_POINTER(2);
350 _ANV_MULTIALLOC_UPDATE_POINTER(3);
351 _ANV_MULTIALLOC_UPDATE_POINTER(4);
352 _ANV_MULTIALLOC_UPDATE_POINTER(5);
353 _ANV_MULTIALLOC_UPDATE_POINTER(6);
354 _ANV_MULTIALLOC_UPDATE_POINTER(7);
355 #undef _ANV_MULTIALLOC_UPDATE_POINTER
360 __attribute__((always_inline
))
362 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
363 const VkAllocationCallbacks
*parent_alloc
,
364 const VkAllocationCallbacks
*alloc
,
365 VkSystemAllocationScope scope
)
367 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
371 * A dynamically growable, circular buffer. Elements are added at head and
372 * removed from tail. head and tail are free-running uint32_t indices and we
373 * only compute the modulo with size when accessing the array. This way,
374 * number of bytes in the queue is always head - tail, even in case of
381 /* Index into the current validation list. This is used by the
382 * validation list building alrogithm to track which buffers are already
383 * in the validation list so that we can ensure uniqueness.
387 /* Last known offset. This value is provided by the kernel when we
388 * execbuf and is used as the presumed offset for the next bunch of
396 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
401 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
403 bo
->gem_handle
= gem_handle
;
411 /* Represents a lock-free linked list of "free" things. This is used by
412 * both the block pool and the state pools. Unfortunately, in order to
413 * solve the ABA problem, we can't use a single uint32_t head.
415 union anv_free_list
{
419 /* A simple count that is incremented every time the head changes. */
425 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
427 struct anv_block_state
{
437 struct anv_block_pool
{
438 struct anv_device
*device
;
442 /* The offset from the start of the bo to the "center" of the block
443 * pool. Pointers to allocated blocks are given by
444 * bo.map + center_bo_offset + offsets.
446 uint32_t center_bo_offset
;
448 /* Current memory map of the block pool. This pointer may or may not
449 * point to the actual beginning of the block pool memory. If
450 * anv_block_pool_alloc_back has ever been called, then this pointer
451 * will point to the "center" position of the buffer and all offsets
452 * (negative or positive) given out by the block pool alloc functions
453 * will be valid relative to this pointer.
455 * In particular, map == bo.map + center_offset
461 * Array of mmaps and gem handles owned by the block pool, reclaimed when
462 * the block pool is destroyed.
464 struct u_vector mmap_cleanups
;
466 struct anv_block_state state
;
468 struct anv_block_state back_state
;
471 /* Block pools are backed by a fixed-size 1GB memfd */
472 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
474 /* The center of the block pool is also the middle of the memfd. This may
475 * change in the future if we decide differently for some reason.
477 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
479 static inline uint32_t
480 anv_block_pool_size(struct anv_block_pool
*pool
)
482 return pool
->state
.end
+ pool
->back_state
.end
;
491 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
493 struct anv_fixed_size_state_pool
{
494 union anv_free_list free_list
;
495 struct anv_block_state block
;
498 #define ANV_MIN_STATE_SIZE_LOG2 6
499 #define ANV_MAX_STATE_SIZE_LOG2 20
501 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
503 struct anv_state_pool
{
504 struct anv_block_pool block_pool
;
506 /* The size of blocks which will be allocated from the block pool */
509 /** Free list for "back" allocations */
510 union anv_free_list back_alloc_free_list
;
512 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
515 struct anv_state_stream_block
;
517 struct anv_state_stream
{
518 struct anv_state_pool
*state_pool
;
520 /* The size of blocks to allocate from the state pool */
523 /* Current block we're allocating from */
524 struct anv_state block
;
526 /* Offset into the current block at which to allocate the next state */
529 /* List of all blocks allocated from this pool */
530 struct anv_state_stream_block
*block_list
;
533 /* The block_pool functions exported for testing only. The block pool should
534 * only be used via a state pool (see below).
536 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
537 struct anv_device
*device
,
538 uint32_t initial_size
);
539 void anv_block_pool_finish(struct anv_block_pool
*pool
);
540 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
541 uint32_t block_size
);
542 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
543 uint32_t block_size
);
545 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
546 struct anv_device
*device
,
547 uint32_t block_size
);
548 void anv_state_pool_finish(struct anv_state_pool
*pool
);
549 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
550 uint32_t state_size
, uint32_t alignment
);
551 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
552 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
553 void anv_state_stream_init(struct anv_state_stream
*stream
,
554 struct anv_state_pool
*state_pool
,
555 uint32_t block_size
);
556 void anv_state_stream_finish(struct anv_state_stream
*stream
);
557 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
558 uint32_t size
, uint32_t alignment
);
561 * Implements a pool of re-usable BOs. The interface is identical to that
562 * of block_pool except that each block is its own BO.
565 struct anv_device
*device
;
570 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
571 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
572 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
574 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
576 struct anv_scratch_bo
{
581 struct anv_scratch_pool
{
582 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
583 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
586 void anv_scratch_pool_init(struct anv_device
*device
,
587 struct anv_scratch_pool
*pool
);
588 void anv_scratch_pool_finish(struct anv_device
*device
,
589 struct anv_scratch_pool
*pool
);
590 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
591 struct anv_scratch_pool
*pool
,
592 gl_shader_stage stage
,
593 unsigned per_thread_scratch
);
595 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
596 struct anv_bo_cache
{
597 struct hash_table
*bo_map
;
598 pthread_mutex_t mutex
;
601 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
602 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
603 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
604 struct anv_bo_cache
*cache
,
605 uint64_t size
, struct anv_bo
**bo
);
606 VkResult
anv_bo_cache_import(struct anv_device
*device
,
607 struct anv_bo_cache
*cache
,
608 int fd
, uint64_t size
, struct anv_bo
**bo
);
609 VkResult
anv_bo_cache_export(struct anv_device
*device
,
610 struct anv_bo_cache
*cache
,
611 struct anv_bo
*bo_in
, int *fd_out
);
612 void anv_bo_cache_release(struct anv_device
*device
,
613 struct anv_bo_cache
*cache
,
616 struct anv_memory_type
{
617 /* Standard bits passed on to the client */
618 VkMemoryPropertyFlags propertyFlags
;
621 /* Driver-internal book-keeping */
622 VkBufferUsageFlags valid_buffer_usage
;
625 struct anv_memory_heap
{
626 /* Standard bits passed on to the client */
628 VkMemoryHeapFlags flags
;
630 /* Driver-internal book-keeping */
631 bool supports_48bit_addresses
;
634 struct anv_physical_device
{
635 VK_LOADER_DATA _loader_data
;
637 struct anv_instance
* instance
;
641 struct gen_device_info info
;
642 /** Amount of "GPU memory" we want to advertise
644 * Clearly, this value is bogus since Intel is a UMA architecture. On
645 * gen7 platforms, we are limited by GTT size unless we want to implement
646 * fine-grained tracking and GTT splitting. On Broadwell and above we are
647 * practically unlimited. However, we will never report more than 3/4 of
648 * the total system ram to try and avoid running out of RAM.
650 bool supports_48bit_addresses
;
651 struct brw_compiler
* compiler
;
652 struct isl_device isl_dev
;
653 int cmd_parser_version
;
657 uint32_t subslice_total
;
661 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
663 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
666 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
667 uint8_t driver_uuid
[VK_UUID_SIZE
];
668 uint8_t device_uuid
[VK_UUID_SIZE
];
670 struct wsi_device wsi_device
;
674 struct anv_instance
{
675 VK_LOADER_DATA _loader_data
;
677 VkAllocationCallbacks alloc
;
680 int physicalDeviceCount
;
681 struct anv_physical_device physicalDevice
;
684 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
685 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
687 bool anv_instance_extension_supported(const char *name
);
688 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
692 VK_LOADER_DATA _loader_data
;
694 struct anv_device
* device
;
696 struct anv_state_pool
* pool
;
699 struct anv_pipeline_cache
{
700 struct anv_device
* device
;
701 pthread_mutex_t mutex
;
703 struct hash_table
* cache
;
706 struct anv_pipeline_bind_map
;
708 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
709 struct anv_device
*device
,
711 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
713 struct anv_shader_bin
*
714 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
715 const void *key
, uint32_t key_size
);
716 struct anv_shader_bin
*
717 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
718 const void *key_data
, uint32_t key_size
,
719 const void *kernel_data
, uint32_t kernel_size
,
720 const struct brw_stage_prog_data
*prog_data
,
721 uint32_t prog_data_size
,
722 const struct anv_pipeline_bind_map
*bind_map
);
725 VK_LOADER_DATA _loader_data
;
727 VkAllocationCallbacks alloc
;
729 struct anv_instance
* instance
;
731 struct gen_device_info info
;
732 struct isl_device isl_dev
;
735 bool can_chain_batches
;
736 bool robust_buffer_access
;
738 struct anv_bo_pool batch_bo_pool
;
740 struct anv_bo_cache bo_cache
;
742 struct anv_state_pool dynamic_state_pool
;
743 struct anv_state_pool instruction_state_pool
;
744 struct anv_state_pool surface_state_pool
;
746 struct anv_bo workaround_bo
;
748 struct anv_pipeline_cache blorp_shader_cache
;
749 struct blorp_context blorp
;
751 struct anv_state border_colors
;
753 struct anv_queue queue
;
755 struct anv_scratch_pool scratch_pool
;
757 uint32_t default_mocs
;
759 pthread_mutex_t mutex
;
760 pthread_cond_t queue_submit
;
765 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
767 if (device
->info
.has_llc
)
770 gen_flush_range(state
.map
, state
.alloc_size
);
773 void anv_device_init_blorp(struct anv_device
*device
);
774 void anv_device_finish_blorp(struct anv_device
*device
);
776 VkResult
anv_device_execbuf(struct anv_device
*device
,
777 struct drm_i915_gem_execbuffer2
*execbuf
,
778 struct anv_bo
**execbuf_bos
);
779 VkResult
anv_device_query_status(struct anv_device
*device
);
780 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
781 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
784 void* anv_gem_mmap(struct anv_device
*device
,
785 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
786 void anv_gem_munmap(void *p
, uint64_t size
);
787 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
788 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
789 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
790 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
791 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
792 int anv_gem_execbuffer(struct anv_device
*device
,
793 struct drm_i915_gem_execbuffer2
*execbuf
);
794 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
795 uint32_t stride
, uint32_t tiling
);
796 int anv_gem_create_context(struct anv_device
*device
);
797 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
798 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
800 int anv_gem_get_param(int fd
, uint32_t param
);
801 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
802 int anv_gem_get_aperture(int fd
, uint64_t *size
);
803 bool anv_gem_supports_48b_addresses(int fd
);
804 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
805 uint32_t *active
, uint32_t *pending
);
806 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
807 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
808 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
809 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
810 uint32_t read_domains
, uint32_t write_domain
);
812 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
814 struct anv_reloc_list
{
816 uint32_t array_length
;
817 struct drm_i915_gem_relocation_entry
* relocs
;
818 struct anv_bo
** reloc_bos
;
821 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
822 const VkAllocationCallbacks
*alloc
);
823 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
824 const VkAllocationCallbacks
*alloc
);
826 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
827 const VkAllocationCallbacks
*alloc
,
828 uint32_t offset
, struct anv_bo
*target_bo
,
831 struct anv_batch_bo
{
832 /* Link in the anv_cmd_buffer.owned_batch_bos list */
833 struct list_head link
;
837 /* Bytes actually consumed in this batch BO */
840 struct anv_reloc_list relocs
;
844 const VkAllocationCallbacks
* alloc
;
850 struct anv_reloc_list
* relocs
;
852 /* This callback is called (with the associated user data) in the event
853 * that the batch runs out of space.
855 VkResult (*extend_cb
)(struct anv_batch
*, void *);
859 * Current error status of the command buffer. Used to track inconsistent
860 * or incomplete command buffer states that are the consequence of run-time
861 * errors such as out of memory scenarios. We want to track this in the
862 * batch because the command buffer object is not visible to some parts
868 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
869 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
870 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
871 void *location
, struct anv_bo
*bo
, uint32_t offset
);
872 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
873 struct anv_batch
*batch
);
875 static inline VkResult
876 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
878 assert(error
!= VK_SUCCESS
);
879 if (batch
->status
== VK_SUCCESS
)
880 batch
->status
= error
;
881 return batch
->status
;
885 anv_batch_has_error(struct anv_batch
*batch
)
887 return batch
->status
!= VK_SUCCESS
;
895 static inline uint64_t
896 _anv_combine_address(struct anv_batch
*batch
, void *location
,
897 const struct anv_address address
, uint32_t delta
)
899 if (address
.bo
== NULL
) {
900 return address
.offset
+ delta
;
902 assert(batch
->start
<= location
&& location
< batch
->end
);
904 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
908 #define __gen_address_type struct anv_address
909 #define __gen_user_data struct anv_batch
910 #define __gen_combine_address _anv_combine_address
912 /* Wrapper macros needed to work around preprocessor argument issues. In
913 * particular, arguments don't get pre-evaluated if they are concatenated.
914 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
915 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
916 * We can work around this easily enough with these helpers.
918 #define __anv_cmd_length(cmd) cmd ## _length
919 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
920 #define __anv_cmd_header(cmd) cmd ## _header
921 #define __anv_cmd_pack(cmd) cmd ## _pack
922 #define __anv_reg_num(reg) reg ## _num
924 #define anv_pack_struct(dst, struc, ...) do { \
925 struct struc __template = { \
928 __anv_cmd_pack(struc)(NULL, dst, &__template); \
929 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
932 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
933 void *__dst = anv_batch_emit_dwords(batch, n); \
935 struct cmd __template = { \
936 __anv_cmd_header(cmd), \
937 .DWordLength = n - __anv_cmd_length_bias(cmd), \
940 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
945 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
949 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
950 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
953 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
954 dw[i] = (dwords0)[i] | (dwords1)[i]; \
955 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
958 #define anv_batch_emit(batch, cmd, name) \
959 for (struct cmd name = { __anv_cmd_header(cmd) }, \
960 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
961 __builtin_expect(_dst != NULL, 1); \
962 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
963 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
967 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
968 .GraphicsDataTypeGFDT = 0, \
969 .LLCCacheabilityControlLLCCC = 0, \
970 .L3CacheabilityControlL3CC = 1, \
973 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
974 .LLCeLLCCacheabilityControlLLCCC = 0, \
975 .L3CacheabilityControlL3CC = 1, \
978 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
979 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
980 .TargetCache = L3DefertoPATforLLCeLLCselection, \
984 /* Skylake: MOCS is now an index into an array of 62 different caching
985 * configurations programmed by the kernel.
988 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
989 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
990 .IndextoMOCSTables = 2 \
993 #define GEN9_MOCS_PTE { \
994 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
995 .IndextoMOCSTables = 1 \
998 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
999 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1000 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1001 .IndextoMOCSTables = 2 \
1004 #define GEN10_MOCS_PTE { \
1005 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1006 .IndextoMOCSTables = 1 \
1009 struct anv_device_memory
{
1011 struct anv_memory_type
* type
;
1012 VkDeviceSize map_size
;
1017 * Header for Vertex URB Entry (VUE)
1019 struct anv_vue_header
{
1021 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1022 uint32_t ViewportIndex
;
1026 struct anv_descriptor_set_binding_layout
{
1028 /* The type of the descriptors in this binding */
1029 VkDescriptorType type
;
1032 /* Number of array elements in this binding */
1033 uint16_t array_size
;
1035 /* Index into the flattend descriptor set */
1036 uint16_t descriptor_index
;
1038 /* Index into the dynamic state array for a dynamic buffer */
1039 int16_t dynamic_offset_index
;
1041 /* Index into the descriptor set buffer views */
1042 int16_t buffer_index
;
1045 /* Index into the binding table for the associated surface */
1046 int16_t surface_index
;
1048 /* Index into the sampler table for the associated sampler */
1049 int16_t sampler_index
;
1051 /* Index into the image table for the associated image */
1052 int16_t image_index
;
1053 } stage
[MESA_SHADER_STAGES
];
1055 /* Immutable samplers (or NULL if no immutable samplers) */
1056 struct anv_sampler
**immutable_samplers
;
1059 struct anv_descriptor_set_layout
{
1060 /* Number of bindings in this descriptor set */
1061 uint16_t binding_count
;
1063 /* Total size of the descriptor set with room for all array entries */
1066 /* Shader stages affected by this descriptor set */
1067 uint16_t shader_stages
;
1069 /* Number of buffers in this descriptor set */
1070 uint16_t buffer_count
;
1072 /* Number of dynamic offsets used by this descriptor set */
1073 uint16_t dynamic_offset_count
;
1075 /* Bindings in this descriptor set */
1076 struct anv_descriptor_set_binding_layout binding
[0];
1079 struct anv_descriptor
{
1080 VkDescriptorType type
;
1084 VkImageLayout layout
;
1085 struct anv_image_view
*image_view
;
1086 struct anv_sampler
*sampler
;
1090 struct anv_buffer
*buffer
;
1095 struct anv_buffer_view
*buffer_view
;
1099 struct anv_descriptor_set
{
1100 const struct anv_descriptor_set_layout
*layout
;
1102 uint32_t buffer_count
;
1103 struct anv_buffer_view
*buffer_views
;
1104 struct anv_descriptor descriptors
[0];
1107 struct anv_buffer_view
{
1108 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1110 uint32_t offset
; /**< Offset into bo. */
1111 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1113 struct anv_state surface_state
;
1114 struct anv_state storage_surface_state
;
1115 struct anv_state writeonly_storage_surface_state
;
1117 struct brw_image_param storage_image_param
;
1120 struct anv_push_descriptor_set
{
1121 struct anv_descriptor_set set
;
1123 /* Put this field right behind anv_descriptor_set so it fills up the
1124 * descriptors[0] field. */
1125 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1127 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1130 struct anv_descriptor_pool
{
1135 struct anv_state_stream surface_state_stream
;
1136 void *surface_state_free_list
;
1141 enum anv_descriptor_template_entry_type
{
1142 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1143 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1144 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1147 struct anv_descriptor_template_entry
{
1148 /* The type of descriptor in this entry */
1149 VkDescriptorType type
;
1151 /* Binding in the descriptor set */
1154 /* Offset at which to write into the descriptor set binding */
1155 uint32_t array_element
;
1157 /* Number of elements to write into the descriptor set binding */
1158 uint32_t array_count
;
1160 /* Offset into the user provided data */
1163 /* Stride between elements into the user provided data */
1167 struct anv_descriptor_update_template
{
1168 /* The descriptor set this template corresponds to. This value is only
1169 * valid if the template was created with the templateType
1170 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1174 /* Number of entries in this template */
1175 uint32_t entry_count
;
1177 /* Entries of the template */
1178 struct anv_descriptor_template_entry entries
[0];
1182 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1185 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1186 const struct gen_device_info
* const devinfo
,
1187 const VkDescriptorImageInfo
* const info
,
1188 VkDescriptorType type
,
1193 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1194 VkDescriptorType type
,
1195 struct anv_buffer_view
*buffer_view
,
1200 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1201 struct anv_device
*device
,
1202 struct anv_state_stream
*alloc_stream
,
1203 VkDescriptorType type
,
1204 struct anv_buffer
*buffer
,
1207 VkDeviceSize offset
,
1208 VkDeviceSize range
);
1211 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1212 struct anv_device
*device
,
1213 struct anv_state_stream
*alloc_stream
,
1214 const struct anv_descriptor_update_template
*template,
1218 anv_descriptor_set_create(struct anv_device
*device
,
1219 struct anv_descriptor_pool
*pool
,
1220 const struct anv_descriptor_set_layout
*layout
,
1221 struct anv_descriptor_set
**out_set
);
1224 anv_descriptor_set_destroy(struct anv_device
*device
,
1225 struct anv_descriptor_pool
*pool
,
1226 struct anv_descriptor_set
*set
);
1228 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1230 struct anv_pipeline_binding
{
1231 /* The descriptor set this surface corresponds to. The special value of
1232 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1233 * to a color attachment and not a regular descriptor.
1237 /* Binding in the descriptor set */
1240 /* Index in the binding */
1243 /* Input attachment index (relative to the subpass) */
1244 uint8_t input_attachment_index
;
1246 /* For a storage image, whether it is write-only */
1250 struct anv_pipeline_layout
{
1252 struct anv_descriptor_set_layout
*layout
;
1253 uint32_t dynamic_offset_start
;
1259 bool has_dynamic_offsets
;
1260 } stage
[MESA_SHADER_STAGES
];
1262 unsigned char sha1
[20];
1266 struct anv_device
* device
;
1269 VkBufferUsageFlags usage
;
1271 /* Set when bound */
1273 VkDeviceSize offset
;
1276 static inline uint64_t
1277 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1279 assert(offset
<= buffer
->size
);
1280 if (range
== VK_WHOLE_SIZE
) {
1281 return buffer
->size
- offset
;
1283 assert(range
<= buffer
->size
);
1288 enum anv_cmd_dirty_bits
{
1289 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1290 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1291 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1292 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1293 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1294 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1295 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1296 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1297 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1298 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1299 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1300 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1301 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1303 typedef uint32_t anv_cmd_dirty_mask_t
;
1305 enum anv_pipe_bits
{
1306 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1307 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1308 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1309 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1310 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1311 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1312 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1313 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1314 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1315 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1316 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1318 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1319 * a flush has happened but not a CS stall. The next time we do any sort
1320 * of invalidation we need to insert a CS stall at that time. Otherwise,
1321 * we would have to CS stall on every flush which could be bad.
1323 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1326 #define ANV_PIPE_FLUSH_BITS ( \
1327 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1328 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1329 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1331 #define ANV_PIPE_STALL_BITS ( \
1332 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1333 ANV_PIPE_DEPTH_STALL_BIT | \
1334 ANV_PIPE_CS_STALL_BIT)
1336 #define ANV_PIPE_INVALIDATE_BITS ( \
1337 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1338 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1339 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1340 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1341 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1342 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1344 static inline enum anv_pipe_bits
1345 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1347 enum anv_pipe_bits pipe_bits
= 0;
1350 for_each_bit(b
, flags
) {
1351 switch ((VkAccessFlagBits
)(1 << b
)) {
1352 case VK_ACCESS_SHADER_WRITE_BIT
:
1353 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1355 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1356 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1358 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1359 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1361 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1362 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1363 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1366 break; /* Nothing to do */
1373 static inline enum anv_pipe_bits
1374 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1376 enum anv_pipe_bits pipe_bits
= 0;
1379 for_each_bit(b
, flags
) {
1380 switch ((VkAccessFlagBits
)(1 << b
)) {
1381 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1382 case VK_ACCESS_INDEX_READ_BIT
:
1383 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1384 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1386 case VK_ACCESS_UNIFORM_READ_BIT
:
1387 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1388 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1390 case VK_ACCESS_SHADER_READ_BIT
:
1391 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1392 case VK_ACCESS_TRANSFER_READ_BIT
:
1393 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1396 break; /* Nothing to do */
1403 struct anv_vertex_binding
{
1404 struct anv_buffer
* buffer
;
1405 VkDeviceSize offset
;
1408 struct anv_push_constants
{
1409 /* Current allocated size of this push constants data structure.
1410 * Because a decent chunk of it may not be used (images on SKL, for
1411 * instance), we won't actually allocate the entire structure up-front.
1415 /* Push constant data provided by the client through vkPushConstants */
1416 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1418 /* Our hardware only provides zero-based vertex and instance id so, in
1419 * order to satisfy the vulkan requirements, we may have to push one or
1420 * both of these into the shader.
1422 uint32_t base_vertex
;
1423 uint32_t base_instance
;
1425 /* Image data for image_load_store on pre-SKL */
1426 struct brw_image_param images
[MAX_IMAGES
];
1429 struct anv_dynamic_state
{
1432 VkViewport viewports
[MAX_VIEWPORTS
];
1437 VkRect2D scissors
[MAX_SCISSORS
];
1448 float blend_constants
[4];
1458 } stencil_compare_mask
;
1463 } stencil_write_mask
;
1468 } stencil_reference
;
1471 extern const struct anv_dynamic_state default_dynamic_state
;
1473 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1474 const struct anv_dynamic_state
*src
,
1475 uint32_t copy_mask
);
1478 * Attachment state when recording a renderpass instance.
1480 * The clear value is valid only if there exists a pending clear.
1482 struct anv_attachment_state
{
1483 enum isl_aux_usage aux_usage
;
1484 enum isl_aux_usage input_aux_usage
;
1485 struct anv_state color_rt_state
;
1486 struct anv_state input_att_state
;
1488 VkImageLayout current_layout
;
1489 VkImageAspectFlags pending_clear_aspects
;
1491 VkClearValue clear_value
;
1492 bool clear_color_is_zero_one
;
1493 bool clear_color_is_zero
;
1496 /** State required while building cmd buffer */
1497 struct anv_cmd_state
{
1498 /* PIPELINE_SELECT.PipelineSelection */
1499 uint32_t current_pipeline
;
1500 const struct gen_l3_config
* current_l3_config
;
1502 anv_cmd_dirty_mask_t dirty
;
1503 anv_cmd_dirty_mask_t compute_dirty
;
1504 enum anv_pipe_bits pending_pipe_bits
;
1505 uint32_t num_workgroups_offset
;
1506 struct anv_bo
*num_workgroups_bo
;
1507 VkShaderStageFlags descriptors_dirty
;
1508 VkShaderStageFlags push_constants_dirty
;
1509 uint32_t scratch_size
;
1510 struct anv_pipeline
* pipeline
;
1511 struct anv_pipeline
* compute_pipeline
;
1512 struct anv_framebuffer
* framebuffer
;
1513 struct anv_render_pass
* pass
;
1514 struct anv_subpass
* subpass
;
1515 VkRect2D render_area
;
1516 uint32_t restart_index
;
1517 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1518 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1519 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
1520 VkShaderStageFlags push_constant_stages
;
1521 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1522 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1523 struct anv_state samplers
[MESA_SHADER_STAGES
];
1524 struct anv_dynamic_state dynamic
;
1527 struct anv_push_descriptor_set push_descriptor
;
1530 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1531 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1532 * and before invoking the secondary in ExecuteCommands.
1534 bool pma_fix_enabled
;
1537 * Whether or not we know for certain that HiZ is enabled for the current
1538 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1539 * enabled or not, this will be false.
1544 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1545 * valid only when recording a render pass instance.
1547 struct anv_attachment_state
* attachments
;
1550 * Surface states for color render targets. These are stored in a single
1551 * flat array. For depth-stencil attachments, the surface state is simply
1554 struct anv_state render_pass_states
;
1557 * A null surface state of the right size to match the framebuffer. This
1558 * is one of the states in render_pass_states.
1560 struct anv_state null_surface_state
;
1563 struct anv_buffer
* index_buffer
;
1564 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1565 uint32_t index_offset
;
1569 struct anv_cmd_pool
{
1570 VkAllocationCallbacks alloc
;
1571 struct list_head cmd_buffers
;
1574 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1576 enum anv_cmd_buffer_exec_mode
{
1577 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1578 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1579 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1580 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1581 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1584 struct anv_cmd_buffer
{
1585 VK_LOADER_DATA _loader_data
;
1587 struct anv_device
* device
;
1589 struct anv_cmd_pool
* pool
;
1590 struct list_head pool_link
;
1592 struct anv_batch batch
;
1594 /* Fields required for the actual chain of anv_batch_bo's.
1596 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1598 struct list_head batch_bos
;
1599 enum anv_cmd_buffer_exec_mode exec_mode
;
1601 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1602 * referenced by this command buffer
1604 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1606 struct u_vector seen_bbos
;
1608 /* A vector of int32_t's for every block of binding tables.
1610 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1612 struct u_vector bt_block_states
;
1615 struct anv_reloc_list surface_relocs
;
1616 /** Last seen surface state block pool center bo offset */
1617 uint32_t last_ss_pool_center
;
1619 /* Serial for tracking buffer completion */
1622 /* Stream objects for storing temporary data */
1623 struct anv_state_stream surface_state_stream
;
1624 struct anv_state_stream dynamic_state_stream
;
1626 VkCommandBufferUsageFlags usage_flags
;
1627 VkCommandBufferLevel level
;
1629 struct anv_cmd_state state
;
1632 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1633 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1634 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1635 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1636 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1637 struct anv_cmd_buffer
*secondary
);
1638 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1639 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1640 struct anv_cmd_buffer
*cmd_buffer
,
1641 const VkSemaphore
*in_semaphores
,
1642 uint32_t num_in_semaphores
,
1643 const VkSemaphore
*out_semaphores
,
1644 uint32_t num_out_semaphores
);
1646 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1649 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1650 gl_shader_stage stage
, uint32_t size
);
1651 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1652 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1653 (offsetof(struct anv_push_constants, field) + \
1654 sizeof(cmd_buffer->state.push_constants[0]->field)))
1656 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1657 const void *data
, uint32_t size
, uint32_t alignment
);
1658 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1659 uint32_t *a
, uint32_t *b
,
1660 uint32_t dwords
, uint32_t alignment
);
1663 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1665 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1666 uint32_t entries
, uint32_t *state_offset
);
1668 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1670 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1671 uint32_t size
, uint32_t alignment
);
1674 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1676 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1677 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1678 bool depth_clamp_enable
);
1679 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1681 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1682 struct anv_render_pass
*pass
,
1683 struct anv_framebuffer
*framebuffer
,
1684 const VkClearValue
*clear_values
);
1686 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1689 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1690 gl_shader_stage stage
);
1692 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1694 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1695 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1697 const struct anv_image_view
*
1698 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1701 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1702 uint32_t num_entries
,
1703 uint32_t *state_offset
,
1704 struct anv_state
*bt_state
);
1706 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1708 enum anv_fence_state
{
1709 /** Indicates that this is a new (or newly reset fence) */
1710 ANV_FENCE_STATE_RESET
,
1712 /** Indicates that this fence has been submitted to the GPU but is still
1713 * (as far as we know) in use by the GPU.
1715 ANV_FENCE_STATE_SUBMITTED
,
1717 ANV_FENCE_STATE_SIGNALED
,
1722 struct drm_i915_gem_execbuffer2 execbuf
;
1723 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1724 enum anv_fence_state state
;
1729 struct anv_state state
;
1732 enum anv_semaphore_type
{
1733 ANV_SEMAPHORE_TYPE_NONE
= 0,
1734 ANV_SEMAPHORE_TYPE_DUMMY
,
1735 ANV_SEMAPHORE_TYPE_BO
,
1738 struct anv_semaphore_impl
{
1739 enum anv_semaphore_type type
;
1741 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1742 * This BO will be added to the object list on any execbuf2 calls for
1743 * which this semaphore is used as a wait or signal fence. When used as
1744 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1749 struct anv_semaphore
{
1750 /* Permanent semaphore state. Every semaphore has some form of permanent
1751 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1752 * (for cross-process semaphores0 or it could just be a dummy for use
1755 struct anv_semaphore_impl permanent
;
1757 /* Temporary semaphore state. A semaphore *may* have temporary state.
1758 * That state is added to the semaphore by an import operation and is reset
1759 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1760 * semaphore with temporary state cannot be signaled because the semaphore
1761 * must already be signaled before the temporary state can be exported from
1762 * the semaphore in the other process and imported here.
1764 struct anv_semaphore_impl temporary
;
1767 struct anv_shader_module
{
1768 unsigned char sha1
[20];
1773 static inline gl_shader_stage
1774 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1776 assert(__builtin_popcount(vk_stage
) == 1);
1777 return ffs(vk_stage
) - 1;
1780 static inline VkShaderStageFlagBits
1781 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1783 return (1 << mesa_stage
);
1786 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1788 #define anv_foreach_stage(stage, stage_bits) \
1789 for (gl_shader_stage stage, \
1790 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1791 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1792 __tmp &= ~(1 << (stage)))
1794 struct anv_pipeline_bind_map
{
1795 uint32_t surface_count
;
1796 uint32_t sampler_count
;
1797 uint32_t image_count
;
1799 struct anv_pipeline_binding
* surface_to_descriptor
;
1800 struct anv_pipeline_binding
* sampler_to_descriptor
;
1803 struct anv_shader_bin_key
{
1808 struct anv_shader_bin
{
1811 const struct anv_shader_bin_key
*key
;
1813 struct anv_state kernel
;
1814 uint32_t kernel_size
;
1816 const struct brw_stage_prog_data
*prog_data
;
1817 uint32_t prog_data_size
;
1819 struct anv_pipeline_bind_map bind_map
;
1821 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1824 struct anv_shader_bin
*
1825 anv_shader_bin_create(struct anv_device
*device
,
1826 const void *key
, uint32_t key_size
,
1827 const void *kernel
, uint32_t kernel_size
,
1828 const struct brw_stage_prog_data
*prog_data
,
1829 uint32_t prog_data_size
, const void *prog_data_param
,
1830 const struct anv_pipeline_bind_map
*bind_map
);
1833 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1836 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1838 assert(shader
&& shader
->ref_cnt
>= 1);
1839 p_atomic_inc(&shader
->ref_cnt
);
1843 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1845 assert(shader
&& shader
->ref_cnt
>= 1);
1846 if (p_atomic_dec_zero(&shader
->ref_cnt
))
1847 anv_shader_bin_destroy(device
, shader
);
1850 struct anv_pipeline
{
1851 struct anv_device
* device
;
1852 struct anv_batch batch
;
1853 uint32_t batch_data
[512];
1854 struct anv_reloc_list batch_relocs
;
1855 uint32_t dynamic_state_mask
;
1856 struct anv_dynamic_state dynamic_state
;
1858 struct anv_subpass
* subpass
;
1859 struct anv_pipeline_layout
* layout
;
1861 bool needs_data_cache
;
1863 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1866 const struct gen_l3_config
* l3_config
;
1867 uint32_t total_size
;
1870 VkShaderStageFlags active_stages
;
1871 struct anv_state blend_state
;
1874 uint32_t binding_stride
[MAX_VBS
];
1875 bool instancing_enable
[MAX_VBS
];
1876 bool primitive_restart
;
1879 uint32_t cs_right_mask
;
1882 bool depth_test_enable
;
1883 bool writes_stencil
;
1884 bool stencil_test_enable
;
1885 bool depth_clamp_enable
;
1886 bool sample_shading_enable
;
1891 uint32_t depth_stencil_state
[3];
1897 uint32_t wm_depth_stencil
[3];
1901 uint32_t wm_depth_stencil
[4];
1904 uint32_t interface_descriptor_data
[8];
1908 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1909 gl_shader_stage stage
)
1911 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1914 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1915 static inline const struct brw_##prefix##_prog_data * \
1916 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1918 if (anv_pipeline_has_stage(pipeline, stage)) { \
1919 return (const struct brw_##prefix##_prog_data *) \
1920 pipeline->shaders[stage]->prog_data; \
1926 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1927 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
1928 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
1929 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1930 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1931 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1933 static inline const struct brw_vue_prog_data
*
1934 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
1936 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1937 return &get_gs_prog_data(pipeline
)->base
;
1938 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1939 return &get_tes_prog_data(pipeline
)->base
;
1941 return &get_vs_prog_data(pipeline
)->base
;
1945 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1946 struct anv_pipeline_cache
*cache
,
1947 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1948 const VkAllocationCallbacks
*alloc
);
1951 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1952 struct anv_pipeline_cache
*cache
,
1953 const VkComputePipelineCreateInfo
*info
,
1954 struct anv_shader_module
*module
,
1955 const char *entrypoint
,
1956 const VkSpecializationInfo
*spec_info
);
1959 enum isl_format isl_format
:16;
1960 struct isl_swizzle swizzle
;
1964 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1965 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1967 static inline enum isl_format
1968 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1969 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1971 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1974 static inline struct isl_swizzle
1975 anv_swizzle_for_render(struct isl_swizzle swizzle
)
1977 /* Sometimes the swizzle will have alpha map to one. We do this to fake
1978 * RGB as RGBA for texturing
1980 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
1981 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
1983 /* But it doesn't matter what we render to that channel */
1984 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
1990 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
1993 * Subsurface of an anv_image.
1995 struct anv_surface
{
1996 /** Valid only if isl_surf::size > 0. */
1997 struct isl_surf isl
;
2000 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2007 /* The original VkFormat provided by the client. This may not match any
2008 * of the actual surface formats.
2011 VkImageAspectFlags aspects
;
2014 uint32_t array_size
;
2015 uint32_t samples
; /**< VkImageCreateInfo::samples */
2016 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2017 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2022 /* Set when bound */
2024 VkDeviceSize offset
;
2029 * For each foo, anv_image::foo_surface is valid if and only if
2030 * anv_image::aspects has a foo aspect.
2032 * The hardware requires that the depth buffer and stencil buffer be
2033 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2034 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2035 * allocate the depth and stencil buffers as separate surfaces in the same
2039 struct anv_surface color_surface
;
2042 struct anv_surface depth_surface
;
2043 struct anv_surface stencil_surface
;
2048 * For color images, this is the aux usage for this image when not used as a
2051 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
2054 enum isl_aux_usage aux_usage
;
2056 struct anv_surface aux_surface
;
2059 /* Returns the number of auxiliary buffer levels attached to an image. */
2060 static inline uint8_t
2061 anv_image_aux_levels(const struct anv_image
* const image
)
2064 return image
->aux_surface
.isl
.size
> 0 ? image
->aux_surface
.isl
.levels
: 0;
2067 /* Returns the number of auxiliary buffer layers attached to an image. */
2068 static inline uint32_t
2069 anv_image_aux_layers(const struct anv_image
* const image
,
2070 const uint8_t miplevel
)
2074 /* The miplevel must exist in the main buffer. */
2075 assert(miplevel
< image
->levels
);
2077 if (miplevel
>= anv_image_aux_levels(image
)) {
2078 /* There are no layers with auxiliary data because the miplevel has no
2083 return MAX2(image
->aux_surface
.isl
.logical_level0_px
.array_len
,
2084 image
->aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
2088 static inline unsigned
2089 anv_fast_clear_state_entry_size(const struct anv_device
*device
)
2093 * +--------------------------------------------+
2094 * | clear value dword(s) | needs resolve dword |
2095 * +--------------------------------------------+
2098 /* Ensure that the needs resolve dword is in fact dword-aligned to enable
2099 * GPU memcpy operations.
2101 assert(device
->isl_dev
.ss
.clear_value_size
% 4 == 0);
2102 return device
->isl_dev
.ss
.clear_value_size
+ 4;
2105 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2107 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
2108 const VkImageAspectFlags aspect_mask
,
2109 const uint32_t samples
)
2111 /* Validate the inputs. */
2112 assert(devinfo
&& aspect_mask
&& samples
);
2113 return devinfo
->gen
>= 8 && (aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2118 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
2119 const struct anv_image
*image
,
2120 enum blorp_hiz_op op
);
2122 anv_ccs_resolve(struct anv_cmd_buffer
* const cmd_buffer
,
2123 const struct anv_state surface_state
,
2124 const struct anv_image
* const image
,
2125 const uint8_t level
, const uint32_t layer_count
,
2126 const enum blorp_fast_clear_op op
);
2129 anv_image_fast_clear(struct anv_cmd_buffer
*cmd_buffer
,
2130 const struct anv_image
*image
,
2131 const uint32_t base_level
, const uint32_t level_count
,
2132 const uint32_t base_layer
, uint32_t layer_count
);
2135 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
2136 const struct anv_image
*image
,
2137 const VkImageAspectFlags aspects
,
2138 const VkImageLayout layout
);
2140 /* This is defined as a macro so that it works for both
2141 * VkImageSubresourceRange and VkImageSubresourceLayers
2143 #define anv_get_layerCount(_image, _range) \
2144 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2145 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2147 static inline uint32_t
2148 anv_get_levelCount(const struct anv_image
*image
,
2149 const VkImageSubresourceRange
*range
)
2151 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
2152 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
2156 struct anv_image_view
{
2157 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
2159 uint32_t offset
; /**< Offset into bo. */
2161 struct isl_view isl
;
2163 VkImageAspectFlags aspect_mask
;
2165 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2168 * RENDER_SURFACE_STATE when using image as a sampler surface with an image
2169 * layout of SHADER_READ_ONLY_OPTIMAL or DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2171 enum isl_aux_usage optimal_sampler_aux_usage
;
2172 struct anv_state optimal_sampler_surface_state
;
2175 * RENDER_SURFACE_STATE when using image as a sampler surface with an image
2176 * layout of GENERAL.
2178 enum isl_aux_usage general_sampler_aux_usage
;
2179 struct anv_state general_sampler_surface_state
;
2182 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
2183 * for write-only and readable, using the real format for write-only and the
2184 * lowered format for readable.
2186 struct anv_state storage_surface_state
;
2187 struct anv_state writeonly_storage_surface_state
;
2189 struct brw_image_param storage_image_param
;
2192 struct anv_image_create_info
{
2193 const VkImageCreateInfo
*vk_info
;
2195 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2196 isl_tiling_flags_t isl_tiling_flags
;
2201 VkResult
anv_image_create(VkDevice _device
,
2202 const struct anv_image_create_info
*info
,
2203 const VkAllocationCallbacks
* alloc
,
2206 const struct anv_surface
*
2207 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
2208 VkImageAspectFlags aspect_mask
);
2211 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
2213 static inline struct VkExtent3D
2214 anv_sanitize_image_extent(const VkImageType imageType
,
2215 const struct VkExtent3D imageExtent
)
2217 switch (imageType
) {
2218 case VK_IMAGE_TYPE_1D
:
2219 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2220 case VK_IMAGE_TYPE_2D
:
2221 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2222 case VK_IMAGE_TYPE_3D
:
2225 unreachable("invalid image type");
2229 static inline struct VkOffset3D
2230 anv_sanitize_image_offset(const VkImageType imageType
,
2231 const struct VkOffset3D imageOffset
)
2233 switch (imageType
) {
2234 case VK_IMAGE_TYPE_1D
:
2235 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2236 case VK_IMAGE_TYPE_2D
:
2237 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2238 case VK_IMAGE_TYPE_3D
:
2241 unreachable("invalid image type");
2246 void anv_fill_buffer_surface_state(struct anv_device
*device
,
2247 struct anv_state state
,
2248 enum isl_format format
,
2249 uint32_t offset
, uint32_t range
,
2252 struct anv_sampler
{
2256 struct anv_framebuffer
{
2261 uint32_t attachment_count
;
2262 struct anv_image_view
* attachments
[0];
2265 struct anv_subpass
{
2266 uint32_t attachment_count
;
2269 * A pointer to all attachment references used in this subpass.
2270 * Only valid if ::attachment_count > 0.
2272 VkAttachmentReference
* attachments
;
2273 uint32_t input_count
;
2274 VkAttachmentReference
* input_attachments
;
2275 uint32_t color_count
;
2276 VkAttachmentReference
* color_attachments
;
2277 VkAttachmentReference
* resolve_attachments
;
2279 VkAttachmentReference depth_stencil_attachment
;
2283 /** Subpass has a depth/stencil self-dependency */
2284 bool has_ds_self_dep
;
2286 /** Subpass has at least one resolve attachment */
2290 static inline unsigned
2291 anv_subpass_view_count(const struct anv_subpass
*subpass
)
2293 return MAX2(1, _mesa_bitcount(subpass
->view_mask
));
2296 struct anv_render_pass_attachment
{
2297 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2298 * its members individually.
2302 VkImageUsageFlags usage
;
2303 VkAttachmentLoadOp load_op
;
2304 VkAttachmentStoreOp store_op
;
2305 VkAttachmentLoadOp stencil_load_op
;
2306 VkImageLayout initial_layout
;
2307 VkImageLayout final_layout
;
2308 VkImageLayout first_subpass_layout
;
2310 /* The subpass id in which the attachment will be used last. */
2311 uint32_t last_subpass_idx
;
2314 struct anv_render_pass
{
2315 uint32_t attachment_count
;
2316 uint32_t subpass_count
;
2317 /* An array of subpass_count+1 flushes, one per subpass boundary */
2318 enum anv_pipe_bits
* subpass_flushes
;
2319 struct anv_render_pass_attachment
* attachments
;
2320 struct anv_subpass subpasses
[0];
2323 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2325 struct anv_query_pool
{
2327 VkQueryPipelineStatisticFlags pipeline_statistics
;
2328 /** Stride between slots, in bytes */
2330 /** Number of slots in this query pool */
2335 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
2338 void anv_dump_image_to_ppm(struct anv_device
*device
,
2339 struct anv_image
*image
, unsigned miplevel
,
2340 unsigned array_layer
, VkImageAspectFlagBits aspect
,
2341 const char *filename
);
2343 enum anv_dump_action
{
2344 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
2347 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
2348 void anv_dump_finish(void);
2350 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
2351 struct anv_framebuffer
*fb
);
2353 static inline uint32_t
2354 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
2356 /* This function must be called from within a subpass. */
2357 assert(cmd_state
->pass
&& cmd_state
->subpass
);
2359 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
2361 /* The id of this subpass shouldn't exceed the number of subpasses in this
2362 * render pass minus 1.
2364 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
2368 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2370 static inline struct __anv_type * \
2371 __anv_type ## _from_handle(__VkType _handle) \
2373 return (struct __anv_type *) _handle; \
2376 static inline __VkType \
2377 __anv_type ## _to_handle(struct __anv_type *_obj) \
2379 return (__VkType) _obj; \
2382 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2384 static inline struct __anv_type * \
2385 __anv_type ## _from_handle(__VkType _handle) \
2387 return (struct __anv_type *)(uintptr_t) _handle; \
2390 static inline __VkType \
2391 __anv_type ## _to_handle(struct __anv_type *_obj) \
2393 return (__VkType)(uintptr_t) _obj; \
2396 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2397 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2399 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
2400 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
2401 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
2402 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
2403 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
2405 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
2406 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
2407 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
2408 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
2409 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
2410 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
2411 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
2412 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
2413 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
2414 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
2415 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
2416 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
2417 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
2418 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
2419 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
2420 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
2421 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
2422 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
2423 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
2424 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
2425 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
2427 /* Gen-specific function declarations */
2429 # include "anv_genX.h"
2431 # define genX(x) gen7_##x
2432 # include "anv_genX.h"
2434 # define genX(x) gen75_##x
2435 # include "anv_genX.h"
2437 # define genX(x) gen8_##x
2438 # include "anv_genX.h"
2440 # define genX(x) gen9_##x
2441 # include "anv_genX.h"
2443 # define genX(x) gen10_##x
2444 # include "anv_genX.h"
2448 #endif /* ANV_PRIVATE_H */