2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
52 /* Pre-declarations needed for WSI entrypoints */
55 typedef struct xcb_connection_t xcb_connection_t
;
56 typedef uint32_t xcb_visualid_t
;
57 typedef uint32_t xcb_window_t
;
60 struct anv_buffer_view
;
61 struct anv_image_view
;
65 #include <vulkan/vulkan.h>
66 #include <vulkan/vulkan_intel.h>
67 #include <vulkan/vk_icd.h>
69 #include "anv_entrypoints.h"
70 #include "brw_context.h"
73 #include "wsi_common.h"
75 /* Allowing different clear colors requires us to perform a depth resolve at
76 * the end of certain render passes. This is because while slow clears store
77 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
78 * See the PRMs for examples describing when additional resolves would be
79 * necessary. To enable fast clears without requiring extra resolves, we set
80 * the clear value to a globally-defined one. We could allow different values
81 * if the user doesn't expect coherent data during or after a render passes
82 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
83 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
84 * 1.0f seems to be the only value used. The only application that doesn't set
85 * this value does so through the usage of an seemingly uninitialized clear
88 #define ANV_HZ_FC_VAL 1.0f
93 #define MAX_VIEWPORTS 16
94 #define MAX_SCISSORS 16
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_DYNAMIC_BUFFERS 16
98 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
100 #define ANV_SVGS_VB_INDEX MAX_VBS
101 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
103 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
105 static inline uint32_t
106 align_down_npot_u32(uint32_t v
, uint32_t a
)
111 static inline uint32_t
112 align_u32(uint32_t v
, uint32_t a
)
114 assert(a
!= 0 && a
== (a
& -a
));
115 return (v
+ a
- 1) & ~(a
- 1);
118 static inline uint64_t
119 align_u64(uint64_t v
, uint64_t a
)
121 assert(a
!= 0 && a
== (a
& -a
));
122 return (v
+ a
- 1) & ~(a
- 1);
125 static inline int32_t
126 align_i32(int32_t v
, int32_t a
)
128 assert(a
!= 0 && a
== (a
& -a
));
129 return (v
+ a
- 1) & ~(a
- 1);
132 /** Alignment must be a power of 2. */
134 anv_is_aligned(uintmax_t n
, uintmax_t a
)
136 assert(a
== (a
& -a
));
137 return (n
& (a
- 1)) == 0;
140 static inline uint32_t
141 anv_minify(uint32_t n
, uint32_t levels
)
143 if (unlikely(n
== 0))
146 return MAX2(n
>> levels
, 1);
150 anv_clamp_f(float f
, float min
, float max
)
163 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
165 if (*inout_mask
& clear_mask
) {
166 *inout_mask
&= ~clear_mask
;
173 static inline union isl_color_value
174 vk_to_isl_color(VkClearColorValue color
)
176 return (union isl_color_value
) {
186 #define for_each_bit(b, dword) \
187 for (uint32_t __dword = (dword); \
188 (b) = __builtin_ffs(__dword) - 1, __dword; \
189 __dword &= ~(1 << (b)))
191 #define typed_memcpy(dest, src, count) ({ \
192 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
193 memcpy((dest), (src), (count) * sizeof(*(src))); \
196 /* Whenever we generate an error, pass it through this function. Useful for
197 * debugging, where we can break on it. Only call at error site, not when
198 * propagating errors. Might be useful to plug in a stack trace here.
201 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
204 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
205 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
206 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
208 #define vk_error(error) error
209 #define vk_errorf(error, format, ...) error
210 #define anv_debug(format, ...)
214 * Warn on ignored extension structs.
216 * The Vulkan spec requires us to ignore unsupported or unknown structs in
217 * a pNext chain. In debug mode, emitting warnings for ignored structs may
218 * help us discover structs that we should not have ignored.
221 * From the Vulkan 1.0.38 spec:
223 * Any component of the implementation (the loader, any enabled layers,
224 * and drivers) must skip over, without processing (other than reading the
225 * sType and pNext members) any chained structures with sType values not
226 * defined by extensions supported by that component.
228 #define anv_debug_ignored_stype(sType) \
229 anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType))
231 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
232 anv_printflike(3, 4);
233 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
234 void anv_loge_v(const char *format
, va_list va
);
237 * Print a FINISHME message, including its source location.
239 #define anv_finishme(format, ...) \
241 static bool reported = false; \
243 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
248 /* A non-fatal assert. Useful for debugging. */
250 #define anv_assert(x) ({ \
251 if (unlikely(!(x))) \
252 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
255 #define anv_assert(x)
259 * If a block of code is annotated with anv_validate, then the block runs only
263 #define anv_validate if (1)
265 #define anv_validate if (0)
268 #define stub_return(v) \
270 anv_finishme("stub %s", __func__); \
276 anv_finishme("stub %s", __func__); \
281 * A dynamically growable, circular buffer. Elements are added at head and
282 * removed from tail. head and tail are free-running uint32_t indices and we
283 * only compute the modulo with size when accessing the array. This way,
284 * number of bytes in the queue is always head - tail, even in case of
291 /* Index into the current validation list. This is used by the
292 * validation list building alrogithm to track which buffers are already
293 * in the validation list so that we can ensure uniqueness.
297 /* Last known offset. This value is provided by the kernel when we
298 * execbuf and is used as the presumed offset for the next bunch of
306 /* We need to set the WRITE flag on winsys bos so GEM will know we're
307 * writing to them and synchronize uses on other rings (eg if the display
308 * server uses the blitter ring).
314 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
316 bo
->gem_handle
= gem_handle
;
321 bo
->is_winsys_bo
= false;
324 /* Represents a lock-free linked list of "free" things. This is used by
325 * both the block pool and the state pools. Unfortunately, in order to
326 * solve the ABA problem, we can't use a single uint32_t head.
328 union anv_free_list
{
332 /* A simple count that is incremented every time the head changes. */
338 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
340 struct anv_block_state
{
350 struct anv_block_pool
{
351 struct anv_device
*device
;
355 /* The offset from the start of the bo to the "center" of the block
356 * pool. Pointers to allocated blocks are given by
357 * bo.map + center_bo_offset + offsets.
359 uint32_t center_bo_offset
;
361 /* Current memory map of the block pool. This pointer may or may not
362 * point to the actual beginning of the block pool memory. If
363 * anv_block_pool_alloc_back has ever been called, then this pointer
364 * will point to the "center" position of the buffer and all offsets
365 * (negative or positive) given out by the block pool alloc functions
366 * will be valid relative to this pointer.
368 * In particular, map == bo.map + center_offset
374 * Array of mmaps and gem handles owned by the block pool, reclaimed when
375 * the block pool is destroyed.
377 struct u_vector mmap_cleanups
;
381 union anv_free_list free_list
;
382 struct anv_block_state state
;
384 union anv_free_list back_free_list
;
385 struct anv_block_state back_state
;
388 /* Block pools are backed by a fixed-size 2GB memfd */
389 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
391 /* The center of the block pool is also the middle of the memfd. This may
392 * change in the future if we decide differently for some reason.
394 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
396 static inline uint32_t
397 anv_block_pool_size(struct anv_block_pool
*pool
)
399 return pool
->state
.end
+ pool
->back_state
.end
;
408 struct anv_fixed_size_state_pool
{
410 union anv_free_list free_list
;
411 struct anv_block_state block
;
414 #define ANV_MIN_STATE_SIZE_LOG2 6
415 #define ANV_MAX_STATE_SIZE_LOG2 20
417 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
419 struct anv_state_pool
{
420 struct anv_block_pool
*block_pool
;
421 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
424 struct anv_state_stream_block
;
426 struct anv_state_stream
{
427 struct anv_block_pool
*block_pool
;
429 /* The current working block */
430 struct anv_state_stream_block
*block
;
432 /* Offset at which the current block starts */
434 /* Offset at which to allocate the next state */
436 /* Offset at which the current block ends */
440 #define CACHELINE_SIZE 64
441 #define CACHELINE_MASK 63
444 anv_clflush_range(void *start
, size_t size
)
446 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
447 void *end
= start
+ size
;
450 __builtin_ia32_clflush(p
);
456 anv_flush_range(void *start
, size_t size
)
458 __builtin_ia32_mfence();
459 anv_clflush_range(start
, size
);
463 anv_invalidate_range(void *start
, size_t size
)
465 anv_clflush_range(start
, size
);
466 __builtin_ia32_mfence();
469 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
470 struct anv_device
*device
, uint32_t block_size
);
471 void anv_block_pool_finish(struct anv_block_pool
*pool
);
472 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
);
473 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
);
474 void anv_block_pool_free(struct anv_block_pool
*pool
, int32_t offset
);
475 void anv_state_pool_init(struct anv_state_pool
*pool
,
476 struct anv_block_pool
*block_pool
);
477 void anv_state_pool_finish(struct anv_state_pool
*pool
);
478 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
479 size_t state_size
, size_t alignment
);
480 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
481 void anv_state_stream_init(struct anv_state_stream
*stream
,
482 struct anv_block_pool
*block_pool
);
483 void anv_state_stream_finish(struct anv_state_stream
*stream
);
484 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
485 uint32_t size
, uint32_t alignment
);
488 * Implements a pool of re-usable BOs. The interface is identical to that
489 * of block_pool except that each block is its own BO.
492 struct anv_device
*device
;
497 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
498 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
499 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
501 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
503 struct anv_scratch_bo
{
508 struct anv_scratch_pool
{
509 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
510 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
513 void anv_scratch_pool_init(struct anv_device
*device
,
514 struct anv_scratch_pool
*pool
);
515 void anv_scratch_pool_finish(struct anv_device
*device
,
516 struct anv_scratch_pool
*pool
);
517 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
518 struct anv_scratch_pool
*pool
,
519 gl_shader_stage stage
,
520 unsigned per_thread_scratch
);
522 struct anv_physical_device
{
523 VK_LOADER_DATA _loader_data
;
525 struct anv_instance
* instance
;
529 struct gen_device_info info
;
530 uint64_t aperture_size
;
531 struct brw_compiler
* compiler
;
532 struct isl_device isl_dev
;
533 int cmd_parser_version
;
536 uint32_t subslice_total
;
538 uint8_t uuid
[VK_UUID_SIZE
];
540 struct wsi_device wsi_device
;
544 struct anv_instance
{
545 VK_LOADER_DATA _loader_data
;
547 VkAllocationCallbacks alloc
;
550 int physicalDeviceCount
;
551 struct anv_physical_device physicalDevice
;
554 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
555 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
558 VK_LOADER_DATA _loader_data
;
560 struct anv_device
* device
;
562 struct anv_state_pool
* pool
;
565 struct anv_pipeline_cache
{
566 struct anv_device
* device
;
567 pthread_mutex_t mutex
;
569 struct hash_table
* cache
;
572 struct anv_pipeline_bind_map
;
574 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
575 struct anv_device
*device
,
577 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
579 struct anv_shader_bin
*
580 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
581 const void *key
, uint32_t key_size
);
582 struct anv_shader_bin
*
583 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
584 const void *key_data
, uint32_t key_size
,
585 const void *kernel_data
, uint32_t kernel_size
,
586 const struct brw_stage_prog_data
*prog_data
,
587 uint32_t prog_data_size
,
588 const struct anv_pipeline_bind_map
*bind_map
);
591 VK_LOADER_DATA _loader_data
;
593 VkAllocationCallbacks alloc
;
595 struct anv_instance
* instance
;
597 struct gen_device_info info
;
598 struct isl_device isl_dev
;
601 bool can_chain_batches
;
602 bool robust_buffer_access
;
604 struct anv_bo_pool batch_bo_pool
;
606 struct anv_block_pool dynamic_state_block_pool
;
607 struct anv_state_pool dynamic_state_pool
;
609 struct anv_block_pool instruction_block_pool
;
610 struct anv_state_pool instruction_state_pool
;
612 struct anv_block_pool surface_state_block_pool
;
613 struct anv_state_pool surface_state_pool
;
615 struct anv_bo workaround_bo
;
617 struct anv_pipeline_cache blorp_shader_cache
;
618 struct blorp_context blorp
;
620 struct anv_state border_colors
;
622 struct anv_queue queue
;
624 struct anv_scratch_pool scratch_pool
;
626 uint32_t default_mocs
;
628 pthread_mutex_t mutex
;
629 pthread_cond_t queue_submit
;
633 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
635 if (device
->info
.has_llc
)
638 anv_flush_range(state
.map
, state
.alloc_size
);
641 void anv_device_init_blorp(struct anv_device
*device
);
642 void anv_device_finish_blorp(struct anv_device
*device
);
644 VkResult
anv_device_execbuf(struct anv_device
*device
,
645 struct drm_i915_gem_execbuffer2
*execbuf
,
646 struct anv_bo
**execbuf_bos
);
648 void* anv_gem_mmap(struct anv_device
*device
,
649 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
650 void anv_gem_munmap(void *p
, uint64_t size
);
651 uint32_t anv_gem_create(struct anv_device
*device
, size_t size
);
652 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
653 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
654 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
655 int anv_gem_execbuffer(struct anv_device
*device
,
656 struct drm_i915_gem_execbuffer2
*execbuf
);
657 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
658 uint32_t stride
, uint32_t tiling
);
659 int anv_gem_create_context(struct anv_device
*device
);
660 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
661 int anv_gem_get_param(int fd
, uint32_t param
);
662 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
663 int anv_gem_get_aperture(int fd
, uint64_t *size
);
664 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
665 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
666 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
667 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
668 uint32_t read_domains
, uint32_t write_domain
);
670 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
672 struct anv_reloc_list
{
675 struct drm_i915_gem_relocation_entry
* relocs
;
676 struct anv_bo
** reloc_bos
;
679 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
680 const VkAllocationCallbacks
*alloc
);
681 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
682 const VkAllocationCallbacks
*alloc
);
684 uint64_t anv_reloc_list_add(struct anv_reloc_list
*list
,
685 const VkAllocationCallbacks
*alloc
,
686 uint32_t offset
, struct anv_bo
*target_bo
,
689 struct anv_batch_bo
{
690 /* Link in the anv_cmd_buffer.owned_batch_bos list */
691 struct list_head link
;
695 /* Bytes actually consumed in this batch BO */
698 struct anv_reloc_list relocs
;
702 const VkAllocationCallbacks
* alloc
;
708 struct anv_reloc_list
* relocs
;
710 /* This callback is called (with the associated user data) in the event
711 * that the batch runs out of space.
713 VkResult (*extend_cb
)(struct anv_batch
*, void *);
717 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
718 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
719 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
720 void *location
, struct anv_bo
*bo
, uint32_t offset
);
721 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
722 struct anv_batch
*batch
);
729 static inline uint64_t
730 _anv_combine_address(struct anv_batch
*batch
, void *location
,
731 const struct anv_address address
, uint32_t delta
)
733 if (address
.bo
== NULL
) {
734 return address
.offset
+ delta
;
736 assert(batch
->start
<= location
&& location
< batch
->end
);
738 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
742 #define __gen_address_type struct anv_address
743 #define __gen_user_data struct anv_batch
744 #define __gen_combine_address _anv_combine_address
746 /* Wrapper macros needed to work around preprocessor argument issues. In
747 * particular, arguments don't get pre-evaluated if they are concatenated.
748 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
749 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
750 * We can work around this easily enough with these helpers.
752 #define __anv_cmd_length(cmd) cmd ## _length
753 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
754 #define __anv_cmd_header(cmd) cmd ## _header
755 #define __anv_cmd_pack(cmd) cmd ## _pack
756 #define __anv_reg_num(reg) reg ## _num
758 #define anv_pack_struct(dst, struc, ...) do { \
759 struct struc __template = { \
762 __anv_cmd_pack(struc)(NULL, dst, &__template); \
763 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
766 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
767 void *__dst = anv_batch_emit_dwords(batch, n); \
768 struct cmd __template = { \
769 __anv_cmd_header(cmd), \
770 .DWordLength = n - __anv_cmd_length_bias(cmd), \
773 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
777 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
781 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
782 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
783 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
784 dw[i] = (dwords0)[i] | (dwords1)[i]; \
785 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
788 #define anv_batch_emit(batch, cmd, name) \
789 for (struct cmd name = { __anv_cmd_header(cmd) }, \
790 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
791 __builtin_expect(_dst != NULL, 1); \
792 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
793 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
797 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
798 .GraphicsDataTypeGFDT = 0, \
799 .LLCCacheabilityControlLLCCC = 0, \
800 .L3CacheabilityControlL3CC = 1, \
803 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
804 .LLCeLLCCacheabilityControlLLCCC = 0, \
805 .L3CacheabilityControlL3CC = 1, \
808 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
809 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
810 .TargetCache = L3DefertoPATforLLCeLLCselection, \
814 /* Skylake: MOCS is now an index into an array of 62 different caching
815 * configurations programmed by the kernel.
818 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
819 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
820 .IndextoMOCSTables = 2 \
823 #define GEN9_MOCS_PTE { \
824 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
825 .IndextoMOCSTables = 1 \
828 struct anv_device_memory
{
831 VkDeviceSize map_size
;
836 * Header for Vertex URB Entry (VUE)
838 struct anv_vue_header
{
840 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
841 uint32_t ViewportIndex
;
845 struct anv_descriptor_set_binding_layout
{
847 /* The type of the descriptors in this binding */
848 VkDescriptorType type
;
851 /* Number of array elements in this binding */
854 /* Index into the flattend descriptor set */
855 uint16_t descriptor_index
;
857 /* Index into the dynamic state array for a dynamic buffer */
858 int16_t dynamic_offset_index
;
860 /* Index into the descriptor set buffer views */
861 int16_t buffer_index
;
864 /* Index into the binding table for the associated surface */
865 int16_t surface_index
;
867 /* Index into the sampler table for the associated sampler */
868 int16_t sampler_index
;
870 /* Index into the image table for the associated image */
872 } stage
[MESA_SHADER_STAGES
];
874 /* Immutable samplers (or NULL if no immutable samplers) */
875 struct anv_sampler
**immutable_samplers
;
878 struct anv_descriptor_set_layout
{
879 /* Number of bindings in this descriptor set */
880 uint16_t binding_count
;
882 /* Total size of the descriptor set with room for all array entries */
885 /* Shader stages affected by this descriptor set */
886 uint16_t shader_stages
;
888 /* Number of buffers in this descriptor set */
889 uint16_t buffer_count
;
891 /* Number of dynamic offsets used by this descriptor set */
892 uint16_t dynamic_offset_count
;
894 /* Bindings in this descriptor set */
895 struct anv_descriptor_set_binding_layout binding
[0];
898 struct anv_descriptor
{
899 VkDescriptorType type
;
903 struct anv_image_view
*image_view
;
904 struct anv_sampler
*sampler
;
907 struct anv_buffer_view
*buffer_view
;
911 struct anv_descriptor_set
{
912 const struct anv_descriptor_set_layout
*layout
;
914 uint32_t buffer_count
;
915 struct anv_buffer_view
*buffer_views
;
916 struct anv_descriptor descriptors
[0];
919 struct anv_buffer_view
{
920 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
922 uint32_t offset
; /**< Offset into bo. */
923 uint64_t range
; /**< VkBufferViewCreateInfo::range */
925 struct anv_state surface_state
;
926 struct anv_state storage_surface_state
;
927 struct anv_state writeonly_storage_surface_state
;
929 struct brw_image_param storage_image_param
;
932 struct anv_push_descriptor_set
{
933 struct anv_descriptor_set set
;
935 /* Put this field right behind anv_descriptor_set so it fills up the
936 * descriptors[0] field. */
937 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
939 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
942 struct anv_descriptor_pool
{
947 struct anv_state_stream surface_state_stream
;
948 void *surface_state_free_list
;
954 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
957 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
958 VkDescriptorType type
,
959 VkImageView _image_view
,
965 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
966 VkDescriptorType type
,
967 struct anv_buffer_view
*buffer_view
,
972 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
973 struct anv_device
*device
,
974 struct anv_state_stream
*alloc_stream
,
975 VkDescriptorType type
,
976 struct anv_buffer
*buffer
,
983 anv_descriptor_set_create(struct anv_device
*device
,
984 struct anv_descriptor_pool
*pool
,
985 const struct anv_descriptor_set_layout
*layout
,
986 struct anv_descriptor_set
**out_set
);
989 anv_descriptor_set_destroy(struct anv_device
*device
,
990 struct anv_descriptor_pool
*pool
,
991 struct anv_descriptor_set
*set
);
993 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
995 struct anv_pipeline_binding
{
996 /* The descriptor set this surface corresponds to. The special value of
997 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
998 * to a color attachment and not a regular descriptor.
1002 /* Binding in the descriptor set */
1005 /* Index in the binding */
1008 /* Input attachment index (relative to the subpass) */
1009 uint8_t input_attachment_index
;
1011 /* For a storage image, whether it is write-only */
1015 struct anv_pipeline_layout
{
1017 struct anv_descriptor_set_layout
*layout
;
1018 uint32_t dynamic_offset_start
;
1024 bool has_dynamic_offsets
;
1025 } stage
[MESA_SHADER_STAGES
];
1027 unsigned char sha1
[20];
1031 struct anv_device
* device
;
1034 VkBufferUsageFlags usage
;
1036 /* Set when bound */
1038 VkDeviceSize offset
;
1041 enum anv_cmd_dirty_bits
{
1042 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1043 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1044 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1045 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1046 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1047 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1048 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1049 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1050 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1051 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1052 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1053 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1054 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1056 typedef uint32_t anv_cmd_dirty_mask_t
;
1058 enum anv_pipe_bits
{
1059 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1060 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1061 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1062 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1063 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1064 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1065 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1066 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1067 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1068 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1069 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1071 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1072 * a flush has happened but not a CS stall. The next time we do any sort
1073 * of invalidation we need to insert a CS stall at that time. Otherwise,
1074 * we would have to CS stall on every flush which could be bad.
1076 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1079 #define ANV_PIPE_FLUSH_BITS ( \
1080 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1081 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1082 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1084 #define ANV_PIPE_STALL_BITS ( \
1085 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1086 ANV_PIPE_DEPTH_STALL_BIT | \
1087 ANV_PIPE_CS_STALL_BIT)
1089 #define ANV_PIPE_INVALIDATE_BITS ( \
1090 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1091 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1092 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1093 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1094 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1095 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1097 struct anv_vertex_binding
{
1098 struct anv_buffer
* buffer
;
1099 VkDeviceSize offset
;
1102 struct anv_push_constants
{
1103 /* Current allocated size of this push constants data structure.
1104 * Because a decent chunk of it may not be used (images on SKL, for
1105 * instance), we won't actually allocate the entire structure up-front.
1109 /* Push constant data provided by the client through vkPushConstants */
1110 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1112 /* Our hardware only provides zero-based vertex and instance id so, in
1113 * order to satisfy the vulkan requirements, we may have to push one or
1114 * both of these into the shader.
1116 uint32_t base_vertex
;
1117 uint32_t base_instance
;
1119 /* Offsets and ranges for dynamically bound buffers */
1123 } dynamic
[MAX_DYNAMIC_BUFFERS
];
1125 /* Image data for image_load_store on pre-SKL */
1126 struct brw_image_param images
[MAX_IMAGES
];
1129 struct anv_dynamic_state
{
1132 VkViewport viewports
[MAX_VIEWPORTS
];
1137 VkRect2D scissors
[MAX_SCISSORS
];
1148 float blend_constants
[4];
1158 } stencil_compare_mask
;
1163 } stencil_write_mask
;
1168 } stencil_reference
;
1171 extern const struct anv_dynamic_state default_dynamic_state
;
1173 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1174 const struct anv_dynamic_state
*src
,
1175 uint32_t copy_mask
);
1178 * Attachment state when recording a renderpass instance.
1180 * The clear value is valid only if there exists a pending clear.
1182 struct anv_attachment_state
{
1183 enum isl_aux_usage aux_usage
;
1184 enum isl_aux_usage input_aux_usage
;
1185 struct anv_state color_rt_state
;
1186 struct anv_state input_att_state
;
1188 VkImageLayout current_layout
;
1189 VkImageAspectFlags pending_clear_aspects
;
1191 VkClearValue clear_value
;
1192 bool clear_color_is_zero_one
;
1195 /** State required while building cmd buffer */
1196 struct anv_cmd_state
{
1197 /* PIPELINE_SELECT.PipelineSelection */
1198 uint32_t current_pipeline
;
1199 const struct gen_l3_config
* current_l3_config
;
1201 anv_cmd_dirty_mask_t dirty
;
1202 anv_cmd_dirty_mask_t compute_dirty
;
1203 enum anv_pipe_bits pending_pipe_bits
;
1204 uint32_t num_workgroups_offset
;
1205 struct anv_bo
*num_workgroups_bo
;
1206 VkShaderStageFlags descriptors_dirty
;
1207 VkShaderStageFlags push_constants_dirty
;
1208 uint32_t scratch_size
;
1209 struct anv_pipeline
* pipeline
;
1210 struct anv_pipeline
* compute_pipeline
;
1211 struct anv_framebuffer
* framebuffer
;
1212 struct anv_render_pass
* pass
;
1213 struct anv_subpass
* subpass
;
1214 VkRect2D render_area
;
1215 uint32_t restart_index
;
1216 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1217 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1218 VkShaderStageFlags push_constant_stages
;
1219 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1220 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1221 struct anv_state samplers
[MESA_SHADER_STAGES
];
1222 struct anv_dynamic_state dynamic
;
1225 struct anv_push_descriptor_set push_descriptor
;
1228 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1229 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1230 * and before invoking the secondary in ExecuteCommands.
1232 bool pma_fix_enabled
;
1235 * Whether or not we know for certain that HiZ is enabled for the current
1236 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1237 * enabled or not, this will be false.
1242 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1243 * valid only when recording a render pass instance.
1245 struct anv_attachment_state
* attachments
;
1248 * Surface states for color render targets. These are stored in a single
1249 * flat array. For depth-stencil attachments, the surface state is simply
1252 struct anv_state render_pass_states
;
1255 * A null surface state of the right size to match the framebuffer. This
1256 * is one of the states in render_pass_states.
1258 struct anv_state null_surface_state
;
1261 struct anv_buffer
* index_buffer
;
1262 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1263 uint32_t index_offset
;
1267 struct anv_cmd_pool
{
1268 VkAllocationCallbacks alloc
;
1269 struct list_head cmd_buffers
;
1272 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1274 enum anv_cmd_buffer_exec_mode
{
1275 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1276 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1277 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1278 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1279 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1282 struct anv_cmd_buffer
{
1283 VK_LOADER_DATA _loader_data
;
1285 struct anv_device
* device
;
1287 struct anv_cmd_pool
* pool
;
1288 struct list_head pool_link
;
1290 struct anv_batch batch
;
1292 /* Fields required for the actual chain of anv_batch_bo's.
1294 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1296 struct list_head batch_bos
;
1297 enum anv_cmd_buffer_exec_mode exec_mode
;
1299 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1300 * referenced by this command buffer
1302 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1304 struct u_vector seen_bbos
;
1306 /* A vector of int32_t's for every block of binding tables.
1308 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1310 struct u_vector bt_blocks
;
1313 struct anv_reloc_list surface_relocs
;
1314 /** Last seen surface state block pool center bo offset */
1315 uint32_t last_ss_pool_center
;
1317 /* Serial for tracking buffer completion */
1320 /* Stream objects for storing temporary data */
1321 struct anv_state_stream surface_state_stream
;
1322 struct anv_state_stream dynamic_state_stream
;
1324 VkCommandBufferUsageFlags usage_flags
;
1325 VkCommandBufferLevel level
;
1327 struct anv_cmd_state state
;
1330 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1331 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1332 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1333 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1334 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1335 struct anv_cmd_buffer
*secondary
);
1336 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1337 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1338 struct anv_cmd_buffer
*cmd_buffer
);
1340 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1343 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1344 gl_shader_stage stage
, uint32_t size
);
1345 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1346 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1347 (offsetof(struct anv_push_constants, field) + \
1348 sizeof(cmd_buffer->state.push_constants[0]->field)))
1350 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1351 const void *data
, uint32_t size
, uint32_t alignment
);
1352 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1353 uint32_t *a
, uint32_t *b
,
1354 uint32_t dwords
, uint32_t alignment
);
1357 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1359 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1360 uint32_t entries
, uint32_t *state_offset
);
1362 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1364 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1365 uint32_t size
, uint32_t alignment
);
1368 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1370 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1371 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1372 bool depth_clamp_enable
);
1373 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1375 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1376 struct anv_render_pass
*pass
,
1377 struct anv_framebuffer
*framebuffer
,
1378 const VkClearValue
*clear_values
);
1380 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1383 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1384 gl_shader_stage stage
);
1386 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1388 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1389 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1391 const struct anv_image_view
*
1392 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1395 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1396 uint32_t num_entries
,
1397 uint32_t *state_offset
);
1399 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1401 enum anv_fence_state
{
1402 /** Indicates that this is a new (or newly reset fence) */
1403 ANV_FENCE_STATE_RESET
,
1405 /** Indicates that this fence has been submitted to the GPU but is still
1406 * (as far as we know) in use by the GPU.
1408 ANV_FENCE_STATE_SUBMITTED
,
1410 ANV_FENCE_STATE_SIGNALED
,
1415 struct drm_i915_gem_execbuffer2 execbuf
;
1416 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1417 enum anv_fence_state state
;
1422 struct anv_state state
;
1425 struct anv_shader_module
{
1426 unsigned char sha1
[20];
1431 void anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
1432 struct anv_shader_module
*module
,
1433 const char *entrypoint
,
1434 const struct anv_pipeline_layout
*pipeline_layout
,
1435 const VkSpecializationInfo
*spec_info
);
1437 static inline gl_shader_stage
1438 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1440 assert(__builtin_popcount(vk_stage
) == 1);
1441 return ffs(vk_stage
) - 1;
1444 static inline VkShaderStageFlagBits
1445 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1447 return (1 << mesa_stage
);
1450 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1452 #define anv_foreach_stage(stage, stage_bits) \
1453 for (gl_shader_stage stage, \
1454 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1455 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1456 __tmp &= ~(1 << (stage)))
1458 struct anv_pipeline_bind_map
{
1459 uint32_t surface_count
;
1460 uint32_t sampler_count
;
1461 uint32_t image_count
;
1463 struct anv_pipeline_binding
* surface_to_descriptor
;
1464 struct anv_pipeline_binding
* sampler_to_descriptor
;
1467 struct anv_shader_bin_key
{
1472 struct anv_shader_bin
{
1475 const struct anv_shader_bin_key
*key
;
1477 struct anv_state kernel
;
1478 uint32_t kernel_size
;
1480 const struct brw_stage_prog_data
*prog_data
;
1481 uint32_t prog_data_size
;
1483 struct anv_pipeline_bind_map bind_map
;
1485 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1488 struct anv_shader_bin
*
1489 anv_shader_bin_create(struct anv_device
*device
,
1490 const void *key
, uint32_t key_size
,
1491 const void *kernel
, uint32_t kernel_size
,
1492 const struct brw_stage_prog_data
*prog_data
,
1493 uint32_t prog_data_size
, const void *prog_data_param
,
1494 const struct anv_pipeline_bind_map
*bind_map
);
1497 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1500 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1502 assert(shader
->ref_cnt
>= 1);
1503 __sync_fetch_and_add(&shader
->ref_cnt
, 1);
1507 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1509 assert(shader
->ref_cnt
>= 1);
1510 if (__sync_fetch_and_add(&shader
->ref_cnt
, -1) == 1)
1511 anv_shader_bin_destroy(device
, shader
);
1514 struct anv_pipeline
{
1515 struct anv_device
* device
;
1516 struct anv_batch batch
;
1517 uint32_t batch_data
[512];
1518 struct anv_reloc_list batch_relocs
;
1519 uint32_t dynamic_state_mask
;
1520 struct anv_dynamic_state dynamic_state
;
1522 struct anv_pipeline_layout
* layout
;
1524 bool needs_data_cache
;
1526 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1529 const struct gen_l3_config
* l3_config
;
1530 uint32_t total_size
;
1533 VkShaderStageFlags active_stages
;
1534 struct anv_state blend_state
;
1537 uint32_t binding_stride
[MAX_VBS
];
1538 bool instancing_enable
[MAX_VBS
];
1539 bool primitive_restart
;
1542 uint32_t cs_right_mask
;
1545 bool depth_test_enable
;
1546 bool writes_stencil
;
1547 bool stencil_test_enable
;
1548 bool depth_clamp_enable
;
1553 uint32_t depth_stencil_state
[3];
1559 uint32_t wm_depth_stencil
[3];
1563 uint32_t wm_depth_stencil
[4];
1566 uint32_t interface_descriptor_data
[8];
1570 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1571 gl_shader_stage stage
)
1573 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1576 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1577 static inline const struct brw_##prefix##_prog_data * \
1578 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1580 if (anv_pipeline_has_stage(pipeline, stage)) { \
1581 return (const struct brw_##prefix##_prog_data *) \
1582 pipeline->shaders[stage]->prog_data; \
1588 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1589 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
1590 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
1591 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1592 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1593 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1595 static inline const struct brw_vue_prog_data
*
1596 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
1598 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1599 return &get_gs_prog_data(pipeline
)->base
;
1600 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1601 return &get_tes_prog_data(pipeline
)->base
;
1603 return &get_vs_prog_data(pipeline
)->base
;
1607 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1608 struct anv_pipeline_cache
*cache
,
1609 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1610 const VkAllocationCallbacks
*alloc
);
1613 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1614 struct anv_pipeline_cache
*cache
,
1615 const VkComputePipelineCreateInfo
*info
,
1616 struct anv_shader_module
*module
,
1617 const char *entrypoint
,
1618 const VkSpecializationInfo
*spec_info
);
1621 enum isl_format isl_format
:16;
1622 struct isl_swizzle swizzle
;
1626 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1627 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1629 static inline enum isl_format
1630 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1631 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1633 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1636 static inline struct isl_swizzle
1637 anv_swizzle_for_render(struct isl_swizzle swizzle
)
1639 /* Sometimes the swizzle will have alpha map to one. We do this to fake
1640 * RGB as RGBA for texturing
1642 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
1643 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
1645 /* But it doesn't matter what we render to that channel */
1646 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
1652 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
1655 * Subsurface of an anv_image.
1657 struct anv_surface
{
1658 /** Valid only if isl_surf::size > 0. */
1659 struct isl_surf isl
;
1662 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1669 /* The original VkFormat provided by the client. This may not match any
1670 * of the actual surface formats.
1673 VkImageAspectFlags aspects
;
1676 uint32_t array_size
;
1677 uint32_t samples
; /**< VkImageCreateInfo::samples */
1678 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1679 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1684 /* Set when bound */
1686 VkDeviceSize offset
;
1691 * For each foo, anv_image::foo_surface is valid if and only if
1692 * anv_image::aspects has a foo aspect.
1694 * The hardware requires that the depth buffer and stencil buffer be
1695 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1696 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1697 * allocate the depth and stencil buffers as separate surfaces in the same
1701 struct anv_surface color_surface
;
1704 struct anv_surface depth_surface
;
1705 struct anv_surface stencil_surface
;
1710 * For color images, this is the aux usage for this image when not used as a
1713 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
1716 enum isl_aux_usage aux_usage
;
1718 struct anv_surface aux_surface
;
1721 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
1723 anv_can_sample_with_hiz(uint8_t gen
, uint32_t samples
)
1725 return gen
>= 8 && samples
== 1;
1729 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
1730 const struct anv_image
*image
,
1731 enum blorp_hiz_op op
);
1733 static inline uint32_t
1734 anv_get_layerCount(const struct anv_image
*image
,
1735 const VkImageSubresourceRange
*range
)
1737 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1738 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1741 static inline uint32_t
1742 anv_get_levelCount(const struct anv_image
*image
,
1743 const VkImageSubresourceRange
*range
)
1745 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1746 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1750 struct anv_image_view
{
1751 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
1753 uint32_t offset
; /**< Offset into bo. */
1755 struct isl_view isl
;
1757 VkImageAspectFlags aspect_mask
;
1759 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1761 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1762 struct anv_state sampler_surface_state
;
1765 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
1766 * for write-only and readable, using the real format for write-only and the
1767 * lowered format for readable.
1769 struct anv_state storage_surface_state
;
1770 struct anv_state writeonly_storage_surface_state
;
1772 struct brw_image_param storage_image_param
;
1775 struct anv_image_create_info
{
1776 const VkImageCreateInfo
*vk_info
;
1778 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1779 isl_tiling_flags_t isl_tiling_flags
;
1784 VkResult
anv_image_create(VkDevice _device
,
1785 const struct anv_image_create_info
*info
,
1786 const VkAllocationCallbacks
* alloc
,
1789 const struct anv_surface
*
1790 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1791 VkImageAspectFlags aspect_mask
);
1794 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
1796 static inline struct VkExtent3D
1797 anv_sanitize_image_extent(const VkImageType imageType
,
1798 const struct VkExtent3D imageExtent
)
1800 switch (imageType
) {
1801 case VK_IMAGE_TYPE_1D
:
1802 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1803 case VK_IMAGE_TYPE_2D
:
1804 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1805 case VK_IMAGE_TYPE_3D
:
1808 unreachable("invalid image type");
1812 static inline struct VkOffset3D
1813 anv_sanitize_image_offset(const VkImageType imageType
,
1814 const struct VkOffset3D imageOffset
)
1816 switch (imageType
) {
1817 case VK_IMAGE_TYPE_1D
:
1818 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1819 case VK_IMAGE_TYPE_2D
:
1820 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1821 case VK_IMAGE_TYPE_3D
:
1824 unreachable("invalid image type");
1829 void anv_fill_buffer_surface_state(struct anv_device
*device
,
1830 struct anv_state state
,
1831 enum isl_format format
,
1832 uint32_t offset
, uint32_t range
,
1835 void anv_image_view_fill_image_param(struct anv_device
*device
,
1836 struct anv_image_view
*view
,
1837 struct brw_image_param
*param
);
1838 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
1839 struct anv_buffer_view
*view
,
1840 struct brw_image_param
*param
);
1842 struct anv_sampler
{
1846 struct anv_framebuffer
{
1851 uint32_t attachment_count
;
1852 struct anv_image_view
* attachments
[0];
1855 struct anv_subpass
{
1856 uint32_t input_count
;
1857 uint32_t * input_attachments
;
1858 uint32_t color_count
;
1859 uint32_t * color_attachments
;
1860 uint32_t * resolve_attachments
;
1862 /* TODO: Consider storing the depth/stencil VkAttachmentReference
1863 * instead of its two structure members (below) individually.
1865 uint32_t depth_stencil_attachment
;
1866 VkImageLayout depth_stencil_layout
;
1868 /** Subpass has a depth/stencil self-dependency */
1869 bool has_ds_self_dep
;
1871 /** Subpass has at least one resolve attachment */
1875 enum anv_subpass_usage
{
1876 ANV_SUBPASS_USAGE_DRAW
= (1 << 0),
1877 ANV_SUBPASS_USAGE_INPUT
= (1 << 1),
1878 ANV_SUBPASS_USAGE_RESOLVE_SRC
= (1 << 2),
1879 ANV_SUBPASS_USAGE_RESOLVE_DST
= (1 << 3),
1882 struct anv_render_pass_attachment
{
1883 /* TODO: Consider using VkAttachmentDescription instead of storing each of
1884 * its members individually.
1888 VkImageUsageFlags usage
;
1889 VkAttachmentLoadOp load_op
;
1890 VkAttachmentStoreOp store_op
;
1891 VkAttachmentLoadOp stencil_load_op
;
1892 VkImageLayout initial_layout
;
1893 VkImageLayout final_layout
;
1895 /* An array, indexed by subpass id, of how the attachment will be used. */
1896 enum anv_subpass_usage
* subpass_usage
;
1898 /* The subpass id in which the attachment will be used last. */
1899 uint32_t last_subpass_idx
;
1902 struct anv_render_pass
{
1903 uint32_t attachment_count
;
1904 uint32_t subpass_count
;
1905 uint32_t * subpass_attachments
;
1906 enum anv_subpass_usage
* subpass_usages
;
1907 struct anv_render_pass_attachment
* attachments
;
1908 struct anv_subpass subpasses
[0];
1911 struct anv_query_pool_slot
{
1917 struct anv_query_pool
{
1923 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
1926 void anv_dump_image_to_ppm(struct anv_device
*device
,
1927 struct anv_image
*image
, unsigned miplevel
,
1928 unsigned array_layer
, VkImageAspectFlagBits aspect
,
1929 const char *filename
);
1931 enum anv_dump_action
{
1932 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
1935 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
1936 void anv_dump_finish(void);
1938 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
1939 struct anv_framebuffer
*fb
);
1941 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1943 static inline struct __anv_type * \
1944 __anv_type ## _from_handle(__VkType _handle) \
1946 return (struct __anv_type *) _handle; \
1949 static inline __VkType \
1950 __anv_type ## _to_handle(struct __anv_type *_obj) \
1952 return (__VkType) _obj; \
1955 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1957 static inline struct __anv_type * \
1958 __anv_type ## _from_handle(__VkType _handle) \
1960 return (struct __anv_type *)(uintptr_t) _handle; \
1963 static inline __VkType \
1964 __anv_type ## _to_handle(struct __anv_type *_obj) \
1966 return (__VkType)(uintptr_t) _obj; \
1969 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1970 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1972 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
1973 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
1974 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
1975 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
1976 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
1978 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
1979 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
1980 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
1981 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
1982 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
1983 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
1984 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
1985 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
1986 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
1987 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
1988 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
1989 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
1990 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
1991 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
1992 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
1993 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
1994 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
1995 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
1996 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
1998 /* Gen-specific function declarations */
2000 # include "anv_genX.h"
2002 # define genX(x) gen7_##x
2003 # include "anv_genX.h"
2005 # define genX(x) gen75_##x
2006 # include "anv_genX.h"
2008 # define genX(x) gen8_##x
2009 # include "anv_genX.h"
2011 # define genX(x) gen9_##x
2012 # include "anv_genX.h"
2016 #endif /* ANV_PRIVATE_H */