2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
52 /* Pre-declarations needed for WSI entrypoints */
55 typedef struct xcb_connection_t xcb_connection_t
;
56 typedef uint32_t xcb_visualid_t
;
57 typedef uint32_t xcb_window_t
;
61 #include <vulkan/vulkan.h>
62 #include <vulkan/vulkan_intel.h>
63 #include <vulkan/vk_icd.h>
65 #include "anv_entrypoints.h"
66 #include "brw_context.h"
69 #include "wsi_common.h"
75 /* Allowing different clear colors requires us to perform a depth resolve at
76 * the end of certain render passes. This is because while slow clears store
77 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
78 * See the PRMs for examples describing when additional resolves would be
79 * necessary. To enable fast clears without requiring extra resolves, we set
80 * the clear value to a globally-defined one. We could allow different values
81 * if the user doesn't expect coherent data during or after a render passes
82 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
83 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
84 * 1.0f seems to be the only value used. The only application that doesn't set
85 * this value does so through the usage of an seemingly uninitialized clear
88 #define ANV_HZ_FC_VAL 1.0f
93 #define MAX_VIEWPORTS 16
94 #define MAX_SCISSORS 16
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_DYNAMIC_BUFFERS 16
98 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
100 #define anv_noreturn __attribute__((__noreturn__))
101 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
103 static inline uint32_t
104 align_down_npot_u32(uint32_t v
, uint32_t a
)
109 static inline uint32_t
110 align_u32(uint32_t v
, uint32_t a
)
112 assert(a
!= 0 && a
== (a
& -a
));
113 return (v
+ a
- 1) & ~(a
- 1);
116 static inline uint64_t
117 align_u64(uint64_t v
, uint64_t a
)
119 assert(a
!= 0 && a
== (a
& -a
));
120 return (v
+ a
- 1) & ~(a
- 1);
123 static inline int32_t
124 align_i32(int32_t v
, int32_t a
)
126 assert(a
!= 0 && a
== (a
& -a
));
127 return (v
+ a
- 1) & ~(a
- 1);
130 /** Alignment must be a power of 2. */
132 anv_is_aligned(uintmax_t n
, uintmax_t a
)
134 assert(a
== (a
& -a
));
135 return (n
& (a
- 1)) == 0;
138 static inline uint32_t
139 anv_minify(uint32_t n
, uint32_t levels
)
141 if (unlikely(n
== 0))
144 return MAX2(n
>> levels
, 1);
148 anv_clamp_f(float f
, float min
, float max
)
161 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
163 if (*inout_mask
& clear_mask
) {
164 *inout_mask
&= ~clear_mask
;
171 static inline union isl_color_value
172 vk_to_isl_color(VkClearColorValue color
)
174 return (union isl_color_value
) {
184 #define for_each_bit(b, dword) \
185 for (uint32_t __dword = (dword); \
186 (b) = __builtin_ffs(__dword) - 1, __dword; \
187 __dword &= ~(1 << (b)))
189 #define typed_memcpy(dest, src, count) ({ \
190 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
191 memcpy((dest), (src), (count) * sizeof(*(src))); \
194 /* Whenever we generate an error, pass it through this function. Useful for
195 * debugging, where we can break on it. Only call at error site, not when
196 * propagating errors. Might be useful to plug in a stack trace here.
199 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
202 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
203 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
205 #define vk_error(error) error
206 #define vk_errorf(error, format, ...) error
209 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
210 anv_printflike(3, 4);
211 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
212 void anv_loge_v(const char *format
, va_list va
);
215 * Print a FINISHME message, including its source location.
217 #define anv_finishme(format, ...) \
219 static bool reported = false; \
221 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
226 /* A non-fatal assert. Useful for debugging. */
228 #define anv_assert(x) ({ \
229 if (unlikely(!(x))) \
230 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
233 #define anv_assert(x)
237 * If a block of code is annotated with anv_validate, then the block runs only
241 #define anv_validate if (1)
243 #define anv_validate if (0)
246 void anv_abortf(const char *format
, ...) anv_noreturn
anv_printflike(1, 2);
247 void anv_abortfv(const char *format
, va_list va
) anv_noreturn
;
249 #define stub_return(v) \
251 anv_finishme("stub %s", __func__); \
257 anv_finishme("stub %s", __func__); \
262 * A dynamically growable, circular buffer. Elements are added at head and
263 * removed from tail. head and tail are free-running uint32_t indices and we
264 * only compute the modulo with size when accessing the array. This way,
265 * number of bytes in the queue is always head - tail, even in case of
272 /* Index into the current validation list. This is used by the
273 * validation list building alrogithm to track which buffers are already
274 * in the validation list so that we can ensure uniqueness.
278 /* Last known offset. This value is provided by the kernel when we
279 * execbuf and is used as the presumed offset for the next bunch of
287 /* We need to set the WRITE flag on winsys bos so GEM will know we're
288 * writing to them and synchronize uses on other rings (eg if the display
289 * server uses the blitter ring).
295 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
297 bo
->gem_handle
= gem_handle
;
302 bo
->is_winsys_bo
= false;
305 /* Represents a lock-free linked list of "free" things. This is used by
306 * both the block pool and the state pools. Unfortunately, in order to
307 * solve the ABA problem, we can't use a single uint32_t head.
309 union anv_free_list
{
313 /* A simple count that is incremented every time the head changes. */
319 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
321 struct anv_block_state
{
331 struct anv_block_pool
{
332 struct anv_device
*device
;
336 /* The offset from the start of the bo to the "center" of the block
337 * pool. Pointers to allocated blocks are given by
338 * bo.map + center_bo_offset + offsets.
340 uint32_t center_bo_offset
;
342 /* Current memory map of the block pool. This pointer may or may not
343 * point to the actual beginning of the block pool memory. If
344 * anv_block_pool_alloc_back has ever been called, then this pointer
345 * will point to the "center" position of the buffer and all offsets
346 * (negative or positive) given out by the block pool alloc functions
347 * will be valid relative to this pointer.
349 * In particular, map == bo.map + center_offset
355 * Array of mmaps and gem handles owned by the block pool, reclaimed when
356 * the block pool is destroyed.
358 struct u_vector mmap_cleanups
;
362 union anv_free_list free_list
;
363 struct anv_block_state state
;
365 union anv_free_list back_free_list
;
366 struct anv_block_state back_state
;
369 /* Block pools are backed by a fixed-size 2GB memfd */
370 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
372 /* The center of the block pool is also the middle of the memfd. This may
373 * change in the future if we decide differently for some reason.
375 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
377 static inline uint32_t
378 anv_block_pool_size(struct anv_block_pool
*pool
)
380 return pool
->state
.end
+ pool
->back_state
.end
;
389 struct anv_fixed_size_state_pool
{
391 union anv_free_list free_list
;
392 struct anv_block_state block
;
395 #define ANV_MIN_STATE_SIZE_LOG2 6
396 #define ANV_MAX_STATE_SIZE_LOG2 17
398 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
400 struct anv_state_pool
{
401 struct anv_block_pool
*block_pool
;
402 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
405 struct anv_state_stream_block
;
407 struct anv_state_stream
{
408 struct anv_block_pool
*block_pool
;
410 /* The current working block */
411 struct anv_state_stream_block
*block
;
413 /* Offset at which the current block starts */
415 /* Offset at which to allocate the next state */
417 /* Offset at which the current block ends */
421 #define CACHELINE_SIZE 64
422 #define CACHELINE_MASK 63
425 anv_clflush_range(void *start
, size_t size
)
427 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
428 void *end
= start
+ size
;
430 __builtin_ia32_mfence();
432 __builtin_ia32_clflush(p
);
438 anv_state_clflush(struct anv_state state
)
440 anv_clflush_range(state
.map
, state
.alloc_size
);
443 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
444 struct anv_device
*device
, uint32_t block_size
);
445 void anv_block_pool_finish(struct anv_block_pool
*pool
);
446 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
);
447 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
);
448 void anv_block_pool_free(struct anv_block_pool
*pool
, int32_t offset
);
449 void anv_state_pool_init(struct anv_state_pool
*pool
,
450 struct anv_block_pool
*block_pool
);
451 void anv_state_pool_finish(struct anv_state_pool
*pool
);
452 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
453 size_t state_size
, size_t alignment
);
454 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
455 void anv_state_stream_init(struct anv_state_stream
*stream
,
456 struct anv_block_pool
*block_pool
);
457 void anv_state_stream_finish(struct anv_state_stream
*stream
);
458 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
459 uint32_t size
, uint32_t alignment
);
462 * Implements a pool of re-usable BOs. The interface is identical to that
463 * of block_pool except that each block is its own BO.
466 struct anv_device
*device
;
471 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
472 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
473 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
475 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
477 struct anv_scratch_bo
{
482 struct anv_scratch_pool
{
483 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
484 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
487 void anv_scratch_pool_init(struct anv_device
*device
,
488 struct anv_scratch_pool
*pool
);
489 void anv_scratch_pool_finish(struct anv_device
*device
,
490 struct anv_scratch_pool
*pool
);
491 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
492 struct anv_scratch_pool
*pool
,
493 gl_shader_stage stage
,
494 unsigned per_thread_scratch
);
496 extern struct anv_dispatch_table dtable
;
498 #define VK_ICD_WSI_PLATFORM_MAX 5
500 struct anv_physical_device
{
501 VK_LOADER_DATA _loader_data
;
503 struct anv_instance
* instance
;
507 struct gen_device_info info
;
508 uint64_t aperture_size
;
509 struct brw_compiler
* compiler
;
510 struct isl_device isl_dev
;
511 int cmd_parser_version
;
514 uint32_t subslice_total
;
516 uint8_t uuid
[VK_UUID_SIZE
];
518 struct wsi_device wsi_device
;
521 struct anv_instance
{
522 VK_LOADER_DATA _loader_data
;
524 VkAllocationCallbacks alloc
;
527 int physicalDeviceCount
;
528 struct anv_physical_device physicalDevice
;
531 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
532 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
535 VK_LOADER_DATA _loader_data
;
537 struct anv_device
* device
;
539 struct anv_state_pool
* pool
;
542 struct anv_pipeline_cache
{
543 struct anv_device
* device
;
544 pthread_mutex_t mutex
;
546 struct hash_table
* cache
;
549 struct anv_pipeline_bind_map
;
551 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
552 struct anv_device
*device
,
554 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
556 struct anv_shader_bin
*
557 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
558 const void *key
, uint32_t key_size
);
559 struct anv_shader_bin
*
560 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
561 const void *key_data
, uint32_t key_size
,
562 const void *kernel_data
, uint32_t kernel_size
,
563 const struct brw_stage_prog_data
*prog_data
,
564 uint32_t prog_data_size
,
565 const struct anv_pipeline_bind_map
*bind_map
);
568 VK_LOADER_DATA _loader_data
;
570 VkAllocationCallbacks alloc
;
572 struct anv_instance
* instance
;
574 struct gen_device_info info
;
575 struct isl_device isl_dev
;
578 bool can_chain_batches
;
579 bool robust_buffer_access
;
581 struct anv_bo_pool batch_bo_pool
;
583 struct anv_block_pool dynamic_state_block_pool
;
584 struct anv_state_pool dynamic_state_pool
;
586 struct anv_block_pool instruction_block_pool
;
587 struct anv_state_pool instruction_state_pool
;
589 struct anv_block_pool surface_state_block_pool
;
590 struct anv_state_pool surface_state_pool
;
592 struct anv_bo workaround_bo
;
594 struct anv_pipeline_cache blorp_shader_cache
;
595 struct blorp_context blorp
;
597 struct anv_state border_colors
;
599 struct anv_queue queue
;
601 struct anv_scratch_pool scratch_pool
;
603 uint32_t default_mocs
;
605 pthread_mutex_t mutex
;
606 pthread_cond_t queue_submit
;
609 void anv_device_init_blorp(struct anv_device
*device
);
610 void anv_device_finish_blorp(struct anv_device
*device
);
612 VkResult
anv_device_execbuf(struct anv_device
*device
,
613 struct drm_i915_gem_execbuffer2
*execbuf
,
614 struct anv_bo
**execbuf_bos
);
616 void* anv_gem_mmap(struct anv_device
*device
,
617 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
618 void anv_gem_munmap(void *p
, uint64_t size
);
619 uint32_t anv_gem_create(struct anv_device
*device
, size_t size
);
620 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
621 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
622 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
623 int anv_gem_execbuffer(struct anv_device
*device
,
624 struct drm_i915_gem_execbuffer2
*execbuf
);
625 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
626 uint32_t stride
, uint32_t tiling
);
627 int anv_gem_create_context(struct anv_device
*device
);
628 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
629 int anv_gem_get_param(int fd
, uint32_t param
);
630 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
631 int anv_gem_get_aperture(int fd
, uint64_t *size
);
632 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
633 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
634 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
635 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
636 uint32_t read_domains
, uint32_t write_domain
);
638 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
640 struct anv_reloc_list
{
643 struct drm_i915_gem_relocation_entry
* relocs
;
644 struct anv_bo
** reloc_bos
;
647 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
648 const VkAllocationCallbacks
*alloc
);
649 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
650 const VkAllocationCallbacks
*alloc
);
652 uint64_t anv_reloc_list_add(struct anv_reloc_list
*list
,
653 const VkAllocationCallbacks
*alloc
,
654 uint32_t offset
, struct anv_bo
*target_bo
,
657 struct anv_batch_bo
{
658 /* Link in the anv_cmd_buffer.owned_batch_bos list */
659 struct list_head link
;
663 /* Bytes actually consumed in this batch BO */
666 struct anv_reloc_list relocs
;
670 const VkAllocationCallbacks
* alloc
;
676 struct anv_reloc_list
* relocs
;
678 /* This callback is called (with the associated user data) in the event
679 * that the batch runs out of space.
681 VkResult (*extend_cb
)(struct anv_batch
*, void *);
685 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
686 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
687 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
688 void *location
, struct anv_bo
*bo
, uint32_t offset
);
689 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
690 struct anv_batch
*batch
);
697 static inline uint64_t
698 _anv_combine_address(struct anv_batch
*batch
, void *location
,
699 const struct anv_address address
, uint32_t delta
)
701 if (address
.bo
== NULL
) {
702 return address
.offset
+ delta
;
704 assert(batch
->start
<= location
&& location
< batch
->end
);
706 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
710 #define __gen_address_type struct anv_address
711 #define __gen_user_data struct anv_batch
712 #define __gen_combine_address _anv_combine_address
714 /* Wrapper macros needed to work around preprocessor argument issues. In
715 * particular, arguments don't get pre-evaluated if they are concatenated.
716 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
717 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
718 * We can work around this easily enough with these helpers.
720 #define __anv_cmd_length(cmd) cmd ## _length
721 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
722 #define __anv_cmd_header(cmd) cmd ## _header
723 #define __anv_cmd_pack(cmd) cmd ## _pack
724 #define __anv_reg_num(reg) reg ## _num
726 #define anv_pack_struct(dst, struc, ...) do { \
727 struct struc __template = { \
730 __anv_cmd_pack(struc)(NULL, dst, &__template); \
731 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
734 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
735 void *__dst = anv_batch_emit_dwords(batch, n); \
736 struct cmd __template = { \
737 __anv_cmd_header(cmd), \
738 .DWordLength = n - __anv_cmd_length_bias(cmd), \
741 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
745 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
749 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
750 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
751 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
752 dw[i] = (dwords0)[i] | (dwords1)[i]; \
753 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
756 #define anv_batch_emit(batch, cmd, name) \
757 for (struct cmd name = { __anv_cmd_header(cmd) }, \
758 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
759 __builtin_expect(_dst != NULL, 1); \
760 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
761 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
765 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
766 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
767 struct anv_state __state = \
768 anv_state_pool_alloc((pool), __size, align); \
769 struct cmd __template = { \
772 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
773 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
774 if (!(pool)->block_pool->device->info.has_llc) \
775 anv_state_clflush(__state); \
779 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
780 .GraphicsDataTypeGFDT = 0, \
781 .LLCCacheabilityControlLLCCC = 0, \
782 .L3CacheabilityControlL3CC = 1, \
785 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
786 .LLCeLLCCacheabilityControlLLCCC = 0, \
787 .L3CacheabilityControlL3CC = 1, \
790 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
791 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
792 .TargetCache = L3DefertoPATforLLCeLLCselection, \
796 /* Skylake: MOCS is now an index into an array of 62 different caching
797 * configurations programmed by the kernel.
800 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
801 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
802 .IndextoMOCSTables = 2 \
805 #define GEN9_MOCS_PTE { \
806 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
807 .IndextoMOCSTables = 1 \
810 struct anv_device_memory
{
813 VkDeviceSize map_size
;
818 * Header for Vertex URB Entry (VUE)
820 struct anv_vue_header
{
822 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
823 uint32_t ViewportIndex
;
827 struct anv_descriptor_set_binding_layout
{
829 /* The type of the descriptors in this binding */
830 VkDescriptorType type
;
833 /* Number of array elements in this binding */
836 /* Index into the flattend descriptor set */
837 uint16_t descriptor_index
;
839 /* Index into the dynamic state array for a dynamic buffer */
840 int16_t dynamic_offset_index
;
842 /* Index into the descriptor set buffer views */
843 int16_t buffer_index
;
846 /* Index into the binding table for the associated surface */
847 int16_t surface_index
;
849 /* Index into the sampler table for the associated sampler */
850 int16_t sampler_index
;
852 /* Index into the image table for the associated image */
854 } stage
[MESA_SHADER_STAGES
];
856 /* Immutable samplers (or NULL if no immutable samplers) */
857 struct anv_sampler
**immutable_samplers
;
860 struct anv_descriptor_set_layout
{
861 /* Number of bindings in this descriptor set */
862 uint16_t binding_count
;
864 /* Total size of the descriptor set with room for all array entries */
867 /* Shader stages affected by this descriptor set */
868 uint16_t shader_stages
;
870 /* Number of buffers in this descriptor set */
871 uint16_t buffer_count
;
873 /* Number of dynamic offsets used by this descriptor set */
874 uint16_t dynamic_offset_count
;
876 /* Bindings in this descriptor set */
877 struct anv_descriptor_set_binding_layout binding
[0];
880 struct anv_descriptor
{
881 VkDescriptorType type
;
885 struct anv_image_view
*image_view
;
886 struct anv_sampler
*sampler
;
889 struct anv_buffer_view
*buffer_view
;
893 struct anv_descriptor_set
{
894 const struct anv_descriptor_set_layout
*layout
;
896 uint32_t buffer_count
;
897 struct anv_buffer_view
*buffer_views
;
898 struct anv_descriptor descriptors
[0];
901 struct anv_descriptor_pool
{
906 struct anv_state_stream surface_state_stream
;
907 void *surface_state_free_list
;
913 anv_descriptor_set_create(struct anv_device
*device
,
914 struct anv_descriptor_pool
*pool
,
915 const struct anv_descriptor_set_layout
*layout
,
916 struct anv_descriptor_set
**out_set
);
919 anv_descriptor_set_destroy(struct anv_device
*device
,
920 struct anv_descriptor_pool
*pool
,
921 struct anv_descriptor_set
*set
);
923 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
925 struct anv_pipeline_binding
{
926 /* The descriptor set this surface corresponds to. The special value of
927 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
928 * to a color attachment and not a regular descriptor.
932 /* Binding in the descriptor set */
935 /* Index in the binding */
938 /* Input attachment index (relative to the subpass) */
939 uint8_t input_attachment_index
;
942 struct anv_pipeline_layout
{
944 struct anv_descriptor_set_layout
*layout
;
945 uint32_t dynamic_offset_start
;
951 bool has_dynamic_offsets
;
952 } stage
[MESA_SHADER_STAGES
];
954 unsigned char sha1
[20];
958 struct anv_device
* device
;
961 VkBufferUsageFlags usage
;
968 enum anv_cmd_dirty_bits
{
969 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
970 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
971 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
972 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
973 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
974 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
975 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
976 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
977 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
978 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
979 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
980 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
981 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
983 typedef uint32_t anv_cmd_dirty_mask_t
;
986 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
987 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
988 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
989 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
990 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
991 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
992 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
993 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
994 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
995 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
996 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
998 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
999 * a flush has happened but not a CS stall. The next time we do any sort
1000 * of invalidation we need to insert a CS stall at that time. Otherwise,
1001 * we would have to CS stall on every flush which could be bad.
1003 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1006 #define ANV_PIPE_FLUSH_BITS ( \
1007 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1008 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1009 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1011 #define ANV_PIPE_STALL_BITS ( \
1012 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1013 ANV_PIPE_DEPTH_STALL_BIT | \
1014 ANV_PIPE_CS_STALL_BIT)
1016 #define ANV_PIPE_INVALIDATE_BITS ( \
1017 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1018 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1019 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1020 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1021 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1022 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1024 struct anv_vertex_binding
{
1025 struct anv_buffer
* buffer
;
1026 VkDeviceSize offset
;
1029 struct anv_push_constants
{
1030 /* Current allocated size of this push constants data structure.
1031 * Because a decent chunk of it may not be used (images on SKL, for
1032 * instance), we won't actually allocate the entire structure up-front.
1036 /* Push constant data provided by the client through vkPushConstants */
1037 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1039 /* Our hardware only provides zero-based vertex and instance id so, in
1040 * order to satisfy the vulkan requirements, we may have to push one or
1041 * both of these into the shader.
1043 uint32_t base_vertex
;
1044 uint32_t base_instance
;
1046 /* Offsets and ranges for dynamically bound buffers */
1050 } dynamic
[MAX_DYNAMIC_BUFFERS
];
1052 /* Image data for image_load_store on pre-SKL */
1053 struct brw_image_param images
[MAX_IMAGES
];
1056 struct anv_dynamic_state
{
1059 VkViewport viewports
[MAX_VIEWPORTS
];
1064 VkRect2D scissors
[MAX_SCISSORS
];
1075 float blend_constants
[4];
1085 } stencil_compare_mask
;
1090 } stencil_write_mask
;
1095 } stencil_reference
;
1098 extern const struct anv_dynamic_state default_dynamic_state
;
1100 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1101 const struct anv_dynamic_state
*src
,
1102 uint32_t copy_mask
);
1105 * Attachment state when recording a renderpass instance.
1107 * The clear value is valid only if there exists a pending clear.
1109 struct anv_attachment_state
{
1110 enum isl_aux_usage aux_usage
;
1111 enum isl_aux_usage input_aux_usage
;
1112 struct anv_state color_rt_state
;
1113 struct anv_state input_att_state
;
1115 VkImageLayout current_layout
;
1116 VkImageAspectFlags pending_clear_aspects
;
1118 VkClearValue clear_value
;
1119 bool clear_color_is_zero_one
;
1122 /** State required while building cmd buffer */
1123 struct anv_cmd_state
{
1124 /* PIPELINE_SELECT.PipelineSelection */
1125 uint32_t current_pipeline
;
1126 const struct gen_l3_config
* current_l3_config
;
1128 anv_cmd_dirty_mask_t dirty
;
1129 anv_cmd_dirty_mask_t compute_dirty
;
1130 enum anv_pipe_bits pending_pipe_bits
;
1131 uint32_t num_workgroups_offset
;
1132 struct anv_bo
*num_workgroups_bo
;
1133 VkShaderStageFlags descriptors_dirty
;
1134 VkShaderStageFlags push_constants_dirty
;
1135 uint32_t scratch_size
;
1136 struct anv_pipeline
* pipeline
;
1137 struct anv_pipeline
* compute_pipeline
;
1138 struct anv_framebuffer
* framebuffer
;
1139 struct anv_render_pass
* pass
;
1140 struct anv_subpass
* subpass
;
1141 VkRect2D render_area
;
1142 uint32_t restart_index
;
1143 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1144 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1145 VkShaderStageFlags push_constant_stages
;
1146 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1147 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1148 struct anv_state samplers
[MESA_SHADER_STAGES
];
1149 struct anv_dynamic_state dynamic
;
1153 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1154 * valid only when recording a render pass instance.
1156 struct anv_attachment_state
* attachments
;
1159 * Surface states for color render targets. These are stored in a single
1160 * flat array. For depth-stencil attachments, the surface state is simply
1163 struct anv_state render_pass_states
;
1166 * A null surface state of the right size to match the framebuffer. This
1167 * is one of the states in render_pass_states.
1169 struct anv_state null_surface_state
;
1172 struct anv_buffer
* index_buffer
;
1173 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1174 uint32_t index_offset
;
1178 struct anv_cmd_pool
{
1179 VkAllocationCallbacks alloc
;
1180 struct list_head cmd_buffers
;
1183 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1185 enum anv_cmd_buffer_exec_mode
{
1186 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1187 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1188 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1189 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1190 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1193 struct anv_cmd_buffer
{
1194 VK_LOADER_DATA _loader_data
;
1196 struct anv_device
* device
;
1198 struct anv_cmd_pool
* pool
;
1199 struct list_head pool_link
;
1201 struct anv_batch batch
;
1203 /* Fields required for the actual chain of anv_batch_bo's.
1205 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1207 struct list_head batch_bos
;
1208 enum anv_cmd_buffer_exec_mode exec_mode
;
1210 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1211 * referenced by this command buffer
1213 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1215 struct u_vector seen_bbos
;
1217 /* A vector of int32_t's for every block of binding tables.
1219 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1221 struct u_vector bt_blocks
;
1224 struct anv_reloc_list surface_relocs
;
1225 /** Last seen surface state block pool center bo offset */
1226 uint32_t last_ss_pool_center
;
1228 /* Serial for tracking buffer completion */
1231 /* Stream objects for storing temporary data */
1232 struct anv_state_stream surface_state_stream
;
1233 struct anv_state_stream dynamic_state_stream
;
1235 VkCommandBufferUsageFlags usage_flags
;
1236 VkCommandBufferLevel level
;
1238 struct anv_cmd_state state
;
1241 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1242 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1243 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1244 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1245 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1246 struct anv_cmd_buffer
*secondary
);
1247 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1248 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1249 struct anv_cmd_buffer
*cmd_buffer
);
1251 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1254 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1255 gl_shader_stage stage
, uint32_t size
);
1256 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1257 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1258 (offsetof(struct anv_push_constants, field) + \
1259 sizeof(cmd_buffer->state.push_constants[0]->field)))
1261 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1262 const void *data
, uint32_t size
, uint32_t alignment
);
1263 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1264 uint32_t *a
, uint32_t *b
,
1265 uint32_t dwords
, uint32_t alignment
);
1268 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1270 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1271 uint32_t entries
, uint32_t *state_offset
);
1273 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1275 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1276 uint32_t size
, uint32_t alignment
);
1279 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1281 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1282 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1283 bool depth_clamp_enable
);
1284 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1286 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1287 struct anv_render_pass
*pass
,
1288 struct anv_framebuffer
*framebuffer
,
1289 const VkClearValue
*clear_values
);
1291 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1294 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1295 gl_shader_stage stage
);
1297 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1299 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1300 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1302 const struct anv_image_view
*
1303 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1306 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1307 uint32_t num_entries
,
1308 uint32_t *state_offset
);
1310 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1312 enum anv_fence_state
{
1313 /** Indicates that this is a new (or newly reset fence) */
1314 ANV_FENCE_STATE_RESET
,
1316 /** Indicates that this fence has been submitted to the GPU but is still
1317 * (as far as we know) in use by the GPU.
1319 ANV_FENCE_STATE_SUBMITTED
,
1321 ANV_FENCE_STATE_SIGNALED
,
1326 struct drm_i915_gem_execbuffer2 execbuf
;
1327 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1328 enum anv_fence_state state
;
1333 struct anv_state state
;
1336 struct anv_shader_module
{
1337 unsigned char sha1
[20];
1342 void anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
1343 struct anv_shader_module
*module
,
1344 const char *entrypoint
,
1345 const struct anv_pipeline_layout
*pipeline_layout
,
1346 const VkSpecializationInfo
*spec_info
);
1348 static inline gl_shader_stage
1349 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1351 assert(__builtin_popcount(vk_stage
) == 1);
1352 return ffs(vk_stage
) - 1;
1355 static inline VkShaderStageFlagBits
1356 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1358 return (1 << mesa_stage
);
1361 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1363 #define anv_foreach_stage(stage, stage_bits) \
1364 for (gl_shader_stage stage, \
1365 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1366 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1367 __tmp &= ~(1 << (stage)))
1369 struct anv_pipeline_bind_map
{
1370 uint32_t surface_count
;
1371 uint32_t sampler_count
;
1372 uint32_t image_count
;
1374 struct anv_pipeline_binding
* surface_to_descriptor
;
1375 struct anv_pipeline_binding
* sampler_to_descriptor
;
1378 struct anv_shader_bin_key
{
1383 struct anv_shader_bin
{
1386 const struct anv_shader_bin_key
*key
;
1388 struct anv_state kernel
;
1389 uint32_t kernel_size
;
1391 const struct brw_stage_prog_data
*prog_data
;
1392 uint32_t prog_data_size
;
1394 struct anv_pipeline_bind_map bind_map
;
1396 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1399 struct anv_shader_bin
*
1400 anv_shader_bin_create(struct anv_device
*device
,
1401 const void *key
, uint32_t key_size
,
1402 const void *kernel
, uint32_t kernel_size
,
1403 const struct brw_stage_prog_data
*prog_data
,
1404 uint32_t prog_data_size
, const void *prog_data_param
,
1405 const struct anv_pipeline_bind_map
*bind_map
);
1408 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1411 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1413 assert(shader
->ref_cnt
>= 1);
1414 __sync_fetch_and_add(&shader
->ref_cnt
, 1);
1418 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1420 assert(shader
->ref_cnt
>= 1);
1421 if (__sync_fetch_and_add(&shader
->ref_cnt
, -1) == 1)
1422 anv_shader_bin_destroy(device
, shader
);
1425 struct anv_pipeline
{
1426 struct anv_device
* device
;
1427 struct anv_batch batch
;
1428 uint32_t batch_data
[512];
1429 struct anv_reloc_list batch_relocs
;
1430 uint32_t dynamic_state_mask
;
1431 struct anv_dynamic_state dynamic_state
;
1433 struct anv_pipeline_layout
* layout
;
1435 bool needs_data_cache
;
1437 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1440 const struct gen_l3_config
* l3_config
;
1441 uint32_t total_size
;
1444 VkShaderStageFlags active_stages
;
1445 struct anv_state blend_state
;
1448 uint32_t binding_stride
[MAX_VBS
];
1449 bool instancing_enable
[MAX_VBS
];
1450 bool primitive_restart
;
1453 uint32_t cs_right_mask
;
1455 bool depth_clamp_enable
;
1459 uint32_t depth_stencil_state
[3];
1465 uint32_t wm_depth_stencil
[3];
1469 uint32_t wm_depth_stencil
[4];
1472 uint32_t interface_descriptor_data
[8];
1476 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1477 gl_shader_stage stage
)
1479 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1482 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1483 static inline const struct brw_##prefix##_prog_data * \
1484 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1486 if (anv_pipeline_has_stage(pipeline, stage)) { \
1487 return (const struct brw_##prefix##_prog_data *) \
1488 pipeline->shaders[stage]->prog_data; \
1494 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1495 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
1496 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
1497 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1498 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1499 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1501 static inline const struct brw_vue_map
*
1502 anv_pipeline_get_fs_input_map(const struct anv_pipeline
*pipeline
)
1504 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1505 return &get_gs_prog_data(pipeline
)->base
.vue_map
;
1506 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1507 return &get_tes_prog_data(pipeline
)->base
.vue_map
;
1509 return &get_vs_prog_data(pipeline
)->base
.vue_map
;
1513 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1514 struct anv_pipeline_cache
*cache
,
1515 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1516 const VkAllocationCallbacks
*alloc
);
1519 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1520 struct anv_pipeline_cache
*cache
,
1521 const VkComputePipelineCreateInfo
*info
,
1522 struct anv_shader_module
*module
,
1523 const char *entrypoint
,
1524 const VkSpecializationInfo
*spec_info
);
1527 enum isl_format isl_format
:16;
1528 struct isl_swizzle swizzle
;
1532 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1533 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1535 static inline enum isl_format
1536 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1537 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1539 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1543 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
1546 * Subsurface of an anv_image.
1548 struct anv_surface
{
1549 /** Valid only if isl_surf::size > 0. */
1550 struct isl_surf isl
;
1553 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1560 /* The original VkFormat provided by the client. This may not match any
1561 * of the actual surface formats.
1564 VkImageAspectFlags aspects
;
1567 uint32_t array_size
;
1568 uint32_t samples
; /**< VkImageCreateInfo::samples */
1569 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1570 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1575 /* Set when bound */
1577 VkDeviceSize offset
;
1582 * For each foo, anv_image::foo_surface is valid if and only if
1583 * anv_image::aspects has a foo aspect.
1585 * The hardware requires that the depth buffer and stencil buffer be
1586 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1587 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1588 * allocate the depth and stencil buffers as separate surfaces in the same
1592 struct anv_surface color_surface
;
1595 struct anv_surface depth_surface
;
1596 struct anv_surface stencil_surface
;
1601 * For color images, this is the aux usage for this image when not used as a
1604 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
1607 enum isl_aux_usage aux_usage
;
1609 struct anv_surface aux_surface
;
1613 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
1614 const struct anv_image
*image
,
1615 enum blorp_hiz_op op
);
1617 static inline uint32_t
1618 anv_get_layerCount(const struct anv_image
*image
,
1619 const VkImageSubresourceRange
*range
)
1621 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1622 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1625 static inline uint32_t
1626 anv_get_levelCount(const struct anv_image
*image
,
1627 const VkImageSubresourceRange
*range
)
1629 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1630 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1634 struct anv_image_view
{
1635 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
1637 uint32_t offset
; /**< Offset into bo. */
1639 struct isl_view isl
;
1641 VkImageAspectFlags aspect_mask
;
1643 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1645 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1646 struct anv_state sampler_surface_state
;
1648 /** RENDER_SURFACE_STATE when using image as a storage image. */
1649 struct anv_state storage_surface_state
;
1651 struct brw_image_param storage_image_param
;
1654 struct anv_image_create_info
{
1655 const VkImageCreateInfo
*vk_info
;
1657 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1658 isl_tiling_flags_t isl_tiling_flags
;
1663 VkResult
anv_image_create(VkDevice _device
,
1664 const struct anv_image_create_info
*info
,
1665 const VkAllocationCallbacks
* alloc
,
1668 const struct anv_surface
*
1669 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1670 VkImageAspectFlags aspect_mask
);
1672 struct anv_buffer_view
{
1673 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1675 uint32_t offset
; /**< Offset into bo. */
1676 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1678 struct anv_state surface_state
;
1679 struct anv_state storage_surface_state
;
1681 struct brw_image_param storage_image_param
;
1685 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
1687 static inline struct VkExtent3D
1688 anv_sanitize_image_extent(const VkImageType imageType
,
1689 const struct VkExtent3D imageExtent
)
1691 switch (imageType
) {
1692 case VK_IMAGE_TYPE_1D
:
1693 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1694 case VK_IMAGE_TYPE_2D
:
1695 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1696 case VK_IMAGE_TYPE_3D
:
1699 unreachable("invalid image type");
1703 static inline struct VkOffset3D
1704 anv_sanitize_image_offset(const VkImageType imageType
,
1705 const struct VkOffset3D imageOffset
)
1707 switch (imageType
) {
1708 case VK_IMAGE_TYPE_1D
:
1709 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1710 case VK_IMAGE_TYPE_2D
:
1711 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1712 case VK_IMAGE_TYPE_3D
:
1715 unreachable("invalid image type");
1720 void anv_fill_buffer_surface_state(struct anv_device
*device
,
1721 struct anv_state state
,
1722 enum isl_format format
,
1723 uint32_t offset
, uint32_t range
,
1726 void anv_image_view_fill_image_param(struct anv_device
*device
,
1727 struct anv_image_view
*view
,
1728 struct brw_image_param
*param
);
1729 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
1730 struct anv_buffer_view
*view
,
1731 struct brw_image_param
*param
);
1733 struct anv_sampler
{
1737 struct anv_framebuffer
{
1742 uint32_t attachment_count
;
1743 struct anv_image_view
* attachments
[0];
1746 struct anv_subpass
{
1747 uint32_t input_count
;
1748 uint32_t * input_attachments
;
1749 uint32_t color_count
;
1750 uint32_t * color_attachments
;
1751 uint32_t * resolve_attachments
;
1753 /* TODO: Consider storing the depth/stencil VkAttachmentReference
1754 * instead of its two structure members (below) individually.
1756 uint32_t depth_stencil_attachment
;
1757 VkImageLayout depth_stencil_layout
;
1759 /** Subpass has a depth/stencil self-dependency */
1760 bool has_ds_self_dep
;
1762 /** Subpass has at least one resolve attachment */
1766 enum anv_subpass_usage
{
1767 ANV_SUBPASS_USAGE_DRAW
= (1 << 0),
1768 ANV_SUBPASS_USAGE_INPUT
= (1 << 1),
1769 ANV_SUBPASS_USAGE_RESOLVE_SRC
= (1 << 2),
1770 ANV_SUBPASS_USAGE_RESOLVE_DST
= (1 << 3),
1773 struct anv_render_pass_attachment
{
1774 /* TODO: Consider using VkAttachmentDescription instead of storing each of
1775 * its members individually.
1779 VkImageUsageFlags usage
;
1780 VkAttachmentLoadOp load_op
;
1781 VkAttachmentStoreOp store_op
;
1782 VkAttachmentLoadOp stencil_load_op
;
1783 VkImageLayout initial_layout
;
1784 VkImageLayout final_layout
;
1786 /* An array, indexed by subpass id, of how the attachment will be used. */
1787 enum anv_subpass_usage
* subpass_usage
;
1789 /* The subpass id in which the attachment will be used last. */
1790 uint32_t last_subpass_idx
;
1793 struct anv_render_pass
{
1794 uint32_t attachment_count
;
1795 uint32_t subpass_count
;
1796 uint32_t * subpass_attachments
;
1797 enum anv_subpass_usage
* subpass_usages
;
1798 struct anv_render_pass_attachment
* attachments
;
1799 struct anv_subpass subpasses
[0];
1802 struct anv_query_pool_slot
{
1808 struct anv_query_pool
{
1814 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
1817 void anv_dump_image_to_ppm(struct anv_device
*device
,
1818 struct anv_image
*image
, unsigned miplevel
,
1819 unsigned array_layer
, VkImageAspectFlagBits aspect
,
1820 const char *filename
);
1822 enum anv_dump_action
{
1823 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
1826 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
1827 void anv_dump_finish(void);
1829 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
1830 struct anv_framebuffer
*fb
);
1832 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1834 static inline struct __anv_type * \
1835 __anv_type ## _from_handle(__VkType _handle) \
1837 return (struct __anv_type *) _handle; \
1840 static inline __VkType \
1841 __anv_type ## _to_handle(struct __anv_type *_obj) \
1843 return (__VkType) _obj; \
1846 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1848 static inline struct __anv_type * \
1849 __anv_type ## _from_handle(__VkType _handle) \
1851 return (struct __anv_type *)(uintptr_t) _handle; \
1854 static inline __VkType \
1855 __anv_type ## _to_handle(struct __anv_type *_obj) \
1857 return (__VkType)(uintptr_t) _obj; \
1860 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1861 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1863 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
1864 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
1865 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
1866 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
1867 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
1869 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
1870 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
1871 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
1872 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
1873 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
1874 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
1875 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
1876 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
1877 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
1878 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
1879 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
1880 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
1881 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
1882 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
1883 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
1884 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
1885 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
1886 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
1887 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
1889 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1891 static inline const __VkType * \
1892 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1894 return (const __VkType *) __anv_obj; \
1897 /* Gen-specific function declarations */
1899 # include "anv_genX.h"
1901 # define genX(x) gen7_##x
1902 # include "anv_genX.h"
1904 # define genX(x) gen75_##x
1905 # include "anv_genX.h"
1907 # define genX(x) gen8_##x
1908 # include "anv_genX.h"
1910 # define genX(x) gen9_##x
1911 # include "anv_genX.h"
1919 #endif /* ANV_PRIVATE_H */