2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/macros.h"
53 #include "util/hash_table.h"
54 #include "util/list.h"
56 #include "util/u_atomic.h"
57 #include "util/u_vector.h"
58 #include "util/u_math.h"
60 #include "util/xmlconfig.h"
62 #include "vk_debug_report.h"
64 /* Pre-declarations needed for WSI entrypoints */
67 typedef struct xcb_connection_t xcb_connection_t
;
68 typedef uint32_t xcb_visualid_t
;
69 typedef uint32_t xcb_window_t
;
72 struct anv_buffer_view
;
73 struct anv_image_view
;
78 #include <vulkan/vulkan.h>
79 #include <vulkan/vulkan_intel.h>
80 #include <vulkan/vk_icd.h>
82 #include "anv_android.h"
83 #include "anv_entrypoints.h"
84 #include "anv_extensions.h"
87 #include "dev/gen_debug.h"
88 #include "common/intel_log.h"
89 #include "wsi_common.h"
91 /* anv Virtual Memory Layout
92 * =========================
94 * When the anv driver is determining the virtual graphics addresses of memory
95 * objects itself using the softpin mechanism, the following memory ranges
98 * Three special considerations to notice:
100 * (1) the dynamic state pool is located within the same 4 GiB as the low
101 * heap. This is to work around a VF cache issue described in a comment in
102 * anv_physical_device_init_heaps.
104 * (2) the binding table pool is located at lower addresses than the surface
105 * state pool, within a 4 GiB range. This allows surface state base addresses
106 * to cover both binding tables (16 bit offsets) and surface states (32 bit
109 * (3) the last 4 GiB of the address space is withheld from the high
110 * heap. Various hardware units will read past the end of an object for
111 * various reasons. This healthy margin prevents reads from wrapping around
114 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
115 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
116 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
117 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
118 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
119 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
120 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
121 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
122 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
123 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
124 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
126 #define LOW_HEAP_SIZE \
127 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
128 #define DYNAMIC_STATE_POOL_SIZE \
129 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
130 #define BINDING_TABLE_POOL_SIZE \
131 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
132 #define SURFACE_STATE_POOL_SIZE \
133 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
134 #define INSTRUCTION_STATE_POOL_SIZE \
135 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
137 /* Allowing different clear colors requires us to perform a depth resolve at
138 * the end of certain render passes. This is because while slow clears store
139 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
140 * See the PRMs for examples describing when additional resolves would be
141 * necessary. To enable fast clears without requiring extra resolves, we set
142 * the clear value to a globally-defined one. We could allow different values
143 * if the user doesn't expect coherent data during or after a render passes
144 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
145 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
146 * 1.0f seems to be the only value used. The only application that doesn't set
147 * this value does so through the usage of an seemingly uninitialized clear
150 #define ANV_HZ_FC_VAL 1.0f
153 #define MAX_XFB_BUFFERS 4
154 #define MAX_XFB_STREAMS 4
157 #define MAX_VIEWPORTS 16
158 #define MAX_SCISSORS 16
159 #define MAX_PUSH_CONSTANTS_SIZE 128
160 #define MAX_DYNAMIC_BUFFERS 16
161 #define MAX_IMAGES 64
162 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
163 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
164 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
166 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
168 * "The surface state model is used when a Binding Table Index (specified
169 * in the message descriptor) of less than 240 is specified. In this model,
170 * the Binding Table Index is used to index into the binding table, and the
171 * binding table entry contains a pointer to the SURFACE_STATE."
173 * Binding table values above 240 are used for various things in the hardware
174 * such as stateless, stateless with incoherent cache, SLM, and bindless.
176 #define MAX_BINDING_TABLE_SIZE 240
178 /* The kernel relocation API has a limitation of a 32-bit delta value
179 * applied to the address before it is written which, in spite of it being
180 * unsigned, is treated as signed . Because of the way that this maps to
181 * the Vulkan API, we cannot handle an offset into a buffer that does not
182 * fit into a signed 32 bits. The only mechanism we have for dealing with
183 * this at the moment is to limit all VkDeviceMemory objects to a maximum
184 * of 2GB each. The Vulkan spec allows us to do this:
186 * "Some platforms may have a limit on the maximum size of a single
187 * allocation. For example, certain systems may fail to create
188 * allocations with a size greater than or equal to 4GB. Such a limit is
189 * implementation-dependent, and if such a failure occurs then the error
190 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
192 * We don't use vk_error here because it's not an error so much as an
193 * indication to the application that the allocation is too large.
195 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
197 #define ANV_SVGS_VB_INDEX MAX_VBS
198 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
200 /* We reserve this MI ALU register for the purpose of handling predication.
201 * Other code which uses the MI ALU should leave it alone.
203 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
205 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
207 static inline uint32_t
208 align_down_npot_u32(uint32_t v
, uint32_t a
)
213 static inline uint32_t
214 align_u32(uint32_t v
, uint32_t a
)
216 assert(a
!= 0 && a
== (a
& -a
));
217 return (v
+ a
- 1) & ~(a
- 1);
220 static inline uint64_t
221 align_u64(uint64_t v
, uint64_t a
)
223 assert(a
!= 0 && a
== (a
& -a
));
224 return (v
+ a
- 1) & ~(a
- 1);
227 static inline int32_t
228 align_i32(int32_t v
, int32_t a
)
230 assert(a
!= 0 && a
== (a
& -a
));
231 return (v
+ a
- 1) & ~(a
- 1);
234 /** Alignment must be a power of 2. */
236 anv_is_aligned(uintmax_t n
, uintmax_t a
)
238 assert(a
== (a
& -a
));
239 return (n
& (a
- 1)) == 0;
242 static inline uint32_t
243 anv_minify(uint32_t n
, uint32_t levels
)
245 if (unlikely(n
== 0))
248 return MAX2(n
>> levels
, 1);
252 anv_clamp_f(float f
, float min
, float max
)
265 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
267 if (*inout_mask
& clear_mask
) {
268 *inout_mask
&= ~clear_mask
;
275 static inline union isl_color_value
276 vk_to_isl_color(VkClearColorValue color
)
278 return (union isl_color_value
) {
288 #define for_each_bit(b, dword) \
289 for (uint32_t __dword = (dword); \
290 (b) = __builtin_ffs(__dword) - 1, __dword; \
291 __dword &= ~(1 << (b)))
293 #define typed_memcpy(dest, src, count) ({ \
294 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
295 memcpy((dest), (src), (count) * sizeof(*(src))); \
298 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
299 * to be added here in order to utilize mapping in debug/error/perf macros.
301 #define REPORT_OBJECT_TYPE(o) \
302 __builtin_choose_expr ( \
303 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
304 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
305 __builtin_choose_expr ( \
306 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
307 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
308 __builtin_choose_expr ( \
309 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
310 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
311 __builtin_choose_expr ( \
312 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
313 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
314 __builtin_choose_expr ( \
315 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
316 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
317 __builtin_choose_expr ( \
318 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
319 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
320 __builtin_choose_expr ( \
321 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
322 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
323 __builtin_choose_expr ( \
324 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
325 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
326 __builtin_choose_expr ( \
327 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
328 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
329 __builtin_choose_expr ( \
330 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
331 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
332 __builtin_choose_expr ( \
333 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
334 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
335 __builtin_choose_expr ( \
336 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
337 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
338 __builtin_choose_expr ( \
339 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
340 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), void*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
395 /* The void expression results in a compile-time error \
396 when assigning the result to something. */ \
397 (void)0)))))))))))))))))))))))))))))))
399 /* Whenever we generate an error, pass it through this function. Useful for
400 * debugging, where we can break on it. Only call at error site, not when
401 * propagating errors. Might be useful to plug in a stack trace here.
404 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
405 VkDebugReportObjectTypeEXT type
, VkResult error
,
406 const char *file
, int line
, const char *format
,
409 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
410 VkDebugReportObjectTypeEXT type
, VkResult error
,
411 const char *file
, int line
, const char *format
, ...);
414 #define vk_error(error) __vk_errorf(NULL, NULL,\
415 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
416 error, __FILE__, __LINE__, NULL)
417 #define vk_errorv(instance, obj, error, format, args)\
418 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
419 __FILE__, __LINE__, format, args)
420 #define vk_errorf(instance, obj, error, format, ...)\
421 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
422 __FILE__, __LINE__, format, ## __VA_ARGS__)
424 #define vk_error(error) error
425 #define vk_errorf(instance, obj, error, format, ...) error
429 * Warn on ignored extension structs.
431 * The Vulkan spec requires us to ignore unsupported or unknown structs in
432 * a pNext chain. In debug mode, emitting warnings for ignored structs may
433 * help us discover structs that we should not have ignored.
436 * From the Vulkan 1.0.38 spec:
438 * Any component of the implementation (the loader, any enabled layers,
439 * and drivers) must skip over, without processing (other than reading the
440 * sType and pNext members) any chained structures with sType values not
441 * defined by extensions supported by that component.
443 #define anv_debug_ignored_stype(sType) \
444 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
446 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
447 VkDebugReportObjectTypeEXT type
, const char *file
,
448 int line
, const char *format
, ...)
449 anv_printflike(6, 7);
450 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
451 void anv_loge_v(const char *format
, va_list va
);
454 * Print a FINISHME message, including its source location.
456 #define anv_finishme(format, ...) \
458 static bool reported = false; \
460 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
467 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
469 #define anv_perf_warn(instance, obj, format, ...) \
471 static bool reported = false; \
472 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
473 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
474 format, ##__VA_ARGS__); \
479 /* A non-fatal assert. Useful for debugging. */
481 #define anv_assert(x) ({ \
482 if (unlikely(!(x))) \
483 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
486 #define anv_assert(x)
489 /* A multi-pointer allocator
491 * When copying data structures from the user (such as a render pass), it's
492 * common to need to allocate data for a bunch of different things. Instead
493 * of doing several allocations and having to handle all of the error checking
494 * that entails, it can be easier to do a single allocation. This struct
495 * helps facilitate that. The intended usage looks like this:
498 * anv_multialloc_add(&ma, &main_ptr, 1);
499 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
500 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
502 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
503 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
505 struct anv_multialloc
{
513 #define ANV_MULTIALLOC_INIT \
514 ((struct anv_multialloc) { 0, })
516 #define ANV_MULTIALLOC(_name) \
517 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
519 __attribute__((always_inline
))
521 _anv_multialloc_add(struct anv_multialloc
*ma
,
522 void **ptr
, size_t size
, size_t align
)
524 size_t offset
= align_u64(ma
->size
, align
);
525 ma
->size
= offset
+ size
;
526 ma
->align
= MAX2(ma
->align
, align
);
528 /* Store the offset in the pointer. */
529 *ptr
= (void *)(uintptr_t)offset
;
531 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
532 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
535 #define anv_multialloc_add_size(_ma, _ptr, _size) \
536 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
538 #define anv_multialloc_add(_ma, _ptr, _count) \
539 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
541 __attribute__((always_inline
))
543 anv_multialloc_alloc(struct anv_multialloc
*ma
,
544 const VkAllocationCallbacks
*alloc
,
545 VkSystemAllocationScope scope
)
547 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
551 /* Fill out each of the pointers with their final value.
553 * for (uint32_t i = 0; i < ma->ptr_count; i++)
554 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
556 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
557 * constant, GCC is incapable of figuring this out and unrolling the loop
558 * so we have to give it a little help.
560 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
561 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
562 if ((_i) < ma->ptr_count) \
563 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
564 _ANV_MULTIALLOC_UPDATE_POINTER(0);
565 _ANV_MULTIALLOC_UPDATE_POINTER(1);
566 _ANV_MULTIALLOC_UPDATE_POINTER(2);
567 _ANV_MULTIALLOC_UPDATE_POINTER(3);
568 _ANV_MULTIALLOC_UPDATE_POINTER(4);
569 _ANV_MULTIALLOC_UPDATE_POINTER(5);
570 _ANV_MULTIALLOC_UPDATE_POINTER(6);
571 _ANV_MULTIALLOC_UPDATE_POINTER(7);
572 #undef _ANV_MULTIALLOC_UPDATE_POINTER
577 __attribute__((always_inline
))
579 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
580 const VkAllocationCallbacks
*parent_alloc
,
581 const VkAllocationCallbacks
*alloc
,
582 VkSystemAllocationScope scope
)
584 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
587 /* Extra ANV-defined BO flags which won't be passed to the kernel */
588 #define ANV_BO_EXTERNAL (1ull << 31)
589 #define ANV_BO_FLAG_MASK (1ull << 31)
594 /* Index into the current validation list. This is used by the
595 * validation list building alrogithm to track which buffers are already
596 * in the validation list so that we can ensure uniqueness.
600 /* Last known offset. This value is provided by the kernel when we
601 * execbuf and is used as the presumed offset for the next bunch of
609 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
614 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
616 bo
->gem_handle
= gem_handle
;
624 /* Represents a lock-free linked list of "free" things. This is used by
625 * both the block pool and the state pools. Unfortunately, in order to
626 * solve the ABA problem, we can't use a single uint32_t head.
628 union anv_free_list
{
632 /* A simple count that is incremented every time the head changes. */
635 /* Make sure it's aligned to 64 bits. This will make atomic operations
636 * faster on 32 bit platforms.
638 uint64_t u64
__attribute__ ((aligned (8)));
641 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
643 struct anv_block_state
{
649 /* Make sure it's aligned to 64 bits. This will make atomic operations
650 * faster on 32 bit platforms.
652 uint64_t u64
__attribute__ ((aligned (8)));
656 #define anv_block_pool_foreach_bo(bo, pool) \
657 for (bo = (pool)->bos; bo != &(pool)->bos[(pool)->nbos]; bo++)
659 #define ANV_MAX_BLOCK_POOL_BOS 20
661 struct anv_block_pool
{
662 struct anv_device
*device
;
666 struct anv_bo bos
[ANV_MAX_BLOCK_POOL_BOS
];
672 /* The address where the start of the pool is pinned. The various bos that
673 * are created as the pool grows will have addresses in the range
674 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
676 uint64_t start_address
;
678 /* The offset from the start of the bo to the "center" of the block
679 * pool. Pointers to allocated blocks are given by
680 * bo.map + center_bo_offset + offsets.
682 uint32_t center_bo_offset
;
684 /* Current memory map of the block pool. This pointer may or may not
685 * point to the actual beginning of the block pool memory. If
686 * anv_block_pool_alloc_back has ever been called, then this pointer
687 * will point to the "center" position of the buffer and all offsets
688 * (negative or positive) given out by the block pool alloc functions
689 * will be valid relative to this pointer.
691 * In particular, map == bo.map + center_offset
693 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
694 * since it will handle the softpin case as well, where this points to NULL.
700 * Array of mmaps and gem handles owned by the block pool, reclaimed when
701 * the block pool is destroyed.
703 struct u_vector mmap_cleanups
;
705 struct anv_block_state state
;
707 struct anv_block_state back_state
;
710 /* Block pools are backed by a fixed-size 1GB memfd */
711 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
713 /* The center of the block pool is also the middle of the memfd. This may
714 * change in the future if we decide differently for some reason.
716 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
718 static inline uint32_t
719 anv_block_pool_size(struct anv_block_pool
*pool
)
721 return pool
->state
.end
+ pool
->back_state
.end
;
731 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
733 struct anv_fixed_size_state_pool
{
734 union anv_free_list free_list
;
735 struct anv_block_state block
;
738 #define ANV_MIN_STATE_SIZE_LOG2 6
739 #define ANV_MAX_STATE_SIZE_LOG2 21
741 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
743 struct anv_free_entry
{
745 struct anv_state state
;
748 struct anv_state_table
{
749 struct anv_device
*device
;
751 struct anv_free_entry
*map
;
753 struct anv_block_state state
;
754 struct u_vector cleanups
;
757 struct anv_state_pool
{
758 struct anv_block_pool block_pool
;
760 struct anv_state_table table
;
762 /* The size of blocks which will be allocated from the block pool */
765 /** Free list for "back" allocations */
766 union anv_free_list back_alloc_free_list
;
768 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
771 struct anv_state_stream_block
;
773 struct anv_state_stream
{
774 struct anv_state_pool
*state_pool
;
776 /* The size of blocks to allocate from the state pool */
779 /* Current block we're allocating from */
780 struct anv_state block
;
782 /* Offset into the current block at which to allocate the next state */
785 /* List of all blocks allocated from this pool */
786 struct anv_state_stream_block
*block_list
;
789 /* The block_pool functions exported for testing only. The block pool should
790 * only be used via a state pool (see below).
792 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
793 struct anv_device
*device
,
794 uint64_t start_address
,
795 uint32_t initial_size
,
797 void anv_block_pool_finish(struct anv_block_pool
*pool
);
798 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
799 uint32_t block_size
, uint32_t *padding
);
800 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
801 uint32_t block_size
);
802 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
804 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
805 struct anv_device
*device
,
806 uint64_t start_address
,
809 void anv_state_pool_finish(struct anv_state_pool
*pool
);
810 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
811 uint32_t state_size
, uint32_t alignment
);
812 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
813 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
814 void anv_state_stream_init(struct anv_state_stream
*stream
,
815 struct anv_state_pool
*state_pool
,
816 uint32_t block_size
);
817 void anv_state_stream_finish(struct anv_state_stream
*stream
);
818 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
819 uint32_t size
, uint32_t alignment
);
821 VkResult
anv_state_table_init(struct anv_state_table
*table
,
822 struct anv_device
*device
,
823 uint32_t initial_entries
);
824 void anv_state_table_finish(struct anv_state_table
*table
);
825 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
827 void anv_free_list_push(union anv_free_list
*list
,
828 struct anv_state_table
*table
,
829 uint32_t idx
, uint32_t count
);
830 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
831 struct anv_state_table
*table
);
834 static inline struct anv_state
*
835 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
837 return &table
->map
[idx
].state
;
840 * Implements a pool of re-usable BOs. The interface is identical to that
841 * of block_pool except that each block is its own BO.
844 struct anv_device
*device
;
851 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
853 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
854 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
856 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
858 struct anv_scratch_bo
{
863 struct anv_scratch_pool
{
864 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
865 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
868 void anv_scratch_pool_init(struct anv_device
*device
,
869 struct anv_scratch_pool
*pool
);
870 void anv_scratch_pool_finish(struct anv_device
*device
,
871 struct anv_scratch_pool
*pool
);
872 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
873 struct anv_scratch_pool
*pool
,
874 gl_shader_stage stage
,
875 unsigned per_thread_scratch
);
877 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
878 struct anv_bo_cache
{
879 struct hash_table
*bo_map
;
880 pthread_mutex_t mutex
;
883 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
884 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
885 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
886 struct anv_bo_cache
*cache
,
887 uint64_t size
, uint64_t bo_flags
,
889 VkResult
anv_bo_cache_import_host_ptr(struct anv_device
*device
,
890 struct anv_bo_cache
*cache
,
891 void *host_ptr
, uint32_t size
,
892 uint64_t bo_flags
, struct anv_bo
**bo_out
);
893 VkResult
anv_bo_cache_import(struct anv_device
*device
,
894 struct anv_bo_cache
*cache
,
895 int fd
, uint64_t bo_flags
,
897 VkResult
anv_bo_cache_export(struct anv_device
*device
,
898 struct anv_bo_cache
*cache
,
899 struct anv_bo
*bo_in
, int *fd_out
);
900 void anv_bo_cache_release(struct anv_device
*device
,
901 struct anv_bo_cache
*cache
,
904 struct anv_memory_type
{
905 /* Standard bits passed on to the client */
906 VkMemoryPropertyFlags propertyFlags
;
909 /* Driver-internal book-keeping */
910 VkBufferUsageFlags valid_buffer_usage
;
913 struct anv_memory_heap
{
914 /* Standard bits passed on to the client */
916 VkMemoryHeapFlags flags
;
918 /* Driver-internal book-keeping */
921 bool supports_48bit_addresses
;
925 struct anv_physical_device
{
926 VK_LOADER_DATA _loader_data
;
928 struct anv_instance
* instance
;
939 struct gen_device_info info
;
940 /** Amount of "GPU memory" we want to advertise
942 * Clearly, this value is bogus since Intel is a UMA architecture. On
943 * gen7 platforms, we are limited by GTT size unless we want to implement
944 * fine-grained tracking and GTT splitting. On Broadwell and above we are
945 * practically unlimited. However, we will never report more than 3/4 of
946 * the total system ram to try and avoid running out of RAM.
948 bool supports_48bit_addresses
;
949 struct brw_compiler
* compiler
;
950 struct isl_device isl_dev
;
951 int cmd_parser_version
;
953 bool has_exec_capture
;
956 bool has_syncobj_wait
;
957 bool has_context_priority
;
959 bool has_context_isolation
;
960 bool has_mem_available
;
961 bool always_use_bindless
;
963 /** True if we can access buffers using A64 messages */
964 bool has_a64_buffer_access
;
965 /** True if we can use bindless access for images */
966 bool has_bindless_images
;
967 /** True if we can use bindless access for samplers */
968 bool has_bindless_samplers
;
970 struct anv_device_extension_table supported_extensions
;
971 struct anv_physical_device_dispatch_table dispatch
;
974 uint32_t subslice_total
;
978 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
980 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
983 uint8_t driver_build_sha1
[20];
984 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
985 uint8_t driver_uuid
[VK_UUID_SIZE
];
986 uint8_t device_uuid
[VK_UUID_SIZE
];
988 struct disk_cache
* disk_cache
;
990 struct wsi_device wsi_device
;
995 struct anv_app_info
{
996 const char* app_name
;
997 uint32_t app_version
;
998 const char* engine_name
;
999 uint32_t engine_version
;
1000 uint32_t api_version
;
1003 struct anv_instance
{
1004 VK_LOADER_DATA _loader_data
;
1006 VkAllocationCallbacks alloc
;
1008 struct anv_app_info app_info
;
1010 struct anv_instance_extension_table enabled_extensions
;
1011 struct anv_instance_dispatch_table dispatch
;
1012 struct anv_device_dispatch_table device_dispatch
;
1014 int physicalDeviceCount
;
1015 struct anv_physical_device physicalDevice
;
1017 bool pipeline_cache_enabled
;
1019 struct vk_debug_report_instance debug_report_callbacks
;
1021 struct driOptionCache dri_options
;
1022 struct driOptionCache available_dri_options
;
1025 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1026 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1028 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1029 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1033 VK_LOADER_DATA _loader_data
;
1035 struct anv_device
* device
;
1037 VkDeviceQueueCreateFlags flags
;
1040 struct anv_pipeline_cache
{
1041 struct anv_device
* device
;
1042 pthread_mutex_t mutex
;
1044 struct hash_table
* nir_cache
;
1046 struct hash_table
* cache
;
1049 struct nir_xfb_info
;
1050 struct anv_pipeline_bind_map
;
1052 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1053 struct anv_device
*device
,
1054 bool cache_enabled
);
1055 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1057 struct anv_shader_bin
*
1058 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1059 const void *key
, uint32_t key_size
);
1060 struct anv_shader_bin
*
1061 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1062 const void *key_data
, uint32_t key_size
,
1063 const void *kernel_data
, uint32_t kernel_size
,
1064 const void *constant_data
,
1065 uint32_t constant_data_size
,
1066 const struct brw_stage_prog_data
*prog_data
,
1067 uint32_t prog_data_size
,
1068 const struct brw_compile_stats
*stats
,
1070 const struct nir_xfb_info
*xfb_info
,
1071 const struct anv_pipeline_bind_map
*bind_map
);
1073 struct anv_shader_bin
*
1074 anv_device_search_for_kernel(struct anv_device
*device
,
1075 struct anv_pipeline_cache
*cache
,
1076 const void *key_data
, uint32_t key_size
,
1077 bool *user_cache_bit
);
1079 struct anv_shader_bin
*
1080 anv_device_upload_kernel(struct anv_device
*device
,
1081 struct anv_pipeline_cache
*cache
,
1082 const void *key_data
, uint32_t key_size
,
1083 const void *kernel_data
, uint32_t kernel_size
,
1084 const void *constant_data
,
1085 uint32_t constant_data_size
,
1086 const struct brw_stage_prog_data
*prog_data
,
1087 uint32_t prog_data_size
,
1088 const struct brw_compile_stats
*stats
,
1090 const struct nir_xfb_info
*xfb_info
,
1091 const struct anv_pipeline_bind_map
*bind_map
);
1094 struct nir_shader_compiler_options
;
1097 anv_device_search_for_nir(struct anv_device
*device
,
1098 struct anv_pipeline_cache
*cache
,
1099 const struct nir_shader_compiler_options
*nir_options
,
1100 unsigned char sha1_key
[20],
1104 anv_device_upload_nir(struct anv_device
*device
,
1105 struct anv_pipeline_cache
*cache
,
1106 const struct nir_shader
*nir
,
1107 unsigned char sha1_key
[20]);
1110 VK_LOADER_DATA _loader_data
;
1112 VkAllocationCallbacks alloc
;
1114 struct anv_instance
* instance
;
1115 uint32_t chipset_id
;
1117 struct gen_device_info info
;
1118 struct isl_device isl_dev
;
1121 bool can_chain_batches
;
1122 bool robust_buffer_access
;
1123 struct anv_device_extension_table enabled_extensions
;
1124 struct anv_device_dispatch_table dispatch
;
1126 pthread_mutex_t vma_mutex
;
1127 struct util_vma_heap vma_lo
;
1128 struct util_vma_heap vma_hi
;
1129 uint64_t vma_lo_available
;
1130 uint64_t vma_hi_available
;
1132 /** List of all anv_device_memory objects */
1133 struct list_head memory_objects
;
1135 struct anv_bo_pool batch_bo_pool
;
1137 struct anv_bo_cache bo_cache
;
1139 struct anv_state_pool dynamic_state_pool
;
1140 struct anv_state_pool instruction_state_pool
;
1141 struct anv_state_pool binding_table_pool
;
1142 struct anv_state_pool surface_state_pool
;
1144 struct anv_bo workaround_bo
;
1145 struct anv_bo trivial_batch_bo
;
1146 struct anv_bo hiz_clear_bo
;
1148 struct anv_pipeline_cache default_pipeline_cache
;
1149 struct blorp_context blorp
;
1151 struct anv_state border_colors
;
1153 struct anv_state slice_hash
;
1155 struct anv_queue queue
;
1157 struct anv_scratch_pool scratch_pool
;
1159 uint32_t default_mocs
;
1160 uint32_t external_mocs
;
1162 pthread_mutex_t mutex
;
1163 pthread_cond_t queue_submit
;
1166 struct gen_batch_decode_ctx decoder_ctx
;
1168 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1169 * the cmd_buffer's list.
1171 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1174 static inline struct anv_state_pool
*
1175 anv_binding_table_pool(struct anv_device
*device
)
1177 if (device
->instance
->physicalDevice
.use_softpin
)
1178 return &device
->binding_table_pool
;
1180 return &device
->surface_state_pool
;
1183 static inline struct anv_state
1184 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1185 if (device
->instance
->physicalDevice
.use_softpin
)
1186 return anv_state_pool_alloc(&device
->binding_table_pool
,
1187 device
->binding_table_pool
.block_size
, 0);
1189 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1193 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1194 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1197 static inline uint32_t
1198 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1200 if (bo
->flags
& ANV_BO_EXTERNAL
)
1201 return device
->external_mocs
;
1203 return device
->default_mocs
;
1206 void anv_device_init_blorp(struct anv_device
*device
);
1207 void anv_device_finish_blorp(struct anv_device
*device
);
1209 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1210 const char *file
, int line
,
1211 const char *msg
, ...);
1212 #define anv_device_set_lost(dev, ...) \
1213 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1216 anv_device_is_lost(struct anv_device
*device
)
1218 return unlikely(device
->_lost
);
1221 VkResult
anv_device_execbuf(struct anv_device
*device
,
1222 struct drm_i915_gem_execbuffer2
*execbuf
,
1223 struct anv_bo
**execbuf_bos
);
1224 VkResult
anv_device_query_status(struct anv_device
*device
);
1225 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1226 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1229 void* anv_gem_mmap(struct anv_device
*device
,
1230 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1231 void anv_gem_munmap(void *p
, uint64_t size
);
1232 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1233 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1234 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1235 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1236 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1237 int anv_gem_execbuffer(struct anv_device
*device
,
1238 struct drm_i915_gem_execbuffer2
*execbuf
);
1239 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1240 uint32_t stride
, uint32_t tiling
);
1241 int anv_gem_create_context(struct anv_device
*device
);
1242 bool anv_gem_has_context_priority(int fd
);
1243 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1244 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1246 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1248 int anv_gem_get_param(int fd
, uint32_t param
);
1249 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1250 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1251 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1252 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1253 uint32_t *active
, uint32_t *pending
);
1254 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1255 int anv_gem_reg_read(struct anv_device
*device
,
1256 uint32_t offset
, uint64_t *result
);
1257 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1258 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1259 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1260 uint32_t read_domains
, uint32_t write_domain
);
1261 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1262 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1263 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1264 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1265 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1266 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1268 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1269 uint32_t handle
, int fd
);
1270 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1271 bool anv_gem_supports_syncobj_wait(int fd
);
1272 int anv_gem_syncobj_wait(struct anv_device
*device
,
1273 uint32_t *handles
, uint32_t num_handles
,
1274 int64_t abs_timeout_ns
, bool wait_all
);
1276 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1277 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1279 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1281 struct anv_reloc_list
{
1282 uint32_t num_relocs
;
1283 uint32_t array_length
;
1284 struct drm_i915_gem_relocation_entry
* relocs
;
1285 struct anv_bo
** reloc_bos
;
1289 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1290 const VkAllocationCallbacks
*alloc
);
1291 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1292 const VkAllocationCallbacks
*alloc
);
1294 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1295 const VkAllocationCallbacks
*alloc
,
1296 uint32_t offset
, struct anv_bo
*target_bo
,
1299 struct anv_batch_bo
{
1300 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1301 struct list_head link
;
1305 /* Bytes actually consumed in this batch BO */
1308 struct anv_reloc_list relocs
;
1312 const VkAllocationCallbacks
* alloc
;
1318 struct anv_reloc_list
* relocs
;
1320 /* This callback is called (with the associated user data) in the event
1321 * that the batch runs out of space.
1323 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1327 * Current error status of the command buffer. Used to track inconsistent
1328 * or incomplete command buffer states that are the consequence of run-time
1329 * errors such as out of memory scenarios. We want to track this in the
1330 * batch because the command buffer object is not visible to some parts
1336 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1337 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1338 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1339 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1340 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1341 struct anv_batch
*batch
);
1343 static inline VkResult
1344 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1346 assert(error
!= VK_SUCCESS
);
1347 if (batch
->status
== VK_SUCCESS
)
1348 batch
->status
= error
;
1349 return batch
->status
;
1353 anv_batch_has_error(struct anv_batch
*batch
)
1355 return batch
->status
!= VK_SUCCESS
;
1358 struct anv_address
{
1363 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1366 anv_address_is_null(struct anv_address addr
)
1368 return addr
.bo
== NULL
&& addr
.offset
== 0;
1371 static inline uint64_t
1372 anv_address_physical(struct anv_address addr
)
1374 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1375 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1377 return gen_canonical_address(addr
.offset
);
1380 static inline struct anv_address
1381 anv_address_add(struct anv_address addr
, uint64_t offset
)
1383 addr
.offset
+= offset
;
1388 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1390 unsigned reloc_size
= 0;
1391 if (device
->info
.gen
>= 8) {
1392 reloc_size
= sizeof(uint64_t);
1393 *(uint64_t *)p
= gen_canonical_address(v
);
1395 reloc_size
= sizeof(uint32_t);
1399 if (flush
&& !device
->info
.has_llc
)
1400 gen_flush_range(p
, reloc_size
);
1403 static inline uint64_t
1404 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1405 const struct anv_address address
, uint32_t delta
)
1407 if (address
.bo
== NULL
) {
1408 return address
.offset
+ delta
;
1410 assert(batch
->start
<= location
&& location
< batch
->end
);
1412 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1416 #define __gen_address_type struct anv_address
1417 #define __gen_user_data struct anv_batch
1418 #define __gen_combine_address _anv_combine_address
1420 /* Wrapper macros needed to work around preprocessor argument issues. In
1421 * particular, arguments don't get pre-evaluated if they are concatenated.
1422 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1423 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1424 * We can work around this easily enough with these helpers.
1426 #define __anv_cmd_length(cmd) cmd ## _length
1427 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1428 #define __anv_cmd_header(cmd) cmd ## _header
1429 #define __anv_cmd_pack(cmd) cmd ## _pack
1430 #define __anv_reg_num(reg) reg ## _num
1432 #define anv_pack_struct(dst, struc, ...) do { \
1433 struct struc __template = { \
1436 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1437 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1440 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1441 void *__dst = anv_batch_emit_dwords(batch, n); \
1443 struct cmd __template = { \
1444 __anv_cmd_header(cmd), \
1445 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1448 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1453 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1457 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1458 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1461 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1462 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1463 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1466 #define anv_batch_emit(batch, cmd, name) \
1467 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1468 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1469 __builtin_expect(_dst != NULL, 1); \
1470 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1471 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1475 /* MEMORY_OBJECT_CONTROL_STATE:
1476 * .GraphicsDataTypeGFDT = 0,
1477 * .LLCCacheabilityControlLLCCC = 0,
1478 * .L3CacheabilityControlL3CC = 1,
1482 /* MEMORY_OBJECT_CONTROL_STATE:
1483 * .LLCeLLCCacheabilityControlLLCCC = 0,
1484 * .L3CacheabilityControlL3CC = 1,
1486 #define GEN75_MOCS 1
1488 /* MEMORY_OBJECT_CONTROL_STATE:
1489 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1490 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1491 * .AgeforQUADLRU = 0
1493 #define GEN8_MOCS 0x78
1495 /* MEMORY_OBJECT_CONTROL_STATE:
1496 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1497 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1498 * .AgeforQUADLRU = 0
1500 #define GEN8_EXTERNAL_MOCS 0x18
1502 /* Skylake: MOCS is now an index into an array of 62 different caching
1503 * configurations programmed by the kernel.
1506 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1507 #define GEN9_MOCS (2 << 1)
1509 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1510 #define GEN9_EXTERNAL_MOCS (1 << 1)
1512 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1513 #define GEN10_MOCS GEN9_MOCS
1514 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1516 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1517 #define GEN11_MOCS GEN9_MOCS
1518 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1520 /* TigerLake MOCS */
1521 #define GEN12_MOCS GEN9_MOCS
1522 /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
1523 #define GEN12_EXTERNAL_MOCS (3 << 1)
1525 struct anv_device_memory
{
1526 struct list_head link
;
1529 struct anv_memory_type
* type
;
1530 VkDeviceSize map_size
;
1533 /* If set, we are holding reference to AHardwareBuffer
1534 * which we must release when memory is freed.
1536 struct AHardwareBuffer
* ahw
;
1538 /* If set, this memory comes from a host pointer. */
1543 * Header for Vertex URB Entry (VUE)
1545 struct anv_vue_header
{
1547 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1548 uint32_t ViewportIndex
;
1552 /** Struct representing a sampled image descriptor
1554 * This descriptor layout is used for sampled images, bare sampler, and
1555 * combined image/sampler descriptors.
1557 struct anv_sampled_image_descriptor
{
1558 /** Bindless image handle
1560 * This is expected to already be shifted such that the 20-bit
1561 * SURFACE_STATE table index is in the top 20 bits.
1565 /** Bindless sampler handle
1567 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1568 * to the dynamic state base address.
1573 struct anv_texture_swizzle_descriptor
{
1576 * See also nir_intrinsic_channel_select_intel
1580 /** Unused padding to ensure the struct is a multiple of 64 bits */
1584 /** Struct representing a storage image descriptor */
1585 struct anv_storage_image_descriptor
{
1586 /** Bindless image handles
1588 * These are expected to already be shifted such that the 20-bit
1589 * SURFACE_STATE table index is in the top 20 bits.
1591 uint32_t read_write
;
1592 uint32_t write_only
;
1595 /** Struct representing a address/range descriptor
1597 * The fields of this struct correspond directly to the data layout of
1598 * nir_address_format_64bit_bounded_global addresses. The last field is the
1599 * offset in the NIR address so it must be zero so that when you load the
1600 * descriptor you get a pointer to the start of the range.
1602 struct anv_address_range_descriptor
{
1608 enum anv_descriptor_data
{
1609 /** The descriptor contains a BTI reference to a surface state */
1610 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1611 /** The descriptor contains a BTI reference to a sampler state */
1612 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1613 /** The descriptor contains an actual buffer view */
1614 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1615 /** The descriptor contains auxiliary image layout data */
1616 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1617 /** The descriptor contains auxiliary image layout data */
1618 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1619 /** anv_address_range_descriptor with a buffer address and range */
1620 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1621 /** Bindless surface handle */
1622 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1623 /** Storage image handles */
1624 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1625 /** Storage image handles */
1626 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1629 struct anv_descriptor_set_binding_layout
{
1631 /* The type of the descriptors in this binding */
1632 VkDescriptorType type
;
1635 /* Flags provided when this binding was created */
1636 VkDescriptorBindingFlagsEXT flags
;
1638 /* Bitfield representing the type of data this descriptor contains */
1639 enum anv_descriptor_data data
;
1641 /* Maximum number of YCbCr texture/sampler planes */
1642 uint8_t max_plane_count
;
1644 /* Number of array elements in this binding (or size in bytes for inline
1647 uint16_t array_size
;
1649 /* Index into the flattend descriptor set */
1650 uint16_t descriptor_index
;
1652 /* Index into the dynamic state array for a dynamic buffer */
1653 int16_t dynamic_offset_index
;
1655 /* Index into the descriptor set buffer views */
1656 int16_t buffer_view_index
;
1658 /* Offset into the descriptor buffer where this descriptor lives */
1659 uint32_t descriptor_offset
;
1661 /* Immutable samplers (or NULL if no immutable samplers) */
1662 struct anv_sampler
**immutable_samplers
;
1665 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1667 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1668 VkDescriptorType type
);
1670 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1671 const struct anv_descriptor_set_binding_layout
*binding
,
1674 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1675 const struct anv_descriptor_set_binding_layout
*binding
,
1678 struct anv_descriptor_set_layout
{
1679 /* Descriptor set layouts can be destroyed at almost any time */
1682 /* Number of bindings in this descriptor set */
1683 uint16_t binding_count
;
1685 /* Total size of the descriptor set with room for all array entries */
1688 /* Shader stages affected by this descriptor set */
1689 uint16_t shader_stages
;
1691 /* Number of buffer views in this descriptor set */
1692 uint16_t buffer_view_count
;
1694 /* Number of dynamic offsets used by this descriptor set */
1695 uint16_t dynamic_offset_count
;
1697 /* Size of the descriptor buffer for this descriptor set */
1698 uint32_t descriptor_buffer_size
;
1700 /* Bindings in this descriptor set */
1701 struct anv_descriptor_set_binding_layout binding
[0];
1705 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1707 assert(layout
&& layout
->ref_cnt
>= 1);
1708 p_atomic_inc(&layout
->ref_cnt
);
1712 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1713 struct anv_descriptor_set_layout
*layout
)
1715 assert(layout
&& layout
->ref_cnt
>= 1);
1716 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1717 vk_free(&device
->alloc
, layout
);
1720 struct anv_descriptor
{
1721 VkDescriptorType type
;
1725 VkImageLayout layout
;
1726 struct anv_image_view
*image_view
;
1727 struct anv_sampler
*sampler
;
1731 struct anv_buffer
*buffer
;
1736 struct anv_buffer_view
*buffer_view
;
1740 struct anv_descriptor_set
{
1741 struct anv_descriptor_pool
*pool
;
1742 struct anv_descriptor_set_layout
*layout
;
1745 /* State relative to anv_descriptor_pool::bo */
1746 struct anv_state desc_mem
;
1747 /* Surface state for the descriptor buffer */
1748 struct anv_state desc_surface_state
;
1750 uint32_t buffer_view_count
;
1751 struct anv_buffer_view
*buffer_views
;
1753 /* Link to descriptor pool's desc_sets list . */
1754 struct list_head pool_link
;
1756 struct anv_descriptor descriptors
[0];
1759 struct anv_buffer_view
{
1760 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1761 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1763 struct anv_address address
;
1765 struct anv_state surface_state
;
1766 struct anv_state storage_surface_state
;
1767 struct anv_state writeonly_storage_surface_state
;
1769 struct brw_image_param storage_image_param
;
1772 struct anv_push_descriptor_set
{
1773 struct anv_descriptor_set set
;
1775 /* Put this field right behind anv_descriptor_set so it fills up the
1776 * descriptors[0] field. */
1777 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1779 /** True if the descriptor set buffer has been referenced by a draw or
1782 bool set_used_on_gpu
;
1784 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1787 struct anv_descriptor_pool
{
1793 struct util_vma_heap bo_heap
;
1795 struct anv_state_stream surface_state_stream
;
1796 void *surface_state_free_list
;
1798 struct list_head desc_sets
;
1803 enum anv_descriptor_template_entry_type
{
1804 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1805 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1806 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1809 struct anv_descriptor_template_entry
{
1810 /* The type of descriptor in this entry */
1811 VkDescriptorType type
;
1813 /* Binding in the descriptor set */
1816 /* Offset at which to write into the descriptor set binding */
1817 uint32_t array_element
;
1819 /* Number of elements to write into the descriptor set binding */
1820 uint32_t array_count
;
1822 /* Offset into the user provided data */
1825 /* Stride between elements into the user provided data */
1829 struct anv_descriptor_update_template
{
1830 VkPipelineBindPoint bind_point
;
1832 /* The descriptor set this template corresponds to. This value is only
1833 * valid if the template was created with the templateType
1834 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1838 /* Number of entries in this template */
1839 uint32_t entry_count
;
1841 /* Entries of the template */
1842 struct anv_descriptor_template_entry entries
[0];
1846 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1849 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1850 struct anv_descriptor_set
*set
,
1851 const VkDescriptorImageInfo
* const info
,
1852 VkDescriptorType type
,
1857 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1858 struct anv_descriptor_set
*set
,
1859 VkDescriptorType type
,
1860 struct anv_buffer_view
*buffer_view
,
1865 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1866 struct anv_descriptor_set
*set
,
1867 struct anv_state_stream
*alloc_stream
,
1868 VkDescriptorType type
,
1869 struct anv_buffer
*buffer
,
1872 VkDeviceSize offset
,
1873 VkDeviceSize range
);
1875 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1876 struct anv_descriptor_set
*set
,
1883 anv_descriptor_set_write_template(struct anv_device
*device
,
1884 struct anv_descriptor_set
*set
,
1885 struct anv_state_stream
*alloc_stream
,
1886 const struct anv_descriptor_update_template
*template,
1890 anv_descriptor_set_create(struct anv_device
*device
,
1891 struct anv_descriptor_pool
*pool
,
1892 struct anv_descriptor_set_layout
*layout
,
1893 struct anv_descriptor_set
**out_set
);
1896 anv_descriptor_set_destroy(struct anv_device
*device
,
1897 struct anv_descriptor_pool
*pool
,
1898 struct anv_descriptor_set
*set
);
1900 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
1901 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
1902 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1903 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1905 struct anv_pipeline_binding
{
1906 /* The descriptor set this surface corresponds to. The special value of
1907 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1908 * to a color attachment and not a regular descriptor.
1912 /* Binding in the descriptor set */
1915 /* Index in the binding */
1918 /* Plane in the binding index */
1921 /* Input attachment index (relative to the subpass) */
1922 uint8_t input_attachment_index
;
1924 /* For a storage image, whether it is write-only */
1928 struct anv_pipeline_layout
{
1930 struct anv_descriptor_set_layout
*layout
;
1931 uint32_t dynamic_offset_start
;
1936 unsigned char sha1
[20];
1940 struct anv_device
* device
;
1943 VkBufferUsageFlags usage
;
1945 /* Set when bound */
1946 struct anv_address address
;
1949 static inline uint64_t
1950 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1952 assert(offset
<= buffer
->size
);
1953 if (range
== VK_WHOLE_SIZE
) {
1954 return buffer
->size
- offset
;
1956 assert(range
+ offset
>= range
);
1957 assert(range
+ offset
<= buffer
->size
);
1962 enum anv_cmd_dirty_bits
{
1963 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1964 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1965 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1966 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1967 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1968 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1969 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1970 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1971 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1972 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1973 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1974 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1975 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
1976 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
1978 typedef uint32_t anv_cmd_dirty_mask_t
;
1980 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
1981 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
1982 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
1983 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
1984 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
1985 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
1986 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
1987 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
1988 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
1989 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
1990 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
1992 static inline enum anv_cmd_dirty_bits
1993 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
1996 case VK_DYNAMIC_STATE_VIEWPORT
:
1997 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
1998 case VK_DYNAMIC_STATE_SCISSOR
:
1999 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2000 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2001 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2002 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2003 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2004 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2005 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2006 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2007 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2008 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2009 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2010 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2011 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2012 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2013 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2014 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2015 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2017 assert(!"Unsupported dynamic state");
2023 enum anv_pipe_bits
{
2024 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2025 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2026 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2027 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2028 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2029 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2030 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2031 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2032 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2033 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2034 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2036 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2037 * a flush has happened but not a CS stall. The next time we do any sort
2038 * of invalidation we need to insert a CS stall at that time. Otherwise,
2039 * we would have to CS stall on every flush which could be bad.
2041 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2043 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2044 * target operations related to transfer commands with VkBuffer as
2045 * destination are ongoing. Some operations like copies on the command
2046 * streamer might need to be aware of this to trigger the appropriate stall
2047 * before they can proceed with the copy.
2049 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2052 #define ANV_PIPE_FLUSH_BITS ( \
2053 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2054 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2055 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
2057 #define ANV_PIPE_STALL_BITS ( \
2058 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2059 ANV_PIPE_DEPTH_STALL_BIT | \
2060 ANV_PIPE_CS_STALL_BIT)
2062 #define ANV_PIPE_INVALIDATE_BITS ( \
2063 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2064 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2065 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2066 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2067 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2068 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2070 static inline enum anv_pipe_bits
2071 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2073 enum anv_pipe_bits pipe_bits
= 0;
2076 for_each_bit(b
, flags
) {
2077 switch ((VkAccessFlagBits
)(1 << b
)) {
2078 case VK_ACCESS_SHADER_WRITE_BIT
:
2079 /* We're transitioning a buffer that was previously used as write
2080 * destination through the data port. To make its content available
2081 * to future operations, flush the data cache.
2083 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2085 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2086 /* We're transitioning a buffer that was previously used as render
2087 * target. To make its content available to future operations, flush
2088 * the render target cache.
2090 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2092 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2093 /* We're transitioning a buffer that was previously used as depth
2094 * buffer. To make its content available to future operations, flush
2097 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2099 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2100 /* We're transitioning a buffer that was previously used as a
2101 * transfer write destination. Generic write operations include color
2102 * & depth operations as well as buffer operations like :
2103 * - vkCmdClearColorImage()
2104 * - vkCmdClearDepthStencilImage()
2105 * - vkCmdBlitImage()
2106 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2108 * Most of these operations are implemented using Blorp which writes
2109 * through the render target, so flush that cache to make it visible
2110 * to future operations. And for depth related operations we also
2111 * need to flush the depth cache.
2113 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2114 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2116 case VK_ACCESS_MEMORY_WRITE_BIT
:
2117 /* We're transitioning a buffer for generic write operations. Flush
2120 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2123 break; /* Nothing to do */
2130 static inline enum anv_pipe_bits
2131 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2133 enum anv_pipe_bits pipe_bits
= 0;
2136 for_each_bit(b
, flags
) {
2137 switch ((VkAccessFlagBits
)(1 << b
)) {
2138 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2139 /* Indirect draw commands take a buffer as input that we're going to
2140 * read from the command streamer to load some of the HW registers
2141 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2142 * command streamer stall so that all the cache flushes have
2143 * completed before the command streamer loads from memory.
2145 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2146 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2147 * through a vertex buffer, so invalidate that cache.
2149 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2150 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2151 * UBO from the buffer, so we need to invalidate constant cache.
2153 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2155 case VK_ACCESS_INDEX_READ_BIT
:
2156 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2157 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2158 * commands, so we invalidate the VF cache to make sure there is no
2159 * stale data when we start rendering.
2161 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2163 case VK_ACCESS_UNIFORM_READ_BIT
:
2164 /* We transitioning a buffer to be used as uniform data. Because
2165 * uniform is accessed through the data port & sampler, we need to
2166 * invalidate the texture cache (sampler) & constant cache (data
2167 * port) to avoid stale data.
2169 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2170 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2172 case VK_ACCESS_SHADER_READ_BIT
:
2173 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2174 case VK_ACCESS_TRANSFER_READ_BIT
:
2175 /* Transitioning a buffer to be read through the sampler, so
2176 * invalidate the texture cache, we don't want any stale data.
2178 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2180 case VK_ACCESS_MEMORY_READ_BIT
:
2181 /* Transitioning a buffer for generic read, invalidate all the
2184 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2186 case VK_ACCESS_MEMORY_WRITE_BIT
:
2187 /* Generic write, make sure all previously written things land in
2190 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2192 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2193 /* Transitioning a buffer for conditional rendering. We'll load the
2194 * content of this buffer into HW registers using the command
2195 * streamer, so we need to stall the command streamer to make sure
2196 * any in-flight flush operations have completed.
2198 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2201 break; /* Nothing to do */
2208 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2209 VK_IMAGE_ASPECT_COLOR_BIT | \
2210 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2211 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2212 VK_IMAGE_ASPECT_PLANE_2_BIT)
2213 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2214 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2215 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2216 VK_IMAGE_ASPECT_PLANE_2_BIT)
2218 struct anv_vertex_binding
{
2219 struct anv_buffer
* buffer
;
2220 VkDeviceSize offset
;
2223 struct anv_xfb_binding
{
2224 struct anv_buffer
* buffer
;
2225 VkDeviceSize offset
;
2229 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
2230 #define ANV_PARAM_IS_PUSH(param) ((uint32_t)(param) >> 16 == 1)
2231 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2233 #define ANV_PARAM_DYN_OFFSET(offset) ((2 << 16) | (uint32_t)(offset))
2234 #define ANV_PARAM_IS_DYN_OFFSET(param) ((uint32_t)(param) >> 16 == 2)
2235 #define ANV_PARAM_DYN_OFFSET_IDX(param) ((param) & 0xffff)
2237 struct anv_push_constants
{
2238 /* Push constant data provided by the client through vkPushConstants */
2239 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2241 /* Used for vkCmdDispatchBase */
2242 uint32_t base_work_group_id
[3];
2245 struct anv_dynamic_state
{
2248 VkViewport viewports
[MAX_VIEWPORTS
];
2253 VkRect2D scissors
[MAX_SCISSORS
];
2264 float blend_constants
[4];
2274 } stencil_compare_mask
;
2279 } stencil_write_mask
;
2284 } stencil_reference
;
2292 extern const struct anv_dynamic_state default_dynamic_state
;
2294 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2295 const struct anv_dynamic_state
*src
,
2296 uint32_t copy_mask
);
2298 struct anv_surface_state
{
2299 struct anv_state state
;
2300 /** Address of the surface referred to by this state
2302 * This address is relative to the start of the BO.
2304 struct anv_address address
;
2305 /* Address of the aux surface, if any
2307 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2309 * With the exception of gen8, the bottom 12 bits of this address' offset
2310 * include extra aux information.
2312 struct anv_address aux_address
;
2313 /* Address of the clear color, if any
2315 * This address is relative to the start of the BO.
2317 struct anv_address clear_address
;
2321 * Attachment state when recording a renderpass instance.
2323 * The clear value is valid only if there exists a pending clear.
2325 struct anv_attachment_state
{
2326 enum isl_aux_usage aux_usage
;
2327 enum isl_aux_usage input_aux_usage
;
2328 struct anv_surface_state color
;
2329 struct anv_surface_state input
;
2331 VkImageLayout current_layout
;
2332 VkImageAspectFlags pending_clear_aspects
;
2333 VkImageAspectFlags pending_load_aspects
;
2335 VkClearValue clear_value
;
2336 bool clear_color_is_zero_one
;
2337 bool clear_color_is_zero
;
2339 /* When multiview is active, attachments with a renderpass clear
2340 * operation have their respective layers cleared on the first
2341 * subpass that uses them, and only in that subpass. We keep track
2342 * of this using a bitfield to indicate which layers of an attachment
2343 * have not been cleared yet when multiview is active.
2345 uint32_t pending_clear_views
;
2346 struct anv_image_view
* image_view
;
2349 /** State tracking for particular pipeline bind point
2351 * This struct is the base struct for anv_cmd_graphics_state and
2352 * anv_cmd_compute_state. These are used to track state which is bound to a
2353 * particular type of pipeline. Generic state that applies per-stage such as
2354 * binding table offsets and push constants is tracked generically with a
2355 * per-stage array in anv_cmd_state.
2357 struct anv_cmd_pipeline_state
{
2358 struct anv_pipeline
*pipeline
;
2359 struct anv_pipeline_layout
*layout
;
2361 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2362 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2364 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2367 /** State tracking for graphics pipeline
2369 * This has anv_cmd_pipeline_state as a base struct to track things which get
2370 * bound to a graphics pipeline. Along with general pipeline bind point state
2371 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2372 * state which is graphics-specific.
2374 struct anv_cmd_graphics_state
{
2375 struct anv_cmd_pipeline_state base
;
2377 anv_cmd_dirty_mask_t dirty
;
2380 struct anv_dynamic_state dynamic
;
2383 struct anv_buffer
*index_buffer
;
2384 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2385 uint32_t index_offset
;
2389 /** State tracking for compute pipeline
2391 * This has anv_cmd_pipeline_state as a base struct to track things which get
2392 * bound to a compute pipeline. Along with general pipeline bind point state
2393 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2394 * state which is compute-specific.
2396 struct anv_cmd_compute_state
{
2397 struct anv_cmd_pipeline_state base
;
2399 bool pipeline_dirty
;
2401 struct anv_address num_workgroups
;
2404 /** State required while building cmd buffer */
2405 struct anv_cmd_state
{
2406 /* PIPELINE_SELECT.PipelineSelection */
2407 uint32_t current_pipeline
;
2408 const struct gen_l3_config
* current_l3_config
;
2410 struct anv_cmd_graphics_state gfx
;
2411 struct anv_cmd_compute_state compute
;
2413 enum anv_pipe_bits pending_pipe_bits
;
2414 VkShaderStageFlags descriptors_dirty
;
2415 VkShaderStageFlags push_constants_dirty
;
2417 struct anv_framebuffer
* framebuffer
;
2418 struct anv_render_pass
* pass
;
2419 struct anv_subpass
* subpass
;
2420 VkRect2D render_area
;
2421 uint32_t restart_index
;
2422 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2424 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2425 VkShaderStageFlags push_constant_stages
;
2426 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2427 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2428 struct anv_state samplers
[MESA_SHADER_STAGES
];
2431 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2432 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2433 * and before invoking the secondary in ExecuteCommands.
2435 bool pma_fix_enabled
;
2438 * Whether or not we know for certain that HiZ is enabled for the current
2439 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2440 * enabled or not, this will be false.
2444 bool conditional_render_enabled
;
2447 * Last rendering scale argument provided to
2448 * genX(cmd_buffer_emit_hashing_mode)().
2450 unsigned current_hash_scale
;
2453 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2454 * valid only when recording a render pass instance.
2456 struct anv_attachment_state
* attachments
;
2459 * Surface states for color render targets. These are stored in a single
2460 * flat array. For depth-stencil attachments, the surface state is simply
2463 struct anv_state render_pass_states
;
2466 * A null surface state of the right size to match the framebuffer. This
2467 * is one of the states in render_pass_states.
2469 struct anv_state null_surface_state
;
2472 struct anv_cmd_pool
{
2473 VkAllocationCallbacks alloc
;
2474 struct list_head cmd_buffers
;
2477 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2479 enum anv_cmd_buffer_exec_mode
{
2480 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2481 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2482 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2483 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2484 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2487 struct anv_cmd_buffer
{
2488 VK_LOADER_DATA _loader_data
;
2490 struct anv_device
* device
;
2492 struct anv_cmd_pool
* pool
;
2493 struct list_head pool_link
;
2495 struct anv_batch batch
;
2497 /* Fields required for the actual chain of anv_batch_bo's.
2499 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2501 struct list_head batch_bos
;
2502 enum anv_cmd_buffer_exec_mode exec_mode
;
2504 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2505 * referenced by this command buffer
2507 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2509 struct u_vector seen_bbos
;
2511 /* A vector of int32_t's for every block of binding tables.
2513 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2515 struct u_vector bt_block_states
;
2518 struct anv_reloc_list surface_relocs
;
2519 /** Last seen surface state block pool center bo offset */
2520 uint32_t last_ss_pool_center
;
2522 /* Serial for tracking buffer completion */
2525 /* Stream objects for storing temporary data */
2526 struct anv_state_stream surface_state_stream
;
2527 struct anv_state_stream dynamic_state_stream
;
2529 VkCommandBufferUsageFlags usage_flags
;
2530 VkCommandBufferLevel level
;
2532 struct anv_cmd_state state
;
2535 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2536 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2537 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2538 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2539 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2540 struct anv_cmd_buffer
*secondary
);
2541 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2542 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2543 struct anv_cmd_buffer
*cmd_buffer
,
2544 const VkSemaphore
*in_semaphores
,
2545 uint32_t num_in_semaphores
,
2546 const VkSemaphore
*out_semaphores
,
2547 uint32_t num_out_semaphores
,
2550 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2552 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2553 const void *data
, uint32_t size
, uint32_t alignment
);
2554 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2555 uint32_t *a
, uint32_t *b
,
2556 uint32_t dwords
, uint32_t alignment
);
2559 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2561 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2562 uint32_t entries
, uint32_t *state_offset
);
2564 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2566 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2567 uint32_t size
, uint32_t alignment
);
2570 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2572 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2573 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2574 bool depth_clamp_enable
);
2575 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2577 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2578 struct anv_render_pass
*pass
,
2579 struct anv_framebuffer
*framebuffer
,
2580 const VkClearValue
*clear_values
);
2582 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2585 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2586 gl_shader_stage stage
);
2588 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2590 const struct anv_image_view
*
2591 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2594 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2595 uint32_t num_entries
,
2596 uint32_t *state_offset
,
2597 struct anv_state
*bt_state
);
2599 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2601 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2603 enum anv_fence_type
{
2604 ANV_FENCE_TYPE_NONE
= 0,
2606 ANV_FENCE_TYPE_SYNCOBJ
,
2610 enum anv_bo_fence_state
{
2611 /** Indicates that this is a new (or newly reset fence) */
2612 ANV_BO_FENCE_STATE_RESET
,
2614 /** Indicates that this fence has been submitted to the GPU but is still
2615 * (as far as we know) in use by the GPU.
2617 ANV_BO_FENCE_STATE_SUBMITTED
,
2619 ANV_BO_FENCE_STATE_SIGNALED
,
2622 struct anv_fence_impl
{
2623 enum anv_fence_type type
;
2626 /** Fence implementation for BO fences
2628 * These fences use a BO and a set of CPU-tracked state flags. The BO
2629 * is added to the object list of the last execbuf call in a QueueSubmit
2630 * and is marked EXEC_WRITE. The state flags track when the BO has been
2631 * submitted to the kernel. We need to do this because Vulkan lets you
2632 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2633 * will say it's idle in this case.
2637 enum anv_bo_fence_state state
;
2640 /** DRM syncobj handle for syncobj-based fences */
2644 struct wsi_fence
*fence_wsi
;
2649 /* Permanent fence state. Every fence has some form of permanent state
2650 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2651 * cross-process fences) or it could just be a dummy for use internally.
2653 struct anv_fence_impl permanent
;
2655 /* Temporary fence state. A fence *may* have temporary state. That state
2656 * is added to the fence by an import operation and is reset back to
2657 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2658 * state cannot be signaled because the fence must already be signaled
2659 * before the temporary state can be exported from the fence in the other
2660 * process and imported here.
2662 struct anv_fence_impl temporary
;
2667 struct anv_state state
;
2670 enum anv_semaphore_type
{
2671 ANV_SEMAPHORE_TYPE_NONE
= 0,
2672 ANV_SEMAPHORE_TYPE_DUMMY
,
2673 ANV_SEMAPHORE_TYPE_BO
,
2674 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2675 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2678 struct anv_semaphore_impl
{
2679 enum anv_semaphore_type type
;
2682 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2683 * This BO will be added to the object list on any execbuf2 calls for
2684 * which this semaphore is used as a wait or signal fence. When used as
2685 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2689 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2690 * If the semaphore is in the unsignaled state due to either just being
2691 * created or because it has been used for a wait, fd will be -1.
2695 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2696 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2697 * import so we don't need to bother with a userspace cache.
2703 struct anv_semaphore
{
2704 /* Permanent semaphore state. Every semaphore has some form of permanent
2705 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2706 * (for cross-process semaphores0 or it could just be a dummy for use
2709 struct anv_semaphore_impl permanent
;
2711 /* Temporary semaphore state. A semaphore *may* have temporary state.
2712 * That state is added to the semaphore by an import operation and is reset
2713 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2714 * semaphore with temporary state cannot be signaled because the semaphore
2715 * must already be signaled before the temporary state can be exported from
2716 * the semaphore in the other process and imported here.
2718 struct anv_semaphore_impl temporary
;
2721 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2722 struct anv_semaphore
*semaphore
);
2724 struct anv_shader_module
{
2725 unsigned char sha1
[20];
2730 static inline gl_shader_stage
2731 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2733 assert(__builtin_popcount(vk_stage
) == 1);
2734 return ffs(vk_stage
) - 1;
2737 static inline VkShaderStageFlagBits
2738 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2740 return (1 << mesa_stage
);
2743 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2745 #define anv_foreach_stage(stage, stage_bits) \
2746 for (gl_shader_stage stage, \
2747 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2748 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2749 __tmp &= ~(1 << (stage)))
2751 struct anv_pipeline_bind_map
{
2752 uint32_t surface_count
;
2753 uint32_t sampler_count
;
2755 struct anv_pipeline_binding
* surface_to_descriptor
;
2756 struct anv_pipeline_binding
* sampler_to_descriptor
;
2759 struct anv_shader_bin_key
{
2764 struct anv_shader_bin
{
2767 const struct anv_shader_bin_key
*key
;
2769 struct anv_state kernel
;
2770 uint32_t kernel_size
;
2772 struct anv_state constant_data
;
2773 uint32_t constant_data_size
;
2775 const struct brw_stage_prog_data
*prog_data
;
2776 uint32_t prog_data_size
;
2778 struct brw_compile_stats stats
[3];
2781 struct nir_xfb_info
*xfb_info
;
2783 struct anv_pipeline_bind_map bind_map
;
2786 struct anv_shader_bin
*
2787 anv_shader_bin_create(struct anv_device
*device
,
2788 const void *key
, uint32_t key_size
,
2789 const void *kernel
, uint32_t kernel_size
,
2790 const void *constant_data
, uint32_t constant_data_size
,
2791 const struct brw_stage_prog_data
*prog_data
,
2792 uint32_t prog_data_size
, const void *prog_data_param
,
2793 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
2794 const struct nir_xfb_info
*xfb_info
,
2795 const struct anv_pipeline_bind_map
*bind_map
);
2798 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2801 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2803 assert(shader
&& shader
->ref_cnt
>= 1);
2804 p_atomic_inc(&shader
->ref_cnt
);
2808 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2810 assert(shader
&& shader
->ref_cnt
>= 1);
2811 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2812 anv_shader_bin_destroy(device
, shader
);
2815 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
2816 #define MAX_PIPELINE_EXECUTABLES 7
2818 struct anv_pipeline_executable
{
2819 gl_shader_stage stage
;
2821 struct brw_compile_stats stats
;
2826 struct anv_pipeline
{
2827 struct anv_device
* device
;
2828 struct anv_batch batch
;
2829 uint32_t batch_data
[512];
2830 struct anv_reloc_list batch_relocs
;
2831 anv_cmd_dirty_mask_t dynamic_state_mask
;
2832 struct anv_dynamic_state dynamic_state
;
2836 VkPipelineCreateFlags flags
;
2837 struct anv_subpass
* subpass
;
2839 bool needs_data_cache
;
2841 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2843 uint32_t num_executables
;
2844 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
2847 const struct gen_l3_config
* l3_config
;
2848 uint32_t total_size
;
2851 VkShaderStageFlags active_stages
;
2852 struct anv_state blend_state
;
2855 struct anv_pipeline_vertex_binding
{
2858 uint32_t instance_divisor
;
2863 bool primitive_restart
;
2866 uint32_t cs_right_mask
;
2869 bool depth_test_enable
;
2870 bool writes_stencil
;
2871 bool stencil_test_enable
;
2872 bool depth_clamp_enable
;
2873 bool depth_clip_enable
;
2874 bool sample_shading_enable
;
2879 uint32_t depth_stencil_state
[3];
2885 uint32_t wm_depth_stencil
[3];
2889 uint32_t wm_depth_stencil
[4];
2892 uint32_t interface_descriptor_data
[8];
2896 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2897 gl_shader_stage stage
)
2899 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2902 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2903 static inline const struct brw_##prefix##_prog_data * \
2904 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2906 if (anv_pipeline_has_stage(pipeline, stage)) { \
2907 return (const struct brw_##prefix##_prog_data *) \
2908 pipeline->shaders[stage]->prog_data; \
2914 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2915 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2916 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2917 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2918 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2919 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2921 static inline const struct brw_vue_prog_data
*
2922 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2924 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2925 return &get_gs_prog_data(pipeline
)->base
;
2926 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2927 return &get_tes_prog_data(pipeline
)->base
;
2929 return &get_vs_prog_data(pipeline
)->base
;
2933 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2934 struct anv_pipeline_cache
*cache
,
2935 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2936 const VkAllocationCallbacks
*alloc
);
2939 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2940 struct anv_pipeline_cache
*cache
,
2941 const VkComputePipelineCreateInfo
*info
,
2942 const struct anv_shader_module
*module
,
2943 const char *entrypoint
,
2944 const VkSpecializationInfo
*spec_info
);
2946 struct anv_format_plane
{
2947 enum isl_format isl_format
:16;
2948 struct isl_swizzle swizzle
;
2950 /* Whether this plane contains chroma channels */
2953 /* For downscaling of YUV planes */
2954 uint8_t denominator_scales
[2];
2956 /* How to map sampled ycbcr planes to a single 4 component element. */
2957 struct isl_swizzle ycbcr_swizzle
;
2959 /* What aspect is associated to this plane */
2960 VkImageAspectFlags aspect
;
2965 struct anv_format_plane planes
[3];
2971 static inline uint32_t
2972 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2973 VkImageAspectFlags aspect_mask
)
2975 switch (aspect_mask
) {
2976 case VK_IMAGE_ASPECT_COLOR_BIT
:
2977 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2978 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2980 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2981 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2984 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2986 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2989 /* Purposefully assert with depth/stencil aspects. */
2990 unreachable("invalid image aspect");
2994 static inline VkImageAspectFlags
2995 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
2998 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2999 if (util_bitcount(image_aspects
) > 1)
3000 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3001 return VK_IMAGE_ASPECT_COLOR_BIT
;
3003 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3004 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3005 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3006 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3009 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3010 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3012 const struct anv_format
*
3013 anv_get_format(VkFormat format
);
3015 static inline uint32_t
3016 anv_get_format_planes(VkFormat vk_format
)
3018 const struct anv_format
*format
= anv_get_format(vk_format
);
3020 return format
!= NULL
? format
->n_planes
: 0;
3023 struct anv_format_plane
3024 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3025 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3027 static inline enum isl_format
3028 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3029 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3031 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3034 static inline struct isl_swizzle
3035 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3037 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3038 * RGB as RGBA for texturing
3040 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3041 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3043 /* But it doesn't matter what we render to that channel */
3044 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3050 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3053 * Subsurface of an anv_image.
3055 struct anv_surface
{
3056 /** Valid only if isl_surf::size_B > 0. */
3057 struct isl_surf isl
;
3060 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3066 VkImageType type
; /**< VkImageCreateInfo::imageType */
3067 /* The original VkFormat provided by the client. This may not match any
3068 * of the actual surface formats.
3071 const struct anv_format
*format
;
3073 VkImageAspectFlags aspects
;
3076 uint32_t array_size
;
3077 uint32_t samples
; /**< VkImageCreateInfo::samples */
3079 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3080 VkImageUsageFlags stencil_usage
;
3081 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3082 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3084 /** True if this is needs to be bound to an appropriately tiled BO.
3086 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3087 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3088 * we require a dedicated allocation so that we can know to allocate a
3091 bool needs_set_tiling
;
3094 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3095 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3097 uint64_t drm_format_mod
;
3102 /* Whether the image is made of several underlying buffer objects rather a
3103 * single one with different offsets.
3107 /* All the formats that can be used when creating views of this image
3108 * are CCS_E compatible.
3110 bool ccs_e_compatible
;
3112 /* Image was created with external format. */
3113 bool external_format
;
3118 * For each foo, anv_image::planes[x].surface is valid if and only if
3119 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3120 * to figure the number associated with a given aspect.
3122 * The hardware requires that the depth buffer and stencil buffer be
3123 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3124 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3125 * allocate the depth and stencil buffers as separate surfaces in the same
3130 * -----------------------
3132 * ----------------------- |
3133 * | shadow surface0 | |
3134 * ----------------------- | Plane 0
3135 * | aux surface0 | |
3136 * ----------------------- |
3137 * | fast clear colors0 | \|/
3138 * -----------------------
3140 * ----------------------- |
3141 * | shadow surface1 | |
3142 * ----------------------- | Plane 1
3143 * | aux surface1 | |
3144 * ----------------------- |
3145 * | fast clear colors1 | \|/
3146 * -----------------------
3149 * -----------------------
3153 * Offset of the entire plane (whenever the image is disjoint this is
3161 struct anv_surface surface
;
3164 * A surface which shadows the main surface and may have different
3165 * tiling. This is used for sampling using a tiling that isn't supported
3166 * for other operations.
3168 struct anv_surface shadow_surface
;
3171 * For color images, this is the aux usage for this image when not used
3172 * as a color attachment.
3174 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3175 * image has a HiZ buffer.
3177 enum isl_aux_usage aux_usage
;
3179 struct anv_surface aux_surface
;
3182 * Offset of the fast clear state (used to compute the
3183 * fast_clear_state_offset of the following planes).
3185 uint32_t fast_clear_state_offset
;
3188 * BO associated with this plane, set when bound.
3190 struct anv_address address
;
3193 * When destroying the image, also free the bo.
3199 /* The ordering of this enum is important */
3200 enum anv_fast_clear_type
{
3201 /** Image does not have/support any fast-clear blocks */
3202 ANV_FAST_CLEAR_NONE
= 0,
3203 /** Image has/supports fast-clear but only to the default value */
3204 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3205 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3206 ANV_FAST_CLEAR_ANY
= 2,
3209 /* Returns the number of auxiliary buffer levels attached to an image. */
3210 static inline uint8_t
3211 anv_image_aux_levels(const struct anv_image
* const image
,
3212 VkImageAspectFlagBits aspect
)
3214 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3215 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3216 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
3219 /* Returns the number of auxiliary buffer layers attached to an image. */
3220 static inline uint32_t
3221 anv_image_aux_layers(const struct anv_image
* const image
,
3222 VkImageAspectFlagBits aspect
,
3223 const uint8_t miplevel
)
3227 /* The miplevel must exist in the main buffer. */
3228 assert(miplevel
< image
->levels
);
3230 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3231 /* There are no layers with auxiliary data because the miplevel has no
3236 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3237 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
3238 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
3242 static inline struct anv_address
3243 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3244 const struct anv_image
*image
,
3245 VkImageAspectFlagBits aspect
)
3247 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3249 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3250 return anv_address_add(image
->planes
[plane
].address
,
3251 image
->planes
[plane
].fast_clear_state_offset
);
3254 static inline struct anv_address
3255 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3256 const struct anv_image
*image
,
3257 VkImageAspectFlagBits aspect
)
3259 struct anv_address addr
=
3260 anv_image_get_clear_color_addr(device
, image
, aspect
);
3262 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3263 device
->isl_dev
.ss
.clear_color_state_size
:
3264 device
->isl_dev
.ss
.clear_value_size
;
3265 return anv_address_add(addr
, clear_color_state_size
);
3268 static inline struct anv_address
3269 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3270 const struct anv_image
*image
,
3271 VkImageAspectFlagBits aspect
,
3272 uint32_t level
, uint32_t array_layer
)
3274 assert(level
< anv_image_aux_levels(image
, aspect
));
3275 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3276 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3277 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3279 struct anv_address addr
=
3280 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3281 addr
.offset
+= 4; /* Go past the fast clear type */
3283 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3284 for (uint32_t l
= 0; l
< level
; l
++)
3285 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3287 addr
.offset
+= level
* image
->array_size
* 4;
3289 addr
.offset
+= array_layer
* 4;
3294 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3296 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3297 const struct anv_image
*image
)
3299 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3302 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3303 * struct. There's documentation which suggests that this feature actually
3304 * reduces performance on BDW, but it has only been observed to help so
3305 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3306 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3308 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3311 return image
->samples
== 1;
3315 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3316 const struct anv_image
*image
,
3317 VkImageAspectFlagBits aspect
,
3318 enum isl_aux_usage aux_usage
,
3320 uint32_t base_layer
,
3321 uint32_t layer_count
);
3324 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3325 const struct anv_image
*image
,
3326 VkImageAspectFlagBits aspect
,
3327 enum isl_aux_usage aux_usage
,
3328 enum isl_format format
, struct isl_swizzle swizzle
,
3329 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3330 VkRect2D area
, union isl_color_value clear_color
);
3332 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3333 const struct anv_image
*image
,
3334 VkImageAspectFlags aspects
,
3335 enum isl_aux_usage depth_aux_usage
,
3337 uint32_t base_layer
, uint32_t layer_count
,
3339 float depth_value
, uint8_t stencil_value
);
3341 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3342 const struct anv_image
*src_image
,
3343 enum isl_aux_usage src_aux_usage
,
3344 uint32_t src_level
, uint32_t src_base_layer
,
3345 const struct anv_image
*dst_image
,
3346 enum isl_aux_usage dst_aux_usage
,
3347 uint32_t dst_level
, uint32_t dst_base_layer
,
3348 VkImageAspectFlagBits aspect
,
3349 uint32_t src_x
, uint32_t src_y
,
3350 uint32_t dst_x
, uint32_t dst_y
,
3351 uint32_t width
, uint32_t height
,
3352 uint32_t layer_count
,
3353 enum blorp_filter filter
);
3355 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3356 const struct anv_image
*image
,
3357 VkImageAspectFlagBits aspect
, uint32_t level
,
3358 uint32_t base_layer
, uint32_t layer_count
,
3359 enum isl_aux_op hiz_op
);
3361 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3362 const struct anv_image
*image
,
3363 VkImageAspectFlags aspects
,
3365 uint32_t base_layer
, uint32_t layer_count
,
3366 VkRect2D area
, uint8_t stencil_value
);
3368 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3369 const struct anv_image
*image
,
3370 enum isl_format format
,
3371 VkImageAspectFlagBits aspect
,
3372 uint32_t base_layer
, uint32_t layer_count
,
3373 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3376 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3377 const struct anv_image
*image
,
3378 enum isl_format format
,
3379 VkImageAspectFlagBits aspect
, uint32_t level
,
3380 uint32_t base_layer
, uint32_t layer_count
,
3381 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3385 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3386 const struct anv_image
*image
,
3387 VkImageAspectFlagBits aspect
,
3388 uint32_t base_level
, uint32_t level_count
,
3389 uint32_t base_layer
, uint32_t layer_count
);
3392 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3393 const struct anv_image
*image
,
3394 const VkImageAspectFlagBits aspect
,
3395 const VkImageLayout layout
);
3397 enum anv_fast_clear_type
3398 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3399 const struct anv_image
* const image
,
3400 const VkImageAspectFlagBits aspect
,
3401 const VkImageLayout layout
);
3403 /* This is defined as a macro so that it works for both
3404 * VkImageSubresourceRange and VkImageSubresourceLayers
3406 #define anv_get_layerCount(_image, _range) \
3407 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3408 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3410 static inline uint32_t
3411 anv_get_levelCount(const struct anv_image
*image
,
3412 const VkImageSubresourceRange
*range
)
3414 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3415 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3418 static inline VkImageAspectFlags
3419 anv_image_expand_aspects(const struct anv_image
*image
,
3420 VkImageAspectFlags aspects
)
3422 /* If the underlying image has color plane aspects and
3423 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3424 * the underlying image. */
3425 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3426 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3427 return image
->aspects
;
3433 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3434 VkImageAspectFlags aspects2
)
3436 if (aspects1
== aspects2
)
3439 /* Only 1 color aspects are compatibles. */
3440 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3441 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3442 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3448 struct anv_image_view
{
3449 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3451 VkImageAspectFlags aspect_mask
;
3453 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3457 uint32_t image_plane
;
3459 struct isl_view isl
;
3462 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3463 * image layout of SHADER_READ_ONLY_OPTIMAL or
3464 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3466 struct anv_surface_state optimal_sampler_surface_state
;
3469 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3470 * image layout of GENERAL.
3472 struct anv_surface_state general_sampler_surface_state
;
3475 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3476 * states for write-only and readable, using the real format for
3477 * write-only and the lowered format for readable.
3479 struct anv_surface_state storage_surface_state
;
3480 struct anv_surface_state writeonly_storage_surface_state
;
3482 struct brw_image_param storage_image_param
;
3486 enum anv_image_view_state_flags
{
3487 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3488 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3491 void anv_image_fill_surface_state(struct anv_device
*device
,
3492 const struct anv_image
*image
,
3493 VkImageAspectFlagBits aspect
,
3494 const struct isl_view
*view
,
3495 isl_surf_usage_flags_t view_usage
,
3496 enum isl_aux_usage aux_usage
,
3497 const union isl_color_value
*clear_color
,
3498 enum anv_image_view_state_flags flags
,
3499 struct anv_surface_state
*state_inout
,
3500 struct brw_image_param
*image_param_out
);
3502 struct anv_image_create_info
{
3503 const VkImageCreateInfo
*vk_info
;
3505 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3506 isl_tiling_flags_t isl_tiling_flags
;
3508 /** These flags will be added to any derived from VkImageCreateInfo. */
3509 isl_surf_usage_flags_t isl_extra_usage_flags
;
3512 bool external_format
;
3515 VkResult
anv_image_create(VkDevice _device
,
3516 const struct anv_image_create_info
*info
,
3517 const VkAllocationCallbacks
* alloc
,
3520 const struct anv_surface
*
3521 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3522 VkImageAspectFlags aspect_mask
);
3525 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3527 static inline struct VkExtent3D
3528 anv_sanitize_image_extent(const VkImageType imageType
,
3529 const struct VkExtent3D imageExtent
)
3531 switch (imageType
) {
3532 case VK_IMAGE_TYPE_1D
:
3533 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3534 case VK_IMAGE_TYPE_2D
:
3535 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3536 case VK_IMAGE_TYPE_3D
:
3539 unreachable("invalid image type");
3543 static inline struct VkOffset3D
3544 anv_sanitize_image_offset(const VkImageType imageType
,
3545 const struct VkOffset3D imageOffset
)
3547 switch (imageType
) {
3548 case VK_IMAGE_TYPE_1D
:
3549 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3550 case VK_IMAGE_TYPE_2D
:
3551 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3552 case VK_IMAGE_TYPE_3D
:
3555 unreachable("invalid image type");
3559 VkFormatFeatureFlags
3560 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3562 const struct anv_format
*anv_format
,
3563 VkImageTiling vk_tiling
);
3565 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3566 struct anv_state state
,
3567 enum isl_format format
,
3568 struct anv_address address
,
3569 uint32_t range
, uint32_t stride
);
3572 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3573 const struct anv_attachment_state
*att_state
,
3574 const struct anv_image_view
*iview
)
3576 const struct isl_format_layout
*view_fmtl
=
3577 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3579 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3580 if (view_fmtl->channels.c.bits) \
3581 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3583 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3584 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3585 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3586 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3588 #undef COPY_CLEAR_COLOR_CHANNEL
3592 struct anv_ycbcr_conversion
{
3593 const struct anv_format
* format
;
3594 VkSamplerYcbcrModelConversion ycbcr_model
;
3595 VkSamplerYcbcrRange ycbcr_range
;
3596 VkComponentSwizzle mapping
[4];
3597 VkChromaLocation chroma_offsets
[2];
3598 VkFilter chroma_filter
;
3599 bool chroma_reconstruction
;
3602 struct anv_sampler
{
3603 uint32_t state
[3][4];
3605 struct anv_ycbcr_conversion
*conversion
;
3607 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3608 * and with a 32-byte stride for use as bindless samplers.
3610 struct anv_state bindless_state
;
3613 struct anv_framebuffer
{
3618 uint32_t attachment_count
;
3619 struct anv_image_view
* attachments
[0];
3622 struct anv_subpass_attachment
{
3623 VkImageUsageFlagBits usage
;
3624 uint32_t attachment
;
3625 VkImageLayout layout
;
3628 struct anv_subpass
{
3629 uint32_t attachment_count
;
3632 * A pointer to all attachment references used in this subpass.
3633 * Only valid if ::attachment_count > 0.
3635 struct anv_subpass_attachment
* attachments
;
3636 uint32_t input_count
;
3637 struct anv_subpass_attachment
* input_attachments
;
3638 uint32_t color_count
;
3639 struct anv_subpass_attachment
* color_attachments
;
3640 struct anv_subpass_attachment
* resolve_attachments
;
3642 struct anv_subpass_attachment
* depth_stencil_attachment
;
3643 struct anv_subpass_attachment
* ds_resolve_attachment
;
3644 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3645 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3649 /** Subpass has a depth/stencil self-dependency */
3650 bool has_ds_self_dep
;
3652 /** Subpass has at least one color resolve attachment */
3653 bool has_color_resolve
;
3656 static inline unsigned
3657 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3659 return MAX2(1, util_bitcount(subpass
->view_mask
));
3662 struct anv_render_pass_attachment
{
3663 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3664 * its members individually.
3668 VkImageUsageFlags usage
;
3669 VkAttachmentLoadOp load_op
;
3670 VkAttachmentStoreOp store_op
;
3671 VkAttachmentLoadOp stencil_load_op
;
3672 VkImageLayout initial_layout
;
3673 VkImageLayout final_layout
;
3674 VkImageLayout first_subpass_layout
;
3676 /* The subpass id in which the attachment will be used last. */
3677 uint32_t last_subpass_idx
;
3680 struct anv_render_pass
{
3681 uint32_t attachment_count
;
3682 uint32_t subpass_count
;
3683 /* An array of subpass_count+1 flushes, one per subpass boundary */
3684 enum anv_pipe_bits
* subpass_flushes
;
3685 struct anv_render_pass_attachment
* attachments
;
3686 struct anv_subpass subpasses
[0];
3689 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3691 struct anv_query_pool
{
3693 VkQueryPipelineStatisticFlags pipeline_statistics
;
3694 /** Stride between slots, in bytes */
3696 /** Number of slots in this query pool */
3701 int anv_get_instance_entrypoint_index(const char *name
);
3702 int anv_get_device_entrypoint_index(const char *name
);
3703 int anv_get_physical_device_entrypoint_index(const char *name
);
3705 const char *anv_get_instance_entry_name(int index
);
3706 const char *anv_get_physical_device_entry_name(int index
);
3707 const char *anv_get_device_entry_name(int index
);
3710 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3711 const struct anv_instance_extension_table
*instance
);
3713 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3714 const struct anv_instance_extension_table
*instance
);
3716 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3717 const struct anv_instance_extension_table
*instance
,
3718 const struct anv_device_extension_table
*device
);
3720 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3723 void anv_dump_image_to_ppm(struct anv_device
*device
,
3724 struct anv_image
*image
, unsigned miplevel
,
3725 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3726 const char *filename
);
3728 enum anv_dump_action
{
3729 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3732 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3733 void anv_dump_finish(void);
3735 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
3737 static inline uint32_t
3738 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3740 /* This function must be called from within a subpass. */
3741 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3743 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3745 /* The id of this subpass shouldn't exceed the number of subpasses in this
3746 * render pass minus 1.
3748 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3752 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3754 static inline struct __anv_type * \
3755 __anv_type ## _from_handle(__VkType _handle) \
3757 return (struct __anv_type *) _handle; \
3760 static inline __VkType \
3761 __anv_type ## _to_handle(struct __anv_type *_obj) \
3763 return (__VkType) _obj; \
3766 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3768 static inline struct __anv_type * \
3769 __anv_type ## _from_handle(__VkType _handle) \
3771 return (struct __anv_type *)(uintptr_t) _handle; \
3774 static inline __VkType \
3775 __anv_type ## _to_handle(struct __anv_type *_obj) \
3777 return (__VkType)(uintptr_t) _obj; \
3780 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3781 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3783 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3784 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3785 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3786 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3787 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3789 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3790 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3791 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3792 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3793 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3794 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3795 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3796 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3797 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3798 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3799 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3800 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3801 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3802 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3803 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3804 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3805 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3806 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3807 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3808 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3809 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3810 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3811 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3813 /* Gen-specific function declarations */
3815 # include "anv_genX.h"
3817 # define genX(x) gen7_##x
3818 # include "anv_genX.h"
3820 # define genX(x) gen75_##x
3821 # include "anv_genX.h"
3823 # define genX(x) gen8_##x
3824 # include "anv_genX.h"
3826 # define genX(x) gen9_##x
3827 # include "anv_genX.h"
3829 # define genX(x) gen10_##x
3830 # include "anv_genX.h"
3832 # define genX(x) gen11_##x
3833 # include "anv_genX.h"
3835 # define genX(x) gen12_##x
3836 # include "anv_genX.h"
3840 #endif /* ANV_PRIVATE_H */