2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
62 #include "util/xmlconfig.h"
64 #include "vk_debug_report.h"
66 /* Pre-declarations needed for WSI entrypoints */
69 typedef struct xcb_connection_t xcb_connection_t
;
70 typedef uint32_t xcb_visualid_t
;
71 typedef uint32_t xcb_window_t
;
75 struct anv_buffer_view
;
76 struct anv_image_view
;
79 struct gen_aux_map_context
;
80 struct gen_perf_config
;
82 #include <vulkan/vulkan.h>
83 #include <vulkan/vulkan_intel.h>
84 #include <vulkan/vk_icd.h>
86 #include "anv_android.h"
87 #include "anv_entrypoints.h"
88 #include "anv_extensions.h"
91 #include "dev/gen_debug.h"
92 #include "common/intel_log.h"
93 #include "wsi_common.h"
95 #define NSEC_PER_SEC 1000000000ull
97 /* anv Virtual Memory Layout
98 * =========================
100 * When the anv driver is determining the virtual graphics addresses of memory
101 * objects itself using the softpin mechanism, the following memory ranges
104 * Three special considerations to notice:
106 * (1) the dynamic state pool is located within the same 4 GiB as the low
107 * heap. This is to work around a VF cache issue described in a comment in
108 * anv_physical_device_init_heaps.
110 * (2) the binding table pool is located at lower addresses than the surface
111 * state pool, within a 4 GiB range. This allows surface state base addresses
112 * to cover both binding tables (16 bit offsets) and surface states (32 bit
115 * (3) the last 4 GiB of the address space is withheld from the high
116 * heap. Various hardware units will read past the end of an object for
117 * various reasons. This healthy margin prevents reads from wrapping around
120 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
121 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
122 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
123 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
124 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
125 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
126 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
127 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
128 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
129 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
130 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
131 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
132 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
134 #define LOW_HEAP_SIZE \
135 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
136 #define DYNAMIC_STATE_POOL_SIZE \
137 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
138 #define BINDING_TABLE_POOL_SIZE \
139 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
140 #define SURFACE_STATE_POOL_SIZE \
141 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
142 #define INSTRUCTION_STATE_POOL_SIZE \
143 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
144 #define CLIENT_VISIBLE_HEAP_SIZE \
145 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
147 /* Allowing different clear colors requires us to perform a depth resolve at
148 * the end of certain render passes. This is because while slow clears store
149 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
150 * See the PRMs for examples describing when additional resolves would be
151 * necessary. To enable fast clears without requiring extra resolves, we set
152 * the clear value to a globally-defined one. We could allow different values
153 * if the user doesn't expect coherent data during or after a render passes
154 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
155 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
156 * 1.0f seems to be the only value used. The only application that doesn't set
157 * this value does so through the usage of an seemingly uninitialized clear
160 #define ANV_HZ_FC_VAL 1.0f
163 #define MAX_XFB_BUFFERS 4
164 #define MAX_XFB_STREAMS 4
167 #define MAX_VIEWPORTS 16
168 #define MAX_SCISSORS 16
169 #define MAX_PUSH_CONSTANTS_SIZE 128
170 #define MAX_DYNAMIC_BUFFERS 16
171 #define MAX_IMAGES 64
172 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
173 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
174 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
175 #define ANV_UBO_BOUNDS_CHECK_ALIGNMENT 32
176 #define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
177 #define MAX_VIEWS_FOR_PRIMITIVE_REPLICATION 16
179 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
181 * "The surface state model is used when a Binding Table Index (specified
182 * in the message descriptor) of less than 240 is specified. In this model,
183 * the Binding Table Index is used to index into the binding table, and the
184 * binding table entry contains a pointer to the SURFACE_STATE."
186 * Binding table values above 240 are used for various things in the hardware
187 * such as stateless, stateless with incoherent cache, SLM, and bindless.
189 #define MAX_BINDING_TABLE_SIZE 240
191 /* The kernel relocation API has a limitation of a 32-bit delta value
192 * applied to the address before it is written which, in spite of it being
193 * unsigned, is treated as signed . Because of the way that this maps to
194 * the Vulkan API, we cannot handle an offset into a buffer that does not
195 * fit into a signed 32 bits. The only mechanism we have for dealing with
196 * this at the moment is to limit all VkDeviceMemory objects to a maximum
197 * of 2GB each. The Vulkan spec allows us to do this:
199 * "Some platforms may have a limit on the maximum size of a single
200 * allocation. For example, certain systems may fail to create
201 * allocations with a size greater than or equal to 4GB. Such a limit is
202 * implementation-dependent, and if such a failure occurs then the error
203 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
205 * We don't use vk_error here because it's not an error so much as an
206 * indication to the application that the allocation is too large.
208 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
210 #define ANV_SVGS_VB_INDEX MAX_VBS
211 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
213 /* We reserve this MI ALU register for the purpose of handling predication.
214 * Other code which uses the MI ALU should leave it alone.
216 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
218 /* For gen12 we set the streamout buffers using 4 separate commands
219 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
220 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
221 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
222 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
223 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
224 * 3DSTATE_SO_BUFFER_INDEX_0.
226 #define SO_BUFFER_INDEX_0_CMD 0x60
227 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
229 static inline uint32_t
230 align_down_npot_u32(uint32_t v
, uint32_t a
)
235 static inline uint32_t
236 align_down_u32(uint32_t v
, uint32_t a
)
238 assert(a
!= 0 && a
== (a
& -a
));
242 static inline uint32_t
243 align_u32(uint32_t v
, uint32_t a
)
245 assert(a
!= 0 && a
== (a
& -a
));
246 return align_down_u32(v
+ a
- 1, a
);
249 static inline uint64_t
250 align_down_u64(uint64_t v
, uint64_t a
)
252 assert(a
!= 0 && a
== (a
& -a
));
256 static inline uint64_t
257 align_u64(uint64_t v
, uint64_t a
)
259 return align_down_u64(v
+ a
- 1, a
);
262 static inline int32_t
263 align_i32(int32_t v
, int32_t a
)
265 assert(a
!= 0 && a
== (a
& -a
));
266 return (v
+ a
- 1) & ~(a
- 1);
269 /** Alignment must be a power of 2. */
271 anv_is_aligned(uintmax_t n
, uintmax_t a
)
273 assert(a
== (a
& -a
));
274 return (n
& (a
- 1)) == 0;
277 static inline uint32_t
278 anv_minify(uint32_t n
, uint32_t levels
)
280 if (unlikely(n
== 0))
283 return MAX2(n
>> levels
, 1);
287 anv_clamp_f(float f
, float min
, float max
)
300 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
302 if (*inout_mask
& clear_mask
) {
303 *inout_mask
&= ~clear_mask
;
310 static inline union isl_color_value
311 vk_to_isl_color(VkClearColorValue color
)
313 return (union isl_color_value
) {
323 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
325 uintptr_t mask
= (1ull << bits
) - 1;
327 return (void *) (ptr
& ~mask
);
330 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
332 uintptr_t value
= (uintptr_t) ptr
;
333 uintptr_t mask
= (1ull << bits
) - 1;
334 return value
| (mask
& flags
);
337 #define for_each_bit(b, dword) \
338 for (uint32_t __dword = (dword); \
339 (b) = __builtin_ffs(__dword) - 1, __dword; \
340 __dword &= ~(1 << (b)))
342 #define typed_memcpy(dest, src, count) ({ \
343 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
344 memcpy((dest), (src), (count) * sizeof(*(src))); \
347 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
348 * to be added here in order to utilize mapping in debug/error/perf macros.
350 #define REPORT_OBJECT_TYPE(o) \
351 __builtin_choose_expr ( \
352 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
353 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
354 __builtin_choose_expr ( \
355 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
356 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
357 __builtin_choose_expr ( \
358 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
359 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
360 __builtin_choose_expr ( \
361 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
362 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
363 __builtin_choose_expr ( \
364 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
365 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
366 __builtin_choose_expr ( \
367 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
368 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
369 __builtin_choose_expr ( \
370 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
371 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
372 __builtin_choose_expr ( \
373 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
374 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
375 __builtin_choose_expr ( \
376 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
377 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
378 __builtin_choose_expr ( \
379 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
380 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
381 __builtin_choose_expr ( \
382 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
383 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
384 __builtin_choose_expr ( \
385 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
386 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
387 __builtin_choose_expr ( \
388 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
389 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
390 __builtin_choose_expr ( \
391 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
392 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
393 __builtin_choose_expr ( \
394 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
395 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
396 __builtin_choose_expr ( \
397 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
398 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
399 __builtin_choose_expr ( \
400 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
401 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
402 __builtin_choose_expr ( \
403 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
404 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
405 __builtin_choose_expr ( \
406 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
407 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
408 __builtin_choose_expr ( \
409 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
410 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
411 __builtin_choose_expr ( \
412 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
413 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
414 __builtin_choose_expr ( \
415 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
416 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
417 __builtin_choose_expr ( \
418 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
419 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
420 __builtin_choose_expr ( \
421 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
422 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
423 __builtin_choose_expr ( \
424 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
425 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
426 __builtin_choose_expr ( \
427 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
428 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
429 __builtin_choose_expr ( \
430 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
431 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
432 __builtin_choose_expr ( \
433 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
434 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
435 __builtin_choose_expr ( \
436 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
437 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
438 __builtin_choose_expr ( \
439 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
440 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
441 __builtin_choose_expr ( \
442 __builtin_types_compatible_p (__typeof (o), void*), \
443 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
444 /* The void expression results in a compile-time error \
445 when assigning the result to something. */ \
446 (void)0)))))))))))))))))))))))))))))))
448 /* Whenever we generate an error, pass it through this function. Useful for
449 * debugging, where we can break on it. Only call at error site, not when
450 * propagating errors. Might be useful to plug in a stack trace here.
453 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
454 VkDebugReportObjectTypeEXT type
, VkResult error
,
455 const char *file
, int line
, const char *format
,
458 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
459 VkDebugReportObjectTypeEXT type
, VkResult error
,
460 const char *file
, int line
, const char *format
, ...)
461 anv_printflike(7, 8);
464 #define vk_error(error) __vk_errorf(NULL, NULL,\
465 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
466 error, __FILE__, __LINE__, NULL)
467 #define vk_errorfi(instance, obj, error, format, ...)\
468 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
469 __FILE__, __LINE__, format, ## __VA_ARGS__)
470 #define vk_errorf(device, obj, error, format, ...)\
471 vk_errorfi(anv_device_instance_or_null(device),\
472 obj, error, format, ## __VA_ARGS__)
474 #define vk_error(error) error
475 #define vk_errorfi(instance, obj, error, format, ...) error
476 #define vk_errorf(device, obj, error, format, ...) error
480 * Warn on ignored extension structs.
482 * The Vulkan spec requires us to ignore unsupported or unknown structs in
483 * a pNext chain. In debug mode, emitting warnings for ignored structs may
484 * help us discover structs that we should not have ignored.
487 * From the Vulkan 1.0.38 spec:
489 * Any component of the implementation (the loader, any enabled layers,
490 * and drivers) must skip over, without processing (other than reading the
491 * sType and pNext members) any chained structures with sType values not
492 * defined by extensions supported by that component.
494 #define anv_debug_ignored_stype(sType) \
495 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
497 void __anv_perf_warn(struct anv_device
*device
, const void *object
,
498 VkDebugReportObjectTypeEXT type
, const char *file
,
499 int line
, const char *format
, ...)
500 anv_printflike(6, 7);
501 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
502 void anv_loge_v(const char *format
, va_list va
);
505 * Print a FINISHME message, including its source location.
507 #define anv_finishme(format, ...) \
509 static bool reported = false; \
511 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
518 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
520 #define anv_perf_warn(instance, obj, format, ...) \
522 static bool reported = false; \
523 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
524 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
525 format, ##__VA_ARGS__); \
530 /* A non-fatal assert. Useful for debugging. */
532 #define anv_assert(x) ({ \
533 if (unlikely(!(x))) \
534 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
537 #define anv_assert(x)
540 /* A multi-pointer allocator
542 * When copying data structures from the user (such as a render pass), it's
543 * common to need to allocate data for a bunch of different things. Instead
544 * of doing several allocations and having to handle all of the error checking
545 * that entails, it can be easier to do a single allocation. This struct
546 * helps facilitate that. The intended usage looks like this:
549 * anv_multialloc_add(&ma, &main_ptr, 1);
550 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
551 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
553 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
554 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
556 struct anv_multialloc
{
564 #define ANV_MULTIALLOC_INIT \
565 ((struct anv_multialloc) { 0, })
567 #define ANV_MULTIALLOC(_name) \
568 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
570 __attribute__((always_inline
))
572 _anv_multialloc_add(struct anv_multialloc
*ma
,
573 void **ptr
, size_t size
, size_t align
)
575 size_t offset
= align_u64(ma
->size
, align
);
576 ma
->size
= offset
+ size
;
577 ma
->align
= MAX2(ma
->align
, align
);
579 /* Store the offset in the pointer. */
580 *ptr
= (void *)(uintptr_t)offset
;
582 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
583 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
586 #define anv_multialloc_add_size(_ma, _ptr, _size) \
587 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
589 #define anv_multialloc_add(_ma, _ptr, _count) \
590 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
592 __attribute__((always_inline
))
594 anv_multialloc_alloc(struct anv_multialloc
*ma
,
595 const VkAllocationCallbacks
*alloc
,
596 VkSystemAllocationScope scope
)
598 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
602 /* Fill out each of the pointers with their final value.
604 * for (uint32_t i = 0; i < ma->ptr_count; i++)
605 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
607 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
608 * constant, GCC is incapable of figuring this out and unrolling the loop
609 * so we have to give it a little help.
611 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
612 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
613 if ((_i) < ma->ptr_count) \
614 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
615 _ANV_MULTIALLOC_UPDATE_POINTER(0);
616 _ANV_MULTIALLOC_UPDATE_POINTER(1);
617 _ANV_MULTIALLOC_UPDATE_POINTER(2);
618 _ANV_MULTIALLOC_UPDATE_POINTER(3);
619 _ANV_MULTIALLOC_UPDATE_POINTER(4);
620 _ANV_MULTIALLOC_UPDATE_POINTER(5);
621 _ANV_MULTIALLOC_UPDATE_POINTER(6);
622 _ANV_MULTIALLOC_UPDATE_POINTER(7);
623 #undef _ANV_MULTIALLOC_UPDATE_POINTER
628 __attribute__((always_inline
))
630 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
631 const VkAllocationCallbacks
*parent_alloc
,
632 const VkAllocationCallbacks
*alloc
,
633 VkSystemAllocationScope scope
)
635 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
643 /* Index into the current validation list. This is used by the
644 * validation list building alrogithm to track which buffers are already
645 * in the validation list so that we can ensure uniqueness.
649 /* Index for use with util_sparse_array_free_list */
652 /* Last known offset. This value is provided by the kernel when we
653 * execbuf and is used as the presumed offset for the next bunch of
658 /** Size of the buffer not including implicit aux */
661 /* Map for internally mapped BOs.
663 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
667 /** Size of the implicit CCS range at the end of the buffer
669 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
670 * page of main surface data maps to a 256B chunk of CCS data and that
671 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
672 * addresses in the main surface to virtual memory addresses for CCS data.
674 * Because we can't change these maps around easily and because Vulkan
675 * allows two VkImages to be bound to overlapping memory regions (as long
676 * as the app is careful), it's not feasible to make this mapping part of
677 * the image. (On Gen11 and earlier, the mapping was provided via
678 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
679 * Instead, we attach the CCS data directly to the buffer object and setup
680 * the AUX table mapping at BO creation time.
682 * This field is for internal tracking use by the BO allocator only and
683 * should not be touched by other parts of the code. If something wants to
684 * know if a BO has implicit CCS data, it should instead look at the
685 * has_implicit_ccs boolean below.
687 * This data is not included in maps of this buffer.
691 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
694 /** True if this BO may be shared with other processes */
697 /** True if this BO is a wrapper
699 * When set to true, none of the fields in this BO are meaningful except
700 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
701 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
702 * is set in the physical device.
706 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
707 bool has_fixed_address
:1;
709 /** True if this BO wraps a host pointer */
710 bool from_host_ptr
:1;
712 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
713 bool has_client_visible_address
:1;
715 /** True if this BO has implicit CCS data attached to it */
716 bool has_implicit_ccs
:1;
719 static inline struct anv_bo
*
720 anv_bo_ref(struct anv_bo
*bo
)
722 p_atomic_inc(&bo
->refcount
);
726 static inline struct anv_bo
*
727 anv_bo_unwrap(struct anv_bo
*bo
)
729 while (bo
->is_wrapper
)
734 /* Represents a lock-free linked list of "free" things. This is used by
735 * both the block pool and the state pools. Unfortunately, in order to
736 * solve the ABA problem, we can't use a single uint32_t head.
738 union anv_free_list
{
742 /* A simple count that is incremented every time the head changes. */
745 /* Make sure it's aligned to 64 bits. This will make atomic operations
746 * faster on 32 bit platforms.
748 uint64_t u64
__attribute__ ((aligned (8)));
751 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
753 struct anv_block_state
{
759 /* Make sure it's aligned to 64 bits. This will make atomic operations
760 * faster on 32 bit platforms.
762 uint64_t u64
__attribute__ ((aligned (8)));
766 #define anv_block_pool_foreach_bo(bo, pool) \
767 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
768 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
771 #define ANV_MAX_BLOCK_POOL_BOS 20
773 struct anv_block_pool
{
774 struct anv_device
*device
;
777 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
778 * around the actual BO so that we grow the pool after the wrapper BO has
779 * been put in a relocation list. This is only used in the non-softpin
782 struct anv_bo wrapper_bo
;
784 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
790 /* The address where the start of the pool is pinned. The various bos that
791 * are created as the pool grows will have addresses in the range
792 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
794 uint64_t start_address
;
796 /* The offset from the start of the bo to the "center" of the block
797 * pool. Pointers to allocated blocks are given by
798 * bo.map + center_bo_offset + offsets.
800 uint32_t center_bo_offset
;
802 /* Current memory map of the block pool. This pointer may or may not
803 * point to the actual beginning of the block pool memory. If
804 * anv_block_pool_alloc_back has ever been called, then this pointer
805 * will point to the "center" position of the buffer and all offsets
806 * (negative or positive) given out by the block pool alloc functions
807 * will be valid relative to this pointer.
809 * In particular, map == bo.map + center_offset
811 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
812 * since it will handle the softpin case as well, where this points to NULL.
818 * Array of mmaps and gem handles owned by the block pool, reclaimed when
819 * the block pool is destroyed.
821 struct u_vector mmap_cleanups
;
823 struct anv_block_state state
;
825 struct anv_block_state back_state
;
828 /* Block pools are backed by a fixed-size 1GB memfd */
829 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
831 /* The center of the block pool is also the middle of the memfd. This may
832 * change in the future if we decide differently for some reason.
834 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
836 static inline uint32_t
837 anv_block_pool_size(struct anv_block_pool
*pool
)
839 return pool
->state
.end
+ pool
->back_state
.end
;
849 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
851 struct anv_fixed_size_state_pool
{
852 union anv_free_list free_list
;
853 struct anv_block_state block
;
856 #define ANV_MIN_STATE_SIZE_LOG2 6
857 #define ANV_MAX_STATE_SIZE_LOG2 21
859 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
861 struct anv_free_entry
{
863 struct anv_state state
;
866 struct anv_state_table
{
867 struct anv_device
*device
;
869 struct anv_free_entry
*map
;
871 struct anv_block_state state
;
872 struct u_vector cleanups
;
875 struct anv_state_pool
{
876 struct anv_block_pool block_pool
;
878 struct anv_state_table table
;
880 /* The size of blocks which will be allocated from the block pool */
883 /** Free list for "back" allocations */
884 union anv_free_list back_alloc_free_list
;
886 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
889 struct anv_state_stream
{
890 struct anv_state_pool
*state_pool
;
892 /* The size of blocks to allocate from the state pool */
895 /* Current block we're allocating from */
896 struct anv_state block
;
898 /* Offset into the current block at which to allocate the next state */
901 /* List of all blocks allocated from this pool */
902 struct util_dynarray all_blocks
;
905 /* The block_pool functions exported for testing only. The block pool should
906 * only be used via a state pool (see below).
908 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
909 struct anv_device
*device
,
910 uint64_t start_address
,
911 uint32_t initial_size
);
912 void anv_block_pool_finish(struct anv_block_pool
*pool
);
913 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
914 uint32_t block_size
, uint32_t *padding
);
915 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
916 uint32_t block_size
);
917 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
, uint32_t
920 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
921 struct anv_device
*device
,
922 uint64_t start_address
,
923 uint32_t block_size
);
924 void anv_state_pool_finish(struct anv_state_pool
*pool
);
925 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
926 uint32_t state_size
, uint32_t alignment
);
927 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
928 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
929 void anv_state_stream_init(struct anv_state_stream
*stream
,
930 struct anv_state_pool
*state_pool
,
931 uint32_t block_size
);
932 void anv_state_stream_finish(struct anv_state_stream
*stream
);
933 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
934 uint32_t size
, uint32_t alignment
);
936 VkResult
anv_state_table_init(struct anv_state_table
*table
,
937 struct anv_device
*device
,
938 uint32_t initial_entries
);
939 void anv_state_table_finish(struct anv_state_table
*table
);
940 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
942 void anv_free_list_push(union anv_free_list
*list
,
943 struct anv_state_table
*table
,
944 uint32_t idx
, uint32_t count
);
945 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
946 struct anv_state_table
*table
);
949 static inline struct anv_state
*
950 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
952 return &table
->map
[idx
].state
;
955 * Implements a pool of re-usable BOs. The interface is identical to that
956 * of block_pool except that each block is its own BO.
959 struct anv_device
*device
;
961 struct util_sparse_array_free_list free_list
[16];
964 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
965 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
966 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
967 struct anv_bo
**bo_out
);
968 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
970 struct anv_scratch_pool
{
971 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
972 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
975 void anv_scratch_pool_init(struct anv_device
*device
,
976 struct anv_scratch_pool
*pool
);
977 void anv_scratch_pool_finish(struct anv_device
*device
,
978 struct anv_scratch_pool
*pool
);
979 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
980 struct anv_scratch_pool
*pool
,
981 gl_shader_stage stage
,
982 unsigned per_thread_scratch
);
984 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
985 struct anv_bo_cache
{
986 struct util_sparse_array bo_map
;
987 pthread_mutex_t mutex
;
990 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
991 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
993 struct anv_memory_type
{
994 /* Standard bits passed on to the client */
995 VkMemoryPropertyFlags propertyFlags
;
999 struct anv_memory_heap
{
1000 /* Standard bits passed on to the client */
1002 VkMemoryHeapFlags flags
;
1004 /* Driver-internal book-keeping */
1008 struct anv_physical_device
{
1009 VK_LOADER_DATA _loader_data
;
1011 /* Link in anv_instance::physical_devices */
1012 struct list_head link
;
1014 struct anv_instance
* instance
;
1024 struct gen_device_info info
;
1025 /** Amount of "GPU memory" we want to advertise
1027 * Clearly, this value is bogus since Intel is a UMA architecture. On
1028 * gen7 platforms, we are limited by GTT size unless we want to implement
1029 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1030 * practically unlimited. However, we will never report more than 3/4 of
1031 * the total system ram to try and avoid running out of RAM.
1033 bool supports_48bit_addresses
;
1034 struct brw_compiler
* compiler
;
1035 struct isl_device isl_dev
;
1036 struct gen_perf_config
* perf
;
1037 int cmd_parser_version
;
1039 bool has_exec_async
;
1040 bool has_exec_capture
;
1041 bool has_exec_fence
;
1043 bool has_syncobj_wait
;
1044 bool has_context_priority
;
1045 bool has_context_isolation
;
1046 bool has_mem_available
;
1050 bool always_use_bindless
;
1052 /** True if we can access buffers using A64 messages */
1053 bool has_a64_buffer_access
;
1054 /** True if we can use bindless access for images */
1055 bool has_bindless_images
;
1056 /** True if we can use bindless access for samplers */
1057 bool has_bindless_samplers
;
1059 /** True if this device has implicit AUX
1061 * If true, CCS is handled as an implicit attachment to the BO rather than
1062 * as an explicitly bound surface.
1064 bool has_implicit_ccs
;
1066 bool always_flush_cache
;
1068 struct anv_device_extension_table supported_extensions
;
1071 uint32_t subslice_total
;
1074 uint32_t type_count
;
1075 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1076 uint32_t heap_count
;
1077 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1080 uint8_t driver_build_sha1
[20];
1081 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1082 uint8_t driver_uuid
[VK_UUID_SIZE
];
1083 uint8_t device_uuid
[VK_UUID_SIZE
];
1085 struct disk_cache
* disk_cache
;
1087 struct wsi_device wsi_device
;
1092 struct anv_app_info
{
1093 const char* app_name
;
1094 uint32_t app_version
;
1095 const char* engine_name
;
1096 uint32_t engine_version
;
1097 uint32_t api_version
;
1100 struct anv_instance
{
1101 VK_LOADER_DATA _loader_data
;
1103 VkAllocationCallbacks alloc
;
1105 struct anv_app_info app_info
;
1107 struct anv_instance_extension_table enabled_extensions
;
1108 struct anv_instance_dispatch_table dispatch
;
1109 struct anv_physical_device_dispatch_table physical_device_dispatch
;
1110 struct anv_device_dispatch_table device_dispatch
;
1112 bool physical_devices_enumerated
;
1113 struct list_head physical_devices
;
1115 bool pipeline_cache_enabled
;
1117 struct vk_debug_report_instance debug_report_callbacks
;
1119 struct driOptionCache dri_options
;
1120 struct driOptionCache available_dri_options
;
1123 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1124 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1126 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1127 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1130 struct anv_queue_submit
{
1131 struct anv_cmd_buffer
* cmd_buffer
;
1133 uint32_t fence_count
;
1134 uint32_t fence_array_length
;
1135 struct drm_i915_gem_exec_fence
* fences
;
1137 uint32_t temporary_semaphore_count
;
1138 uint32_t temporary_semaphore_array_length
;
1139 struct anv_semaphore_impl
* temporary_semaphores
;
1141 /* Semaphores to be signaled with a SYNC_FD. */
1142 struct anv_semaphore
** sync_fd_semaphores
;
1143 uint32_t sync_fd_semaphore_count
;
1144 uint32_t sync_fd_semaphore_array_length
;
1146 /* Allocated only with non shareable timelines. */
1147 struct anv_timeline
** wait_timelines
;
1148 uint32_t wait_timeline_count
;
1149 uint32_t wait_timeline_array_length
;
1150 uint64_t * wait_timeline_values
;
1152 struct anv_timeline
** signal_timelines
;
1153 uint32_t signal_timeline_count
;
1154 uint32_t signal_timeline_array_length
;
1155 uint64_t * signal_timeline_values
;
1158 bool need_out_fence
;
1161 uint32_t fence_bo_count
;
1162 uint32_t fence_bo_array_length
;
1163 /* An array of struct anv_bo pointers with lower bit used as a flag to
1164 * signal we will wait on that BO (see anv_(un)pack_ptr).
1166 uintptr_t * fence_bos
;
1168 const VkAllocationCallbacks
* alloc
;
1169 VkSystemAllocationScope alloc_scope
;
1171 struct anv_bo
* simple_bo
;
1172 uint32_t simple_bo_size
;
1174 struct list_head link
;
1178 VK_LOADER_DATA _loader_data
;
1180 struct anv_device
* device
;
1183 * A list of struct anv_queue_submit to be submitted to i915.
1185 struct list_head queued_submits
;
1187 VkDeviceQueueCreateFlags flags
;
1190 struct anv_pipeline_cache
{
1191 struct anv_device
* device
;
1192 pthread_mutex_t mutex
;
1194 struct hash_table
* nir_cache
;
1196 struct hash_table
* cache
;
1199 struct nir_xfb_info
;
1200 struct anv_pipeline_bind_map
;
1202 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1203 struct anv_device
*device
,
1204 bool cache_enabled
);
1205 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1207 struct anv_shader_bin
*
1208 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1209 const void *key
, uint32_t key_size
);
1210 struct anv_shader_bin
*
1211 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1212 gl_shader_stage stage
,
1213 const void *key_data
, uint32_t key_size
,
1214 const void *kernel_data
, uint32_t kernel_size
,
1215 const void *constant_data
,
1216 uint32_t constant_data_size
,
1217 const struct brw_stage_prog_data
*prog_data
,
1218 uint32_t prog_data_size
,
1219 const struct brw_compile_stats
*stats
,
1221 const struct nir_xfb_info
*xfb_info
,
1222 const struct anv_pipeline_bind_map
*bind_map
);
1224 struct anv_shader_bin
*
1225 anv_device_search_for_kernel(struct anv_device
*device
,
1226 struct anv_pipeline_cache
*cache
,
1227 const void *key_data
, uint32_t key_size
,
1228 bool *user_cache_bit
);
1230 struct anv_shader_bin
*
1231 anv_device_upload_kernel(struct anv_device
*device
,
1232 struct anv_pipeline_cache
*cache
,
1233 gl_shader_stage stage
,
1234 const void *key_data
, uint32_t key_size
,
1235 const void *kernel_data
, uint32_t kernel_size
,
1236 const void *constant_data
,
1237 uint32_t constant_data_size
,
1238 const struct brw_stage_prog_data
*prog_data
,
1239 uint32_t prog_data_size
,
1240 const struct brw_compile_stats
*stats
,
1242 const struct nir_xfb_info
*xfb_info
,
1243 const struct anv_pipeline_bind_map
*bind_map
);
1246 struct nir_shader_compiler_options
;
1249 anv_device_search_for_nir(struct anv_device
*device
,
1250 struct anv_pipeline_cache
*cache
,
1251 const struct nir_shader_compiler_options
*nir_options
,
1252 unsigned char sha1_key
[20],
1256 anv_device_upload_nir(struct anv_device
*device
,
1257 struct anv_pipeline_cache
*cache
,
1258 const struct nir_shader
*nir
,
1259 unsigned char sha1_key
[20]);
1262 VK_LOADER_DATA _loader_data
;
1264 VkAllocationCallbacks alloc
;
1266 struct anv_physical_device
* physical
;
1268 struct gen_device_info info
;
1269 struct isl_device isl_dev
;
1272 bool can_chain_batches
;
1273 bool robust_buffer_access
;
1274 struct anv_device_extension_table enabled_extensions
;
1275 struct anv_device_dispatch_table dispatch
;
1277 pthread_mutex_t vma_mutex
;
1278 struct util_vma_heap vma_lo
;
1279 struct util_vma_heap vma_cva
;
1280 struct util_vma_heap vma_hi
;
1282 /** List of all anv_device_memory objects */
1283 struct list_head memory_objects
;
1285 struct anv_bo_pool batch_bo_pool
;
1287 struct anv_bo_cache bo_cache
;
1289 struct anv_state_pool dynamic_state_pool
;
1290 struct anv_state_pool instruction_state_pool
;
1291 struct anv_state_pool binding_table_pool
;
1292 struct anv_state_pool surface_state_pool
;
1294 struct anv_bo
* workaround_bo
;
1295 struct anv_bo
* trivial_batch_bo
;
1296 struct anv_bo
* hiz_clear_bo
;
1298 struct anv_pipeline_cache default_pipeline_cache
;
1299 struct blorp_context blorp
;
1301 struct anv_state border_colors
;
1303 struct anv_state slice_hash
;
1305 struct anv_queue queue
;
1307 struct anv_scratch_pool scratch_pool
;
1309 pthread_mutex_t mutex
;
1310 pthread_cond_t queue_submit
;
1313 struct gen_batch_decode_ctx decoder_ctx
;
1315 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1316 * the cmd_buffer's list.
1318 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1320 int perf_fd
; /* -1 if no opened */
1321 uint64_t perf_metric
; /* 0 if unset */
1323 struct gen_aux_map_context
*aux_map_ctx
;
1326 static inline struct anv_instance
*
1327 anv_device_instance_or_null(const struct anv_device
*device
)
1329 return device
? device
->physical
->instance
: NULL
;
1332 static inline struct anv_state_pool
*
1333 anv_binding_table_pool(struct anv_device
*device
)
1335 if (device
->physical
->use_softpin
)
1336 return &device
->binding_table_pool
;
1338 return &device
->surface_state_pool
;
1341 static inline struct anv_state
1342 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1343 if (device
->physical
->use_softpin
)
1344 return anv_state_pool_alloc(&device
->binding_table_pool
,
1345 device
->binding_table_pool
.block_size
, 0);
1347 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1351 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1352 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1355 static inline uint32_t
1356 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1358 if (bo
->is_external
)
1359 return device
->isl_dev
.mocs
.external
;
1361 return device
->isl_dev
.mocs
.internal
;
1364 void anv_device_init_blorp(struct anv_device
*device
);
1365 void anv_device_finish_blorp(struct anv_device
*device
);
1367 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1368 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1369 const char *file
, int line
,
1370 const char *msg
, ...)
1371 anv_printflike(4, 5);
1372 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1373 const char *file
, int line
,
1374 const char *msg
, ...)
1375 anv_printflike(4, 5);
1376 #define anv_device_set_lost(dev, ...) \
1377 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1378 #define anv_queue_set_lost(queue, ...) \
1379 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1382 anv_device_is_lost(struct anv_device
*device
)
1384 return unlikely(p_atomic_read(&device
->_lost
));
1387 VkResult
anv_device_query_status(struct anv_device
*device
);
1390 enum anv_bo_alloc_flags
{
1391 /** Specifies that the BO must have a 32-bit address
1393 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1395 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1397 /** Specifies that the BO may be shared externally */
1398 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1400 /** Specifies that the BO should be mapped */
1401 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1403 /** Specifies that the BO should be snooped so we get coherency */
1404 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1406 /** Specifies that the BO should be captured in error states */
1407 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1409 /** Specifies that the BO will have an address assigned by the caller
1411 * Such BOs do not exist in any VMA heap.
1413 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1415 /** Enables implicit synchronization on the BO
1417 * This is the opposite of EXEC_OBJECT_ASYNC.
1419 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1421 /** Enables implicit synchronization on the BO
1423 * This is equivalent to EXEC_OBJECT_WRITE.
1425 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1427 /** Has an address which is visible to the client */
1428 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS
= (1 << 8),
1430 /** This buffer has implicit CCS data attached to it */
1431 ANV_BO_ALLOC_IMPLICIT_CCS
= (1 << 9),
1434 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1435 enum anv_bo_alloc_flags alloc_flags
,
1436 uint64_t explicit_address
,
1437 struct anv_bo
**bo
);
1438 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1439 void *host_ptr
, uint32_t size
,
1440 enum anv_bo_alloc_flags alloc_flags
,
1441 uint64_t client_address
,
1442 struct anv_bo
**bo_out
);
1443 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1444 enum anv_bo_alloc_flags alloc_flags
,
1445 uint64_t client_address
,
1446 struct anv_bo
**bo
);
1447 VkResult
anv_device_export_bo(struct anv_device
*device
,
1448 struct anv_bo
*bo
, int *fd_out
);
1449 void anv_device_release_bo(struct anv_device
*device
,
1452 static inline struct anv_bo
*
1453 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1455 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1458 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1459 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1462 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1463 void anv_queue_finish(struct anv_queue
*queue
);
1465 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1466 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1467 struct anv_batch
*batch
);
1469 uint64_t anv_gettime_ns(void);
1470 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1472 void* anv_gem_mmap(struct anv_device
*device
,
1473 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1474 void anv_gem_munmap(void *p
, uint64_t size
);
1475 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1476 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1477 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1478 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1479 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1480 int anv_gem_execbuffer(struct anv_device
*device
,
1481 struct drm_i915_gem_execbuffer2
*execbuf
);
1482 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1483 uint32_t stride
, uint32_t tiling
);
1484 int anv_gem_create_context(struct anv_device
*device
);
1485 bool anv_gem_has_context_priority(int fd
);
1486 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1487 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1489 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1491 int anv_gem_get_param(int fd
, uint32_t param
);
1492 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1493 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1494 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1495 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1496 uint32_t *active
, uint32_t *pending
);
1497 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1498 int anv_gem_reg_read(struct anv_device
*device
,
1499 uint32_t offset
, uint64_t *result
);
1500 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1501 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1502 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1503 uint32_t read_domains
, uint32_t write_domain
);
1504 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1505 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1506 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1507 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1508 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1509 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1511 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1512 uint32_t handle
, int fd
);
1513 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1514 bool anv_gem_supports_syncobj_wait(int fd
);
1515 int anv_gem_syncobj_wait(struct anv_device
*device
,
1516 uint32_t *handles
, uint32_t num_handles
,
1517 int64_t abs_timeout_ns
, bool wait_all
);
1519 uint64_t anv_vma_alloc(struct anv_device
*device
,
1520 uint64_t size
, uint64_t align
,
1521 enum anv_bo_alloc_flags alloc_flags
,
1522 uint64_t client_address
);
1523 void anv_vma_free(struct anv_device
*device
,
1524 uint64_t address
, uint64_t size
);
1526 struct anv_reloc_list
{
1527 uint32_t num_relocs
;
1528 uint32_t array_length
;
1529 struct drm_i915_gem_relocation_entry
* relocs
;
1530 struct anv_bo
** reloc_bos
;
1535 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1536 const VkAllocationCallbacks
*alloc
);
1537 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1538 const VkAllocationCallbacks
*alloc
);
1540 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1541 const VkAllocationCallbacks
*alloc
,
1542 uint32_t offset
, struct anv_bo
*target_bo
,
1543 uint32_t delta
, uint64_t *address_u64_out
);
1545 struct anv_batch_bo
{
1546 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1547 struct list_head link
;
1551 /* Bytes actually consumed in this batch BO */
1554 struct anv_reloc_list relocs
;
1558 const VkAllocationCallbacks
* alloc
;
1564 struct anv_reloc_list
* relocs
;
1566 /* This callback is called (with the associated user data) in the event
1567 * that the batch runs out of space.
1569 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1573 * Current error status of the command buffer. Used to track inconsistent
1574 * or incomplete command buffer states that are the consequence of run-time
1575 * errors such as out of memory scenarios. We want to track this in the
1576 * batch because the command buffer object is not visible to some parts
1582 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1583 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1584 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1585 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1587 static inline VkResult
1588 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1590 assert(error
!= VK_SUCCESS
);
1591 if (batch
->status
== VK_SUCCESS
)
1592 batch
->status
= error
;
1593 return batch
->status
;
1597 anv_batch_has_error(struct anv_batch
*batch
)
1599 return batch
->status
!= VK_SUCCESS
;
1602 struct anv_address
{
1607 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1610 anv_address_is_null(struct anv_address addr
)
1612 return addr
.bo
== NULL
&& addr
.offset
== 0;
1615 static inline uint64_t
1616 anv_address_physical(struct anv_address addr
)
1618 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1619 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1621 return gen_canonical_address(addr
.offset
);
1624 static inline struct anv_address
1625 anv_address_add(struct anv_address addr
, uint64_t offset
)
1627 addr
.offset
+= offset
;
1632 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1634 unsigned reloc_size
= 0;
1635 if (device
->info
.gen
>= 8) {
1636 reloc_size
= sizeof(uint64_t);
1637 *(uint64_t *)p
= gen_canonical_address(v
);
1639 reloc_size
= sizeof(uint32_t);
1643 if (flush
&& !device
->info
.has_llc
)
1644 gen_flush_range(p
, reloc_size
);
1647 static inline uint64_t
1648 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1649 const struct anv_address address
, uint32_t delta
)
1651 if (address
.bo
== NULL
) {
1652 return address
.offset
+ delta
;
1654 assert(batch
->start
<= location
&& location
< batch
->end
);
1656 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1660 #define __gen_address_type struct anv_address
1661 #define __gen_user_data struct anv_batch
1662 #define __gen_combine_address _anv_combine_address
1664 /* Wrapper macros needed to work around preprocessor argument issues. In
1665 * particular, arguments don't get pre-evaluated if they are concatenated.
1666 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1667 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1668 * We can work around this easily enough with these helpers.
1670 #define __anv_cmd_length(cmd) cmd ## _length
1671 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1672 #define __anv_cmd_header(cmd) cmd ## _header
1673 #define __anv_cmd_pack(cmd) cmd ## _pack
1674 #define __anv_reg_num(reg) reg ## _num
1676 #define anv_pack_struct(dst, struc, ...) do { \
1677 struct struc __template = { \
1680 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1681 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1684 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1685 void *__dst = anv_batch_emit_dwords(batch, n); \
1687 struct cmd __template = { \
1688 __anv_cmd_header(cmd), \
1689 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1692 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1697 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1701 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1702 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1705 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1706 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1707 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1710 #define anv_batch_emit(batch, cmd, name) \
1711 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1712 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1713 __builtin_expect(_dst != NULL, 1); \
1714 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1715 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1719 struct anv_device_memory
{
1720 struct list_head link
;
1723 struct anv_memory_type
* type
;
1724 VkDeviceSize map_size
;
1727 /* If set, we are holding reference to AHardwareBuffer
1728 * which we must release when memory is freed.
1730 struct AHardwareBuffer
* ahw
;
1732 /* If set, this memory comes from a host pointer. */
1737 * Header for Vertex URB Entry (VUE)
1739 struct anv_vue_header
{
1741 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1742 uint32_t ViewportIndex
;
1746 /** Struct representing a sampled image descriptor
1748 * This descriptor layout is used for sampled images, bare sampler, and
1749 * combined image/sampler descriptors.
1751 struct anv_sampled_image_descriptor
{
1752 /** Bindless image handle
1754 * This is expected to already be shifted such that the 20-bit
1755 * SURFACE_STATE table index is in the top 20 bits.
1759 /** Bindless sampler handle
1761 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1762 * to the dynamic state base address.
1767 struct anv_texture_swizzle_descriptor
{
1770 * See also nir_intrinsic_channel_select_intel
1774 /** Unused padding to ensure the struct is a multiple of 64 bits */
1778 /** Struct representing a storage image descriptor */
1779 struct anv_storage_image_descriptor
{
1780 /** Bindless image handles
1782 * These are expected to already be shifted such that the 20-bit
1783 * SURFACE_STATE table index is in the top 20 bits.
1785 uint32_t read_write
;
1786 uint32_t write_only
;
1789 /** Struct representing a address/range descriptor
1791 * The fields of this struct correspond directly to the data layout of
1792 * nir_address_format_64bit_bounded_global addresses. The last field is the
1793 * offset in the NIR address so it must be zero so that when you load the
1794 * descriptor you get a pointer to the start of the range.
1796 struct anv_address_range_descriptor
{
1802 enum anv_descriptor_data
{
1803 /** The descriptor contains a BTI reference to a surface state */
1804 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1805 /** The descriptor contains a BTI reference to a sampler state */
1806 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1807 /** The descriptor contains an actual buffer view */
1808 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1809 /** The descriptor contains auxiliary image layout data */
1810 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1811 /** The descriptor contains auxiliary image layout data */
1812 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1813 /** anv_address_range_descriptor with a buffer address and range */
1814 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1815 /** Bindless surface handle */
1816 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1817 /** Storage image handles */
1818 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1819 /** Storage image handles */
1820 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1823 struct anv_descriptor_set_binding_layout
{
1825 /* The type of the descriptors in this binding */
1826 VkDescriptorType type
;
1829 /* Flags provided when this binding was created */
1830 VkDescriptorBindingFlagsEXT flags
;
1832 /* Bitfield representing the type of data this descriptor contains */
1833 enum anv_descriptor_data data
;
1835 /* Maximum number of YCbCr texture/sampler planes */
1836 uint8_t max_plane_count
;
1838 /* Number of array elements in this binding (or size in bytes for inline
1841 uint16_t array_size
;
1843 /* Index into the flattend descriptor set */
1844 uint16_t descriptor_index
;
1846 /* Index into the dynamic state array for a dynamic buffer */
1847 int16_t dynamic_offset_index
;
1849 /* Index into the descriptor set buffer views */
1850 int16_t buffer_view_index
;
1852 /* Offset into the descriptor buffer where this descriptor lives */
1853 uint32_t descriptor_offset
;
1855 /* Immutable samplers (or NULL if no immutable samplers) */
1856 struct anv_sampler
**immutable_samplers
;
1859 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1861 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1862 VkDescriptorType type
);
1864 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1865 const struct anv_descriptor_set_binding_layout
*binding
,
1868 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1869 const struct anv_descriptor_set_binding_layout
*binding
,
1872 struct anv_descriptor_set_layout
{
1873 /* Descriptor set layouts can be destroyed at almost any time */
1876 /* Number of bindings in this descriptor set */
1877 uint16_t binding_count
;
1879 /* Total size of the descriptor set with room for all array entries */
1882 /* Shader stages affected by this descriptor set */
1883 uint16_t shader_stages
;
1885 /* Number of buffer views in this descriptor set */
1886 uint16_t buffer_view_count
;
1888 /* Number of dynamic offsets used by this descriptor set */
1889 uint16_t dynamic_offset_count
;
1891 /* For each shader stage, which offsets apply to that stage */
1892 uint16_t stage_dynamic_offsets
[MESA_SHADER_STAGES
];
1894 /* Size of the descriptor buffer for this descriptor set */
1895 uint32_t descriptor_buffer_size
;
1897 /* Bindings in this descriptor set */
1898 struct anv_descriptor_set_binding_layout binding
[0];
1902 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1904 assert(layout
&& layout
->ref_cnt
>= 1);
1905 p_atomic_inc(&layout
->ref_cnt
);
1909 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1910 struct anv_descriptor_set_layout
*layout
)
1912 assert(layout
&& layout
->ref_cnt
>= 1);
1913 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1914 vk_free(&device
->alloc
, layout
);
1917 struct anv_descriptor
{
1918 VkDescriptorType type
;
1922 VkImageLayout layout
;
1923 struct anv_image_view
*image_view
;
1924 struct anv_sampler
*sampler
;
1928 struct anv_buffer
*buffer
;
1933 struct anv_buffer_view
*buffer_view
;
1937 struct anv_descriptor_set
{
1938 struct anv_descriptor_pool
*pool
;
1939 struct anv_descriptor_set_layout
*layout
;
1942 /* State relative to anv_descriptor_pool::bo */
1943 struct anv_state desc_mem
;
1944 /* Surface state for the descriptor buffer */
1945 struct anv_state desc_surface_state
;
1947 uint32_t buffer_view_count
;
1948 struct anv_buffer_view
*buffer_views
;
1950 /* Link to descriptor pool's desc_sets list . */
1951 struct list_head pool_link
;
1953 struct anv_descriptor descriptors
[0];
1956 struct anv_buffer_view
{
1957 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1958 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1960 struct anv_address address
;
1962 struct anv_state surface_state
;
1963 struct anv_state storage_surface_state
;
1964 struct anv_state writeonly_storage_surface_state
;
1966 struct brw_image_param storage_image_param
;
1969 struct anv_push_descriptor_set
{
1970 struct anv_descriptor_set set
;
1972 /* Put this field right behind anv_descriptor_set so it fills up the
1973 * descriptors[0] field. */
1974 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1976 /** True if the descriptor set buffer has been referenced by a draw or
1979 bool set_used_on_gpu
;
1981 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1984 struct anv_descriptor_pool
{
1990 struct util_vma_heap bo_heap
;
1992 struct anv_state_stream surface_state_stream
;
1993 void *surface_state_free_list
;
1995 struct list_head desc_sets
;
2000 enum anv_descriptor_template_entry_type
{
2001 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
2002 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
2003 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
2006 struct anv_descriptor_template_entry
{
2007 /* The type of descriptor in this entry */
2008 VkDescriptorType type
;
2010 /* Binding in the descriptor set */
2013 /* Offset at which to write into the descriptor set binding */
2014 uint32_t array_element
;
2016 /* Number of elements to write into the descriptor set binding */
2017 uint32_t array_count
;
2019 /* Offset into the user provided data */
2022 /* Stride between elements into the user provided data */
2026 struct anv_descriptor_update_template
{
2027 VkPipelineBindPoint bind_point
;
2029 /* The descriptor set this template corresponds to. This value is only
2030 * valid if the template was created with the templateType
2031 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2035 /* Number of entries in this template */
2036 uint32_t entry_count
;
2038 /* Entries of the template */
2039 struct anv_descriptor_template_entry entries
[0];
2043 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
2046 anv_descriptor_set_write_image_view(struct anv_device
*device
,
2047 struct anv_descriptor_set
*set
,
2048 const VkDescriptorImageInfo
* const info
,
2049 VkDescriptorType type
,
2054 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
2055 struct anv_descriptor_set
*set
,
2056 VkDescriptorType type
,
2057 struct anv_buffer_view
*buffer_view
,
2062 anv_descriptor_set_write_buffer(struct anv_device
*device
,
2063 struct anv_descriptor_set
*set
,
2064 struct anv_state_stream
*alloc_stream
,
2065 VkDescriptorType type
,
2066 struct anv_buffer
*buffer
,
2069 VkDeviceSize offset
,
2070 VkDeviceSize range
);
2072 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
2073 struct anv_descriptor_set
*set
,
2080 anv_descriptor_set_write_template(struct anv_device
*device
,
2081 struct anv_descriptor_set
*set
,
2082 struct anv_state_stream
*alloc_stream
,
2083 const struct anv_descriptor_update_template
*template,
2087 anv_descriptor_set_create(struct anv_device
*device
,
2088 struct anv_descriptor_pool
*pool
,
2089 struct anv_descriptor_set_layout
*layout
,
2090 struct anv_descriptor_set
**out_set
);
2093 anv_descriptor_set_destroy(struct anv_device
*device
,
2094 struct anv_descriptor_pool
*pool
,
2095 struct anv_descriptor_set
*set
);
2097 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2098 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2099 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2100 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2101 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2102 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2104 struct anv_pipeline_binding
{
2105 /** Index in the descriptor set
2107 * This is a flattened index; the descriptor set layout is already taken
2112 /** The descriptor set this surface corresponds to.
2114 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2115 * binding is not a normal descriptor set but something else.
2120 /** Plane in the binding index for images */
2123 /** Input attachment index (relative to the subpass) */
2124 uint8_t input_attachment_index
;
2126 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2127 uint8_t dynamic_offset_index
;
2130 /** For a storage image, whether it is write-only */
2133 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2134 * assuming POD zero-initialization.
2139 struct anv_push_range
{
2140 /** Index in the descriptor set */
2143 /** Descriptor set index */
2146 /** Dynamic offset index (for dynamic UBOs) */
2147 uint8_t dynamic_offset_index
;
2149 /** Start offset in units of 32B */
2152 /** Range in units of 32B */
2156 struct anv_pipeline_layout
{
2158 struct anv_descriptor_set_layout
*layout
;
2159 uint32_t dynamic_offset_start
;
2164 unsigned char sha1
[20];
2168 struct anv_device
* device
;
2171 VkBufferUsageFlags usage
;
2173 /* Set when bound */
2174 struct anv_address address
;
2177 static inline uint64_t
2178 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2180 assert(offset
<= buffer
->size
);
2181 if (range
== VK_WHOLE_SIZE
) {
2182 return buffer
->size
- offset
;
2184 assert(range
+ offset
>= range
);
2185 assert(range
+ offset
<= buffer
->size
);
2190 enum anv_cmd_dirty_bits
{
2191 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2192 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2193 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2194 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2195 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2196 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2197 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2198 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2199 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2200 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2201 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2202 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2203 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2204 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2206 typedef uint32_t anv_cmd_dirty_mask_t
;
2208 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2209 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2210 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2211 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2212 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2213 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2214 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2215 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2216 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2217 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2218 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2220 static inline enum anv_cmd_dirty_bits
2221 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2224 case VK_DYNAMIC_STATE_VIEWPORT
:
2225 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2226 case VK_DYNAMIC_STATE_SCISSOR
:
2227 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2228 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2229 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2230 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2231 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2232 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2233 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2234 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2235 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2236 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2237 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2238 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2239 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2240 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2241 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2242 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2243 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2245 assert(!"Unsupported dynamic state");
2251 enum anv_pipe_bits
{
2252 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2253 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2254 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2255 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2256 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2257 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2258 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2259 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2260 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2261 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2262 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2263 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2264 ANV_PIPE_END_OF_PIPE_SYNC_BIT
= (1 << 21),
2266 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2267 * a flush has happened but not a CS stall. The next time we do any sort
2268 * of invalidation we need to insert a CS stall at that time. Otherwise,
2269 * we would have to CS stall on every flush which could be bad.
2271 ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
= (1 << 22),
2273 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2274 * target operations related to transfer commands with VkBuffer as
2275 * destination are ongoing. Some operations like copies on the command
2276 * streamer might need to be aware of this to trigger the appropriate stall
2277 * before they can proceed with the copy.
2279 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 23),
2281 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2282 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2283 * done by writing the AUX-TT register.
2285 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
= (1 << 24),
2287 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2288 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2289 * implement a workaround for Gen9.
2291 ANV_PIPE_POST_SYNC_BIT
= (1 << 25),
2294 #define ANV_PIPE_FLUSH_BITS ( \
2295 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2296 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2297 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2298 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2300 #define ANV_PIPE_STALL_BITS ( \
2301 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2302 ANV_PIPE_DEPTH_STALL_BIT | \
2303 ANV_PIPE_CS_STALL_BIT)
2305 #define ANV_PIPE_INVALIDATE_BITS ( \
2306 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2307 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2308 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2309 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2310 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2311 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2312 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2314 static inline enum anv_pipe_bits
2315 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2317 enum anv_pipe_bits pipe_bits
= 0;
2320 for_each_bit(b
, flags
) {
2321 switch ((VkAccessFlagBits
)(1 << b
)) {
2322 case VK_ACCESS_SHADER_WRITE_BIT
:
2323 /* We're transitioning a buffer that was previously used as write
2324 * destination through the data port. To make its content available
2325 * to future operations, flush the data cache.
2327 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2329 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2330 /* We're transitioning a buffer that was previously used as render
2331 * target. To make its content available to future operations, flush
2332 * the render target cache.
2334 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2336 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2337 /* We're transitioning a buffer that was previously used as depth
2338 * buffer. To make its content available to future operations, flush
2341 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2343 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2344 /* We're transitioning a buffer that was previously used as a
2345 * transfer write destination. Generic write operations include color
2346 * & depth operations as well as buffer operations like :
2347 * - vkCmdClearColorImage()
2348 * - vkCmdClearDepthStencilImage()
2349 * - vkCmdBlitImage()
2350 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2352 * Most of these operations are implemented using Blorp which writes
2353 * through the render target, so flush that cache to make it visible
2354 * to future operations. And for depth related operations we also
2355 * need to flush the depth cache.
2357 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2358 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2360 case VK_ACCESS_MEMORY_WRITE_BIT
:
2361 /* We're transitioning a buffer for generic write operations. Flush
2364 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2367 break; /* Nothing to do */
2374 static inline enum anv_pipe_bits
2375 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2377 enum anv_pipe_bits pipe_bits
= 0;
2380 for_each_bit(b
, flags
) {
2381 switch ((VkAccessFlagBits
)(1 << b
)) {
2382 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2383 /* Indirect draw commands take a buffer as input that we're going to
2384 * read from the command streamer to load some of the HW registers
2385 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2386 * command streamer stall so that all the cache flushes have
2387 * completed before the command streamer loads from memory.
2389 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2390 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2391 * through a vertex buffer, so invalidate that cache.
2393 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2394 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2395 * UBO from the buffer, so we need to invalidate constant cache.
2397 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2399 case VK_ACCESS_INDEX_READ_BIT
:
2400 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2401 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2402 * commands, so we invalidate the VF cache to make sure there is no
2403 * stale data when we start rendering.
2405 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2407 case VK_ACCESS_UNIFORM_READ_BIT
:
2408 /* We transitioning a buffer to be used as uniform data. Because
2409 * uniform is accessed through the data port & sampler, we need to
2410 * invalidate the texture cache (sampler) & constant cache (data
2411 * port) to avoid stale data.
2413 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2414 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2416 case VK_ACCESS_SHADER_READ_BIT
:
2417 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2418 case VK_ACCESS_TRANSFER_READ_BIT
:
2419 /* Transitioning a buffer to be read through the sampler, so
2420 * invalidate the texture cache, we don't want any stale data.
2422 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2424 case VK_ACCESS_MEMORY_READ_BIT
:
2425 /* Transitioning a buffer for generic read, invalidate all the
2428 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2430 case VK_ACCESS_MEMORY_WRITE_BIT
:
2431 /* Generic write, make sure all previously written things land in
2434 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2436 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2437 /* Transitioning a buffer for conditional rendering. We'll load the
2438 * content of this buffer into HW registers using the command
2439 * streamer, so we need to stall the command streamer to make sure
2440 * any in-flight flush operations have completed.
2442 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2445 break; /* Nothing to do */
2452 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2453 VK_IMAGE_ASPECT_COLOR_BIT | \
2454 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2455 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2456 VK_IMAGE_ASPECT_PLANE_2_BIT)
2457 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2458 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2459 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2460 VK_IMAGE_ASPECT_PLANE_2_BIT)
2462 struct anv_vertex_binding
{
2463 struct anv_buffer
* buffer
;
2464 VkDeviceSize offset
;
2467 struct anv_xfb_binding
{
2468 struct anv_buffer
* buffer
;
2469 VkDeviceSize offset
;
2473 struct anv_push_constants
{
2474 /** Push constant data provided by the client through vkPushConstants */
2475 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2477 /** Dynamic offsets for dynamic UBOs and SSBOs */
2478 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2480 /** Pad out to a multiple of 32 bytes */
2481 uint32_t push_ubo_sizes
[4];
2484 /** Base workgroup ID
2486 * Used for vkCmdDispatchBase.
2488 uint32_t base_work_group_id
[3];
2492 * This is never set by software but is implicitly filled out when
2493 * uploading the push constants for compute shaders.
2495 uint32_t subgroup_id
;
2499 struct anv_dynamic_state
{
2502 VkViewport viewports
[MAX_VIEWPORTS
];
2507 VkRect2D scissors
[MAX_SCISSORS
];
2518 float blend_constants
[4];
2528 } stencil_compare_mask
;
2533 } stencil_write_mask
;
2538 } stencil_reference
;
2546 extern const struct anv_dynamic_state default_dynamic_state
;
2548 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2549 const struct anv_dynamic_state
*src
,
2550 uint32_t copy_mask
);
2552 struct anv_surface_state
{
2553 struct anv_state state
;
2554 /** Address of the surface referred to by this state
2556 * This address is relative to the start of the BO.
2558 struct anv_address address
;
2559 /* Address of the aux surface, if any
2561 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2563 * With the exception of gen8, the bottom 12 bits of this address' offset
2564 * include extra aux information.
2566 struct anv_address aux_address
;
2567 /* Address of the clear color, if any
2569 * This address is relative to the start of the BO.
2571 struct anv_address clear_address
;
2575 * Attachment state when recording a renderpass instance.
2577 * The clear value is valid only if there exists a pending clear.
2579 struct anv_attachment_state
{
2580 enum isl_aux_usage aux_usage
;
2581 enum isl_aux_usage input_aux_usage
;
2582 struct anv_surface_state color
;
2583 struct anv_surface_state input
;
2585 VkImageLayout current_layout
;
2586 VkImageLayout current_stencil_layout
;
2587 VkImageAspectFlags pending_clear_aspects
;
2588 VkImageAspectFlags pending_load_aspects
;
2590 VkClearValue clear_value
;
2591 bool clear_color_is_zero_one
;
2592 bool clear_color_is_zero
;
2594 /* When multiview is active, attachments with a renderpass clear
2595 * operation have their respective layers cleared on the first
2596 * subpass that uses them, and only in that subpass. We keep track
2597 * of this using a bitfield to indicate which layers of an attachment
2598 * have not been cleared yet when multiview is active.
2600 uint32_t pending_clear_views
;
2601 struct anv_image_view
* image_view
;
2604 /** State tracking for vertex buffer flushes
2606 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2607 * addresses. If you happen to have two vertex buffers which get placed
2608 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2609 * collisions. In order to solve this problem, we track vertex address ranges
2610 * which are live in the cache and invalidate the cache if one ever exceeds 32
2613 struct anv_vb_cache_range
{
2614 /* Virtual address at which the live vertex buffer cache range starts for
2615 * this vertex buffer index.
2619 /* Virtual address of the byte after where vertex buffer cache range ends.
2620 * This is exclusive such that end - start is the size of the range.
2625 /** State tracking for particular pipeline bind point
2627 * This struct is the base struct for anv_cmd_graphics_state and
2628 * anv_cmd_compute_state. These are used to track state which is bound to a
2629 * particular type of pipeline. Generic state that applies per-stage such as
2630 * binding table offsets and push constants is tracked generically with a
2631 * per-stage array in anv_cmd_state.
2633 struct anv_cmd_pipeline_state
{
2634 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2635 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2638 /** State tracking for graphics pipeline
2640 * This has anv_cmd_pipeline_state as a base struct to track things which get
2641 * bound to a graphics pipeline. Along with general pipeline bind point state
2642 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2643 * state which is graphics-specific.
2645 struct anv_cmd_graphics_state
{
2646 struct anv_cmd_pipeline_state base
;
2648 struct anv_graphics_pipeline
*pipeline
;
2650 anv_cmd_dirty_mask_t dirty
;
2653 struct anv_vb_cache_range ib_bound_range
;
2654 struct anv_vb_cache_range ib_dirty_range
;
2655 struct anv_vb_cache_range vb_bound_ranges
[33];
2656 struct anv_vb_cache_range vb_dirty_ranges
[33];
2658 struct anv_dynamic_state dynamic
;
2661 struct anv_buffer
*index_buffer
;
2662 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2663 uint32_t index_offset
;
2667 /** State tracking for compute pipeline
2669 * This has anv_cmd_pipeline_state as a base struct to track things which get
2670 * bound to a compute pipeline. Along with general pipeline bind point state
2671 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2672 * state which is compute-specific.
2674 struct anv_cmd_compute_state
{
2675 struct anv_cmd_pipeline_state base
;
2677 struct anv_compute_pipeline
*pipeline
;
2679 bool pipeline_dirty
;
2681 struct anv_address num_workgroups
;
2684 /** State required while building cmd buffer */
2685 struct anv_cmd_state
{
2686 /* PIPELINE_SELECT.PipelineSelection */
2687 uint32_t current_pipeline
;
2688 const struct gen_l3_config
* current_l3_config
;
2689 uint32_t last_aux_map_state
;
2691 struct anv_cmd_graphics_state gfx
;
2692 struct anv_cmd_compute_state compute
;
2694 enum anv_pipe_bits pending_pipe_bits
;
2695 VkShaderStageFlags descriptors_dirty
;
2696 VkShaderStageFlags push_constants_dirty
;
2698 struct anv_framebuffer
* framebuffer
;
2699 struct anv_render_pass
* pass
;
2700 struct anv_subpass
* subpass
;
2701 VkRect2D render_area
;
2702 uint32_t restart_index
;
2703 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2705 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2706 VkShaderStageFlags push_constant_stages
;
2707 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2708 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2709 struct anv_state samplers
[MESA_SHADER_STAGES
];
2711 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2712 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2713 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2716 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2717 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2718 * and before invoking the secondary in ExecuteCommands.
2720 bool pma_fix_enabled
;
2723 * Whether or not we know for certain that HiZ is enabled for the current
2724 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2725 * enabled or not, this will be false.
2729 bool conditional_render_enabled
;
2732 * Last rendering scale argument provided to
2733 * genX(cmd_buffer_emit_hashing_mode)().
2735 unsigned current_hash_scale
;
2738 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2739 * valid only when recording a render pass instance.
2741 struct anv_attachment_state
* attachments
;
2744 * Surface states for color render targets. These are stored in a single
2745 * flat array. For depth-stencil attachments, the surface state is simply
2748 struct anv_state render_pass_states
;
2751 * A null surface state of the right size to match the framebuffer. This
2752 * is one of the states in render_pass_states.
2754 struct anv_state null_surface_state
;
2757 struct anv_cmd_pool
{
2758 VkAllocationCallbacks alloc
;
2759 struct list_head cmd_buffers
;
2762 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2764 enum anv_cmd_buffer_exec_mode
{
2765 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2766 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2767 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2768 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2769 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2772 struct anv_cmd_buffer
{
2773 VK_LOADER_DATA _loader_data
;
2775 struct anv_device
* device
;
2777 struct anv_cmd_pool
* pool
;
2778 struct list_head pool_link
;
2780 struct anv_batch batch
;
2782 /* Fields required for the actual chain of anv_batch_bo's.
2784 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2786 struct list_head batch_bos
;
2787 enum anv_cmd_buffer_exec_mode exec_mode
;
2789 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2790 * referenced by this command buffer
2792 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2794 struct u_vector seen_bbos
;
2796 /* A vector of int32_t's for every block of binding tables.
2798 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2800 struct u_vector bt_block_states
;
2801 struct anv_state bt_next
;
2803 struct anv_reloc_list surface_relocs
;
2804 /** Last seen surface state block pool center bo offset */
2805 uint32_t last_ss_pool_center
;
2807 /* Serial for tracking buffer completion */
2810 /* Stream objects for storing temporary data */
2811 struct anv_state_stream surface_state_stream
;
2812 struct anv_state_stream dynamic_state_stream
;
2814 VkCommandBufferUsageFlags usage_flags
;
2815 VkCommandBufferLevel level
;
2817 struct anv_cmd_state state
;
2819 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2820 uint64_t intel_perf_marker
;
2823 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2824 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2825 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2826 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2827 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2828 struct anv_cmd_buffer
*secondary
);
2829 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2830 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
2831 struct anv_cmd_buffer
*cmd_buffer
,
2832 const VkSemaphore
*in_semaphores
,
2833 const uint64_t *in_wait_values
,
2834 uint32_t num_in_semaphores
,
2835 const VkSemaphore
*out_semaphores
,
2836 const uint64_t *out_signal_values
,
2837 uint32_t num_out_semaphores
,
2840 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2842 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2843 const void *data
, uint32_t size
, uint32_t alignment
);
2844 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2845 uint32_t *a
, uint32_t *b
,
2846 uint32_t dwords
, uint32_t alignment
);
2849 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2851 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2852 uint32_t entries
, uint32_t *state_offset
);
2854 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2856 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2857 uint32_t size
, uint32_t alignment
);
2860 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2862 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2863 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2864 bool depth_clamp_enable
);
2865 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2867 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2868 struct anv_render_pass
*pass
,
2869 struct anv_framebuffer
*framebuffer
,
2870 const VkClearValue
*clear_values
);
2872 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2875 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2876 gl_shader_stage stage
);
2878 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2880 const struct anv_image_view
*
2881 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2884 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2885 uint32_t num_entries
,
2886 uint32_t *state_offset
,
2887 struct anv_state
*bt_state
);
2889 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2891 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2893 enum anv_fence_type
{
2894 ANV_FENCE_TYPE_NONE
= 0,
2896 ANV_FENCE_TYPE_WSI_BO
,
2897 ANV_FENCE_TYPE_SYNCOBJ
,
2901 enum anv_bo_fence_state
{
2902 /** Indicates that this is a new (or newly reset fence) */
2903 ANV_BO_FENCE_STATE_RESET
,
2905 /** Indicates that this fence has been submitted to the GPU but is still
2906 * (as far as we know) in use by the GPU.
2908 ANV_BO_FENCE_STATE_SUBMITTED
,
2910 ANV_BO_FENCE_STATE_SIGNALED
,
2913 struct anv_fence_impl
{
2914 enum anv_fence_type type
;
2917 /** Fence implementation for BO fences
2919 * These fences use a BO and a set of CPU-tracked state flags. The BO
2920 * is added to the object list of the last execbuf call in a QueueSubmit
2921 * and is marked EXEC_WRITE. The state flags track when the BO has been
2922 * submitted to the kernel. We need to do this because Vulkan lets you
2923 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2924 * will say it's idle in this case.
2928 enum anv_bo_fence_state state
;
2931 /** DRM syncobj handle for syncobj-based fences */
2935 struct wsi_fence
*fence_wsi
;
2940 /* Permanent fence state. Every fence has some form of permanent state
2941 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2942 * cross-process fences) or it could just be a dummy for use internally.
2944 struct anv_fence_impl permanent
;
2946 /* Temporary fence state. A fence *may* have temporary state. That state
2947 * is added to the fence by an import operation and is reset back to
2948 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2949 * state cannot be signaled because the fence must already be signaled
2950 * before the temporary state can be exported from the fence in the other
2951 * process and imported here.
2953 struct anv_fence_impl temporary
;
2956 void anv_fence_reset_temporary(struct anv_device
*device
,
2957 struct anv_fence
*fence
);
2961 struct anv_state state
;
2964 enum anv_semaphore_type
{
2965 ANV_SEMAPHORE_TYPE_NONE
= 0,
2966 ANV_SEMAPHORE_TYPE_DUMMY
,
2967 ANV_SEMAPHORE_TYPE_BO
,
2968 ANV_SEMAPHORE_TYPE_WSI_BO
,
2969 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2970 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2971 ANV_SEMAPHORE_TYPE_TIMELINE
,
2974 struct anv_timeline_point
{
2975 struct list_head link
;
2979 /* Number of waiter on this point, when > 0 the point should not be garbage
2984 /* BO used for synchronization. */
2988 struct anv_timeline
{
2989 pthread_mutex_t mutex
;
2990 pthread_cond_t cond
;
2992 uint64_t highest_past
;
2993 uint64_t highest_pending
;
2995 struct list_head points
;
2996 struct list_head free_points
;
2999 struct anv_semaphore_impl
{
3000 enum anv_semaphore_type type
;
3003 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
3004 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
3005 * object list on any execbuf2 calls for which this semaphore is used as
3006 * a wait or signal fence. When used as a signal fence or when type ==
3007 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
3011 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
3012 * If the semaphore is in the unsignaled state due to either just being
3013 * created or because it has been used for a wait, fd will be -1.
3017 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3018 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3019 * import so we don't need to bother with a userspace cache.
3023 /* Non shareable timeline semaphore
3025 * Used when kernel don't have support for timeline semaphores.
3027 struct anv_timeline timeline
;
3031 struct anv_semaphore
{
3034 /* Permanent semaphore state. Every semaphore has some form of permanent
3035 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3036 * (for cross-process semaphores0 or it could just be a dummy for use
3039 struct anv_semaphore_impl permanent
;
3041 /* Temporary semaphore state. A semaphore *may* have temporary state.
3042 * That state is added to the semaphore by an import operation and is reset
3043 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3044 * semaphore with temporary state cannot be signaled because the semaphore
3045 * must already be signaled before the temporary state can be exported from
3046 * the semaphore in the other process and imported here.
3048 struct anv_semaphore_impl temporary
;
3051 void anv_semaphore_reset_temporary(struct anv_device
*device
,
3052 struct anv_semaphore
*semaphore
);
3054 struct anv_shader_module
{
3055 unsigned char sha1
[20];
3060 static inline gl_shader_stage
3061 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
3063 assert(__builtin_popcount(vk_stage
) == 1);
3064 return ffs(vk_stage
) - 1;
3067 static inline VkShaderStageFlagBits
3068 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
3070 return (1 << mesa_stage
);
3073 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3075 #define anv_foreach_stage(stage, stage_bits) \
3076 for (gl_shader_stage stage, \
3077 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3078 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3079 __tmp &= ~(1 << (stage)))
3081 struct anv_pipeline_bind_map
{
3082 unsigned char surface_sha1
[20];
3083 unsigned char sampler_sha1
[20];
3084 unsigned char push_sha1
[20];
3086 uint32_t surface_count
;
3087 uint32_t sampler_count
;
3089 struct anv_pipeline_binding
* surface_to_descriptor
;
3090 struct anv_pipeline_binding
* sampler_to_descriptor
;
3092 struct anv_push_range push_ranges
[4];
3095 struct anv_shader_bin_key
{
3100 struct anv_shader_bin
{
3103 gl_shader_stage stage
;
3105 const struct anv_shader_bin_key
*key
;
3107 struct anv_state kernel
;
3108 uint32_t kernel_size
;
3110 struct anv_state constant_data
;
3111 uint32_t constant_data_size
;
3113 const struct brw_stage_prog_data
*prog_data
;
3114 uint32_t prog_data_size
;
3116 struct brw_compile_stats stats
[3];
3119 struct nir_xfb_info
*xfb_info
;
3121 struct anv_pipeline_bind_map bind_map
;
3124 struct anv_shader_bin
*
3125 anv_shader_bin_create(struct anv_device
*device
,
3126 gl_shader_stage stage
,
3127 const void *key
, uint32_t key_size
,
3128 const void *kernel
, uint32_t kernel_size
,
3129 const void *constant_data
, uint32_t constant_data_size
,
3130 const struct brw_stage_prog_data
*prog_data
,
3131 uint32_t prog_data_size
,
3132 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
3133 const struct nir_xfb_info
*xfb_info
,
3134 const struct anv_pipeline_bind_map
*bind_map
);
3137 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3140 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3142 assert(shader
&& shader
->ref_cnt
>= 1);
3143 p_atomic_inc(&shader
->ref_cnt
);
3147 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3149 assert(shader
&& shader
->ref_cnt
>= 1);
3150 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3151 anv_shader_bin_destroy(device
, shader
);
3154 struct anv_pipeline_executable
{
3155 gl_shader_stage stage
;
3157 struct brw_compile_stats stats
;
3163 enum anv_pipeline_type
{
3164 ANV_PIPELINE_GRAPHICS
,
3165 ANV_PIPELINE_COMPUTE
,
3168 struct anv_pipeline
{
3169 struct anv_device
* device
;
3171 struct anv_batch batch
;
3172 struct anv_reloc_list batch_relocs
;
3176 enum anv_pipeline_type type
;
3177 VkPipelineCreateFlags flags
;
3179 struct util_dynarray executables
;
3181 const struct gen_l3_config
* l3_config
;
3184 struct anv_graphics_pipeline
{
3185 struct anv_pipeline base
;
3187 uint32_t batch_data
[512];
3189 anv_cmd_dirty_mask_t dynamic_state_mask
;
3190 struct anv_dynamic_state dynamic_state
;
3194 struct anv_subpass
* subpass
;
3196 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3198 VkShaderStageFlags active_stages
;
3200 bool primitive_restart
;
3202 bool depth_test_enable
;
3203 bool writes_stencil
;
3204 bool stencil_test_enable
;
3205 bool depth_clamp_enable
;
3206 bool depth_clip_enable
;
3207 bool sample_shading_enable
;
3209 bool depth_bounds_test_enable
;
3211 /* When primitive replication is used, subpass->view_mask will describe what
3212 * views to replicate.
3214 bool use_primitive_replication
;
3216 struct anv_state blend_state
;
3219 struct anv_pipeline_vertex_binding
{
3222 uint32_t instance_divisor
;
3227 uint32_t depth_stencil_state
[3];
3233 uint32_t wm_depth_stencil
[3];
3237 uint32_t wm_depth_stencil
[4];
3241 struct anv_compute_pipeline
{
3242 struct anv_pipeline base
;
3244 struct anv_shader_bin
* cs
;
3245 uint32_t cs_right_mask
;
3246 uint32_t batch_data
[9];
3247 uint32_t interface_descriptor_data
[8];
3250 #define ANV_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
3251 static inline struct anv_##pipe_type##_pipeline * \
3252 anv_pipeline_to_##pipe_type(struct anv_pipeline *pipeline) \
3254 assert(pipeline->type == pipe_enum); \
3255 return (struct anv_##pipe_type##_pipeline *) pipeline; \
3258 ANV_DECL_PIPELINE_DOWNCAST(graphics
, ANV_PIPELINE_GRAPHICS
)
3259 ANV_DECL_PIPELINE_DOWNCAST(compute
, ANV_PIPELINE_COMPUTE
)
3262 anv_pipeline_has_stage(const struct anv_graphics_pipeline
*pipeline
,
3263 gl_shader_stage stage
)
3265 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3268 #define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \
3269 static inline const struct brw_##prefix##_prog_data * \
3270 get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \
3272 if (anv_pipeline_has_stage(pipeline, stage)) { \
3273 return (const struct brw_##prefix##_prog_data *) \
3274 pipeline->shaders[stage]->prog_data; \
3280 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3281 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3282 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3283 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3284 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3286 static inline const struct brw_cs_prog_data
*
3287 get_cs_prog_data(const struct anv_compute_pipeline
*pipeline
)
3289 assert(pipeline
->cs
);
3290 return (const struct brw_cs_prog_data
*) pipeline
->cs
->prog_data
;
3293 static inline const struct brw_vue_prog_data
*
3294 anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline
*pipeline
)
3296 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3297 return &get_gs_prog_data(pipeline
)->base
;
3298 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3299 return &get_tes_prog_data(pipeline
)->base
;
3301 return &get_vs_prog_data(pipeline
)->base
;
3305 anv_pipeline_init(struct anv_graphics_pipeline
*pipeline
, struct anv_device
*device
,
3306 struct anv_pipeline_cache
*cache
,
3307 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3308 const VkAllocationCallbacks
*alloc
);
3311 anv_pipeline_compile_cs(struct anv_compute_pipeline
*pipeline
,
3312 struct anv_pipeline_cache
*cache
,
3313 const VkComputePipelineCreateInfo
*info
,
3314 const struct anv_shader_module
*module
,
3315 const char *entrypoint
,
3316 const VkSpecializationInfo
*spec_info
);
3319 anv_cs_workgroup_size(const struct anv_compute_pipeline
*pipeline
);
3322 anv_cs_threads(const struct anv_compute_pipeline
*pipeline
);
3324 struct anv_format_plane
{
3325 enum isl_format isl_format
:16;
3326 struct isl_swizzle swizzle
;
3328 /* Whether this plane contains chroma channels */
3331 /* For downscaling of YUV planes */
3332 uint8_t denominator_scales
[2];
3334 /* How to map sampled ycbcr planes to a single 4 component element. */
3335 struct isl_swizzle ycbcr_swizzle
;
3337 /* What aspect is associated to this plane */
3338 VkImageAspectFlags aspect
;
3343 struct anv_format_plane planes
[3];
3350 * Return the aspect's _format_ plane, not its _memory_ plane (using the
3351 * vocabulary of VK_EXT_image_drm_format_modifier). As a consequence, \a
3352 * aspect_mask may contain VK_IMAGE_ASPECT_PLANE_*, but must not contain
3353 * VK_IMAGE_ASPECT_MEMORY_PLANE_* .
3355 static inline uint32_t
3356 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3357 VkImageAspectFlags aspect_mask
)
3359 switch (aspect_mask
) {
3360 case VK_IMAGE_ASPECT_COLOR_BIT
:
3361 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3362 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3364 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3365 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3368 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3370 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3373 /* Purposefully assert with depth/stencil aspects. */
3374 unreachable("invalid image aspect");
3378 static inline VkImageAspectFlags
3379 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3382 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3383 if (util_bitcount(image_aspects
) > 1)
3384 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3385 return VK_IMAGE_ASPECT_COLOR_BIT
;
3387 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3388 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3389 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3390 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3393 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3394 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3396 const struct anv_format
*
3397 anv_get_format(VkFormat format
);
3399 static inline uint32_t
3400 anv_get_format_planes(VkFormat vk_format
)
3402 const struct anv_format
*format
= anv_get_format(vk_format
);
3404 return format
!= NULL
? format
->n_planes
: 0;
3407 struct anv_format_plane
3408 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3409 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3411 static inline enum isl_format
3412 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3413 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3415 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3418 bool anv_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
3419 VkImageCreateFlags create_flags
,
3421 VkImageTiling vk_tiling
,
3422 const VkImageFormatListCreateInfoKHR
*fmt_list
);
3424 static inline struct isl_swizzle
3425 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3427 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3428 * RGB as RGBA for texturing
3430 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3431 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3433 /* But it doesn't matter what we render to that channel */
3434 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3440 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3443 * Subsurface of an anv_image.
3445 struct anv_surface
{
3446 /** Valid only if isl_surf::size_B > 0. */
3447 struct isl_surf isl
;
3450 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3456 VkImageType type
; /**< VkImageCreateInfo::imageType */
3457 /* The original VkFormat provided by the client. This may not match any
3458 * of the actual surface formats.
3461 const struct anv_format
*format
;
3463 VkImageAspectFlags aspects
;
3466 uint32_t array_size
;
3467 uint32_t samples
; /**< VkImageCreateInfo::samples */
3469 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3470 VkImageUsageFlags stencil_usage
;
3471 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3472 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3474 /** True if this is needs to be bound to an appropriately tiled BO.
3476 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3477 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3478 * we require a dedicated allocation so that we can know to allocate a
3481 bool needs_set_tiling
;
3484 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3485 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3487 uint64_t drm_format_mod
;
3492 /* Whether the image is made of several underlying buffer objects rather a
3493 * single one with different offsets.
3497 /* Image was created with external format. */
3498 bool external_format
;
3503 * For each foo, anv_image::planes[x].surface is valid if and only if
3504 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3505 * to figure the number associated with a given aspect.
3507 * The hardware requires that the depth buffer and stencil buffer be
3508 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3509 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3510 * allocate the depth and stencil buffers as separate surfaces in the same
3515 * -----------------------
3517 * ----------------------- |
3518 * | shadow surface0 | |
3519 * ----------------------- | Plane 0
3520 * | aux surface0 | |
3521 * ----------------------- |
3522 * | fast clear colors0 | \|/
3523 * -----------------------
3525 * ----------------------- |
3526 * | shadow surface1 | |
3527 * ----------------------- | Plane 1
3528 * | aux surface1 | |
3529 * ----------------------- |
3530 * | fast clear colors1 | \|/
3531 * -----------------------
3534 * -----------------------
3538 * Offset of the entire plane (whenever the image is disjoint this is
3546 struct anv_surface surface
;
3549 * A surface which shadows the main surface and may have different
3550 * tiling. This is used for sampling using a tiling that isn't supported
3551 * for other operations.
3553 struct anv_surface shadow_surface
;
3556 * The base aux usage for this image. For color images, this can be
3557 * either CCS_E or CCS_D depending on whether or not we can reliably
3558 * leave CCS on all the time.
3560 enum isl_aux_usage aux_usage
;
3562 struct anv_surface aux_surface
;
3565 * Offset of the fast clear state (used to compute the
3566 * fast_clear_state_offset of the following planes).
3568 uint32_t fast_clear_state_offset
;
3571 * BO associated with this plane, set when bound.
3573 struct anv_address address
;
3576 * When destroying the image, also free the bo.
3582 /* The ordering of this enum is important */
3583 enum anv_fast_clear_type
{
3584 /** Image does not have/support any fast-clear blocks */
3585 ANV_FAST_CLEAR_NONE
= 0,
3586 /** Image has/supports fast-clear but only to the default value */
3587 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3588 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3589 ANV_FAST_CLEAR_ANY
= 2,
3592 /* Returns the number of auxiliary buffer levels attached to an image. */
3593 static inline uint8_t
3594 anv_image_aux_levels(const struct anv_image
* const image
,
3595 VkImageAspectFlagBits aspect
)
3597 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3598 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
3601 /* The Gen12 CCS aux surface is represented with only one level. */
3602 return image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3603 image
->planes
[plane
].surface
.isl
.levels
:
3604 image
->planes
[plane
].aux_surface
.isl
.levels
;
3607 /* Returns the number of auxiliary buffer layers attached to an image. */
3608 static inline uint32_t
3609 anv_image_aux_layers(const struct anv_image
* const image
,
3610 VkImageAspectFlagBits aspect
,
3611 const uint8_t miplevel
)
3615 /* The miplevel must exist in the main buffer. */
3616 assert(miplevel
< image
->levels
);
3618 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3619 /* There are no layers with auxiliary data because the miplevel has no
3624 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3626 /* The Gen12 CCS aux surface is represented with only one layer. */
3627 const struct isl_extent4d
*aux_logical_level0_px
=
3628 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3629 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3630 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3632 return MAX2(aux_logical_level0_px
->array_len
,
3633 aux_logical_level0_px
->depth
>> miplevel
);
3637 static inline struct anv_address
3638 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3639 const struct anv_image
*image
,
3640 VkImageAspectFlagBits aspect
)
3642 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3644 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3645 return anv_address_add(image
->planes
[plane
].address
,
3646 image
->planes
[plane
].fast_clear_state_offset
);
3649 static inline struct anv_address
3650 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3651 const struct anv_image
*image
,
3652 VkImageAspectFlagBits aspect
)
3654 struct anv_address addr
=
3655 anv_image_get_clear_color_addr(device
, image
, aspect
);
3657 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3658 device
->isl_dev
.ss
.clear_color_state_size
:
3659 device
->isl_dev
.ss
.clear_value_size
;
3660 return anv_address_add(addr
, clear_color_state_size
);
3663 static inline struct anv_address
3664 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3665 const struct anv_image
*image
,
3666 VkImageAspectFlagBits aspect
,
3667 uint32_t level
, uint32_t array_layer
)
3669 assert(level
< anv_image_aux_levels(image
, aspect
));
3670 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3671 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3672 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3674 struct anv_address addr
=
3675 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3676 addr
.offset
+= 4; /* Go past the fast clear type */
3678 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3679 for (uint32_t l
= 0; l
< level
; l
++)
3680 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3682 addr
.offset
+= level
* image
->array_size
* 4;
3684 addr
.offset
+= array_layer
* 4;
3686 assert(addr
.offset
<
3687 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3691 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3693 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3694 const struct anv_image
*image
)
3696 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3699 /* For Gen8-11, there are some restrictions around sampling from HiZ.
3700 * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
3703 * "If this field is set to AUX_HIZ, Number of Multisamples must
3704 * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
3706 if (image
->type
== VK_IMAGE_TYPE_3D
)
3709 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3710 * struct. There's documentation which suggests that this feature actually
3711 * reduces performance on BDW, but it has only been observed to help so
3712 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3713 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3715 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3718 return image
->samples
== 1;
3722 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3723 const struct anv_image
*image
,
3726 return device
->info
.has_aux_map
&&
3727 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3731 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3732 const struct anv_image
*image
,
3733 VkImageAspectFlagBits aspect
,
3734 enum isl_aux_usage aux_usage
,
3736 uint32_t base_layer
,
3737 uint32_t layer_count
);
3740 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3741 const struct anv_image
*image
,
3742 VkImageAspectFlagBits aspect
,
3743 enum isl_aux_usage aux_usage
,
3744 enum isl_format format
, struct isl_swizzle swizzle
,
3745 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3746 VkRect2D area
, union isl_color_value clear_color
);
3748 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3749 const struct anv_image
*image
,
3750 VkImageAspectFlags aspects
,
3751 enum isl_aux_usage depth_aux_usage
,
3753 uint32_t base_layer
, uint32_t layer_count
,
3755 float depth_value
, uint8_t stencil_value
);
3757 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3758 const struct anv_image
*src_image
,
3759 enum isl_aux_usage src_aux_usage
,
3760 uint32_t src_level
, uint32_t src_base_layer
,
3761 const struct anv_image
*dst_image
,
3762 enum isl_aux_usage dst_aux_usage
,
3763 uint32_t dst_level
, uint32_t dst_base_layer
,
3764 VkImageAspectFlagBits aspect
,
3765 uint32_t src_x
, uint32_t src_y
,
3766 uint32_t dst_x
, uint32_t dst_y
,
3767 uint32_t width
, uint32_t height
,
3768 uint32_t layer_count
,
3769 enum blorp_filter filter
);
3771 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3772 const struct anv_image
*image
,
3773 VkImageAspectFlagBits aspect
, uint32_t level
,
3774 uint32_t base_layer
, uint32_t layer_count
,
3775 enum isl_aux_op hiz_op
);
3777 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3778 const struct anv_image
*image
,
3779 VkImageAspectFlags aspects
,
3781 uint32_t base_layer
, uint32_t layer_count
,
3782 VkRect2D area
, uint8_t stencil_value
);
3784 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3785 const struct anv_image
*image
,
3786 enum isl_format format
, struct isl_swizzle swizzle
,
3787 VkImageAspectFlagBits aspect
,
3788 uint32_t base_layer
, uint32_t layer_count
,
3789 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3792 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3793 const struct anv_image
*image
,
3794 enum isl_format format
, struct isl_swizzle swizzle
,
3795 VkImageAspectFlagBits aspect
, uint32_t level
,
3796 uint32_t base_layer
, uint32_t layer_count
,
3797 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3801 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3802 const struct anv_image
*image
,
3803 VkImageAspectFlagBits aspect
,
3804 uint32_t base_level
, uint32_t level_count
,
3805 uint32_t base_layer
, uint32_t layer_count
);
3808 anv_layout_to_aux_state(const struct gen_device_info
* const devinfo
,
3809 const struct anv_image
*image
,
3810 const VkImageAspectFlagBits aspect
,
3811 const VkImageLayout layout
);
3814 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3815 const struct anv_image
*image
,
3816 const VkImageAspectFlagBits aspect
,
3817 const VkImageUsageFlagBits usage
,
3818 const VkImageLayout layout
);
3820 enum anv_fast_clear_type
3821 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3822 const struct anv_image
* const image
,
3823 const VkImageAspectFlagBits aspect
,
3824 const VkImageLayout layout
);
3826 /* This is defined as a macro so that it works for both
3827 * VkImageSubresourceRange and VkImageSubresourceLayers
3829 #define anv_get_layerCount(_image, _range) \
3830 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3831 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3833 static inline uint32_t
3834 anv_get_levelCount(const struct anv_image
*image
,
3835 const VkImageSubresourceRange
*range
)
3837 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3838 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3841 static inline VkImageAspectFlags
3842 anv_image_expand_aspects(const struct anv_image
*image
,
3843 VkImageAspectFlags aspects
)
3845 /* If the underlying image has color plane aspects and
3846 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3847 * the underlying image. */
3848 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3849 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3850 return image
->aspects
;
3856 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3857 VkImageAspectFlags aspects2
)
3859 if (aspects1
== aspects2
)
3862 /* Only 1 color aspects are compatibles. */
3863 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3864 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3865 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3871 struct anv_image_view
{
3872 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3874 VkImageAspectFlags aspect_mask
;
3876 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3880 uint32_t image_plane
;
3882 struct isl_view isl
;
3885 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3886 * image layout of SHADER_READ_ONLY_OPTIMAL or
3887 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3889 struct anv_surface_state optimal_sampler_surface_state
;
3892 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3893 * image layout of GENERAL.
3895 struct anv_surface_state general_sampler_surface_state
;
3898 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3899 * states for write-only and readable, using the real format for
3900 * write-only and the lowered format for readable.
3902 struct anv_surface_state storage_surface_state
;
3903 struct anv_surface_state writeonly_storage_surface_state
;
3905 struct brw_image_param storage_image_param
;
3909 enum anv_image_view_state_flags
{
3910 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3911 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3914 void anv_image_fill_surface_state(struct anv_device
*device
,
3915 const struct anv_image
*image
,
3916 VkImageAspectFlagBits aspect
,
3917 const struct isl_view
*view
,
3918 isl_surf_usage_flags_t view_usage
,
3919 enum isl_aux_usage aux_usage
,
3920 const union isl_color_value
*clear_color
,
3921 enum anv_image_view_state_flags flags
,
3922 struct anv_surface_state
*state_inout
,
3923 struct brw_image_param
*image_param_out
);
3925 struct anv_image_create_info
{
3926 const VkImageCreateInfo
*vk_info
;
3928 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3929 isl_tiling_flags_t isl_tiling_flags
;
3931 /** These flags will be added to any derived from VkImageCreateInfo. */
3932 isl_surf_usage_flags_t isl_extra_usage_flags
;
3935 bool external_format
;
3938 VkResult
anv_image_create(VkDevice _device
,
3939 const struct anv_image_create_info
*info
,
3940 const VkAllocationCallbacks
* alloc
,
3944 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3946 static inline VkExtent3D
3947 anv_sanitize_image_extent(const VkImageType imageType
,
3948 const VkExtent3D imageExtent
)
3950 switch (imageType
) {
3951 case VK_IMAGE_TYPE_1D
:
3952 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3953 case VK_IMAGE_TYPE_2D
:
3954 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3955 case VK_IMAGE_TYPE_3D
:
3958 unreachable("invalid image type");
3962 static inline VkOffset3D
3963 anv_sanitize_image_offset(const VkImageType imageType
,
3964 const VkOffset3D imageOffset
)
3966 switch (imageType
) {
3967 case VK_IMAGE_TYPE_1D
:
3968 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3969 case VK_IMAGE_TYPE_2D
:
3970 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3971 case VK_IMAGE_TYPE_3D
:
3974 unreachable("invalid image type");
3978 VkFormatFeatureFlags
3979 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3981 const struct anv_format
*anv_format
,
3982 VkImageTiling vk_tiling
);
3984 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3985 struct anv_state state
,
3986 enum isl_format format
,
3987 struct anv_address address
,
3988 uint32_t range
, uint32_t stride
);
3991 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3992 const struct anv_attachment_state
*att_state
,
3993 const struct anv_image_view
*iview
)
3995 const struct isl_format_layout
*view_fmtl
=
3996 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3998 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3999 if (view_fmtl->channels.c.bits) \
4000 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
4002 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
4003 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
4004 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
4005 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
4007 #undef COPY_CLEAR_COLOR_CHANNEL
4011 struct anv_ycbcr_conversion
{
4012 const struct anv_format
* format
;
4013 VkSamplerYcbcrModelConversion ycbcr_model
;
4014 VkSamplerYcbcrRange ycbcr_range
;
4015 VkComponentSwizzle mapping
[4];
4016 VkChromaLocation chroma_offsets
[2];
4017 VkFilter chroma_filter
;
4018 bool chroma_reconstruction
;
4021 struct anv_sampler
{
4022 uint32_t state
[3][4];
4024 struct anv_ycbcr_conversion
*conversion
;
4026 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
4027 * and with a 32-byte stride for use as bindless samplers.
4029 struct anv_state bindless_state
;
4032 struct anv_framebuffer
{
4037 uint32_t attachment_count
;
4038 struct anv_image_view
* attachments
[0];
4041 struct anv_subpass_attachment
{
4042 VkImageUsageFlagBits usage
;
4043 uint32_t attachment
;
4044 VkImageLayout layout
;
4046 /* Used only with attachment containing stencil data. */
4047 VkImageLayout stencil_layout
;
4050 struct anv_subpass
{
4051 uint32_t attachment_count
;
4054 * A pointer to all attachment references used in this subpass.
4055 * Only valid if ::attachment_count > 0.
4057 struct anv_subpass_attachment
* attachments
;
4058 uint32_t input_count
;
4059 struct anv_subpass_attachment
* input_attachments
;
4060 uint32_t color_count
;
4061 struct anv_subpass_attachment
* color_attachments
;
4062 struct anv_subpass_attachment
* resolve_attachments
;
4064 struct anv_subpass_attachment
* depth_stencil_attachment
;
4065 struct anv_subpass_attachment
* ds_resolve_attachment
;
4066 VkResolveModeFlagBitsKHR depth_resolve_mode
;
4067 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
4071 /** Subpass has a depth/stencil self-dependency */
4072 bool has_ds_self_dep
;
4074 /** Subpass has at least one color resolve attachment */
4075 bool has_color_resolve
;
4078 static inline unsigned
4079 anv_subpass_view_count(const struct anv_subpass
*subpass
)
4081 return MAX2(1, util_bitcount(subpass
->view_mask
));
4084 struct anv_render_pass_attachment
{
4085 /* TODO: Consider using VkAttachmentDescription instead of storing each of
4086 * its members individually.
4090 VkImageUsageFlags usage
;
4091 VkAttachmentLoadOp load_op
;
4092 VkAttachmentStoreOp store_op
;
4093 VkAttachmentLoadOp stencil_load_op
;
4094 VkImageLayout initial_layout
;
4095 VkImageLayout final_layout
;
4096 VkImageLayout first_subpass_layout
;
4098 VkImageLayout stencil_initial_layout
;
4099 VkImageLayout stencil_final_layout
;
4101 /* The subpass id in which the attachment will be used last. */
4102 uint32_t last_subpass_idx
;
4105 struct anv_render_pass
{
4106 uint32_t attachment_count
;
4107 uint32_t subpass_count
;
4108 /* An array of subpass_count+1 flushes, one per subpass boundary */
4109 enum anv_pipe_bits
* subpass_flushes
;
4110 struct anv_render_pass_attachment
* attachments
;
4111 struct anv_subpass subpasses
[0];
4114 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
4116 struct anv_query_pool
{
4118 VkQueryPipelineStatisticFlags pipeline_statistics
;
4119 /** Stride between slots, in bytes */
4121 /** Number of slots in this query pool */
4126 int anv_get_instance_entrypoint_index(const char *name
);
4127 int anv_get_device_entrypoint_index(const char *name
);
4128 int anv_get_physical_device_entrypoint_index(const char *name
);
4130 const char *anv_get_instance_entry_name(int index
);
4131 const char *anv_get_physical_device_entry_name(int index
);
4132 const char *anv_get_device_entry_name(int index
);
4135 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
4136 const struct anv_instance_extension_table
*instance
);
4138 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4139 const struct anv_instance_extension_table
*instance
);
4141 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4142 const struct anv_instance_extension_table
*instance
,
4143 const struct anv_device_extension_table
*device
);
4145 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
4148 void anv_dump_image_to_ppm(struct anv_device
*device
,
4149 struct anv_image
*image
, unsigned miplevel
,
4150 unsigned array_layer
, VkImageAspectFlagBits aspect
,
4151 const char *filename
);
4153 enum anv_dump_action
{
4154 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
4157 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
4158 void anv_dump_finish(void);
4160 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
4162 static inline uint32_t
4163 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
4165 /* This function must be called from within a subpass. */
4166 assert(cmd_state
->pass
&& cmd_state
->subpass
);
4168 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
4170 /* The id of this subpass shouldn't exceed the number of subpasses in this
4171 * render pass minus 1.
4173 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
4177 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
4178 void anv_device_perf_init(struct anv_device
*device
);
4180 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
4182 static inline struct __anv_type * \
4183 __anv_type ## _from_handle(__VkType _handle) \
4185 return (struct __anv_type *) _handle; \
4188 static inline __VkType \
4189 __anv_type ## _to_handle(struct __anv_type *_obj) \
4191 return (__VkType) _obj; \
4194 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
4196 static inline struct __anv_type * \
4197 __anv_type ## _from_handle(__VkType _handle) \
4199 return (struct __anv_type *)(uintptr_t) _handle; \
4202 static inline __VkType \
4203 __anv_type ## _to_handle(struct __anv_type *_obj) \
4205 return (__VkType)(uintptr_t) _obj; \
4208 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4209 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
4211 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
4212 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
4213 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
4214 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
4215 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
4217 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
4218 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
4219 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
4220 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
4221 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
4222 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
4223 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
4224 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
4225 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
4226 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
4227 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
4228 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
4229 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
4230 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
4231 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
4232 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
4233 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
4234 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
4235 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
4236 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
4237 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
4238 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
4239 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
4241 /* Gen-specific function declarations */
4243 # include "anv_genX.h"
4245 # define genX(x) gen7_##x
4246 # include "anv_genX.h"
4248 # define genX(x) gen75_##x
4249 # include "anv_genX.h"
4251 # define genX(x) gen8_##x
4252 # include "anv_genX.h"
4254 # define genX(x) gen9_##x
4255 # include "anv_genX.h"
4257 # define genX(x) gen10_##x
4258 # include "anv_genX.h"
4260 # define genX(x) gen11_##x
4261 # include "anv_genX.h"
4263 # define genX(x) gen12_##x
4264 # include "anv_genX.h"
4268 #endif /* ANV_PRIVATE_H */