2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "compiler/brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
52 /* Pre-declarations needed for WSI entrypoints */
55 typedef struct xcb_connection_t xcb_connection_t
;
56 typedef uint32_t xcb_visualid_t
;
57 typedef uint32_t xcb_window_t
;
60 struct anv_buffer_view
;
61 struct anv_image_view
;
65 #include <vulkan/vulkan.h>
66 #include <vulkan/vulkan_intel.h>
67 #include <vulkan/vk_icd.h>
69 #include "anv_entrypoints.h"
72 #include "common/gen_debug.h"
73 #include "wsi_common.h"
75 /* Allowing different clear colors requires us to perform a depth resolve at
76 * the end of certain render passes. This is because while slow clears store
77 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
78 * See the PRMs for examples describing when additional resolves would be
79 * necessary. To enable fast clears without requiring extra resolves, we set
80 * the clear value to a globally-defined one. We could allow different values
81 * if the user doesn't expect coherent data during or after a render passes
82 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
83 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
84 * 1.0f seems to be the only value used. The only application that doesn't set
85 * this value does so through the usage of an seemingly uninitialized clear
88 #define ANV_HZ_FC_VAL 1.0f
93 #define MAX_VIEWPORTS 16
94 #define MAX_SCISSORS 16
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_DYNAMIC_BUFFERS 16
98 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
100 #define ANV_SVGS_VB_INDEX MAX_VBS
101 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
103 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
105 static inline uint32_t
106 align_down_npot_u32(uint32_t v
, uint32_t a
)
111 static inline uint32_t
112 align_u32(uint32_t v
, uint32_t a
)
114 assert(a
!= 0 && a
== (a
& -a
));
115 return (v
+ a
- 1) & ~(a
- 1);
118 static inline uint64_t
119 align_u64(uint64_t v
, uint64_t a
)
121 assert(a
!= 0 && a
== (a
& -a
));
122 return (v
+ a
- 1) & ~(a
- 1);
125 static inline int32_t
126 align_i32(int32_t v
, int32_t a
)
128 assert(a
!= 0 && a
== (a
& -a
));
129 return (v
+ a
- 1) & ~(a
- 1);
132 /** Alignment must be a power of 2. */
134 anv_is_aligned(uintmax_t n
, uintmax_t a
)
136 assert(a
== (a
& -a
));
137 return (n
& (a
- 1)) == 0;
140 static inline uint32_t
141 anv_minify(uint32_t n
, uint32_t levels
)
143 if (unlikely(n
== 0))
146 return MAX2(n
>> levels
, 1);
150 anv_clamp_f(float f
, float min
, float max
)
163 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
165 if (*inout_mask
& clear_mask
) {
166 *inout_mask
&= ~clear_mask
;
173 static inline union isl_color_value
174 vk_to_isl_color(VkClearColorValue color
)
176 return (union isl_color_value
) {
186 #define for_each_bit(b, dword) \
187 for (uint32_t __dword = (dword); \
188 (b) = __builtin_ffs(__dword) - 1, __dword; \
189 __dword &= ~(1 << (b)))
191 #define typed_memcpy(dest, src, count) ({ \
192 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
193 memcpy((dest), (src), (count) * sizeof(*(src))); \
196 /* Whenever we generate an error, pass it through this function. Useful for
197 * debugging, where we can break on it. Only call at error site, not when
198 * propagating errors. Might be useful to plug in a stack trace here.
201 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
204 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
205 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
206 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
208 #define vk_error(error) error
209 #define vk_errorf(error, format, ...) error
210 #define anv_debug(format, ...)
214 * Warn on ignored extension structs.
216 * The Vulkan spec requires us to ignore unsupported or unknown structs in
217 * a pNext chain. In debug mode, emitting warnings for ignored structs may
218 * help us discover structs that we should not have ignored.
221 * From the Vulkan 1.0.38 spec:
223 * Any component of the implementation (the loader, any enabled layers,
224 * and drivers) must skip over, without processing (other than reading the
225 * sType and pNext members) any chained structures with sType values not
226 * defined by extensions supported by that component.
228 #define anv_debug_ignored_stype(sType) \
229 anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType))
231 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
232 anv_printflike(3, 4);
233 void __anv_perf_warn(const char *file
, int line
, const char *format
, ...)
234 anv_printflike(3, 4);
235 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
236 void anv_loge_v(const char *format
, va_list va
);
239 * Print a FINISHME message, including its source location.
241 #define anv_finishme(format, ...) \
243 static bool reported = false; \
245 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
251 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
253 #define anv_perf_warn(format, ...) \
255 static bool reported = false; \
256 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
257 __anv_perf_warn(__FILE__, __LINE__, format, ##__VA_ARGS__); \
262 /* A non-fatal assert. Useful for debugging. */
264 #define anv_assert(x) ({ \
265 if (unlikely(!(x))) \
266 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
269 #define anv_assert(x)
272 /* A multi-pointer allocator
274 * When copying data structures from the user (such as a render pass), it's
275 * common to need to allocate data for a bunch of different things. Instead
276 * of doing several allocations and having to handle all of the error checking
277 * that entails, it can be easier to do a single allocation. This struct
278 * helps facilitate that. The intended usage looks like this:
281 * anv_multialloc_add(&ma, &main_ptr, 1);
282 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
283 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
285 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
286 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
288 struct anv_multialloc
{
296 #define ANV_MULTIALLOC_INIT \
297 ((struct anv_multialloc) { 0, })
299 #define ANV_MULTIALLOC(_name) \
300 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
302 __attribute__((always_inline
))
304 _anv_multialloc_add(struct anv_multialloc
*ma
,
305 void **ptr
, size_t size
, size_t align
)
307 size_t offset
= align_u64(ma
->size
, align
);
308 ma
->size
= offset
+ size
;
309 ma
->align
= MAX2(ma
->align
, align
);
311 /* Store the offset in the pointer. */
312 *ptr
= (void *)(uintptr_t)offset
;
314 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
315 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
318 #define anv_multialloc_add(_ma, _ptr, _count) \
319 _anv_multialloc_add((_ma), (void **)(_ptr), \
320 (_count) * sizeof(**(_ptr)), __alignof__(**(_ptr)))
322 __attribute__((always_inline
))
324 anv_multialloc_alloc(struct anv_multialloc
*ma
,
325 const VkAllocationCallbacks
*alloc
,
326 VkSystemAllocationScope scope
)
328 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
332 /* Fill out each of the pointers with their final value.
334 * for (uint32_t i = 0; i < ma->ptr_count; i++)
335 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
337 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
338 * constant, GCC is incapable of figuring this out and unrolling the loop
339 * so we have to give it a little help.
341 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
342 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
343 if ((_i) < ma->ptr_count) \
344 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
345 _ANV_MULTIALLOC_UPDATE_POINTER(0);
346 _ANV_MULTIALLOC_UPDATE_POINTER(1);
347 _ANV_MULTIALLOC_UPDATE_POINTER(2);
348 _ANV_MULTIALLOC_UPDATE_POINTER(3);
349 _ANV_MULTIALLOC_UPDATE_POINTER(4);
350 _ANV_MULTIALLOC_UPDATE_POINTER(5);
351 _ANV_MULTIALLOC_UPDATE_POINTER(6);
352 _ANV_MULTIALLOC_UPDATE_POINTER(7);
353 #undef _ANV_MULTIALLOC_UPDATE_POINTER
358 __attribute__((always_inline
))
360 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
361 const VkAllocationCallbacks
*parent_alloc
,
362 const VkAllocationCallbacks
*alloc
,
363 VkSystemAllocationScope scope
)
365 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
369 * A dynamically growable, circular buffer. Elements are added at head and
370 * removed from tail. head and tail are free-running uint32_t indices and we
371 * only compute the modulo with size when accessing the array. This way,
372 * number of bytes in the queue is always head - tail, even in case of
379 /* Index into the current validation list. This is used by the
380 * validation list building alrogithm to track which buffers are already
381 * in the validation list so that we can ensure uniqueness.
385 /* Last known offset. This value is provided by the kernel when we
386 * execbuf and is used as the presumed offset for the next bunch of
394 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
399 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
401 bo
->gem_handle
= gem_handle
;
409 /* Represents a lock-free linked list of "free" things. This is used by
410 * both the block pool and the state pools. Unfortunately, in order to
411 * solve the ABA problem, we can't use a single uint32_t head.
413 union anv_free_list
{
417 /* A simple count that is incremented every time the head changes. */
423 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
425 struct anv_block_state
{
435 struct anv_block_pool
{
436 struct anv_device
*device
;
440 /* The offset from the start of the bo to the "center" of the block
441 * pool. Pointers to allocated blocks are given by
442 * bo.map + center_bo_offset + offsets.
444 uint32_t center_bo_offset
;
446 /* Current memory map of the block pool. This pointer may or may not
447 * point to the actual beginning of the block pool memory. If
448 * anv_block_pool_alloc_back has ever been called, then this pointer
449 * will point to the "center" position of the buffer and all offsets
450 * (negative or positive) given out by the block pool alloc functions
451 * will be valid relative to this pointer.
453 * In particular, map == bo.map + center_offset
459 * Array of mmaps and gem handles owned by the block pool, reclaimed when
460 * the block pool is destroyed.
462 struct u_vector mmap_cleanups
;
466 union anv_free_list free_list
;
467 struct anv_block_state state
;
469 union anv_free_list back_free_list
;
470 struct anv_block_state back_state
;
473 /* Block pools are backed by a fixed-size 1GB memfd */
474 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
476 /* The center of the block pool is also the middle of the memfd. This may
477 * change in the future if we decide differently for some reason.
479 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
481 static inline uint32_t
482 anv_block_pool_size(struct anv_block_pool
*pool
)
484 return pool
->state
.end
+ pool
->back_state
.end
;
493 struct anv_fixed_size_state_pool
{
495 union anv_free_list free_list
;
496 struct anv_block_state block
;
499 #define ANV_MIN_STATE_SIZE_LOG2 6
500 #define ANV_MAX_STATE_SIZE_LOG2 20
502 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
504 struct anv_state_pool
{
505 struct anv_block_pool
*block_pool
;
506 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
509 struct anv_state_stream_block
;
511 struct anv_state_stream
{
512 struct anv_block_pool
*block_pool
;
514 /* The current working block */
515 struct anv_state_stream_block
*block
;
517 /* Offset at which the current block starts */
519 /* Offset at which to allocate the next state */
521 /* Offset at which the current block ends */
525 #define CACHELINE_SIZE 64
526 #define CACHELINE_MASK 63
529 anv_clflush_range(void *start
, size_t size
)
531 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
532 void *end
= start
+ size
;
535 __builtin_ia32_clflush(p
);
541 anv_flush_range(void *start
, size_t size
)
543 __builtin_ia32_mfence();
544 anv_clflush_range(start
, size
);
548 anv_invalidate_range(void *start
, size_t size
)
550 anv_clflush_range(start
, size
);
551 __builtin_ia32_mfence();
554 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
555 struct anv_device
*device
, uint32_t block_size
);
556 void anv_block_pool_finish(struct anv_block_pool
*pool
);
557 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
);
558 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
);
559 void anv_block_pool_free(struct anv_block_pool
*pool
, int32_t offset
);
560 void anv_state_pool_init(struct anv_state_pool
*pool
,
561 struct anv_block_pool
*block_pool
);
562 void anv_state_pool_finish(struct anv_state_pool
*pool
);
563 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
564 size_t state_size
, size_t alignment
);
565 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
566 void anv_state_stream_init(struct anv_state_stream
*stream
,
567 struct anv_block_pool
*block_pool
);
568 void anv_state_stream_finish(struct anv_state_stream
*stream
);
569 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
570 uint32_t size
, uint32_t alignment
);
573 * Implements a pool of re-usable BOs. The interface is identical to that
574 * of block_pool except that each block is its own BO.
577 struct anv_device
*device
;
582 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
583 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
584 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
586 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
588 struct anv_scratch_bo
{
593 struct anv_scratch_pool
{
594 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
595 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
598 void anv_scratch_pool_init(struct anv_device
*device
,
599 struct anv_scratch_pool
*pool
);
600 void anv_scratch_pool_finish(struct anv_device
*device
,
601 struct anv_scratch_pool
*pool
);
602 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
603 struct anv_scratch_pool
*pool
,
604 gl_shader_stage stage
,
605 unsigned per_thread_scratch
);
607 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
608 struct anv_bo_cache
{
609 struct hash_table
*bo_map
;
610 pthread_mutex_t mutex
;
613 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
614 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
615 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
616 struct anv_bo_cache
*cache
,
617 uint64_t size
, struct anv_bo
**bo
);
618 VkResult
anv_bo_cache_import(struct anv_device
*device
,
619 struct anv_bo_cache
*cache
,
620 int fd
, uint64_t size
, struct anv_bo
**bo
);
621 VkResult
anv_bo_cache_export(struct anv_device
*device
,
622 struct anv_bo_cache
*cache
,
623 struct anv_bo
*bo_in
, int *fd_out
);
624 void anv_bo_cache_release(struct anv_device
*device
,
625 struct anv_bo_cache
*cache
,
628 struct anv_physical_device
{
629 VK_LOADER_DATA _loader_data
;
631 struct anv_instance
* instance
;
635 struct gen_device_info info
;
636 /** Amount of "GPU memory" we want to advertise
638 * Clearly, this value is bogus since Intel is a UMA architecture. On
639 * gen7 platforms, we are limited by GTT size unless we want to implement
640 * fine-grained tracking and GTT splitting. On Broadwell and above we are
641 * practically unlimited. However, we will never report more than 3/4 of
642 * the total system ram to try and avoid running out of RAM.
645 bool supports_48bit_addresses
;
646 struct brw_compiler
* compiler
;
647 struct isl_device isl_dev
;
648 int cmd_parser_version
;
652 uint32_t subslice_total
;
654 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
655 uint8_t driver_uuid
[VK_UUID_SIZE
];
656 uint8_t device_uuid
[VK_UUID_SIZE
];
658 struct wsi_device wsi_device
;
662 struct anv_instance
{
663 VK_LOADER_DATA _loader_data
;
665 VkAllocationCallbacks alloc
;
668 int physicalDeviceCount
;
669 struct anv_physical_device physicalDevice
;
672 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
673 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
676 VK_LOADER_DATA _loader_data
;
678 struct anv_device
* device
;
680 struct anv_state_pool
* pool
;
683 struct anv_pipeline_cache
{
684 struct anv_device
* device
;
685 pthread_mutex_t mutex
;
687 struct hash_table
* cache
;
690 struct anv_pipeline_bind_map
;
692 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
693 struct anv_device
*device
,
695 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
697 struct anv_shader_bin
*
698 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
699 const void *key
, uint32_t key_size
);
700 struct anv_shader_bin
*
701 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
702 const void *key_data
, uint32_t key_size
,
703 const void *kernel_data
, uint32_t kernel_size
,
704 const struct brw_stage_prog_data
*prog_data
,
705 uint32_t prog_data_size
,
706 const struct anv_pipeline_bind_map
*bind_map
);
709 VK_LOADER_DATA _loader_data
;
711 VkAllocationCallbacks alloc
;
713 struct anv_instance
* instance
;
715 struct gen_device_info info
;
716 struct isl_device isl_dev
;
719 bool can_chain_batches
;
720 bool robust_buffer_access
;
722 struct anv_bo_pool batch_bo_pool
;
724 struct anv_bo_cache bo_cache
;
726 struct anv_block_pool dynamic_state_block_pool
;
727 struct anv_state_pool dynamic_state_pool
;
729 struct anv_block_pool instruction_block_pool
;
730 struct anv_state_pool instruction_state_pool
;
732 struct anv_block_pool surface_state_block_pool
;
733 struct anv_state_pool surface_state_pool
;
735 struct anv_bo workaround_bo
;
737 struct anv_pipeline_cache blorp_shader_cache
;
738 struct blorp_context blorp
;
740 struct anv_state border_colors
;
742 struct anv_queue queue
;
744 struct anv_scratch_pool scratch_pool
;
746 uint32_t default_mocs
;
748 pthread_mutex_t mutex
;
749 pthread_cond_t queue_submit
;
754 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
756 if (device
->info
.has_llc
)
759 anv_flush_range(state
.map
, state
.alloc_size
);
762 void anv_device_init_blorp(struct anv_device
*device
);
763 void anv_device_finish_blorp(struct anv_device
*device
);
765 VkResult
anv_device_execbuf(struct anv_device
*device
,
766 struct drm_i915_gem_execbuffer2
*execbuf
,
767 struct anv_bo
**execbuf_bos
);
768 VkResult
anv_device_query_status(struct anv_device
*device
);
769 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
770 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
773 void* anv_gem_mmap(struct anv_device
*device
,
774 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
775 void anv_gem_munmap(void *p
, uint64_t size
);
776 uint32_t anv_gem_create(struct anv_device
*device
, size_t size
);
777 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
778 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
779 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
780 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
781 int anv_gem_execbuffer(struct anv_device
*device
,
782 struct drm_i915_gem_execbuffer2
*execbuf
);
783 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
784 uint32_t stride
, uint32_t tiling
);
785 int anv_gem_create_context(struct anv_device
*device
);
786 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
787 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
789 int anv_gem_get_param(int fd
, uint32_t param
);
790 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
791 int anv_gem_get_aperture(int fd
, uint64_t *size
);
792 bool anv_gem_supports_48b_addresses(int fd
);
793 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
794 uint32_t *active
, uint32_t *pending
);
795 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
796 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
797 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
798 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
799 uint32_t read_domains
, uint32_t write_domain
);
801 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
803 struct anv_reloc_list
{
806 struct drm_i915_gem_relocation_entry
* relocs
;
807 struct anv_bo
** reloc_bos
;
810 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
811 const VkAllocationCallbacks
*alloc
);
812 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
813 const VkAllocationCallbacks
*alloc
);
815 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
816 const VkAllocationCallbacks
*alloc
,
817 uint32_t offset
, struct anv_bo
*target_bo
,
820 struct anv_batch_bo
{
821 /* Link in the anv_cmd_buffer.owned_batch_bos list */
822 struct list_head link
;
826 /* Bytes actually consumed in this batch BO */
829 struct anv_reloc_list relocs
;
833 const VkAllocationCallbacks
* alloc
;
839 struct anv_reloc_list
* relocs
;
841 /* This callback is called (with the associated user data) in the event
842 * that the batch runs out of space.
844 VkResult (*extend_cb
)(struct anv_batch
*, void *);
848 * Current error status of the command buffer. Used to track inconsistent
849 * or incomplete command buffer states that are the consequence of run-time
850 * errors such as out of memory scenarios. We want to track this in the
851 * batch because the command buffer object is not visible to some parts
857 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
858 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
859 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
860 void *location
, struct anv_bo
*bo
, uint32_t offset
);
861 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
862 struct anv_batch
*batch
);
864 static inline VkResult
865 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
867 assert(error
!= VK_SUCCESS
);
868 if (batch
->status
== VK_SUCCESS
)
869 batch
->status
= error
;
870 return batch
->status
;
874 anv_batch_has_error(struct anv_batch
*batch
)
876 return batch
->status
!= VK_SUCCESS
;
884 static inline uint64_t
885 _anv_combine_address(struct anv_batch
*batch
, void *location
,
886 const struct anv_address address
, uint32_t delta
)
888 if (address
.bo
== NULL
) {
889 return address
.offset
+ delta
;
891 assert(batch
->start
<= location
&& location
< batch
->end
);
893 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
897 #define __gen_address_type struct anv_address
898 #define __gen_user_data struct anv_batch
899 #define __gen_combine_address _anv_combine_address
901 /* Wrapper macros needed to work around preprocessor argument issues. In
902 * particular, arguments don't get pre-evaluated if they are concatenated.
903 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
904 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
905 * We can work around this easily enough with these helpers.
907 #define __anv_cmd_length(cmd) cmd ## _length
908 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
909 #define __anv_cmd_header(cmd) cmd ## _header
910 #define __anv_cmd_pack(cmd) cmd ## _pack
911 #define __anv_reg_num(reg) reg ## _num
913 #define anv_pack_struct(dst, struc, ...) do { \
914 struct struc __template = { \
917 __anv_cmd_pack(struc)(NULL, dst, &__template); \
918 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
921 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
922 void *__dst = anv_batch_emit_dwords(batch, n); \
924 struct cmd __template = { \
925 __anv_cmd_header(cmd), \
926 .DWordLength = n - __anv_cmd_length_bias(cmd), \
929 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
934 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
938 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
939 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
942 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
943 dw[i] = (dwords0)[i] | (dwords1)[i]; \
944 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
947 #define anv_batch_emit(batch, cmd, name) \
948 for (struct cmd name = { __anv_cmd_header(cmd) }, \
949 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
950 __builtin_expect(_dst != NULL, 1); \
951 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
952 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
956 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
957 .GraphicsDataTypeGFDT = 0, \
958 .LLCCacheabilityControlLLCCC = 0, \
959 .L3CacheabilityControlL3CC = 1, \
962 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
963 .LLCeLLCCacheabilityControlLLCCC = 0, \
964 .L3CacheabilityControlL3CC = 1, \
967 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
968 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
969 .TargetCache = L3DefertoPATforLLCeLLCselection, \
973 /* Skylake: MOCS is now an index into an array of 62 different caching
974 * configurations programmed by the kernel.
977 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
978 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
979 .IndextoMOCSTables = 2 \
982 #define GEN9_MOCS_PTE { \
983 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
984 .IndextoMOCSTables = 1 \
987 struct anv_device_memory
{
990 VkDeviceSize map_size
;
995 * Header for Vertex URB Entry (VUE)
997 struct anv_vue_header
{
999 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1000 uint32_t ViewportIndex
;
1004 struct anv_descriptor_set_binding_layout
{
1006 /* The type of the descriptors in this binding */
1007 VkDescriptorType type
;
1010 /* Number of array elements in this binding */
1011 uint16_t array_size
;
1013 /* Index into the flattend descriptor set */
1014 uint16_t descriptor_index
;
1016 /* Index into the dynamic state array for a dynamic buffer */
1017 int16_t dynamic_offset_index
;
1019 /* Index into the descriptor set buffer views */
1020 int16_t buffer_index
;
1023 /* Index into the binding table for the associated surface */
1024 int16_t surface_index
;
1026 /* Index into the sampler table for the associated sampler */
1027 int16_t sampler_index
;
1029 /* Index into the image table for the associated image */
1030 int16_t image_index
;
1031 } stage
[MESA_SHADER_STAGES
];
1033 /* Immutable samplers (or NULL if no immutable samplers) */
1034 struct anv_sampler
**immutable_samplers
;
1037 struct anv_descriptor_set_layout
{
1038 /* Number of bindings in this descriptor set */
1039 uint16_t binding_count
;
1041 /* Total size of the descriptor set with room for all array entries */
1044 /* Shader stages affected by this descriptor set */
1045 uint16_t shader_stages
;
1047 /* Number of buffers in this descriptor set */
1048 uint16_t buffer_count
;
1050 /* Number of dynamic offsets used by this descriptor set */
1051 uint16_t dynamic_offset_count
;
1053 /* Bindings in this descriptor set */
1054 struct anv_descriptor_set_binding_layout binding
[0];
1057 struct anv_descriptor
{
1058 VkDescriptorType type
;
1062 struct anv_image_view
*image_view
;
1063 struct anv_sampler
*sampler
;
1065 /* Used to determine whether or not we need the surface state to have
1066 * the auxiliary buffer enabled.
1068 enum isl_aux_usage aux_usage
;
1072 struct anv_buffer
*buffer
;
1077 struct anv_buffer_view
*buffer_view
;
1081 struct anv_descriptor_set
{
1082 const struct anv_descriptor_set_layout
*layout
;
1084 uint32_t buffer_count
;
1085 struct anv_buffer_view
*buffer_views
;
1086 struct anv_descriptor descriptors
[0];
1089 struct anv_buffer_view
{
1090 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1092 uint32_t offset
; /**< Offset into bo. */
1093 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1095 struct anv_state surface_state
;
1096 struct anv_state storage_surface_state
;
1097 struct anv_state writeonly_storage_surface_state
;
1099 struct brw_image_param storage_image_param
;
1102 struct anv_push_descriptor_set
{
1103 struct anv_descriptor_set set
;
1105 /* Put this field right behind anv_descriptor_set so it fills up the
1106 * descriptors[0] field. */
1107 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1109 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1112 struct anv_descriptor_pool
{
1117 struct anv_state_stream surface_state_stream
;
1118 void *surface_state_free_list
;
1123 enum anv_descriptor_template_entry_type
{
1124 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1125 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1126 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1129 struct anv_descriptor_template_entry
{
1130 /* The type of descriptor in this entry */
1131 VkDescriptorType type
;
1133 /* Binding in the descriptor set */
1136 /* Offset at which to write into the descriptor set binding */
1137 uint32_t array_element
;
1139 /* Number of elements to write into the descriptor set binding */
1140 uint32_t array_count
;
1142 /* Offset into the user provided data */
1145 /* Stride between elements into the user provided data */
1149 struct anv_descriptor_update_template
{
1150 /* The descriptor set this template corresponds to. This value is only
1151 * valid if the template was created with the templateType
1152 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1156 /* Number of entries in this template */
1157 uint32_t entry_count
;
1159 /* Entries of the template */
1160 struct anv_descriptor_template_entry entries
[0];
1164 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1167 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1168 const struct gen_device_info
* const devinfo
,
1169 const VkDescriptorImageInfo
* const info
,
1170 VkDescriptorType type
,
1175 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1176 VkDescriptorType type
,
1177 struct anv_buffer_view
*buffer_view
,
1182 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1183 struct anv_device
*device
,
1184 struct anv_state_stream
*alloc_stream
,
1185 VkDescriptorType type
,
1186 struct anv_buffer
*buffer
,
1189 VkDeviceSize offset
,
1190 VkDeviceSize range
);
1193 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1194 struct anv_device
*device
,
1195 struct anv_state_stream
*alloc_stream
,
1196 const struct anv_descriptor_update_template
*template,
1200 anv_descriptor_set_create(struct anv_device
*device
,
1201 struct anv_descriptor_pool
*pool
,
1202 const struct anv_descriptor_set_layout
*layout
,
1203 struct anv_descriptor_set
**out_set
);
1206 anv_descriptor_set_destroy(struct anv_device
*device
,
1207 struct anv_descriptor_pool
*pool
,
1208 struct anv_descriptor_set
*set
);
1210 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1212 struct anv_pipeline_binding
{
1213 /* The descriptor set this surface corresponds to. The special value of
1214 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1215 * to a color attachment and not a regular descriptor.
1219 /* Binding in the descriptor set */
1222 /* Index in the binding */
1225 /* Input attachment index (relative to the subpass) */
1226 uint8_t input_attachment_index
;
1228 /* For a storage image, whether it is write-only */
1232 struct anv_pipeline_layout
{
1234 struct anv_descriptor_set_layout
*layout
;
1235 uint32_t dynamic_offset_start
;
1241 bool has_dynamic_offsets
;
1242 } stage
[MESA_SHADER_STAGES
];
1244 unsigned char sha1
[20];
1248 struct anv_device
* device
;
1251 VkBufferUsageFlags usage
;
1253 /* Set when bound */
1255 VkDeviceSize offset
;
1258 static inline uint64_t
1259 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1261 assert(offset
<= buffer
->size
);
1262 if (range
== VK_WHOLE_SIZE
) {
1263 return buffer
->size
- offset
;
1265 assert(range
<= buffer
->size
);
1270 enum anv_cmd_dirty_bits
{
1271 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1272 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1273 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1274 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1275 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1276 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1277 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1278 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1279 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1280 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1281 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1282 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1283 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1285 typedef uint32_t anv_cmd_dirty_mask_t
;
1287 enum anv_pipe_bits
{
1288 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1289 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1290 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1291 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1292 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1293 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1294 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1295 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1296 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1297 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1298 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1300 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1301 * a flush has happened but not a CS stall. The next time we do any sort
1302 * of invalidation we need to insert a CS stall at that time. Otherwise,
1303 * we would have to CS stall on every flush which could be bad.
1305 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1308 #define ANV_PIPE_FLUSH_BITS ( \
1309 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1310 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1311 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1313 #define ANV_PIPE_STALL_BITS ( \
1314 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1315 ANV_PIPE_DEPTH_STALL_BIT | \
1316 ANV_PIPE_CS_STALL_BIT)
1318 #define ANV_PIPE_INVALIDATE_BITS ( \
1319 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1320 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1321 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1322 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1323 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1324 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1326 static inline enum anv_pipe_bits
1327 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1329 enum anv_pipe_bits pipe_bits
= 0;
1332 for_each_bit(b
, flags
) {
1333 switch ((VkAccessFlagBits
)(1 << b
)) {
1334 case VK_ACCESS_SHADER_WRITE_BIT
:
1335 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1337 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1338 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1340 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1341 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1343 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1344 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1345 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1348 break; /* Nothing to do */
1355 static inline enum anv_pipe_bits
1356 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1358 enum anv_pipe_bits pipe_bits
= 0;
1361 for_each_bit(b
, flags
) {
1362 switch ((VkAccessFlagBits
)(1 << b
)) {
1363 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1364 case VK_ACCESS_INDEX_READ_BIT
:
1365 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1366 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1368 case VK_ACCESS_UNIFORM_READ_BIT
:
1369 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1370 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1372 case VK_ACCESS_SHADER_READ_BIT
:
1373 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1374 case VK_ACCESS_TRANSFER_READ_BIT
:
1375 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1378 break; /* Nothing to do */
1385 struct anv_vertex_binding
{
1386 struct anv_buffer
* buffer
;
1387 VkDeviceSize offset
;
1390 struct anv_push_constants
{
1391 /* Current allocated size of this push constants data structure.
1392 * Because a decent chunk of it may not be used (images on SKL, for
1393 * instance), we won't actually allocate the entire structure up-front.
1397 /* Push constant data provided by the client through vkPushConstants */
1398 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1400 /* Our hardware only provides zero-based vertex and instance id so, in
1401 * order to satisfy the vulkan requirements, we may have to push one or
1402 * both of these into the shader.
1404 uint32_t base_vertex
;
1405 uint32_t base_instance
;
1407 /* Image data for image_load_store on pre-SKL */
1408 struct brw_image_param images
[MAX_IMAGES
];
1411 struct anv_dynamic_state
{
1414 VkViewport viewports
[MAX_VIEWPORTS
];
1419 VkRect2D scissors
[MAX_SCISSORS
];
1430 float blend_constants
[4];
1440 } stencil_compare_mask
;
1445 } stencil_write_mask
;
1450 } stencil_reference
;
1453 extern const struct anv_dynamic_state default_dynamic_state
;
1455 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1456 const struct anv_dynamic_state
*src
,
1457 uint32_t copy_mask
);
1460 * Attachment state when recording a renderpass instance.
1462 * The clear value is valid only if there exists a pending clear.
1464 struct anv_attachment_state
{
1465 enum isl_aux_usage aux_usage
;
1466 enum isl_aux_usage input_aux_usage
;
1467 struct anv_state color_rt_state
;
1468 struct anv_state input_att_state
;
1470 VkImageLayout current_layout
;
1471 VkImageAspectFlags pending_clear_aspects
;
1473 VkClearValue clear_value
;
1474 bool clear_color_is_zero_one
;
1477 /** State required while building cmd buffer */
1478 struct anv_cmd_state
{
1479 /* PIPELINE_SELECT.PipelineSelection */
1480 uint32_t current_pipeline
;
1481 const struct gen_l3_config
* current_l3_config
;
1483 anv_cmd_dirty_mask_t dirty
;
1484 anv_cmd_dirty_mask_t compute_dirty
;
1485 enum anv_pipe_bits pending_pipe_bits
;
1486 uint32_t num_workgroups_offset
;
1487 struct anv_bo
*num_workgroups_bo
;
1488 VkShaderStageFlags descriptors_dirty
;
1489 VkShaderStageFlags push_constants_dirty
;
1490 uint32_t scratch_size
;
1491 struct anv_pipeline
* pipeline
;
1492 struct anv_pipeline
* compute_pipeline
;
1493 struct anv_framebuffer
* framebuffer
;
1494 struct anv_render_pass
* pass
;
1495 struct anv_subpass
* subpass
;
1496 VkRect2D render_area
;
1497 uint32_t restart_index
;
1498 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1499 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1500 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
1501 VkShaderStageFlags push_constant_stages
;
1502 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1503 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1504 struct anv_state samplers
[MESA_SHADER_STAGES
];
1505 struct anv_dynamic_state dynamic
;
1508 struct anv_push_descriptor_set push_descriptor
;
1511 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1512 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1513 * and before invoking the secondary in ExecuteCommands.
1515 bool pma_fix_enabled
;
1518 * Whether or not we know for certain that HiZ is enabled for the current
1519 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1520 * enabled or not, this will be false.
1525 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1526 * valid only when recording a render pass instance.
1528 struct anv_attachment_state
* attachments
;
1531 * Surface states for color render targets. These are stored in a single
1532 * flat array. For depth-stencil attachments, the surface state is simply
1535 struct anv_state render_pass_states
;
1538 * A null surface state of the right size to match the framebuffer. This
1539 * is one of the states in render_pass_states.
1541 struct anv_state null_surface_state
;
1544 struct anv_buffer
* index_buffer
;
1545 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1546 uint32_t index_offset
;
1550 struct anv_cmd_pool
{
1551 VkAllocationCallbacks alloc
;
1552 struct list_head cmd_buffers
;
1555 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1557 enum anv_cmd_buffer_exec_mode
{
1558 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1559 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1560 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1561 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1562 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1565 struct anv_cmd_buffer
{
1566 VK_LOADER_DATA _loader_data
;
1568 struct anv_device
* device
;
1570 struct anv_cmd_pool
* pool
;
1571 struct list_head pool_link
;
1573 struct anv_batch batch
;
1575 /* Fields required for the actual chain of anv_batch_bo's.
1577 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1579 struct list_head batch_bos
;
1580 enum anv_cmd_buffer_exec_mode exec_mode
;
1582 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1583 * referenced by this command buffer
1585 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1587 struct u_vector seen_bbos
;
1589 /* A vector of int32_t's for every block of binding tables.
1591 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1593 struct u_vector bt_blocks
;
1596 struct anv_reloc_list surface_relocs
;
1597 /** Last seen surface state block pool center bo offset */
1598 uint32_t last_ss_pool_center
;
1600 /* Serial for tracking buffer completion */
1603 /* Stream objects for storing temporary data */
1604 struct anv_state_stream surface_state_stream
;
1605 struct anv_state_stream dynamic_state_stream
;
1607 VkCommandBufferUsageFlags usage_flags
;
1608 VkCommandBufferLevel level
;
1610 struct anv_cmd_state state
;
1613 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1614 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1615 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1616 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1617 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1618 struct anv_cmd_buffer
*secondary
);
1619 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1620 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1621 struct anv_cmd_buffer
*cmd_buffer
);
1623 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1626 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1627 gl_shader_stage stage
, uint32_t size
);
1628 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1629 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1630 (offsetof(struct anv_push_constants, field) + \
1631 sizeof(cmd_buffer->state.push_constants[0]->field)))
1633 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1634 const void *data
, uint32_t size
, uint32_t alignment
);
1635 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1636 uint32_t *a
, uint32_t *b
,
1637 uint32_t dwords
, uint32_t alignment
);
1640 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1642 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1643 uint32_t entries
, uint32_t *state_offset
);
1645 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1647 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1648 uint32_t size
, uint32_t alignment
);
1651 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1653 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1654 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1655 bool depth_clamp_enable
);
1656 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1658 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1659 struct anv_render_pass
*pass
,
1660 struct anv_framebuffer
*framebuffer
,
1661 const VkClearValue
*clear_values
);
1663 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1666 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1667 gl_shader_stage stage
);
1669 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1671 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1672 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1674 const struct anv_image_view
*
1675 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1678 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1679 uint32_t num_entries
,
1680 uint32_t *state_offset
,
1681 struct anv_state
*bt_state
);
1683 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1685 enum anv_fence_state
{
1686 /** Indicates that this is a new (or newly reset fence) */
1687 ANV_FENCE_STATE_RESET
,
1689 /** Indicates that this fence has been submitted to the GPU but is still
1690 * (as far as we know) in use by the GPU.
1692 ANV_FENCE_STATE_SUBMITTED
,
1694 ANV_FENCE_STATE_SIGNALED
,
1699 struct drm_i915_gem_execbuffer2 execbuf
;
1700 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1701 enum anv_fence_state state
;
1706 struct anv_state state
;
1709 struct anv_shader_module
{
1710 unsigned char sha1
[20];
1715 void anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
1716 struct anv_shader_module
*module
,
1717 const char *entrypoint
,
1718 const struct anv_pipeline_layout
*pipeline_layout
,
1719 const VkSpecializationInfo
*spec_info
);
1721 static inline gl_shader_stage
1722 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1724 assert(__builtin_popcount(vk_stage
) == 1);
1725 return ffs(vk_stage
) - 1;
1728 static inline VkShaderStageFlagBits
1729 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1731 return (1 << mesa_stage
);
1734 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1736 #define anv_foreach_stage(stage, stage_bits) \
1737 for (gl_shader_stage stage, \
1738 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1739 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1740 __tmp &= ~(1 << (stage)))
1742 struct anv_pipeline_bind_map
{
1743 uint32_t surface_count
;
1744 uint32_t sampler_count
;
1745 uint32_t image_count
;
1747 struct anv_pipeline_binding
* surface_to_descriptor
;
1748 struct anv_pipeline_binding
* sampler_to_descriptor
;
1751 struct anv_shader_bin_key
{
1756 struct anv_shader_bin
{
1759 const struct anv_shader_bin_key
*key
;
1761 struct anv_state kernel
;
1762 uint32_t kernel_size
;
1764 const struct brw_stage_prog_data
*prog_data
;
1765 uint32_t prog_data_size
;
1767 struct anv_pipeline_bind_map bind_map
;
1769 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1772 struct anv_shader_bin
*
1773 anv_shader_bin_create(struct anv_device
*device
,
1774 const void *key
, uint32_t key_size
,
1775 const void *kernel
, uint32_t kernel_size
,
1776 const struct brw_stage_prog_data
*prog_data
,
1777 uint32_t prog_data_size
, const void *prog_data_param
,
1778 const struct anv_pipeline_bind_map
*bind_map
);
1781 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1784 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1786 assert(shader
&& shader
->ref_cnt
>= 1);
1787 __sync_fetch_and_add(&shader
->ref_cnt
, 1);
1791 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1793 assert(shader
&& shader
->ref_cnt
>= 1);
1794 if (__sync_fetch_and_add(&shader
->ref_cnt
, -1) == 1)
1795 anv_shader_bin_destroy(device
, shader
);
1798 struct anv_pipeline
{
1799 struct anv_device
* device
;
1800 struct anv_batch batch
;
1801 uint32_t batch_data
[512];
1802 struct anv_reloc_list batch_relocs
;
1803 uint32_t dynamic_state_mask
;
1804 struct anv_dynamic_state dynamic_state
;
1806 struct anv_pipeline_layout
* layout
;
1808 bool needs_data_cache
;
1810 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1813 const struct gen_l3_config
* l3_config
;
1814 uint32_t total_size
;
1817 VkShaderStageFlags active_stages
;
1818 struct anv_state blend_state
;
1821 uint32_t binding_stride
[MAX_VBS
];
1822 bool instancing_enable
[MAX_VBS
];
1823 bool primitive_restart
;
1826 uint32_t cs_right_mask
;
1829 bool depth_test_enable
;
1830 bool writes_stencil
;
1831 bool stencil_test_enable
;
1832 bool depth_clamp_enable
;
1833 bool sample_shading_enable
;
1838 uint32_t depth_stencil_state
[3];
1844 uint32_t wm_depth_stencil
[3];
1848 uint32_t wm_depth_stencil
[4];
1851 uint32_t interface_descriptor_data
[8];
1855 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1856 gl_shader_stage stage
)
1858 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1861 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1862 static inline const struct brw_##prefix##_prog_data * \
1863 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1865 if (anv_pipeline_has_stage(pipeline, stage)) { \
1866 return (const struct brw_##prefix##_prog_data *) \
1867 pipeline->shaders[stage]->prog_data; \
1873 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1874 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
1875 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
1876 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1877 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1878 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1880 static inline const struct brw_vue_prog_data
*
1881 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
1883 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1884 return &get_gs_prog_data(pipeline
)->base
;
1885 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1886 return &get_tes_prog_data(pipeline
)->base
;
1888 return &get_vs_prog_data(pipeline
)->base
;
1892 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1893 struct anv_pipeline_cache
*cache
,
1894 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1895 const VkAllocationCallbacks
*alloc
);
1898 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1899 struct anv_pipeline_cache
*cache
,
1900 const VkComputePipelineCreateInfo
*info
,
1901 struct anv_shader_module
*module
,
1902 const char *entrypoint
,
1903 const VkSpecializationInfo
*spec_info
);
1906 enum isl_format isl_format
:16;
1907 struct isl_swizzle swizzle
;
1911 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1912 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1914 static inline enum isl_format
1915 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1916 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1918 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1921 static inline struct isl_swizzle
1922 anv_swizzle_for_render(struct isl_swizzle swizzle
)
1924 /* Sometimes the swizzle will have alpha map to one. We do this to fake
1925 * RGB as RGBA for texturing
1927 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
1928 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
1930 /* But it doesn't matter what we render to that channel */
1931 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
1937 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
1940 * Subsurface of an anv_image.
1942 struct anv_surface
{
1943 /** Valid only if isl_surf::size > 0. */
1944 struct isl_surf isl
;
1947 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1954 /* The original VkFormat provided by the client. This may not match any
1955 * of the actual surface formats.
1958 VkImageAspectFlags aspects
;
1961 uint32_t array_size
;
1962 uint32_t samples
; /**< VkImageCreateInfo::samples */
1963 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1964 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1969 /* Set when bound */
1971 VkDeviceSize offset
;
1976 * For each foo, anv_image::foo_surface is valid if and only if
1977 * anv_image::aspects has a foo aspect.
1979 * The hardware requires that the depth buffer and stencil buffer be
1980 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1981 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1982 * allocate the depth and stencil buffers as separate surfaces in the same
1986 struct anv_surface color_surface
;
1989 struct anv_surface depth_surface
;
1990 struct anv_surface stencil_surface
;
1995 * For color images, this is the aux usage for this image when not used as a
1998 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
2001 enum isl_aux_usage aux_usage
;
2003 struct anv_surface aux_surface
;
2006 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2008 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
2009 const VkImageAspectFlags aspect_mask
,
2010 const uint32_t samples
)
2012 /* Validate the inputs. */
2013 assert(devinfo
&& aspect_mask
&& samples
);
2014 return devinfo
->gen
>= 8 && (aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2019 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
2020 const struct anv_image
*image
,
2021 enum blorp_hiz_op op
);
2024 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
2025 const struct anv_image
*image
,
2026 const VkImageAspectFlags aspects
,
2027 const VkImageLayout layout
);
2029 /* This is defined as a macro so that it works for both
2030 * VkImageSubresourceRange and VkImageSubresourceLayers
2032 #define anv_get_layerCount(_image, _range) \
2033 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2034 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2036 static inline uint32_t
2037 anv_get_levelCount(const struct anv_image
*image
,
2038 const VkImageSubresourceRange
*range
)
2040 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
2041 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
2045 struct anv_image_view
{
2046 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
2048 uint32_t offset
; /**< Offset into bo. */
2050 struct isl_view isl
;
2052 VkImageAspectFlags aspect_mask
;
2054 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2056 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
2057 struct anv_state sampler_surface_state
;
2060 * RENDER_SURFACE_STATE when using image as a sampler surface with the
2061 * auxiliary buffer disabled.
2063 struct anv_state no_aux_sampler_surface_state
;
2066 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
2067 * for write-only and readable, using the real format for write-only and the
2068 * lowered format for readable.
2070 struct anv_state storage_surface_state
;
2071 struct anv_state writeonly_storage_surface_state
;
2073 struct brw_image_param storage_image_param
;
2076 struct anv_image_create_info
{
2077 const VkImageCreateInfo
*vk_info
;
2079 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2080 isl_tiling_flags_t isl_tiling_flags
;
2085 VkResult
anv_image_create(VkDevice _device
,
2086 const struct anv_image_create_info
*info
,
2087 const VkAllocationCallbacks
* alloc
,
2090 const struct anv_surface
*
2091 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
2092 VkImageAspectFlags aspect_mask
);
2095 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
2097 static inline struct VkExtent3D
2098 anv_sanitize_image_extent(const VkImageType imageType
,
2099 const struct VkExtent3D imageExtent
)
2101 switch (imageType
) {
2102 case VK_IMAGE_TYPE_1D
:
2103 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2104 case VK_IMAGE_TYPE_2D
:
2105 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2106 case VK_IMAGE_TYPE_3D
:
2109 unreachable("invalid image type");
2113 static inline struct VkOffset3D
2114 anv_sanitize_image_offset(const VkImageType imageType
,
2115 const struct VkOffset3D imageOffset
)
2117 switch (imageType
) {
2118 case VK_IMAGE_TYPE_1D
:
2119 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2120 case VK_IMAGE_TYPE_2D
:
2121 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2122 case VK_IMAGE_TYPE_3D
:
2125 unreachable("invalid image type");
2130 void anv_fill_buffer_surface_state(struct anv_device
*device
,
2131 struct anv_state state
,
2132 enum isl_format format
,
2133 uint32_t offset
, uint32_t range
,
2136 void anv_image_view_fill_image_param(struct anv_device
*device
,
2137 struct anv_image_view
*view
,
2138 struct brw_image_param
*param
);
2139 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
2140 struct anv_buffer_view
*view
,
2141 struct brw_image_param
*param
);
2143 struct anv_sampler
{
2147 struct anv_framebuffer
{
2152 uint32_t attachment_count
;
2153 struct anv_image_view
* attachments
[0];
2156 struct anv_subpass
{
2157 uint32_t attachment_count
;
2160 * A pointer to all attachment references used in this subpass.
2161 * Only valid if ::attachment_count > 0.
2163 VkAttachmentReference
* attachments
;
2164 uint32_t input_count
;
2165 VkAttachmentReference
* input_attachments
;
2166 uint32_t color_count
;
2167 VkAttachmentReference
* color_attachments
;
2168 VkAttachmentReference
* resolve_attachments
;
2170 VkAttachmentReference depth_stencil_attachment
;
2174 /** Subpass has a depth/stencil self-dependency */
2175 bool has_ds_self_dep
;
2177 /** Subpass has at least one resolve attachment */
2181 enum anv_subpass_usage
{
2182 ANV_SUBPASS_USAGE_DRAW
= (1 << 0),
2183 ANV_SUBPASS_USAGE_INPUT
= (1 << 1),
2184 ANV_SUBPASS_USAGE_RESOLVE_SRC
= (1 << 2),
2185 ANV_SUBPASS_USAGE_RESOLVE_DST
= (1 << 3),
2188 struct anv_render_pass_attachment
{
2189 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2190 * its members individually.
2194 VkImageUsageFlags usage
;
2195 VkAttachmentLoadOp load_op
;
2196 VkAttachmentStoreOp store_op
;
2197 VkAttachmentLoadOp stencil_load_op
;
2198 VkImageLayout initial_layout
;
2199 VkImageLayout final_layout
;
2201 /* An array, indexed by subpass id, of how the attachment will be used. */
2202 enum anv_subpass_usage
* subpass_usage
;
2204 /* The subpass id in which the attachment will be used last. */
2205 uint32_t last_subpass_idx
;
2208 struct anv_render_pass
{
2209 uint32_t attachment_count
;
2210 uint32_t subpass_count
;
2211 /* An array of subpass_count+1 flushes, one per subpass boundary */
2212 enum anv_pipe_bits
* subpass_flushes
;
2213 struct anv_render_pass_attachment
* attachments
;
2214 struct anv_subpass subpasses
[0];
2217 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2219 struct anv_query_pool
{
2221 VkQueryPipelineStatisticFlags pipeline_statistics
;
2222 /** Stride between slots, in bytes */
2224 /** Number of slots in this query pool */
2229 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
2232 void anv_dump_image_to_ppm(struct anv_device
*device
,
2233 struct anv_image
*image
, unsigned miplevel
,
2234 unsigned array_layer
, VkImageAspectFlagBits aspect
,
2235 const char *filename
);
2237 enum anv_dump_action
{
2238 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
2241 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
2242 void anv_dump_finish(void);
2244 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
2245 struct anv_framebuffer
*fb
);
2247 static inline uint32_t
2248 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
2250 /* This function must be called from within a subpass. */
2251 assert(cmd_state
->pass
&& cmd_state
->subpass
);
2253 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
2255 /* The id of this subpass shouldn't exceed the number of subpasses in this
2256 * render pass minus 1.
2258 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
2262 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2264 static inline struct __anv_type * \
2265 __anv_type ## _from_handle(__VkType _handle) \
2267 return (struct __anv_type *) _handle; \
2270 static inline __VkType \
2271 __anv_type ## _to_handle(struct __anv_type *_obj) \
2273 return (__VkType) _obj; \
2276 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2278 static inline struct __anv_type * \
2279 __anv_type ## _from_handle(__VkType _handle) \
2281 return (struct __anv_type *)(uintptr_t) _handle; \
2284 static inline __VkType \
2285 __anv_type ## _to_handle(struct __anv_type *_obj) \
2287 return (__VkType)(uintptr_t) _obj; \
2290 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2291 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2293 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
2294 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
2295 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
2296 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
2297 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
2299 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
2300 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
2301 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
2302 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
2303 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
2304 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
2305 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
2306 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
2307 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
2308 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
2309 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
2310 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
2311 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
2312 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
2313 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
2314 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
2315 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
2316 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
2317 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
2318 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
2320 /* Gen-specific function declarations */
2322 # include "anv_genX.h"
2324 # define genX(x) gen7_##x
2325 # include "anv_genX.h"
2327 # define genX(x) gen75_##x
2328 # include "anv_genX.h"
2330 # define genX(x) gen8_##x
2331 # include "anv_genX.h"
2333 # define genX(x) gen9_##x
2334 # include "anv_genX.h"
2338 #endif /* ANV_PRIVATE_H */