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b138dea6ed00b7cea6e0b17e195987d2b6ad112b
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
51
52 /* Pre-declarations needed for WSI entrypoints */
53 struct wl_surface;
54 struct wl_display;
55 typedef struct xcb_connection_t xcb_connection_t;
56 typedef uint32_t xcb_visualid_t;
57 typedef uint32_t xcb_window_t;
58
59 struct gen_l3_config;
60
61 #include <vulkan/vulkan.h>
62 #include <vulkan/vulkan_intel.h>
63 #include <vulkan/vk_icd.h>
64
65 #include "anv_entrypoints.h"
66 #include "brw_context.h"
67 #include "isl/isl.h"
68
69 #include "wsi_common.h"
70
71 #ifdef __cplusplus
72 extern "C" {
73 #endif
74
75 #define MAX_VBS 32
76 #define MAX_SETS 8
77 #define MAX_RTS 8
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
82 #define MAX_IMAGES 8
83 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
84
85 #define anv_noreturn __attribute__((__noreturn__))
86 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
87
88 static inline uint32_t
89 align_down_npot_u32(uint32_t v, uint32_t a)
90 {
91 return v - (v % a);
92 }
93
94 static inline uint32_t
95 align_u32(uint32_t v, uint32_t a)
96 {
97 assert(a != 0 && a == (a & -a));
98 return (v + a - 1) & ~(a - 1);
99 }
100
101 static inline uint64_t
102 align_u64(uint64_t v, uint64_t a)
103 {
104 assert(a != 0 && a == (a & -a));
105 return (v + a - 1) & ~(a - 1);
106 }
107
108 static inline int32_t
109 align_i32(int32_t v, int32_t a)
110 {
111 assert(a != 0 && a == (a & -a));
112 return (v + a - 1) & ~(a - 1);
113 }
114
115 /** Alignment must be a power of 2. */
116 static inline bool
117 anv_is_aligned(uintmax_t n, uintmax_t a)
118 {
119 assert(a == (a & -a));
120 return (n & (a - 1)) == 0;
121 }
122
123 static inline uint32_t
124 anv_minify(uint32_t n, uint32_t levels)
125 {
126 if (unlikely(n == 0))
127 return 0;
128 else
129 return MAX2(n >> levels, 1);
130 }
131
132 static inline float
133 anv_clamp_f(float f, float min, float max)
134 {
135 assert(min < max);
136
137 if (f > max)
138 return max;
139 else if (f < min)
140 return min;
141 else
142 return f;
143 }
144
145 static inline bool
146 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
147 {
148 if (*inout_mask & clear_mask) {
149 *inout_mask &= ~clear_mask;
150 return true;
151 } else {
152 return false;
153 }
154 }
155
156 #define for_each_bit(b, dword) \
157 for (uint32_t __dword = (dword); \
158 (b) = __builtin_ffs(__dword) - 1, __dword; \
159 __dword &= ~(1 << (b)))
160
161 #define typed_memcpy(dest, src, count) ({ \
162 static_assert(sizeof(*src) == sizeof(*dest), ""); \
163 memcpy((dest), (src), (count) * sizeof(*(src))); \
164 })
165
166 /* Define no kernel as 1, since that's an illegal offset for a kernel */
167 #define NO_KERNEL 1
168
169 struct anv_common {
170 VkStructureType sType;
171 const void* pNext;
172 };
173
174 /* Whenever we generate an error, pass it through this function. Useful for
175 * debugging, where we can break on it. Only call at error site, not when
176 * propagating errors. Might be useful to plug in a stack trace here.
177 */
178
179 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
180
181 #ifdef DEBUG
182 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
183 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
184 #else
185 #define vk_error(error) error
186 #define vk_errorf(error, format, ...) error
187 #endif
188
189 void __anv_finishme(const char *file, int line, const char *format, ...)
190 anv_printflike(3, 4);
191 void anv_loge(const char *format, ...) anv_printflike(1, 2);
192 void anv_loge_v(const char *format, va_list va);
193
194 /**
195 * Print a FINISHME message, including its source location.
196 */
197 #define anv_finishme(format, ...) ({ \
198 static bool reported = false; \
199 if (!reported) { \
200 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
201 reported = true; \
202 } \
203 })
204
205 /* A non-fatal assert. Useful for debugging. */
206 #ifdef DEBUG
207 #define anv_assert(x) ({ \
208 if (unlikely(!(x))) \
209 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
210 })
211 #else
212 #define anv_assert(x)
213 #endif
214
215 /**
216 * If a block of code is annotated with anv_validate, then the block runs only
217 * in debug builds.
218 */
219 #ifdef DEBUG
220 #define anv_validate if (1)
221 #else
222 #define anv_validate if (0)
223 #endif
224
225 void anv_abortf(const char *format, ...) anv_noreturn anv_printflike(1, 2);
226 void anv_abortfv(const char *format, va_list va) anv_noreturn;
227
228 #define stub_return(v) \
229 do { \
230 anv_finishme("stub %s", __func__); \
231 return (v); \
232 } while (0)
233
234 #define stub() \
235 do { \
236 anv_finishme("stub %s", __func__); \
237 return; \
238 } while (0)
239
240 /**
241 * A dynamically growable, circular buffer. Elements are added at head and
242 * removed from tail. head and tail are free-running uint32_t indices and we
243 * only compute the modulo with size when accessing the array. This way,
244 * number of bytes in the queue is always head - tail, even in case of
245 * wraparound.
246 */
247
248 struct anv_bo {
249 uint32_t gem_handle;
250
251 /* Index into the current validation list. This is used by the
252 * validation list building alrogithm to track which buffers are already
253 * in the validation list so that we can ensure uniqueness.
254 */
255 uint32_t index;
256
257 /* Last known offset. This value is provided by the kernel when we
258 * execbuf and is used as the presumed offset for the next bunch of
259 * relocations.
260 */
261 uint64_t offset;
262
263 uint64_t size;
264 void *map;
265
266 /* We need to set the WRITE flag on winsys bos so GEM will know we're
267 * writing to them and synchronize uses on other rings (eg if the display
268 * server uses the blitter ring).
269 */
270 bool is_winsys_bo;
271 };
272
273 static inline void
274 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
275 {
276 bo->gem_handle = gem_handle;
277 bo->index = 0;
278 bo->offset = 0;
279 bo->size = size;
280 bo->map = NULL;
281 bo->is_winsys_bo = false;
282 }
283
284 /* Represents a lock-free linked list of "free" things. This is used by
285 * both the block pool and the state pools. Unfortunately, in order to
286 * solve the ABA problem, we can't use a single uint32_t head.
287 */
288 union anv_free_list {
289 struct {
290 int32_t offset;
291
292 /* A simple count that is incremented every time the head changes. */
293 uint32_t count;
294 };
295 uint64_t u64;
296 };
297
298 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
299
300 struct anv_block_state {
301 union {
302 struct {
303 uint32_t next;
304 uint32_t end;
305 };
306 uint64_t u64;
307 };
308 };
309
310 struct anv_block_pool {
311 struct anv_device *device;
312
313 struct anv_bo bo;
314
315 /* The offset from the start of the bo to the "center" of the block
316 * pool. Pointers to allocated blocks are given by
317 * bo.map + center_bo_offset + offsets.
318 */
319 uint32_t center_bo_offset;
320
321 /* Current memory map of the block pool. This pointer may or may not
322 * point to the actual beginning of the block pool memory. If
323 * anv_block_pool_alloc_back has ever been called, then this pointer
324 * will point to the "center" position of the buffer and all offsets
325 * (negative or positive) given out by the block pool alloc functions
326 * will be valid relative to this pointer.
327 *
328 * In particular, map == bo.map + center_offset
329 */
330 void *map;
331 int fd;
332
333 /**
334 * Array of mmaps and gem handles owned by the block pool, reclaimed when
335 * the block pool is destroyed.
336 */
337 struct u_vector mmap_cleanups;
338
339 uint32_t block_size;
340
341 union anv_free_list free_list;
342 struct anv_block_state state;
343
344 union anv_free_list back_free_list;
345 struct anv_block_state back_state;
346 };
347
348 /* Block pools are backed by a fixed-size 2GB memfd */
349 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
350
351 /* The center of the block pool is also the middle of the memfd. This may
352 * change in the future if we decide differently for some reason.
353 */
354 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
355
356 static inline uint32_t
357 anv_block_pool_size(struct anv_block_pool *pool)
358 {
359 return pool->state.end + pool->back_state.end;
360 }
361
362 struct anv_state {
363 int32_t offset;
364 uint32_t alloc_size;
365 void *map;
366 };
367
368 struct anv_fixed_size_state_pool {
369 size_t state_size;
370 union anv_free_list free_list;
371 struct anv_block_state block;
372 };
373
374 #define ANV_MIN_STATE_SIZE_LOG2 6
375 #define ANV_MAX_STATE_SIZE_LOG2 17
376
377 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
378
379 struct anv_state_pool {
380 struct anv_block_pool *block_pool;
381 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
382 };
383
384 struct anv_state_stream_block;
385
386 struct anv_state_stream {
387 struct anv_block_pool *block_pool;
388
389 /* The current working block */
390 struct anv_state_stream_block *block;
391
392 /* Offset at which the current block starts */
393 uint32_t start;
394 /* Offset at which to allocate the next state */
395 uint32_t next;
396 /* Offset at which the current block ends */
397 uint32_t end;
398 };
399
400 #define CACHELINE_SIZE 64
401 #define CACHELINE_MASK 63
402
403 static inline void
404 anv_clflush_range(void *start, size_t size)
405 {
406 void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
407 void *end = start + size;
408
409 __builtin_ia32_mfence();
410 while (p < end) {
411 __builtin_ia32_clflush(p);
412 p += CACHELINE_SIZE;
413 }
414 }
415
416 static void inline
417 anv_state_clflush(struct anv_state state)
418 {
419 anv_clflush_range(state.map, state.alloc_size);
420 }
421
422 void anv_block_pool_init(struct anv_block_pool *pool,
423 struct anv_device *device, uint32_t block_size);
424 void anv_block_pool_finish(struct anv_block_pool *pool);
425 int32_t anv_block_pool_alloc(struct anv_block_pool *pool);
426 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool);
427 void anv_block_pool_free(struct anv_block_pool *pool, int32_t offset);
428 void anv_state_pool_init(struct anv_state_pool *pool,
429 struct anv_block_pool *block_pool);
430 void anv_state_pool_finish(struct anv_state_pool *pool);
431 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
432 size_t state_size, size_t alignment);
433 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
434 void anv_state_stream_init(struct anv_state_stream *stream,
435 struct anv_block_pool *block_pool);
436 void anv_state_stream_finish(struct anv_state_stream *stream);
437 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
438 uint32_t size, uint32_t alignment);
439
440 /**
441 * Implements a pool of re-usable BOs. The interface is identical to that
442 * of block_pool except that each block is its own BO.
443 */
444 struct anv_bo_pool {
445 struct anv_device *device;
446
447 void *free_list[16];
448 };
449
450 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
451 void anv_bo_pool_finish(struct anv_bo_pool *pool);
452 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
453 uint32_t size);
454 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
455
456 struct anv_scratch_pool {
457 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
458 struct anv_bo bos[16][MESA_SHADER_STAGES];
459 };
460
461 void anv_scratch_pool_init(struct anv_device *device,
462 struct anv_scratch_pool *pool);
463 void anv_scratch_pool_finish(struct anv_device *device,
464 struct anv_scratch_pool *pool);
465 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
466 struct anv_scratch_pool *pool,
467 gl_shader_stage stage,
468 unsigned per_thread_scratch);
469
470 extern struct anv_dispatch_table dtable;
471
472 #define VK_ICD_WSI_PLATFORM_MAX 5
473
474 struct anv_physical_device {
475 VK_LOADER_DATA _loader_data;
476
477 struct anv_instance * instance;
478 uint32_t chipset_id;
479 char path[20];
480 const char * name;
481 struct gen_device_info info;
482 uint64_t aperture_size;
483 struct brw_compiler * compiler;
484 struct isl_device isl_dev;
485 int cmd_parser_version;
486
487 uint32_t eu_total;
488 uint32_t subslice_total;
489
490 struct wsi_device wsi_device;
491 };
492
493 struct anv_instance {
494 VK_LOADER_DATA _loader_data;
495
496 VkAllocationCallbacks alloc;
497
498 uint32_t apiVersion;
499 int physicalDeviceCount;
500 struct anv_physical_device physicalDevice;
501 };
502
503 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
504 void anv_finish_wsi(struct anv_physical_device *physical_device);
505
506 struct anv_queue {
507 VK_LOADER_DATA _loader_data;
508
509 struct anv_device * device;
510
511 struct anv_state_pool * pool;
512 };
513
514 struct anv_pipeline_cache {
515 struct anv_device * device;
516 pthread_mutex_t mutex;
517
518 struct hash_table * cache;
519 };
520
521 struct anv_pipeline_bind_map;
522
523 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
524 struct anv_device *device,
525 bool cache_enabled);
526 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
527
528 struct anv_shader_bin *
529 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
530 const void *key, uint32_t key_size);
531 struct anv_shader_bin *
532 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
533 const void *key_data, uint32_t key_size,
534 const void *kernel_data, uint32_t kernel_size,
535 const struct brw_stage_prog_data *prog_data,
536 uint32_t prog_data_size,
537 const struct anv_pipeline_bind_map *bind_map);
538
539 struct anv_device {
540 VK_LOADER_DATA _loader_data;
541
542 VkAllocationCallbacks alloc;
543
544 struct anv_instance * instance;
545 uint32_t chipset_id;
546 struct gen_device_info info;
547 struct isl_device isl_dev;
548 int context_id;
549 int fd;
550 bool can_chain_batches;
551 bool robust_buffer_access;
552
553 struct anv_bo_pool batch_bo_pool;
554
555 struct anv_block_pool dynamic_state_block_pool;
556 struct anv_state_pool dynamic_state_pool;
557
558 struct anv_block_pool instruction_block_pool;
559 struct anv_state_pool instruction_state_pool;
560
561 struct anv_block_pool surface_state_block_pool;
562 struct anv_state_pool surface_state_pool;
563
564 struct anv_bo workaround_bo;
565
566 struct anv_pipeline_cache blorp_shader_cache;
567 struct blorp_context blorp;
568
569 struct anv_state border_colors;
570
571 struct anv_queue queue;
572
573 struct anv_scratch_pool scratch_pool;
574
575 uint32_t default_mocs;
576
577 pthread_mutex_t mutex;
578 };
579
580 void anv_device_get_cache_uuid(void *uuid);
581
582 void anv_device_init_blorp(struct anv_device *device);
583 void anv_device_finish_blorp(struct anv_device *device);
584
585 VkResult anv_device_execbuf(struct anv_device *device,
586 struct drm_i915_gem_execbuffer2 *execbuf,
587 struct anv_bo **execbuf_bos);
588
589 void* anv_gem_mmap(struct anv_device *device,
590 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
591 void anv_gem_munmap(void *p, uint64_t size);
592 uint32_t anv_gem_create(struct anv_device *device, size_t size);
593 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
594 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
595 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
596 int anv_gem_execbuffer(struct anv_device *device,
597 struct drm_i915_gem_execbuffer2 *execbuf);
598 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
599 uint32_t stride, uint32_t tiling);
600 int anv_gem_create_context(struct anv_device *device);
601 int anv_gem_destroy_context(struct anv_device *device, int context);
602 int anv_gem_get_param(int fd, uint32_t param);
603 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
604 int anv_gem_get_aperture(int fd, uint64_t *size);
605 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
606 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
607 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
608 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
609 uint32_t read_domains, uint32_t write_domain);
610
611 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
612
613 struct anv_reloc_list {
614 size_t num_relocs;
615 size_t array_length;
616 struct drm_i915_gem_relocation_entry * relocs;
617 struct anv_bo ** reloc_bos;
618 };
619
620 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
621 const VkAllocationCallbacks *alloc);
622 void anv_reloc_list_finish(struct anv_reloc_list *list,
623 const VkAllocationCallbacks *alloc);
624
625 uint64_t anv_reloc_list_add(struct anv_reloc_list *list,
626 const VkAllocationCallbacks *alloc,
627 uint32_t offset, struct anv_bo *target_bo,
628 uint32_t delta);
629
630 struct anv_batch_bo {
631 /* Link in the anv_cmd_buffer.owned_batch_bos list */
632 struct list_head link;
633
634 struct anv_bo bo;
635
636 /* Bytes actually consumed in this batch BO */
637 size_t length;
638
639 /* Last seen surface state block pool bo offset */
640 uint32_t last_ss_pool_bo_offset;
641
642 struct anv_reloc_list relocs;
643 };
644
645 struct anv_batch {
646 const VkAllocationCallbacks * alloc;
647
648 void * start;
649 void * end;
650 void * next;
651
652 struct anv_reloc_list * relocs;
653
654 /* This callback is called (with the associated user data) in the event
655 * that the batch runs out of space.
656 */
657 VkResult (*extend_cb)(struct anv_batch *, void *);
658 void * user_data;
659 };
660
661 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
662 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
663 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
664 void *location, struct anv_bo *bo, uint32_t offset);
665 VkResult anv_device_submit_simple_batch(struct anv_device *device,
666 struct anv_batch *batch);
667
668 struct anv_address {
669 struct anv_bo *bo;
670 uint32_t offset;
671 };
672
673 static inline uint64_t
674 _anv_combine_address(struct anv_batch *batch, void *location,
675 const struct anv_address address, uint32_t delta)
676 {
677 if (address.bo == NULL) {
678 return address.offset + delta;
679 } else {
680 assert(batch->start <= location && location < batch->end);
681
682 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
683 }
684 }
685
686 #define __gen_address_type struct anv_address
687 #define __gen_user_data struct anv_batch
688 #define __gen_combine_address _anv_combine_address
689
690 /* Wrapper macros needed to work around preprocessor argument issues. In
691 * particular, arguments don't get pre-evaluated if they are concatenated.
692 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
693 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
694 * We can work around this easily enough with these helpers.
695 */
696 #define __anv_cmd_length(cmd) cmd ## _length
697 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
698 #define __anv_cmd_header(cmd) cmd ## _header
699 #define __anv_cmd_pack(cmd) cmd ## _pack
700 #define __anv_reg_num(reg) reg ## _num
701
702 #define anv_pack_struct(dst, struc, ...) do { \
703 struct struc __template = { \
704 __VA_ARGS__ \
705 }; \
706 __anv_cmd_pack(struc)(NULL, dst, &__template); \
707 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
708 } while (0)
709
710 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
711 void *__dst = anv_batch_emit_dwords(batch, n); \
712 struct cmd __template = { \
713 __anv_cmd_header(cmd), \
714 .DWordLength = n - __anv_cmd_length_bias(cmd), \
715 __VA_ARGS__ \
716 }; \
717 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
718 __dst; \
719 })
720
721 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
722 do { \
723 uint32_t *dw; \
724 \
725 static_assert(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1), "mismatch merge"); \
726 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
727 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
728 dw[i] = (dwords0)[i] | (dwords1)[i]; \
729 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
730 } while (0)
731
732 #define anv_batch_emit(batch, cmd, name) \
733 for (struct cmd name = { __anv_cmd_header(cmd) }, \
734 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
735 __builtin_expect(_dst != NULL, 1); \
736 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
737 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
738 _dst = NULL; \
739 }))
740
741 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
742 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
743 struct anv_state __state = \
744 anv_state_pool_alloc((pool), __size, align); \
745 struct cmd __template = { \
746 __VA_ARGS__ \
747 }; \
748 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
749 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
750 if (!(pool)->block_pool->device->info.has_llc) \
751 anv_state_clflush(__state); \
752 __state; \
753 })
754
755 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
756 .GraphicsDataTypeGFDT = 0, \
757 .LLCCacheabilityControlLLCCC = 0, \
758 .L3CacheabilityControlL3CC = 1, \
759 }
760
761 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
762 .LLCeLLCCacheabilityControlLLCCC = 0, \
763 .L3CacheabilityControlL3CC = 1, \
764 }
765
766 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
767 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
768 .TargetCache = L3DefertoPATforLLCeLLCselection, \
769 .AgeforQUADLRU = 0 \
770 }
771
772 /* Skylake: MOCS is now an index into an array of 62 different caching
773 * configurations programmed by the kernel.
774 */
775
776 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
777 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
778 .IndextoMOCSTables = 2 \
779 }
780
781 #define GEN9_MOCS_PTE { \
782 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
783 .IndextoMOCSTables = 1 \
784 }
785
786 struct anv_device_memory {
787 struct anv_bo bo;
788 uint32_t type_index;
789 VkDeviceSize map_size;
790 void * map;
791 };
792
793 /**
794 * Header for Vertex URB Entry (VUE)
795 */
796 struct anv_vue_header {
797 uint32_t Reserved;
798 uint32_t RTAIndex; /* RenderTargetArrayIndex */
799 uint32_t ViewportIndex;
800 float PointWidth;
801 };
802
803 struct anv_descriptor_set_binding_layout {
804 #ifndef NDEBUG
805 /* The type of the descriptors in this binding */
806 VkDescriptorType type;
807 #endif
808
809 /* Number of array elements in this binding */
810 uint16_t array_size;
811
812 /* Index into the flattend descriptor set */
813 uint16_t descriptor_index;
814
815 /* Index into the dynamic state array for a dynamic buffer */
816 int16_t dynamic_offset_index;
817
818 /* Index into the descriptor set buffer views */
819 int16_t buffer_index;
820
821 struct {
822 /* Index into the binding table for the associated surface */
823 int16_t surface_index;
824
825 /* Index into the sampler table for the associated sampler */
826 int16_t sampler_index;
827
828 /* Index into the image table for the associated image */
829 int16_t image_index;
830 } stage[MESA_SHADER_STAGES];
831
832 /* Immutable samplers (or NULL if no immutable samplers) */
833 struct anv_sampler **immutable_samplers;
834 };
835
836 struct anv_descriptor_set_layout {
837 /* Number of bindings in this descriptor set */
838 uint16_t binding_count;
839
840 /* Total size of the descriptor set with room for all array entries */
841 uint16_t size;
842
843 /* Shader stages affected by this descriptor set */
844 uint16_t shader_stages;
845
846 /* Number of buffers in this descriptor set */
847 uint16_t buffer_count;
848
849 /* Number of dynamic offsets used by this descriptor set */
850 uint16_t dynamic_offset_count;
851
852 /* Bindings in this descriptor set */
853 struct anv_descriptor_set_binding_layout binding[0];
854 };
855
856 struct anv_descriptor {
857 VkDescriptorType type;
858
859 union {
860 struct {
861 struct anv_image_view *image_view;
862 struct anv_sampler *sampler;
863 };
864
865 struct anv_buffer_view *buffer_view;
866 };
867 };
868
869 struct anv_descriptor_set {
870 const struct anv_descriptor_set_layout *layout;
871 uint32_t size;
872 uint32_t buffer_count;
873 struct anv_buffer_view *buffer_views;
874 struct anv_descriptor descriptors[0];
875 };
876
877 struct anv_descriptor_pool {
878 uint32_t size;
879 uint32_t next;
880 uint32_t free_list;
881
882 struct anv_state_stream surface_state_stream;
883 void *surface_state_free_list;
884
885 char data[0];
886 };
887
888 VkResult
889 anv_descriptor_set_create(struct anv_device *device,
890 struct anv_descriptor_pool *pool,
891 const struct anv_descriptor_set_layout *layout,
892 struct anv_descriptor_set **out_set);
893
894 void
895 anv_descriptor_set_destroy(struct anv_device *device,
896 struct anv_descriptor_pool *pool,
897 struct anv_descriptor_set *set);
898
899 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
900
901 struct anv_pipeline_binding {
902 /* The descriptor set this surface corresponds to. The special value of
903 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
904 * to a color attachment and not a regular descriptor.
905 */
906 uint8_t set;
907
908 /* Binding in the descriptor set */
909 uint8_t binding;
910
911 /* Index in the binding */
912 uint8_t index;
913 };
914
915 struct anv_pipeline_layout {
916 struct {
917 struct anv_descriptor_set_layout *layout;
918 uint32_t dynamic_offset_start;
919 } set[MAX_SETS];
920
921 uint32_t num_sets;
922
923 struct {
924 bool has_dynamic_offsets;
925 } stage[MESA_SHADER_STAGES];
926
927 unsigned char sha1[20];
928 };
929
930 struct anv_buffer {
931 struct anv_device * device;
932 VkDeviceSize size;
933
934 VkBufferUsageFlags usage;
935
936 /* Set when bound */
937 struct anv_bo * bo;
938 VkDeviceSize offset;
939 };
940
941 enum anv_cmd_dirty_bits {
942 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
943 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
944 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
945 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
946 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
947 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
948 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
949 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
950 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
951 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
952 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
953 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
954 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
955 };
956 typedef uint32_t anv_cmd_dirty_mask_t;
957
958 enum anv_pipe_bits {
959 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
960 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
961 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
962 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
963 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
964 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
965 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
966 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
967 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
968 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
969 ANV_PIPE_CS_STALL_BIT = (1 << 20),
970
971 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
972 * a flush has happened but not a CS stall. The next time we do any sort
973 * of invalidation we need to insert a CS stall at that time. Otherwise,
974 * we would have to CS stall on every flush which could be bad.
975 */
976 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
977 };
978
979 #define ANV_PIPE_FLUSH_BITS ( \
980 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
981 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
982 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
983
984 #define ANV_PIPE_STALL_BITS ( \
985 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
986 ANV_PIPE_DEPTH_STALL_BIT | \
987 ANV_PIPE_CS_STALL_BIT)
988
989 #define ANV_PIPE_INVALIDATE_BITS ( \
990 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
991 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
992 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
993 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
994 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
995 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
996
997 struct anv_vertex_binding {
998 struct anv_buffer * buffer;
999 VkDeviceSize offset;
1000 };
1001
1002 struct anv_push_constants {
1003 /* Current allocated size of this push constants data structure.
1004 * Because a decent chunk of it may not be used (images on SKL, for
1005 * instance), we won't actually allocate the entire structure up-front.
1006 */
1007 uint32_t size;
1008
1009 /* Push constant data provided by the client through vkPushConstants */
1010 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1011
1012 /* Our hardware only provides zero-based vertex and instance id so, in
1013 * order to satisfy the vulkan requirements, we may have to push one or
1014 * both of these into the shader.
1015 */
1016 uint32_t base_vertex;
1017 uint32_t base_instance;
1018
1019 /* Offsets and ranges for dynamically bound buffers */
1020 struct {
1021 uint32_t offset;
1022 uint32_t range;
1023 } dynamic[MAX_DYNAMIC_BUFFERS];
1024
1025 /* Image data for image_load_store on pre-SKL */
1026 struct brw_image_param images[MAX_IMAGES];
1027 };
1028
1029 struct anv_dynamic_state {
1030 struct {
1031 uint32_t count;
1032 VkViewport viewports[MAX_VIEWPORTS];
1033 } viewport;
1034
1035 struct {
1036 uint32_t count;
1037 VkRect2D scissors[MAX_SCISSORS];
1038 } scissor;
1039
1040 float line_width;
1041
1042 struct {
1043 float bias;
1044 float clamp;
1045 float slope;
1046 } depth_bias;
1047
1048 float blend_constants[4];
1049
1050 struct {
1051 float min;
1052 float max;
1053 } depth_bounds;
1054
1055 struct {
1056 uint32_t front;
1057 uint32_t back;
1058 } stencil_compare_mask;
1059
1060 struct {
1061 uint32_t front;
1062 uint32_t back;
1063 } stencil_write_mask;
1064
1065 struct {
1066 uint32_t front;
1067 uint32_t back;
1068 } stencil_reference;
1069 };
1070
1071 extern const struct anv_dynamic_state default_dynamic_state;
1072
1073 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1074 const struct anv_dynamic_state *src,
1075 uint32_t copy_mask);
1076
1077 /**
1078 * Attachment state when recording a renderpass instance.
1079 *
1080 * The clear value is valid only if there exists a pending clear.
1081 */
1082 struct anv_attachment_state {
1083 VkImageAspectFlags pending_clear_aspects;
1084 VkClearValue clear_value;
1085 };
1086
1087 /** State required while building cmd buffer */
1088 struct anv_cmd_state {
1089 /* PIPELINE_SELECT.PipelineSelection */
1090 uint32_t current_pipeline;
1091 const struct gen_l3_config * current_l3_config;
1092 uint32_t vb_dirty;
1093 anv_cmd_dirty_mask_t dirty;
1094 anv_cmd_dirty_mask_t compute_dirty;
1095 enum anv_pipe_bits pending_pipe_bits;
1096 uint32_t num_workgroups_offset;
1097 struct anv_bo *num_workgroups_bo;
1098 VkShaderStageFlags descriptors_dirty;
1099 VkShaderStageFlags push_constants_dirty;
1100 uint32_t scratch_size;
1101 struct anv_pipeline * pipeline;
1102 struct anv_pipeline * compute_pipeline;
1103 struct anv_framebuffer * framebuffer;
1104 struct anv_render_pass * pass;
1105 struct anv_subpass * subpass;
1106 VkRect2D render_area;
1107 uint32_t restart_index;
1108 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1109 struct anv_descriptor_set * descriptors[MAX_SETS];
1110 VkShaderStageFlags push_constant_stages;
1111 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1112 struct anv_state binding_tables[MESA_SHADER_STAGES];
1113 struct anv_state samplers[MESA_SHADER_STAGES];
1114 struct anv_dynamic_state dynamic;
1115 bool need_query_wa;
1116
1117 /**
1118 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1119 * valid only when recording a render pass instance.
1120 */
1121 struct anv_attachment_state * attachments;
1122
1123 struct {
1124 struct anv_buffer * index_buffer;
1125 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1126 uint32_t index_offset;
1127 } gen7;
1128 };
1129
1130 struct anv_cmd_pool {
1131 VkAllocationCallbacks alloc;
1132 struct list_head cmd_buffers;
1133 };
1134
1135 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1136
1137 enum anv_cmd_buffer_exec_mode {
1138 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1139 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1140 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1141 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1142 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1143 };
1144
1145 struct anv_cmd_buffer {
1146 VK_LOADER_DATA _loader_data;
1147
1148 struct anv_device * device;
1149
1150 struct anv_cmd_pool * pool;
1151 struct list_head pool_link;
1152
1153 struct anv_batch batch;
1154
1155 /* Fields required for the actual chain of anv_batch_bo's.
1156 *
1157 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1158 */
1159 struct list_head batch_bos;
1160 enum anv_cmd_buffer_exec_mode exec_mode;
1161
1162 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1163 * referenced by this command buffer
1164 *
1165 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1166 */
1167 struct u_vector seen_bbos;
1168
1169 /* A vector of int32_t's for every block of binding tables.
1170 *
1171 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1172 */
1173 struct u_vector bt_blocks;
1174 uint32_t bt_next;
1175 struct anv_reloc_list surface_relocs;
1176
1177 /* Information needed for execbuf
1178 *
1179 * These fields are generated by anv_cmd_buffer_prepare_execbuf().
1180 */
1181 struct {
1182 struct drm_i915_gem_execbuffer2 execbuf;
1183
1184 struct drm_i915_gem_exec_object2 * objects;
1185 uint32_t bo_count;
1186 struct anv_bo ** bos;
1187
1188 /* Allocated length of the 'objects' and 'bos' arrays */
1189 uint32_t array_length;
1190 } execbuf2;
1191
1192 /* Serial for tracking buffer completion */
1193 uint32_t serial;
1194
1195 /* Stream objects for storing temporary data */
1196 struct anv_state_stream surface_state_stream;
1197 struct anv_state_stream dynamic_state_stream;
1198
1199 VkCommandBufferUsageFlags usage_flags;
1200 VkCommandBufferLevel level;
1201
1202 struct anv_cmd_state state;
1203 };
1204
1205 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1206 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1207 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1208 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1209 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1210 struct anv_cmd_buffer *secondary);
1211 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1212 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1213 struct anv_cmd_buffer *cmd_buffer);
1214
1215 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1216
1217 VkResult
1218 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1219 gl_shader_stage stage, uint32_t size);
1220 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1221 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1222 (offsetof(struct anv_push_constants, field) + \
1223 sizeof(cmd_buffer->state.push_constants[0]->field)))
1224
1225 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1226 const void *data, uint32_t size, uint32_t alignment);
1227 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1228 uint32_t *a, uint32_t *b,
1229 uint32_t dwords, uint32_t alignment);
1230
1231 struct anv_address
1232 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1233 struct anv_state
1234 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1235 uint32_t entries, uint32_t *state_offset);
1236 struct anv_state
1237 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1238 struct anv_state
1239 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1240 uint32_t size, uint32_t alignment);
1241
1242 VkResult
1243 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1244
1245 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1246 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1247 bool depth_clamp_enable);
1248 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1249
1250 void anv_cmd_state_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1251 const VkRenderPassBeginInfo *info);
1252
1253 struct anv_state
1254 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1255 gl_shader_stage stage);
1256 struct anv_state
1257 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1258
1259 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1260 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1261
1262 const struct anv_image_view *
1263 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1264
1265 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1266
1267 struct anv_fence {
1268 struct anv_bo bo;
1269 struct drm_i915_gem_execbuffer2 execbuf;
1270 struct drm_i915_gem_exec_object2 exec2_objects[1];
1271 bool ready;
1272 };
1273
1274 struct anv_event {
1275 uint64_t semaphore;
1276 struct anv_state state;
1277 };
1278
1279 struct anv_shader_module {
1280 unsigned char sha1[20];
1281 uint32_t size;
1282 char data[0];
1283 };
1284
1285 void anv_hash_shader(unsigned char *hash, const void *key, size_t key_size,
1286 struct anv_shader_module *module,
1287 const char *entrypoint,
1288 const struct anv_pipeline_layout *pipeline_layout,
1289 const VkSpecializationInfo *spec_info);
1290
1291 static inline gl_shader_stage
1292 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1293 {
1294 assert(__builtin_popcount(vk_stage) == 1);
1295 return ffs(vk_stage) - 1;
1296 }
1297
1298 static inline VkShaderStageFlagBits
1299 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1300 {
1301 return (1 << mesa_stage);
1302 }
1303
1304 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1305
1306 #define anv_foreach_stage(stage, stage_bits) \
1307 for (gl_shader_stage stage, \
1308 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1309 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1310 __tmp &= ~(1 << (stage)))
1311
1312 struct anv_pipeline_bind_map {
1313 uint32_t surface_count;
1314 uint32_t sampler_count;
1315 uint32_t image_count;
1316
1317 struct anv_pipeline_binding * surface_to_descriptor;
1318 struct anv_pipeline_binding * sampler_to_descriptor;
1319 };
1320
1321 struct anv_shader_bin_key {
1322 uint32_t size;
1323 uint8_t data[0];
1324 };
1325
1326 struct anv_shader_bin {
1327 uint32_t ref_cnt;
1328
1329 const struct anv_shader_bin_key *key;
1330
1331 struct anv_state kernel;
1332 uint32_t kernel_size;
1333
1334 const struct brw_stage_prog_data *prog_data;
1335 uint32_t prog_data_size;
1336
1337 struct anv_pipeline_bind_map bind_map;
1338
1339 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1340 };
1341
1342 struct anv_shader_bin *
1343 anv_shader_bin_create(struct anv_device *device,
1344 const void *key, uint32_t key_size,
1345 const void *kernel, uint32_t kernel_size,
1346 const struct brw_stage_prog_data *prog_data,
1347 uint32_t prog_data_size, const void *prog_data_param,
1348 const struct anv_pipeline_bind_map *bind_map);
1349
1350 void
1351 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
1352
1353 static inline void
1354 anv_shader_bin_ref(struct anv_shader_bin *shader)
1355 {
1356 assert(shader->ref_cnt >= 1);
1357 __sync_fetch_and_add(&shader->ref_cnt, 1);
1358 }
1359
1360 static inline void
1361 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
1362 {
1363 assert(shader->ref_cnt >= 1);
1364 if (__sync_fetch_and_add(&shader->ref_cnt, -1) == 1)
1365 anv_shader_bin_destroy(device, shader);
1366 }
1367
1368 struct anv_pipeline {
1369 struct anv_device * device;
1370 struct anv_batch batch;
1371 uint32_t batch_data[512];
1372 struct anv_reloc_list batch_relocs;
1373 uint32_t dynamic_state_mask;
1374 struct anv_dynamic_state dynamic_state;
1375
1376 struct anv_pipeline_layout * layout;
1377
1378 bool needs_data_cache;
1379
1380 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
1381
1382 struct {
1383 const struct gen_l3_config * l3_config;
1384 uint32_t total_size;
1385 } urb;
1386
1387 VkShaderStageFlags active_stages;
1388 struct anv_state blend_state;
1389 uint32_t vs_simd8;
1390 uint32_t vs_vec4;
1391 uint32_t ps_ksp0;
1392 uint32_t gs_kernel;
1393 uint32_t cs_simd;
1394
1395 uint32_t vb_used;
1396 uint32_t binding_stride[MAX_VBS];
1397 bool instancing_enable[MAX_VBS];
1398 bool primitive_restart;
1399 uint32_t topology;
1400
1401 uint32_t cs_right_mask;
1402
1403 bool depth_clamp_enable;
1404
1405 struct {
1406 uint32_t sf[7];
1407 uint32_t depth_stencil_state[3];
1408 } gen7;
1409
1410 struct {
1411 uint32_t sf[4];
1412 uint32_t raster[5];
1413 uint32_t wm_depth_stencil[3];
1414 } gen8;
1415
1416 struct {
1417 uint32_t wm_depth_stencil[4];
1418 } gen9;
1419 };
1420
1421 static inline bool
1422 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
1423 gl_shader_stage stage)
1424 {
1425 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
1426 }
1427
1428 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1429 static inline const struct brw_##prefix##_prog_data * \
1430 get_##prefix##_prog_data(struct anv_pipeline *pipeline) \
1431 { \
1432 if (anv_pipeline_has_stage(pipeline, stage)) { \
1433 return (const struct brw_##prefix##_prog_data *) \
1434 pipeline->shaders[stage]->prog_data; \
1435 } else { \
1436 return NULL; \
1437 } \
1438 }
1439
1440 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
1441 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
1442 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
1443 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
1444
1445 VkResult
1446 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
1447 struct anv_pipeline_cache *cache,
1448 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1449 const VkAllocationCallbacks *alloc);
1450
1451 VkResult
1452 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1453 struct anv_pipeline_cache *cache,
1454 const VkComputePipelineCreateInfo *info,
1455 struct anv_shader_module *module,
1456 const char *entrypoint,
1457 const VkSpecializationInfo *spec_info);
1458
1459 struct anv_format {
1460 enum isl_format isl_format:16;
1461 struct isl_swizzle swizzle;
1462 };
1463
1464 struct anv_format
1465 anv_get_format(const struct gen_device_info *devinfo, VkFormat format,
1466 VkImageAspectFlags aspect, VkImageTiling tiling);
1467
1468 static inline enum isl_format
1469 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
1470 VkImageAspectFlags aspect, VkImageTiling tiling)
1471 {
1472 return anv_get_format(devinfo, vk_format, aspect, tiling).isl_format;
1473 }
1474
1475 void
1476 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
1477
1478 /**
1479 * Subsurface of an anv_image.
1480 */
1481 struct anv_surface {
1482 /** Valid only if isl_surf::size > 0. */
1483 struct isl_surf isl;
1484
1485 /**
1486 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1487 */
1488 uint32_t offset;
1489 };
1490
1491 struct anv_image {
1492 VkImageType type;
1493 /* The original VkFormat provided by the client. This may not match any
1494 * of the actual surface formats.
1495 */
1496 VkFormat vk_format;
1497 VkImageAspectFlags aspects;
1498 VkExtent3D extent;
1499 uint32_t levels;
1500 uint32_t array_size;
1501 uint32_t samples; /**< VkImageCreateInfo::samples */
1502 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1503 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1504
1505 VkDeviceSize size;
1506 uint32_t alignment;
1507
1508 /* Set when bound */
1509 struct anv_bo *bo;
1510 VkDeviceSize offset;
1511
1512 /**
1513 * Image subsurfaces
1514 *
1515 * For each foo, anv_image::foo_surface is valid if and only if
1516 * anv_image::aspects has a foo aspect.
1517 *
1518 * The hardware requires that the depth buffer and stencil buffer be
1519 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1520 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1521 * allocate the depth and stencil buffers as separate surfaces in the same
1522 * bo.
1523 */
1524 union {
1525 struct anv_surface color_surface;
1526
1527 struct {
1528 struct anv_surface depth_surface;
1529 struct anv_surface hiz_surface;
1530 struct anv_surface stencil_surface;
1531 };
1532 };
1533 };
1534
1535 static inline uint32_t
1536 anv_get_layerCount(const struct anv_image *image,
1537 const VkImageSubresourceRange *range)
1538 {
1539 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1540 image->array_size - range->baseArrayLayer : range->layerCount;
1541 }
1542
1543 static inline uint32_t
1544 anv_get_levelCount(const struct anv_image *image,
1545 const VkImageSubresourceRange *range)
1546 {
1547 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1548 image->levels - range->baseMipLevel : range->levelCount;
1549 }
1550
1551
1552 struct anv_image_view {
1553 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
1554 struct anv_bo *bo;
1555 uint32_t offset; /**< Offset into bo. */
1556
1557 struct isl_view isl;
1558
1559 VkImageAspectFlags aspect_mask;
1560 VkFormat vk_format;
1561 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1562
1563 /** RENDER_SURFACE_STATE when using image as a color render target. */
1564 struct anv_state color_rt_surface_state;
1565
1566 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1567 struct anv_state sampler_surface_state;
1568
1569 /** RENDER_SURFACE_STATE when using image as a storage image. */
1570 struct anv_state storage_surface_state;
1571
1572 struct brw_image_param storage_image_param;
1573 };
1574
1575 struct anv_image_create_info {
1576 const VkImageCreateInfo *vk_info;
1577
1578 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1579 isl_tiling_flags_t isl_tiling_flags;
1580
1581 uint32_t stride;
1582 };
1583
1584 VkResult anv_image_create(VkDevice _device,
1585 const struct anv_image_create_info *info,
1586 const VkAllocationCallbacks* alloc,
1587 VkImage *pImage);
1588
1589 const struct anv_surface *
1590 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
1591 VkImageAspectFlags aspect_mask);
1592
1593 static inline bool
1594 anv_image_has_hiz(const struct anv_image *image)
1595 {
1596 /* We must check the aspect because anv_image::hiz_surface belongs to
1597 * a union.
1598 */
1599 return (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1600 image->hiz_surface.isl.size > 0;
1601 }
1602
1603 struct anv_buffer_view {
1604 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1605 struct anv_bo *bo;
1606 uint32_t offset; /**< Offset into bo. */
1607 uint64_t range; /**< VkBufferViewCreateInfo::range */
1608
1609 struct anv_state surface_state;
1610 struct anv_state storage_surface_state;
1611
1612 struct brw_image_param storage_image_param;
1613 };
1614
1615 enum isl_format
1616 anv_isl_format_for_descriptor_type(VkDescriptorType type);
1617
1618 static inline struct VkExtent3D
1619 anv_sanitize_image_extent(const VkImageType imageType,
1620 const struct VkExtent3D imageExtent)
1621 {
1622 switch (imageType) {
1623 case VK_IMAGE_TYPE_1D:
1624 return (VkExtent3D) { imageExtent.width, 1, 1 };
1625 case VK_IMAGE_TYPE_2D:
1626 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1627 case VK_IMAGE_TYPE_3D:
1628 return imageExtent;
1629 default:
1630 unreachable("invalid image type");
1631 }
1632 }
1633
1634 static inline struct VkOffset3D
1635 anv_sanitize_image_offset(const VkImageType imageType,
1636 const struct VkOffset3D imageOffset)
1637 {
1638 switch (imageType) {
1639 case VK_IMAGE_TYPE_1D:
1640 return (VkOffset3D) { imageOffset.x, 0, 0 };
1641 case VK_IMAGE_TYPE_2D:
1642 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1643 case VK_IMAGE_TYPE_3D:
1644 return imageOffset;
1645 default:
1646 unreachable("invalid image type");
1647 }
1648 }
1649
1650
1651 void anv_fill_buffer_surface_state(struct anv_device *device,
1652 struct anv_state state,
1653 enum isl_format format,
1654 uint32_t offset, uint32_t range,
1655 uint32_t stride);
1656
1657 void anv_image_view_fill_image_param(struct anv_device *device,
1658 struct anv_image_view *view,
1659 struct brw_image_param *param);
1660 void anv_buffer_view_fill_image_param(struct anv_device *device,
1661 struct anv_buffer_view *view,
1662 struct brw_image_param *param);
1663
1664 struct anv_sampler {
1665 uint32_t state[4];
1666 };
1667
1668 struct anv_framebuffer {
1669 uint32_t width;
1670 uint32_t height;
1671 uint32_t layers;
1672
1673 uint32_t attachment_count;
1674 struct anv_image_view * attachments[0];
1675 };
1676
1677 struct anv_subpass {
1678 uint32_t input_count;
1679 uint32_t * input_attachments;
1680 uint32_t color_count;
1681 uint32_t * color_attachments;
1682 uint32_t * resolve_attachments;
1683 uint32_t depth_stencil_attachment;
1684
1685 /** Subpass has at least one resolve attachment */
1686 bool has_resolve;
1687 };
1688
1689 struct anv_render_pass_attachment {
1690 VkFormat format;
1691 uint32_t samples;
1692 VkAttachmentLoadOp load_op;
1693 VkAttachmentStoreOp store_op;
1694 VkAttachmentLoadOp stencil_load_op;
1695 };
1696
1697 struct anv_render_pass {
1698 uint32_t attachment_count;
1699 uint32_t subpass_count;
1700 uint32_t * subpass_attachments;
1701 struct anv_render_pass_attachment * attachments;
1702 struct anv_subpass subpasses[0];
1703 };
1704
1705 struct anv_query_pool_slot {
1706 uint64_t begin;
1707 uint64_t end;
1708 uint64_t available;
1709 };
1710
1711 struct anv_query_pool {
1712 VkQueryType type;
1713 uint32_t slots;
1714 struct anv_bo bo;
1715 };
1716
1717 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
1718 const char *name);
1719
1720 void anv_dump_image_to_ppm(struct anv_device *device,
1721 struct anv_image *image, unsigned miplevel,
1722 unsigned array_layer, VkImageAspectFlagBits aspect,
1723 const char *filename);
1724
1725 enum anv_dump_action {
1726 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
1727 };
1728
1729 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
1730 void anv_dump_finish(void);
1731
1732 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
1733 struct anv_framebuffer *fb);
1734
1735 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1736 \
1737 static inline struct __anv_type * \
1738 __anv_type ## _from_handle(__VkType _handle) \
1739 { \
1740 return (struct __anv_type *) _handle; \
1741 } \
1742 \
1743 static inline __VkType \
1744 __anv_type ## _to_handle(struct __anv_type *_obj) \
1745 { \
1746 return (__VkType) _obj; \
1747 }
1748
1749 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1750 \
1751 static inline struct __anv_type * \
1752 __anv_type ## _from_handle(__VkType _handle) \
1753 { \
1754 return (struct __anv_type *)(uintptr_t) _handle; \
1755 } \
1756 \
1757 static inline __VkType \
1758 __anv_type ## _to_handle(struct __anv_type *_obj) \
1759 { \
1760 return (__VkType)(uintptr_t) _obj; \
1761 }
1762
1763 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1764 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1765
1766 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
1767 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
1768 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
1769 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
1770 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
1771
1772 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
1773 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
1774 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
1775 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
1776 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
1777 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
1778 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
1779 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
1780 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
1781 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
1782 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
1783 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
1784 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
1785 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
1786 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
1787 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
1788 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
1789 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
1790 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
1791
1792 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1793 \
1794 static inline const __VkType * \
1795 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1796 { \
1797 return (const __VkType *) __anv_obj; \
1798 }
1799
1800 #define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1801 const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name)
1802
1803 ANV_DEFINE_STRUCT_CASTS(anv_common, VkMemoryBarrier)
1804 ANV_DEFINE_STRUCT_CASTS(anv_common, VkBufferMemoryBarrier)
1805 ANV_DEFINE_STRUCT_CASTS(anv_common, VkImageMemoryBarrier)
1806
1807 /* Gen-specific function declarations */
1808 #ifdef genX
1809 # include "anv_genX.h"
1810 #else
1811 # define genX(x) gen7_##x
1812 # include "anv_genX.h"
1813 # undef genX
1814 # define genX(x) gen75_##x
1815 # include "anv_genX.h"
1816 # undef genX
1817 # define genX(x) gen8_##x
1818 # include "anv_genX.h"
1819 # undef genX
1820 # define genX(x) gen9_##x
1821 # include "anv_genX.h"
1822 # undef genX
1823 #endif
1824
1825 #ifdef __cplusplus
1826 }
1827 #endif
1828
1829 #endif /* ANV_PRIVATE_H */