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anv: Better types for 'aspect' function params
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53
54 /* Pre-declarations needed for WSI entrypoints */
55 struct wl_surface;
56 struct wl_display;
57 typedef struct xcb_connection_t xcb_connection_t;
58 typedef uint32_t xcb_visualid_t;
59 typedef uint32_t xcb_window_t;
60
61 struct anv_buffer;
62 struct anv_buffer_view;
63 struct anv_image_view;
64 struct anv_instance;
65 struct anv_debug_report_callback;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72 #include <vulkan/vk_android_native_buffer.h>
73
74 #include "anv_entrypoints.h"
75 #include "isl/isl.h"
76
77 #include "common/gen_debug.h"
78 #include "common/intel_log.h"
79 #include "wsi_common.h"
80
81 /* Allowing different clear colors requires us to perform a depth resolve at
82 * the end of certain render passes. This is because while slow clears store
83 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
84 * See the PRMs for examples describing when additional resolves would be
85 * necessary. To enable fast clears without requiring extra resolves, we set
86 * the clear value to a globally-defined one. We could allow different values
87 * if the user doesn't expect coherent data during or after a render passes
88 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
89 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
90 * 1.0f seems to be the only value used. The only application that doesn't set
91 * this value does so through the usage of an seemingly uninitialized clear
92 * value.
93 */
94 #define ANV_HZ_FC_VAL 1.0f
95
96 #define MAX_VBS 28
97 #define MAX_SETS 8
98 #define MAX_RTS 8
99 #define MAX_VIEWPORTS 16
100 #define MAX_SCISSORS 16
101 #define MAX_PUSH_CONSTANTS_SIZE 128
102 #define MAX_DYNAMIC_BUFFERS 16
103 #define MAX_IMAGES 8
104 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
105
106 #define ANV_SVGS_VB_INDEX MAX_VBS
107 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
108
109 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_down_npot_u32(uint32_t v, uint32_t a)
113 {
114 return v - (v % a);
115 }
116
117 static inline uint32_t
118 align_u32(uint32_t v, uint32_t a)
119 {
120 assert(a != 0 && a == (a & -a));
121 return (v + a - 1) & ~(a - 1);
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 anv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 anv_minify(uint32_t n, uint32_t levels)
148 {
149 if (unlikely(n == 0))
150 return 0;
151 else
152 return MAX2(n >> levels, 1);
153 }
154
155 static inline float
156 anv_clamp_f(float f, float min, float max)
157 {
158 assert(min < max);
159
160 if (f > max)
161 return max;
162 else if (f < min)
163 return min;
164 else
165 return f;
166 }
167
168 static inline bool
169 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
170 {
171 if (*inout_mask & clear_mask) {
172 *inout_mask &= ~clear_mask;
173 return true;
174 } else {
175 return false;
176 }
177 }
178
179 static inline union isl_color_value
180 vk_to_isl_color(VkClearColorValue color)
181 {
182 return (union isl_color_value) {
183 .u32 = {
184 color.uint32[0],
185 color.uint32[1],
186 color.uint32[2],
187 color.uint32[3],
188 },
189 };
190 }
191
192 #define for_each_bit(b, dword) \
193 for (uint32_t __dword = (dword); \
194 (b) = __builtin_ffs(__dword) - 1, __dword; \
195 __dword &= ~(1 << (b)))
196
197 #define typed_memcpy(dest, src, count) ({ \
198 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
199 memcpy((dest), (src), (count) * sizeof(*(src))); \
200 })
201
202 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
203 * to be added here in order to utilize mapping in debug/error/perf macros.
204 */
205 #define REPORT_OBJECT_TYPE(o) \
206 __builtin_choose_expr ( \
207 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
208 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
209 __builtin_choose_expr ( \
210 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
211 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
212 __builtin_choose_expr ( \
213 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
214 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
215 __builtin_choose_expr ( \
216 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
217 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
218 __builtin_choose_expr ( \
219 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
220 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
221 __builtin_choose_expr ( \
222 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
223 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
224 __builtin_choose_expr ( \
225 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
226 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
227 __builtin_choose_expr ( \
228 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
229 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
230 __builtin_choose_expr ( \
231 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
232 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
233 __builtin_choose_expr ( \
234 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
235 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
236 __builtin_choose_expr ( \
237 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
238 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
239 __builtin_choose_expr ( \
240 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
241 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
242 __builtin_choose_expr ( \
243 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
244 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
245 __builtin_choose_expr ( \
246 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
247 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
248 __builtin_choose_expr ( \
249 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
250 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
251 __builtin_choose_expr ( \
252 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
253 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
254 __builtin_choose_expr ( \
255 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
256 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
257 __builtin_choose_expr ( \
258 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
259 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
260 __builtin_choose_expr ( \
261 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
262 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
263 __builtin_choose_expr ( \
264 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
265 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
266 __builtin_choose_expr ( \
267 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
268 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
269 __builtin_choose_expr ( \
270 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
271 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
272 __builtin_choose_expr ( \
273 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
274 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
275 __builtin_choose_expr ( \
276 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
277 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
278 __builtin_choose_expr ( \
279 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
280 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
281 __builtin_choose_expr ( \
282 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
283 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
284 __builtin_choose_expr ( \
285 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
286 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
287 __builtin_choose_expr ( \
288 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
289 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
290 __builtin_choose_expr ( \
291 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
292 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
293 __builtin_choose_expr ( \
294 __builtin_types_compatible_p (__typeof (o), struct anv_debug_callback*), \
295 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
296 __builtin_choose_expr ( \
297 __builtin_types_compatible_p (__typeof (o), void*), \
298 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
299 /* The void expression results in a compile-time error \
300 when assigning the result to something. */ \
301 (void)0)))))))))))))))))))))))))))))))
302
303 /* Whenever we generate an error, pass it through this function. Useful for
304 * debugging, where we can break on it. Only call at error site, not when
305 * propagating errors. Might be useful to plug in a stack trace here.
306 */
307
308 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
309 VkDebugReportObjectTypeEXT type, VkResult error,
310 const char *file, int line, const char *format, ...);
311
312 #ifdef DEBUG
313 #define vk_error(error) __vk_errorf(NULL, NULL,\
314 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
315 error, __FILE__, __LINE__, NULL);
316 #define vk_errorf(instance, obj, error, format, ...)\
317 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
318 __FILE__, __LINE__, format, ## __VA_ARGS__);
319 #else
320 #define vk_error(error) error
321 #define vk_errorf(instance, obj, error, format, ...) error
322 #endif
323
324 /**
325 * Warn on ignored extension structs.
326 *
327 * The Vulkan spec requires us to ignore unsupported or unknown structs in
328 * a pNext chain. In debug mode, emitting warnings for ignored structs may
329 * help us discover structs that we should not have ignored.
330 *
331 *
332 * From the Vulkan 1.0.38 spec:
333 *
334 * Any component of the implementation (the loader, any enabled layers,
335 * and drivers) must skip over, without processing (other than reading the
336 * sType and pNext members) any chained structures with sType values not
337 * defined by extensions supported by that component.
338 */
339 #define anv_debug_ignored_stype(sType) \
340 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
341
342 void __anv_perf_warn(struct anv_instance *instance, const void *object,
343 VkDebugReportObjectTypeEXT type, const char *file,
344 int line, const char *format, ...)
345 anv_printflike(6, 7);
346 void anv_loge(const char *format, ...) anv_printflike(1, 2);
347 void anv_loge_v(const char *format, va_list va);
348
349 void anv_debug_report(struct anv_instance *instance,
350 VkDebugReportFlagsEXT flags,
351 VkDebugReportObjectTypeEXT object_type,
352 uint64_t handle,
353 size_t location,
354 int32_t messageCode,
355 const char* pLayerPrefix,
356 const char *pMessage);
357
358 /**
359 * Print a FINISHME message, including its source location.
360 */
361 #define anv_finishme(format, ...) \
362 do { \
363 static bool reported = false; \
364 if (!reported) { \
365 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
366 ##__VA_ARGS__); \
367 reported = true; \
368 } \
369 } while (0)
370
371 /**
372 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
373 */
374 #define anv_perf_warn(instance, obj, format, ...) \
375 do { \
376 static bool reported = false; \
377 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
378 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
379 format, ##__VA_ARGS__); \
380 reported = true; \
381 } \
382 } while (0)
383
384 /* A non-fatal assert. Useful for debugging. */
385 #ifdef DEBUG
386 #define anv_assert(x) ({ \
387 if (unlikely(!(x))) \
388 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
389 })
390 #else
391 #define anv_assert(x)
392 #endif
393
394 /* A multi-pointer allocator
395 *
396 * When copying data structures from the user (such as a render pass), it's
397 * common to need to allocate data for a bunch of different things. Instead
398 * of doing several allocations and having to handle all of the error checking
399 * that entails, it can be easier to do a single allocation. This struct
400 * helps facilitate that. The intended usage looks like this:
401 *
402 * ANV_MULTIALLOC(ma)
403 * anv_multialloc_add(&ma, &main_ptr, 1);
404 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
405 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
406 *
407 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
408 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
409 */
410 struct anv_multialloc {
411 size_t size;
412 size_t align;
413
414 uint32_t ptr_count;
415 void **ptrs[8];
416 };
417
418 #define ANV_MULTIALLOC_INIT \
419 ((struct anv_multialloc) { 0, })
420
421 #define ANV_MULTIALLOC(_name) \
422 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
423
424 __attribute__((always_inline))
425 static inline void
426 _anv_multialloc_add(struct anv_multialloc *ma,
427 void **ptr, size_t size, size_t align)
428 {
429 size_t offset = align_u64(ma->size, align);
430 ma->size = offset + size;
431 ma->align = MAX2(ma->align, align);
432
433 /* Store the offset in the pointer. */
434 *ptr = (void *)(uintptr_t)offset;
435
436 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
437 ma->ptrs[ma->ptr_count++] = ptr;
438 }
439
440 #define anv_multialloc_add_size(_ma, _ptr, _size) \
441 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
442
443 #define anv_multialloc_add(_ma, _ptr, _count) \
444 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
445
446 __attribute__((always_inline))
447 static inline void *
448 anv_multialloc_alloc(struct anv_multialloc *ma,
449 const VkAllocationCallbacks *alloc,
450 VkSystemAllocationScope scope)
451 {
452 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
453 if (!ptr)
454 return NULL;
455
456 /* Fill out each of the pointers with their final value.
457 *
458 * for (uint32_t i = 0; i < ma->ptr_count; i++)
459 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
460 *
461 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
462 * constant, GCC is incapable of figuring this out and unrolling the loop
463 * so we have to give it a little help.
464 */
465 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
466 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
467 if ((_i) < ma->ptr_count) \
468 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
469 _ANV_MULTIALLOC_UPDATE_POINTER(0);
470 _ANV_MULTIALLOC_UPDATE_POINTER(1);
471 _ANV_MULTIALLOC_UPDATE_POINTER(2);
472 _ANV_MULTIALLOC_UPDATE_POINTER(3);
473 _ANV_MULTIALLOC_UPDATE_POINTER(4);
474 _ANV_MULTIALLOC_UPDATE_POINTER(5);
475 _ANV_MULTIALLOC_UPDATE_POINTER(6);
476 _ANV_MULTIALLOC_UPDATE_POINTER(7);
477 #undef _ANV_MULTIALLOC_UPDATE_POINTER
478
479 return ptr;
480 }
481
482 __attribute__((always_inline))
483 static inline void *
484 anv_multialloc_alloc2(struct anv_multialloc *ma,
485 const VkAllocationCallbacks *parent_alloc,
486 const VkAllocationCallbacks *alloc,
487 VkSystemAllocationScope scope)
488 {
489 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
490 }
491
492 struct anv_bo {
493 uint32_t gem_handle;
494
495 /* Index into the current validation list. This is used by the
496 * validation list building alrogithm to track which buffers are already
497 * in the validation list so that we can ensure uniqueness.
498 */
499 uint32_t index;
500
501 /* Last known offset. This value is provided by the kernel when we
502 * execbuf and is used as the presumed offset for the next bunch of
503 * relocations.
504 */
505 uint64_t offset;
506
507 uint64_t size;
508 void *map;
509
510 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
511 uint32_t flags;
512 };
513
514 static inline void
515 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
516 {
517 bo->gem_handle = gem_handle;
518 bo->index = 0;
519 bo->offset = -1;
520 bo->size = size;
521 bo->map = NULL;
522 bo->flags = 0;
523 }
524
525 /* Represents a lock-free linked list of "free" things. This is used by
526 * both the block pool and the state pools. Unfortunately, in order to
527 * solve the ABA problem, we can't use a single uint32_t head.
528 */
529 union anv_free_list {
530 struct {
531 int32_t offset;
532
533 /* A simple count that is incremented every time the head changes. */
534 uint32_t count;
535 };
536 uint64_t u64;
537 };
538
539 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
540
541 struct anv_block_state {
542 union {
543 struct {
544 uint32_t next;
545 uint32_t end;
546 };
547 uint64_t u64;
548 };
549 };
550
551 struct anv_block_pool {
552 struct anv_device *device;
553
554 struct anv_bo bo;
555
556 /* The offset from the start of the bo to the "center" of the block
557 * pool. Pointers to allocated blocks are given by
558 * bo.map + center_bo_offset + offsets.
559 */
560 uint32_t center_bo_offset;
561
562 /* Current memory map of the block pool. This pointer may or may not
563 * point to the actual beginning of the block pool memory. If
564 * anv_block_pool_alloc_back has ever been called, then this pointer
565 * will point to the "center" position of the buffer and all offsets
566 * (negative or positive) given out by the block pool alloc functions
567 * will be valid relative to this pointer.
568 *
569 * In particular, map == bo.map + center_offset
570 */
571 void *map;
572 int fd;
573
574 /**
575 * Array of mmaps and gem handles owned by the block pool, reclaimed when
576 * the block pool is destroyed.
577 */
578 struct u_vector mmap_cleanups;
579
580 struct anv_block_state state;
581
582 struct anv_block_state back_state;
583 };
584
585 /* Block pools are backed by a fixed-size 1GB memfd */
586 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
587
588 /* The center of the block pool is also the middle of the memfd. This may
589 * change in the future if we decide differently for some reason.
590 */
591 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
592
593 static inline uint32_t
594 anv_block_pool_size(struct anv_block_pool *pool)
595 {
596 return pool->state.end + pool->back_state.end;
597 }
598
599 struct anv_state {
600 int32_t offset;
601 uint32_t alloc_size;
602 void *map;
603 };
604
605 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
606
607 struct anv_fixed_size_state_pool {
608 union anv_free_list free_list;
609 struct anv_block_state block;
610 };
611
612 #define ANV_MIN_STATE_SIZE_LOG2 6
613 #define ANV_MAX_STATE_SIZE_LOG2 20
614
615 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
616
617 struct anv_state_pool {
618 struct anv_block_pool block_pool;
619
620 /* The size of blocks which will be allocated from the block pool */
621 uint32_t block_size;
622
623 /** Free list for "back" allocations */
624 union anv_free_list back_alloc_free_list;
625
626 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
627 };
628
629 struct anv_state_stream_block;
630
631 struct anv_state_stream {
632 struct anv_state_pool *state_pool;
633
634 /* The size of blocks to allocate from the state pool */
635 uint32_t block_size;
636
637 /* Current block we're allocating from */
638 struct anv_state block;
639
640 /* Offset into the current block at which to allocate the next state */
641 uint32_t next;
642
643 /* List of all blocks allocated from this pool */
644 struct anv_state_stream_block *block_list;
645 };
646
647 /* The block_pool functions exported for testing only. The block pool should
648 * only be used via a state pool (see below).
649 */
650 VkResult anv_block_pool_init(struct anv_block_pool *pool,
651 struct anv_device *device,
652 uint32_t initial_size);
653 void anv_block_pool_finish(struct anv_block_pool *pool);
654 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
655 uint32_t block_size);
656 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
657 uint32_t block_size);
658
659 VkResult anv_state_pool_init(struct anv_state_pool *pool,
660 struct anv_device *device,
661 uint32_t block_size);
662 void anv_state_pool_finish(struct anv_state_pool *pool);
663 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
664 uint32_t state_size, uint32_t alignment);
665 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
666 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
667 void anv_state_stream_init(struct anv_state_stream *stream,
668 struct anv_state_pool *state_pool,
669 uint32_t block_size);
670 void anv_state_stream_finish(struct anv_state_stream *stream);
671 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
672 uint32_t size, uint32_t alignment);
673
674 /**
675 * Implements a pool of re-usable BOs. The interface is identical to that
676 * of block_pool except that each block is its own BO.
677 */
678 struct anv_bo_pool {
679 struct anv_device *device;
680
681 void *free_list[16];
682 };
683
684 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
685 void anv_bo_pool_finish(struct anv_bo_pool *pool);
686 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
687 uint32_t size);
688 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
689
690 struct anv_scratch_bo {
691 bool exists;
692 struct anv_bo bo;
693 };
694
695 struct anv_scratch_pool {
696 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
697 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
698 };
699
700 void anv_scratch_pool_init(struct anv_device *device,
701 struct anv_scratch_pool *pool);
702 void anv_scratch_pool_finish(struct anv_device *device,
703 struct anv_scratch_pool *pool);
704 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
705 struct anv_scratch_pool *pool,
706 gl_shader_stage stage,
707 unsigned per_thread_scratch);
708
709 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
710 struct anv_bo_cache {
711 struct hash_table *bo_map;
712 pthread_mutex_t mutex;
713 };
714
715 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
716 void anv_bo_cache_finish(struct anv_bo_cache *cache);
717 VkResult anv_bo_cache_alloc(struct anv_device *device,
718 struct anv_bo_cache *cache,
719 uint64_t size, struct anv_bo **bo);
720 VkResult anv_bo_cache_import(struct anv_device *device,
721 struct anv_bo_cache *cache,
722 int fd, struct anv_bo **bo);
723 VkResult anv_bo_cache_export(struct anv_device *device,
724 struct anv_bo_cache *cache,
725 struct anv_bo *bo_in, int *fd_out);
726 void anv_bo_cache_release(struct anv_device *device,
727 struct anv_bo_cache *cache,
728 struct anv_bo *bo);
729
730 struct anv_memory_type {
731 /* Standard bits passed on to the client */
732 VkMemoryPropertyFlags propertyFlags;
733 uint32_t heapIndex;
734
735 /* Driver-internal book-keeping */
736 VkBufferUsageFlags valid_buffer_usage;
737 };
738
739 struct anv_memory_heap {
740 /* Standard bits passed on to the client */
741 VkDeviceSize size;
742 VkMemoryHeapFlags flags;
743
744 /* Driver-internal book-keeping */
745 bool supports_48bit_addresses;
746 };
747
748 struct anv_physical_device {
749 VK_LOADER_DATA _loader_data;
750
751 struct anv_instance * instance;
752 uint32_t chipset_id;
753 char path[20];
754 const char * name;
755 struct gen_device_info info;
756 /** Amount of "GPU memory" we want to advertise
757 *
758 * Clearly, this value is bogus since Intel is a UMA architecture. On
759 * gen7 platforms, we are limited by GTT size unless we want to implement
760 * fine-grained tracking and GTT splitting. On Broadwell and above we are
761 * practically unlimited. However, we will never report more than 3/4 of
762 * the total system ram to try and avoid running out of RAM.
763 */
764 bool supports_48bit_addresses;
765 struct brw_compiler * compiler;
766 struct isl_device isl_dev;
767 int cmd_parser_version;
768 bool has_exec_async;
769 bool has_exec_fence;
770 bool has_syncobj;
771 bool has_syncobj_wait;
772
773 uint32_t eu_total;
774 uint32_t subslice_total;
775
776 struct {
777 uint32_t type_count;
778 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
779 uint32_t heap_count;
780 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
781 } memory;
782
783 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
784 uint8_t driver_uuid[VK_UUID_SIZE];
785 uint8_t device_uuid[VK_UUID_SIZE];
786
787 struct wsi_device wsi_device;
788 int local_fd;
789 };
790
791 struct anv_debug_report_callback {
792 /* Link in the 'callbacks' list in anv_instance struct. */
793 struct list_head link;
794 VkDebugReportFlagsEXT flags;
795 PFN_vkDebugReportCallbackEXT callback;
796 void * data;
797 };
798
799 struct anv_instance {
800 VK_LOADER_DATA _loader_data;
801
802 VkAllocationCallbacks alloc;
803
804 uint32_t apiVersion;
805 int physicalDeviceCount;
806 struct anv_physical_device physicalDevice;
807
808 /* VK_EXT_debug_report debug callbacks */
809 pthread_mutex_t callbacks_mutex;
810 struct list_head callbacks;
811 struct anv_debug_report_callback destroy_debug_cb;
812 };
813
814 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
815 void anv_finish_wsi(struct anv_physical_device *physical_device);
816
817 bool anv_instance_extension_supported(const char *name);
818 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
819 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
820 const char *name);
821
822 struct anv_queue {
823 VK_LOADER_DATA _loader_data;
824
825 struct anv_device * device;
826
827 struct anv_state_pool * pool;
828 };
829
830 struct anv_pipeline_cache {
831 struct anv_device * device;
832 pthread_mutex_t mutex;
833
834 struct hash_table * cache;
835 };
836
837 struct anv_pipeline_bind_map;
838
839 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
840 struct anv_device *device,
841 bool cache_enabled);
842 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
843
844 struct anv_shader_bin *
845 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
846 const void *key, uint32_t key_size);
847 struct anv_shader_bin *
848 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
849 const void *key_data, uint32_t key_size,
850 const void *kernel_data, uint32_t kernel_size,
851 const struct brw_stage_prog_data *prog_data,
852 uint32_t prog_data_size,
853 const struct anv_pipeline_bind_map *bind_map);
854
855 struct anv_device {
856 VK_LOADER_DATA _loader_data;
857
858 VkAllocationCallbacks alloc;
859
860 struct anv_instance * instance;
861 uint32_t chipset_id;
862 struct gen_device_info info;
863 struct isl_device isl_dev;
864 int context_id;
865 int fd;
866 bool can_chain_batches;
867 bool robust_buffer_access;
868
869 struct anv_bo_pool batch_bo_pool;
870
871 struct anv_bo_cache bo_cache;
872
873 struct anv_state_pool dynamic_state_pool;
874 struct anv_state_pool instruction_state_pool;
875 struct anv_state_pool surface_state_pool;
876
877 struct anv_bo workaround_bo;
878 struct anv_bo trivial_batch_bo;
879
880 struct anv_pipeline_cache blorp_shader_cache;
881 struct blorp_context blorp;
882
883 struct anv_state border_colors;
884
885 struct anv_queue queue;
886
887 struct anv_scratch_pool scratch_pool;
888
889 uint32_t default_mocs;
890
891 pthread_mutex_t mutex;
892 pthread_cond_t queue_submit;
893 bool lost;
894 };
895
896 static void inline
897 anv_state_flush(struct anv_device *device, struct anv_state state)
898 {
899 if (device->info.has_llc)
900 return;
901
902 gen_flush_range(state.map, state.alloc_size);
903 }
904
905 void anv_device_init_blorp(struct anv_device *device);
906 void anv_device_finish_blorp(struct anv_device *device);
907
908 VkResult anv_device_execbuf(struct anv_device *device,
909 struct drm_i915_gem_execbuffer2 *execbuf,
910 struct anv_bo **execbuf_bos);
911 VkResult anv_device_query_status(struct anv_device *device);
912 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
913 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
914 int64_t timeout);
915
916 void* anv_gem_mmap(struct anv_device *device,
917 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
918 void anv_gem_munmap(void *p, uint64_t size);
919 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
920 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
921 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
922 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
923 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
924 int anv_gem_execbuffer(struct anv_device *device,
925 struct drm_i915_gem_execbuffer2 *execbuf);
926 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
927 uint32_t stride, uint32_t tiling);
928 int anv_gem_create_context(struct anv_device *device);
929 int anv_gem_destroy_context(struct anv_device *device, int context);
930 int anv_gem_get_context_param(int fd, int context, uint32_t param,
931 uint64_t *value);
932 int anv_gem_get_param(int fd, uint32_t param);
933 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
934 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
935 int anv_gem_get_aperture(int fd, uint64_t *size);
936 bool anv_gem_supports_48b_addresses(int fd);
937 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
938 uint32_t *active, uint32_t *pending);
939 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
940 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
941 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
942 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
943 uint32_t read_domains, uint32_t write_domain);
944 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
945 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
946 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
947 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
948 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
949 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
950 uint32_t handle);
951 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
952 uint32_t handle, int fd);
953 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
954 bool anv_gem_supports_syncobj_wait(int fd);
955 int anv_gem_syncobj_wait(struct anv_device *device,
956 uint32_t *handles, uint32_t num_handles,
957 int64_t abs_timeout_ns, bool wait_all);
958
959 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
960
961 struct anv_reloc_list {
962 uint32_t num_relocs;
963 uint32_t array_length;
964 struct drm_i915_gem_relocation_entry * relocs;
965 struct anv_bo ** reloc_bos;
966 };
967
968 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
969 const VkAllocationCallbacks *alloc);
970 void anv_reloc_list_finish(struct anv_reloc_list *list,
971 const VkAllocationCallbacks *alloc);
972
973 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
974 const VkAllocationCallbacks *alloc,
975 uint32_t offset, struct anv_bo *target_bo,
976 uint32_t delta);
977
978 struct anv_batch_bo {
979 /* Link in the anv_cmd_buffer.owned_batch_bos list */
980 struct list_head link;
981
982 struct anv_bo bo;
983
984 /* Bytes actually consumed in this batch BO */
985 uint32_t length;
986
987 struct anv_reloc_list relocs;
988 };
989
990 struct anv_batch {
991 const VkAllocationCallbacks * alloc;
992
993 void * start;
994 void * end;
995 void * next;
996
997 struct anv_reloc_list * relocs;
998
999 /* This callback is called (with the associated user data) in the event
1000 * that the batch runs out of space.
1001 */
1002 VkResult (*extend_cb)(struct anv_batch *, void *);
1003 void * user_data;
1004
1005 /**
1006 * Current error status of the command buffer. Used to track inconsistent
1007 * or incomplete command buffer states that are the consequence of run-time
1008 * errors such as out of memory scenarios. We want to track this in the
1009 * batch because the command buffer object is not visible to some parts
1010 * of the driver.
1011 */
1012 VkResult status;
1013 };
1014
1015 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1016 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1017 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1018 void *location, struct anv_bo *bo, uint32_t offset);
1019 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1020 struct anv_batch *batch);
1021
1022 static inline VkResult
1023 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1024 {
1025 assert(error != VK_SUCCESS);
1026 if (batch->status == VK_SUCCESS)
1027 batch->status = error;
1028 return batch->status;
1029 }
1030
1031 static inline bool
1032 anv_batch_has_error(struct anv_batch *batch)
1033 {
1034 return batch->status != VK_SUCCESS;
1035 }
1036
1037 struct anv_address {
1038 struct anv_bo *bo;
1039 uint32_t offset;
1040 };
1041
1042 static inline uint64_t
1043 _anv_combine_address(struct anv_batch *batch, void *location,
1044 const struct anv_address address, uint32_t delta)
1045 {
1046 if (address.bo == NULL) {
1047 return address.offset + delta;
1048 } else {
1049 assert(batch->start <= location && location < batch->end);
1050
1051 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1052 }
1053 }
1054
1055 #define __gen_address_type struct anv_address
1056 #define __gen_user_data struct anv_batch
1057 #define __gen_combine_address _anv_combine_address
1058
1059 /* Wrapper macros needed to work around preprocessor argument issues. In
1060 * particular, arguments don't get pre-evaluated if they are concatenated.
1061 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1062 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1063 * We can work around this easily enough with these helpers.
1064 */
1065 #define __anv_cmd_length(cmd) cmd ## _length
1066 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1067 #define __anv_cmd_header(cmd) cmd ## _header
1068 #define __anv_cmd_pack(cmd) cmd ## _pack
1069 #define __anv_reg_num(reg) reg ## _num
1070
1071 #define anv_pack_struct(dst, struc, ...) do { \
1072 struct struc __template = { \
1073 __VA_ARGS__ \
1074 }; \
1075 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1076 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1077 } while (0)
1078
1079 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1080 void *__dst = anv_batch_emit_dwords(batch, n); \
1081 if (__dst) { \
1082 struct cmd __template = { \
1083 __anv_cmd_header(cmd), \
1084 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1085 __VA_ARGS__ \
1086 }; \
1087 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1088 } \
1089 __dst; \
1090 })
1091
1092 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1093 do { \
1094 uint32_t *dw; \
1095 \
1096 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1097 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1098 if (!dw) \
1099 break; \
1100 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1101 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1102 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1103 } while (0)
1104
1105 #define anv_batch_emit(batch, cmd, name) \
1106 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1107 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1108 __builtin_expect(_dst != NULL, 1); \
1109 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1110 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1111 _dst = NULL; \
1112 }))
1113
1114 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1115 .GraphicsDataTypeGFDT = 0, \
1116 .LLCCacheabilityControlLLCCC = 0, \
1117 .L3CacheabilityControlL3CC = 1, \
1118 }
1119
1120 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1121 .LLCeLLCCacheabilityControlLLCCC = 0, \
1122 .L3CacheabilityControlL3CC = 1, \
1123 }
1124
1125 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1126 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1127 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1128 .AgeforQUADLRU = 0 \
1129 }
1130
1131 /* Skylake: MOCS is now an index into an array of 62 different caching
1132 * configurations programmed by the kernel.
1133 */
1134
1135 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1136 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1137 .IndextoMOCSTables = 2 \
1138 }
1139
1140 #define GEN9_MOCS_PTE { \
1141 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1142 .IndextoMOCSTables = 1 \
1143 }
1144
1145 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1146 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1147 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1148 .IndextoMOCSTables = 2 \
1149 }
1150
1151 #define GEN10_MOCS_PTE { \
1152 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1153 .IndextoMOCSTables = 1 \
1154 }
1155
1156 struct anv_device_memory {
1157 struct anv_bo * bo;
1158 struct anv_memory_type * type;
1159 VkDeviceSize map_size;
1160 void * map;
1161 };
1162
1163 /**
1164 * Header for Vertex URB Entry (VUE)
1165 */
1166 struct anv_vue_header {
1167 uint32_t Reserved;
1168 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1169 uint32_t ViewportIndex;
1170 float PointWidth;
1171 };
1172
1173 struct anv_descriptor_set_binding_layout {
1174 #ifndef NDEBUG
1175 /* The type of the descriptors in this binding */
1176 VkDescriptorType type;
1177 #endif
1178
1179 /* Number of array elements in this binding */
1180 uint16_t array_size;
1181
1182 /* Index into the flattend descriptor set */
1183 uint16_t descriptor_index;
1184
1185 /* Index into the dynamic state array for a dynamic buffer */
1186 int16_t dynamic_offset_index;
1187
1188 /* Index into the descriptor set buffer views */
1189 int16_t buffer_index;
1190
1191 struct {
1192 /* Index into the binding table for the associated surface */
1193 int16_t surface_index;
1194
1195 /* Index into the sampler table for the associated sampler */
1196 int16_t sampler_index;
1197
1198 /* Index into the image table for the associated image */
1199 int16_t image_index;
1200 } stage[MESA_SHADER_STAGES];
1201
1202 /* Immutable samplers (or NULL if no immutable samplers) */
1203 struct anv_sampler **immutable_samplers;
1204 };
1205
1206 struct anv_descriptor_set_layout {
1207 /* Number of bindings in this descriptor set */
1208 uint16_t binding_count;
1209
1210 /* Total size of the descriptor set with room for all array entries */
1211 uint16_t size;
1212
1213 /* Shader stages affected by this descriptor set */
1214 uint16_t shader_stages;
1215
1216 /* Number of buffers in this descriptor set */
1217 uint16_t buffer_count;
1218
1219 /* Number of dynamic offsets used by this descriptor set */
1220 uint16_t dynamic_offset_count;
1221
1222 /* Bindings in this descriptor set */
1223 struct anv_descriptor_set_binding_layout binding[0];
1224 };
1225
1226 struct anv_descriptor {
1227 VkDescriptorType type;
1228
1229 union {
1230 struct {
1231 VkImageLayout layout;
1232 struct anv_image_view *image_view;
1233 struct anv_sampler *sampler;
1234 };
1235
1236 struct {
1237 struct anv_buffer *buffer;
1238 uint64_t offset;
1239 uint64_t range;
1240 };
1241
1242 struct anv_buffer_view *buffer_view;
1243 };
1244 };
1245
1246 struct anv_descriptor_set {
1247 const struct anv_descriptor_set_layout *layout;
1248 uint32_t size;
1249 uint32_t buffer_count;
1250 struct anv_buffer_view *buffer_views;
1251 struct anv_descriptor descriptors[0];
1252 };
1253
1254 struct anv_buffer_view {
1255 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1256 struct anv_bo *bo;
1257 uint32_t offset; /**< Offset into bo. */
1258 uint64_t range; /**< VkBufferViewCreateInfo::range */
1259
1260 struct anv_state surface_state;
1261 struct anv_state storage_surface_state;
1262 struct anv_state writeonly_storage_surface_state;
1263
1264 struct brw_image_param storage_image_param;
1265 };
1266
1267 struct anv_push_descriptor_set {
1268 struct anv_descriptor_set set;
1269
1270 /* Put this field right behind anv_descriptor_set so it fills up the
1271 * descriptors[0] field. */
1272 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1273 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1274 };
1275
1276 struct anv_descriptor_pool {
1277 uint32_t size;
1278 uint32_t next;
1279 uint32_t free_list;
1280
1281 struct anv_state_stream surface_state_stream;
1282 void *surface_state_free_list;
1283
1284 char data[0];
1285 };
1286
1287 enum anv_descriptor_template_entry_type {
1288 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1289 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1290 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1291 };
1292
1293 struct anv_descriptor_template_entry {
1294 /* The type of descriptor in this entry */
1295 VkDescriptorType type;
1296
1297 /* Binding in the descriptor set */
1298 uint32_t binding;
1299
1300 /* Offset at which to write into the descriptor set binding */
1301 uint32_t array_element;
1302
1303 /* Number of elements to write into the descriptor set binding */
1304 uint32_t array_count;
1305
1306 /* Offset into the user provided data */
1307 size_t offset;
1308
1309 /* Stride between elements into the user provided data */
1310 size_t stride;
1311 };
1312
1313 struct anv_descriptor_update_template {
1314 /* The descriptor set this template corresponds to. This value is only
1315 * valid if the template was created with the templateType
1316 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1317 */
1318 uint8_t set;
1319
1320 /* Number of entries in this template */
1321 uint32_t entry_count;
1322
1323 /* Entries of the template */
1324 struct anv_descriptor_template_entry entries[0];
1325 };
1326
1327 size_t
1328 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1329
1330 size_t
1331 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1332
1333 void
1334 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1335 const struct gen_device_info * const devinfo,
1336 const VkDescriptorImageInfo * const info,
1337 VkDescriptorType type,
1338 uint32_t binding,
1339 uint32_t element);
1340
1341 void
1342 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1343 VkDescriptorType type,
1344 struct anv_buffer_view *buffer_view,
1345 uint32_t binding,
1346 uint32_t element);
1347
1348 void
1349 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1350 struct anv_device *device,
1351 struct anv_state_stream *alloc_stream,
1352 VkDescriptorType type,
1353 struct anv_buffer *buffer,
1354 uint32_t binding,
1355 uint32_t element,
1356 VkDeviceSize offset,
1357 VkDeviceSize range);
1358
1359 void
1360 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1361 struct anv_device *device,
1362 struct anv_state_stream *alloc_stream,
1363 const struct anv_descriptor_update_template *template,
1364 const void *data);
1365
1366 VkResult
1367 anv_descriptor_set_create(struct anv_device *device,
1368 struct anv_descriptor_pool *pool,
1369 const struct anv_descriptor_set_layout *layout,
1370 struct anv_descriptor_set **out_set);
1371
1372 void
1373 anv_descriptor_set_destroy(struct anv_device *device,
1374 struct anv_descriptor_pool *pool,
1375 struct anv_descriptor_set *set);
1376
1377 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1378
1379 struct anv_pipeline_binding {
1380 /* The descriptor set this surface corresponds to. The special value of
1381 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1382 * to a color attachment and not a regular descriptor.
1383 */
1384 uint8_t set;
1385
1386 /* Binding in the descriptor set */
1387 uint32_t binding;
1388
1389 /* Index in the binding */
1390 uint32_t index;
1391
1392 /* Plane in the binding index */
1393 uint8_t plane;
1394
1395 /* Input attachment index (relative to the subpass) */
1396 uint8_t input_attachment_index;
1397
1398 /* For a storage image, whether it is write-only */
1399 bool write_only;
1400 };
1401
1402 struct anv_pipeline_layout {
1403 struct {
1404 struct anv_descriptor_set_layout *layout;
1405 uint32_t dynamic_offset_start;
1406 } set[MAX_SETS];
1407
1408 uint32_t num_sets;
1409
1410 struct {
1411 bool has_dynamic_offsets;
1412 } stage[MESA_SHADER_STAGES];
1413
1414 unsigned char sha1[20];
1415 };
1416
1417 struct anv_buffer {
1418 struct anv_device * device;
1419 VkDeviceSize size;
1420
1421 VkBufferUsageFlags usage;
1422
1423 /* Set when bound */
1424 struct anv_bo * bo;
1425 VkDeviceSize offset;
1426 };
1427
1428 static inline uint64_t
1429 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1430 {
1431 assert(offset <= buffer->size);
1432 if (range == VK_WHOLE_SIZE) {
1433 return buffer->size - offset;
1434 } else {
1435 assert(range <= buffer->size);
1436 return range;
1437 }
1438 }
1439
1440 enum anv_cmd_dirty_bits {
1441 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1442 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1443 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1444 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1445 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1446 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1447 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1448 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1449 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1450 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1451 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1452 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1453 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1454 };
1455 typedef uint32_t anv_cmd_dirty_mask_t;
1456
1457 enum anv_pipe_bits {
1458 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1459 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1460 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1461 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1462 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1463 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1464 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1465 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1466 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1467 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1468 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1469
1470 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1471 * a flush has happened but not a CS stall. The next time we do any sort
1472 * of invalidation we need to insert a CS stall at that time. Otherwise,
1473 * we would have to CS stall on every flush which could be bad.
1474 */
1475 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1476 };
1477
1478 #define ANV_PIPE_FLUSH_BITS ( \
1479 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1480 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1481 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1482
1483 #define ANV_PIPE_STALL_BITS ( \
1484 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1485 ANV_PIPE_DEPTH_STALL_BIT | \
1486 ANV_PIPE_CS_STALL_BIT)
1487
1488 #define ANV_PIPE_INVALIDATE_BITS ( \
1489 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1490 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1491 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1492 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1493 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1494 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1495
1496 static inline enum anv_pipe_bits
1497 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1498 {
1499 enum anv_pipe_bits pipe_bits = 0;
1500
1501 unsigned b;
1502 for_each_bit(b, flags) {
1503 switch ((VkAccessFlagBits)(1 << b)) {
1504 case VK_ACCESS_SHADER_WRITE_BIT:
1505 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1506 break;
1507 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1508 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1509 break;
1510 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1511 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1512 break;
1513 case VK_ACCESS_TRANSFER_WRITE_BIT:
1514 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1515 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1516 break;
1517 default:
1518 break; /* Nothing to do */
1519 }
1520 }
1521
1522 return pipe_bits;
1523 }
1524
1525 static inline enum anv_pipe_bits
1526 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1527 {
1528 enum anv_pipe_bits pipe_bits = 0;
1529
1530 unsigned b;
1531 for_each_bit(b, flags) {
1532 switch ((VkAccessFlagBits)(1 << b)) {
1533 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1534 case VK_ACCESS_INDEX_READ_BIT:
1535 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1536 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1537 break;
1538 case VK_ACCESS_UNIFORM_READ_BIT:
1539 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1540 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1541 break;
1542 case VK_ACCESS_SHADER_READ_BIT:
1543 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1544 case VK_ACCESS_TRANSFER_READ_BIT:
1545 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1546 break;
1547 default:
1548 break; /* Nothing to do */
1549 }
1550 }
1551
1552 return pipe_bits;
1553 }
1554
1555 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1556 VK_IMAGE_ASPECT_COLOR_BIT | \
1557 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1558 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1559 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1560 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1561 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1562 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1563 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1564
1565 struct anv_vertex_binding {
1566 struct anv_buffer * buffer;
1567 VkDeviceSize offset;
1568 };
1569
1570 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1571 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1572
1573 struct anv_push_constants {
1574 /* Current allocated size of this push constants data structure.
1575 * Because a decent chunk of it may not be used (images on SKL, for
1576 * instance), we won't actually allocate the entire structure up-front.
1577 */
1578 uint32_t size;
1579
1580 /* Push constant data provided by the client through vkPushConstants */
1581 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1582
1583 /* Image data for image_load_store on pre-SKL */
1584 struct brw_image_param images[MAX_IMAGES];
1585 };
1586
1587 struct anv_dynamic_state {
1588 struct {
1589 uint32_t count;
1590 VkViewport viewports[MAX_VIEWPORTS];
1591 } viewport;
1592
1593 struct {
1594 uint32_t count;
1595 VkRect2D scissors[MAX_SCISSORS];
1596 } scissor;
1597
1598 float line_width;
1599
1600 struct {
1601 float bias;
1602 float clamp;
1603 float slope;
1604 } depth_bias;
1605
1606 float blend_constants[4];
1607
1608 struct {
1609 float min;
1610 float max;
1611 } depth_bounds;
1612
1613 struct {
1614 uint32_t front;
1615 uint32_t back;
1616 } stencil_compare_mask;
1617
1618 struct {
1619 uint32_t front;
1620 uint32_t back;
1621 } stencil_write_mask;
1622
1623 struct {
1624 uint32_t front;
1625 uint32_t back;
1626 } stencil_reference;
1627 };
1628
1629 extern const struct anv_dynamic_state default_dynamic_state;
1630
1631 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1632 const struct anv_dynamic_state *src,
1633 uint32_t copy_mask);
1634
1635 struct anv_surface_state {
1636 struct anv_state state;
1637 /** Address of the surface referred to by this state
1638 *
1639 * This address is relative to the start of the BO.
1640 */
1641 uint64_t address;
1642 /* Address of the aux surface, if any
1643 *
1644 * This field is 0 if and only if no aux surface exists.
1645 *
1646 * This address is relative to the start of the BO. On gen7, the bottom 12
1647 * bits of this address include extra aux information.
1648 */
1649 uint64_t aux_address;
1650 };
1651
1652 /**
1653 * Attachment state when recording a renderpass instance.
1654 *
1655 * The clear value is valid only if there exists a pending clear.
1656 */
1657 struct anv_attachment_state {
1658 enum isl_aux_usage aux_usage;
1659 enum isl_aux_usage input_aux_usage;
1660 struct anv_surface_state color;
1661 struct anv_surface_state input;
1662
1663 VkImageLayout current_layout;
1664 VkImageAspectFlags pending_clear_aspects;
1665 bool fast_clear;
1666 VkClearValue clear_value;
1667 bool clear_color_is_zero_one;
1668 bool clear_color_is_zero;
1669 };
1670
1671 /** State required while building cmd buffer */
1672 struct anv_cmd_state {
1673 /* PIPELINE_SELECT.PipelineSelection */
1674 uint32_t current_pipeline;
1675 const struct gen_l3_config * current_l3_config;
1676 uint32_t vb_dirty;
1677 anv_cmd_dirty_mask_t dirty;
1678 anv_cmd_dirty_mask_t compute_dirty;
1679 enum anv_pipe_bits pending_pipe_bits;
1680 uint32_t num_workgroups_offset;
1681 struct anv_bo *num_workgroups_bo;
1682 VkShaderStageFlags descriptors_dirty;
1683 VkShaderStageFlags push_constants_dirty;
1684 uint32_t scratch_size;
1685 struct anv_pipeline * pipeline;
1686 struct anv_pipeline * compute_pipeline;
1687 struct anv_framebuffer * framebuffer;
1688 struct anv_render_pass * pass;
1689 struct anv_subpass * subpass;
1690 VkRect2D render_area;
1691 uint32_t restart_index;
1692 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1693 struct anv_descriptor_set * descriptors[MAX_SETS];
1694 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1695 VkShaderStageFlags push_constant_stages;
1696 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1697 struct anv_state binding_tables[MESA_SHADER_STAGES];
1698 struct anv_state samplers[MESA_SHADER_STAGES];
1699 struct anv_dynamic_state dynamic;
1700 bool need_query_wa;
1701
1702 struct anv_push_descriptor_set * push_descriptors[MAX_SETS];
1703
1704 /**
1705 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1706 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1707 * and before invoking the secondary in ExecuteCommands.
1708 */
1709 bool pma_fix_enabled;
1710
1711 /**
1712 * Whether or not we know for certain that HiZ is enabled for the current
1713 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1714 * enabled or not, this will be false.
1715 */
1716 bool hiz_enabled;
1717
1718 /**
1719 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1720 * valid only when recording a render pass instance.
1721 */
1722 struct anv_attachment_state * attachments;
1723
1724 /**
1725 * Surface states for color render targets. These are stored in a single
1726 * flat array. For depth-stencil attachments, the surface state is simply
1727 * left blank.
1728 */
1729 struct anv_state render_pass_states;
1730
1731 /**
1732 * A null surface state of the right size to match the framebuffer. This
1733 * is one of the states in render_pass_states.
1734 */
1735 struct anv_state null_surface_state;
1736
1737 struct {
1738 struct anv_buffer * index_buffer;
1739 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1740 uint32_t index_offset;
1741 } gen7;
1742 };
1743
1744 struct anv_cmd_pool {
1745 VkAllocationCallbacks alloc;
1746 struct list_head cmd_buffers;
1747 };
1748
1749 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1750
1751 enum anv_cmd_buffer_exec_mode {
1752 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1753 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1754 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1755 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1756 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1757 };
1758
1759 struct anv_cmd_buffer {
1760 VK_LOADER_DATA _loader_data;
1761
1762 struct anv_device * device;
1763
1764 struct anv_cmd_pool * pool;
1765 struct list_head pool_link;
1766
1767 struct anv_batch batch;
1768
1769 /* Fields required for the actual chain of anv_batch_bo's.
1770 *
1771 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1772 */
1773 struct list_head batch_bos;
1774 enum anv_cmd_buffer_exec_mode exec_mode;
1775
1776 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1777 * referenced by this command buffer
1778 *
1779 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1780 */
1781 struct u_vector seen_bbos;
1782
1783 /* A vector of int32_t's for every block of binding tables.
1784 *
1785 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1786 */
1787 struct u_vector bt_block_states;
1788 uint32_t bt_next;
1789
1790 struct anv_reloc_list surface_relocs;
1791 /** Last seen surface state block pool center bo offset */
1792 uint32_t last_ss_pool_center;
1793
1794 /* Serial for tracking buffer completion */
1795 uint32_t serial;
1796
1797 /* Stream objects for storing temporary data */
1798 struct anv_state_stream surface_state_stream;
1799 struct anv_state_stream dynamic_state_stream;
1800
1801 VkCommandBufferUsageFlags usage_flags;
1802 VkCommandBufferLevel level;
1803
1804 struct anv_cmd_state state;
1805 };
1806
1807 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1808 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1809 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1810 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1811 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1812 struct anv_cmd_buffer *secondary);
1813 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1814 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1815 struct anv_cmd_buffer *cmd_buffer,
1816 const VkSemaphore *in_semaphores,
1817 uint32_t num_in_semaphores,
1818 const VkSemaphore *out_semaphores,
1819 uint32_t num_out_semaphores,
1820 VkFence fence);
1821
1822 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1823
1824 VkResult
1825 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1826 gl_shader_stage stage, uint32_t size);
1827 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1828 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1829 (offsetof(struct anv_push_constants, field) + \
1830 sizeof(cmd_buffer->state.push_constants[0]->field)))
1831
1832 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1833 const void *data, uint32_t size, uint32_t alignment);
1834 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1835 uint32_t *a, uint32_t *b,
1836 uint32_t dwords, uint32_t alignment);
1837
1838 struct anv_address
1839 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1840 struct anv_state
1841 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1842 uint32_t entries, uint32_t *state_offset);
1843 struct anv_state
1844 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1845 struct anv_state
1846 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1847 uint32_t size, uint32_t alignment);
1848
1849 VkResult
1850 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1851
1852 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1853 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1854 bool depth_clamp_enable);
1855 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1856
1857 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1858 struct anv_render_pass *pass,
1859 struct anv_framebuffer *framebuffer,
1860 const VkClearValue *clear_values);
1861
1862 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1863
1864 struct anv_state
1865 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1866 gl_shader_stage stage);
1867 struct anv_state
1868 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1869
1870 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1871 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1872
1873 const struct anv_image_view *
1874 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1875
1876 VkResult
1877 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1878 uint32_t num_entries,
1879 uint32_t *state_offset,
1880 struct anv_state *bt_state);
1881
1882 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1883
1884 enum anv_fence_type {
1885 ANV_FENCE_TYPE_NONE = 0,
1886 ANV_FENCE_TYPE_BO,
1887 ANV_FENCE_TYPE_SYNCOBJ,
1888 };
1889
1890 enum anv_bo_fence_state {
1891 /** Indicates that this is a new (or newly reset fence) */
1892 ANV_BO_FENCE_STATE_RESET,
1893
1894 /** Indicates that this fence has been submitted to the GPU but is still
1895 * (as far as we know) in use by the GPU.
1896 */
1897 ANV_BO_FENCE_STATE_SUBMITTED,
1898
1899 ANV_BO_FENCE_STATE_SIGNALED,
1900 };
1901
1902 struct anv_fence_impl {
1903 enum anv_fence_type type;
1904
1905 union {
1906 /** Fence implementation for BO fences
1907 *
1908 * These fences use a BO and a set of CPU-tracked state flags. The BO
1909 * is added to the object list of the last execbuf call in a QueueSubmit
1910 * and is marked EXEC_WRITE. The state flags track when the BO has been
1911 * submitted to the kernel. We need to do this because Vulkan lets you
1912 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1913 * will say it's idle in this case.
1914 */
1915 struct {
1916 struct anv_bo bo;
1917 enum anv_bo_fence_state state;
1918 } bo;
1919
1920 /** DRM syncobj handle for syncobj-based fences */
1921 uint32_t syncobj;
1922 };
1923 };
1924
1925 struct anv_fence {
1926 /* Permanent fence state. Every fence has some form of permanent state
1927 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
1928 * cross-process fences) or it could just be a dummy for use internally.
1929 */
1930 struct anv_fence_impl permanent;
1931
1932 /* Temporary fence state. A fence *may* have temporary state. That state
1933 * is added to the fence by an import operation and is reset back to
1934 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
1935 * state cannot be signaled because the fence must already be signaled
1936 * before the temporary state can be exported from the fence in the other
1937 * process and imported here.
1938 */
1939 struct anv_fence_impl temporary;
1940 };
1941
1942 struct anv_event {
1943 uint64_t semaphore;
1944 struct anv_state state;
1945 };
1946
1947 enum anv_semaphore_type {
1948 ANV_SEMAPHORE_TYPE_NONE = 0,
1949 ANV_SEMAPHORE_TYPE_DUMMY,
1950 ANV_SEMAPHORE_TYPE_BO,
1951 ANV_SEMAPHORE_TYPE_SYNC_FILE,
1952 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
1953 };
1954
1955 struct anv_semaphore_impl {
1956 enum anv_semaphore_type type;
1957
1958 union {
1959 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1960 * This BO will be added to the object list on any execbuf2 calls for
1961 * which this semaphore is used as a wait or signal fence. When used as
1962 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1963 */
1964 struct anv_bo *bo;
1965
1966 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
1967 * If the semaphore is in the unsignaled state due to either just being
1968 * created or because it has been used for a wait, fd will be -1.
1969 */
1970 int fd;
1971
1972 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
1973 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
1974 * import so we don't need to bother with a userspace cache.
1975 */
1976 uint32_t syncobj;
1977 };
1978 };
1979
1980 struct anv_semaphore {
1981 /* Permanent semaphore state. Every semaphore has some form of permanent
1982 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1983 * (for cross-process semaphores0 or it could just be a dummy for use
1984 * internally.
1985 */
1986 struct anv_semaphore_impl permanent;
1987
1988 /* Temporary semaphore state. A semaphore *may* have temporary state.
1989 * That state is added to the semaphore by an import operation and is reset
1990 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1991 * semaphore with temporary state cannot be signaled because the semaphore
1992 * must already be signaled before the temporary state can be exported from
1993 * the semaphore in the other process and imported here.
1994 */
1995 struct anv_semaphore_impl temporary;
1996 };
1997
1998 void anv_semaphore_reset_temporary(struct anv_device *device,
1999 struct anv_semaphore *semaphore);
2000
2001 struct anv_shader_module {
2002 unsigned char sha1[20];
2003 uint32_t size;
2004 char data[0];
2005 };
2006
2007 static inline gl_shader_stage
2008 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2009 {
2010 assert(__builtin_popcount(vk_stage) == 1);
2011 return ffs(vk_stage) - 1;
2012 }
2013
2014 static inline VkShaderStageFlagBits
2015 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2016 {
2017 return (1 << mesa_stage);
2018 }
2019
2020 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2021
2022 #define anv_foreach_stage(stage, stage_bits) \
2023 for (gl_shader_stage stage, \
2024 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2025 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2026 __tmp &= ~(1 << (stage)))
2027
2028 struct anv_pipeline_bind_map {
2029 uint32_t surface_count;
2030 uint32_t sampler_count;
2031 uint32_t image_count;
2032
2033 struct anv_pipeline_binding * surface_to_descriptor;
2034 struct anv_pipeline_binding * sampler_to_descriptor;
2035 };
2036
2037 struct anv_shader_bin_key {
2038 uint32_t size;
2039 uint8_t data[0];
2040 };
2041
2042 struct anv_shader_bin {
2043 uint32_t ref_cnt;
2044
2045 const struct anv_shader_bin_key *key;
2046
2047 struct anv_state kernel;
2048 uint32_t kernel_size;
2049
2050 const struct brw_stage_prog_data *prog_data;
2051 uint32_t prog_data_size;
2052
2053 struct anv_pipeline_bind_map bind_map;
2054 };
2055
2056 struct anv_shader_bin *
2057 anv_shader_bin_create(struct anv_device *device,
2058 const void *key, uint32_t key_size,
2059 const void *kernel, uint32_t kernel_size,
2060 const struct brw_stage_prog_data *prog_data,
2061 uint32_t prog_data_size, const void *prog_data_param,
2062 const struct anv_pipeline_bind_map *bind_map);
2063
2064 void
2065 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2066
2067 static inline void
2068 anv_shader_bin_ref(struct anv_shader_bin *shader)
2069 {
2070 assert(shader && shader->ref_cnt >= 1);
2071 p_atomic_inc(&shader->ref_cnt);
2072 }
2073
2074 static inline void
2075 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2076 {
2077 assert(shader && shader->ref_cnt >= 1);
2078 if (p_atomic_dec_zero(&shader->ref_cnt))
2079 anv_shader_bin_destroy(device, shader);
2080 }
2081
2082 struct anv_pipeline {
2083 struct anv_device * device;
2084 struct anv_batch batch;
2085 uint32_t batch_data[512];
2086 struct anv_reloc_list batch_relocs;
2087 uint32_t dynamic_state_mask;
2088 struct anv_dynamic_state dynamic_state;
2089
2090 struct anv_subpass * subpass;
2091 struct anv_pipeline_layout * layout;
2092
2093 bool needs_data_cache;
2094
2095 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2096
2097 struct {
2098 const struct gen_l3_config * l3_config;
2099 uint32_t total_size;
2100 } urb;
2101
2102 VkShaderStageFlags active_stages;
2103 struct anv_state blend_state;
2104
2105 uint32_t vb_used;
2106 uint32_t binding_stride[MAX_VBS];
2107 bool instancing_enable[MAX_VBS];
2108 bool primitive_restart;
2109 uint32_t topology;
2110
2111 uint32_t cs_right_mask;
2112
2113 bool writes_depth;
2114 bool depth_test_enable;
2115 bool writes_stencil;
2116 bool stencil_test_enable;
2117 bool depth_clamp_enable;
2118 bool sample_shading_enable;
2119 bool kill_pixel;
2120
2121 struct {
2122 uint32_t sf[7];
2123 uint32_t depth_stencil_state[3];
2124 } gen7;
2125
2126 struct {
2127 uint32_t sf[4];
2128 uint32_t raster[5];
2129 uint32_t wm_depth_stencil[3];
2130 } gen8;
2131
2132 struct {
2133 uint32_t wm_depth_stencil[4];
2134 } gen9;
2135
2136 uint32_t interface_descriptor_data[8];
2137 };
2138
2139 static inline bool
2140 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2141 gl_shader_stage stage)
2142 {
2143 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2144 }
2145
2146 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2147 static inline const struct brw_##prefix##_prog_data * \
2148 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2149 { \
2150 if (anv_pipeline_has_stage(pipeline, stage)) { \
2151 return (const struct brw_##prefix##_prog_data *) \
2152 pipeline->shaders[stage]->prog_data; \
2153 } else { \
2154 return NULL; \
2155 } \
2156 }
2157
2158 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2159 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2160 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2161 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2162 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2163 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2164
2165 static inline const struct brw_vue_prog_data *
2166 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2167 {
2168 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2169 return &get_gs_prog_data(pipeline)->base;
2170 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2171 return &get_tes_prog_data(pipeline)->base;
2172 else
2173 return &get_vs_prog_data(pipeline)->base;
2174 }
2175
2176 VkResult
2177 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2178 struct anv_pipeline_cache *cache,
2179 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2180 const VkAllocationCallbacks *alloc);
2181
2182 VkResult
2183 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2184 struct anv_pipeline_cache *cache,
2185 const VkComputePipelineCreateInfo *info,
2186 struct anv_shader_module *module,
2187 const char *entrypoint,
2188 const VkSpecializationInfo *spec_info);
2189
2190 struct anv_format_plane {
2191 enum isl_format isl_format:16;
2192 struct isl_swizzle swizzle;
2193
2194 /* Whether this plane contains chroma channels */
2195 bool has_chroma;
2196
2197 /* For downscaling of YUV planes */
2198 uint8_t denominator_scales[2];
2199
2200 /* How to map sampled ycbcr planes to a single 4 component element. */
2201 struct isl_swizzle ycbcr_swizzle;
2202 };
2203
2204
2205 struct anv_format {
2206 struct anv_format_plane planes[3];
2207 uint8_t n_planes;
2208 bool can_ycbcr;
2209 };
2210
2211 static inline uint32_t
2212 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2213 VkImageAspectFlags aspect_mask)
2214 {
2215 switch (aspect_mask) {
2216 case VK_IMAGE_ASPECT_COLOR_BIT:
2217 case VK_IMAGE_ASPECT_DEPTH_BIT:
2218 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
2219 return 0;
2220 case VK_IMAGE_ASPECT_STENCIL_BIT:
2221 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2222 return 0;
2223 /* Fall-through */
2224 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
2225 return 1;
2226 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
2227 return 2;
2228 default:
2229 /* Purposefully assert with depth/stencil aspects. */
2230 unreachable("invalid image aspect");
2231 }
2232 }
2233
2234 static inline uint32_t
2235 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2236 {
2237 uint32_t planes = 0;
2238
2239 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2240 VK_IMAGE_ASPECT_DEPTH_BIT |
2241 VK_IMAGE_ASPECT_STENCIL_BIT |
2242 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR))
2243 planes++;
2244 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT_KHR)
2245 planes++;
2246 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
2247 planes++;
2248
2249 return planes;
2250 }
2251
2252 static inline VkImageAspectFlags
2253 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2254 uint32_t plane)
2255 {
2256 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2257 if (_mesa_bitcount(image_aspects) > 1)
2258 return VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << plane;
2259 return VK_IMAGE_ASPECT_COLOR_BIT;
2260 }
2261 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2262 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2263 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2264 return VK_IMAGE_ASPECT_STENCIL_BIT;
2265 }
2266
2267 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2268 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2269
2270 const struct anv_format *
2271 anv_get_format(VkFormat format);
2272
2273 static inline uint32_t
2274 anv_get_format_planes(VkFormat vk_format)
2275 {
2276 const struct anv_format *format = anv_get_format(vk_format);
2277
2278 return format != NULL ? format->n_planes : 0;
2279 }
2280
2281 struct anv_format_plane
2282 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2283 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2284
2285 static inline enum isl_format
2286 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2287 VkImageAspectFlags aspect, VkImageTiling tiling)
2288 {
2289 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2290 }
2291
2292 static inline struct isl_swizzle
2293 anv_swizzle_for_render(struct isl_swizzle swizzle)
2294 {
2295 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2296 * RGB as RGBA for texturing
2297 */
2298 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2299 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2300
2301 /* But it doesn't matter what we render to that channel */
2302 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2303
2304 return swizzle;
2305 }
2306
2307 void
2308 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2309
2310 /**
2311 * Subsurface of an anv_image.
2312 */
2313 struct anv_surface {
2314 /** Valid only if isl_surf::size > 0. */
2315 struct isl_surf isl;
2316
2317 /**
2318 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2319 */
2320 uint32_t offset;
2321 };
2322
2323 struct anv_image {
2324 VkImageType type;
2325 /* The original VkFormat provided by the client. This may not match any
2326 * of the actual surface formats.
2327 */
2328 VkFormat vk_format;
2329 const struct anv_format *format;
2330
2331 VkImageAspectFlags aspects;
2332 VkExtent3D extent;
2333 uint32_t levels;
2334 uint32_t array_size;
2335 uint32_t samples; /**< VkImageCreateInfo::samples */
2336 uint32_t n_planes;
2337 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2338 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2339
2340 VkDeviceSize size;
2341 uint32_t alignment;
2342
2343 /* Whether the image is made of several underlying buffer objects rather a
2344 * single one with different offsets.
2345 */
2346 bool disjoint;
2347
2348 /**
2349 * Image subsurfaces
2350 *
2351 * For each foo, anv_image::planes[x].surface is valid if and only if
2352 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2353 * to figure the number associated with a given aspect.
2354 *
2355 * The hardware requires that the depth buffer and stencil buffer be
2356 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2357 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2358 * allocate the depth and stencil buffers as separate surfaces in the same
2359 * bo.
2360 *
2361 * Memory layout :
2362 *
2363 * -----------------------
2364 * | surface0 | /|\
2365 * ----------------------- |
2366 * | shadow surface0 | |
2367 * ----------------------- | Plane 0
2368 * | aux surface0 | |
2369 * ----------------------- |
2370 * | fast clear colors0 | \|/
2371 * -----------------------
2372 * | surface1 | /|\
2373 * ----------------------- |
2374 * | shadow surface1 | |
2375 * ----------------------- | Plane 1
2376 * | aux surface1 | |
2377 * ----------------------- |
2378 * | fast clear colors1 | \|/
2379 * -----------------------
2380 * | ... |
2381 * | |
2382 * -----------------------
2383 */
2384 struct {
2385 /**
2386 * Offset of the entire plane (whenever the image is disjoint this is
2387 * set to 0).
2388 */
2389 uint32_t offset;
2390
2391 VkDeviceSize size;
2392 uint32_t alignment;
2393
2394 struct anv_surface surface;
2395
2396 /**
2397 * A surface which shadows the main surface and may have different
2398 * tiling. This is used for sampling using a tiling that isn't supported
2399 * for other operations.
2400 */
2401 struct anv_surface shadow_surface;
2402
2403 /**
2404 * For color images, this is the aux usage for this image when not used
2405 * as a color attachment.
2406 *
2407 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2408 * image has a HiZ buffer.
2409 */
2410 enum isl_aux_usage aux_usage;
2411
2412 struct anv_surface aux_surface;
2413
2414 /**
2415 * Offset of the fast clear state (used to compute the
2416 * fast_clear_state_offset of the following planes).
2417 */
2418 uint32_t fast_clear_state_offset;
2419
2420 /**
2421 * BO associated with this plane, set when bound.
2422 */
2423 struct anv_bo *bo;
2424 VkDeviceSize bo_offset;
2425
2426 /**
2427 * When destroying the image, also free the bo.
2428 * */
2429 bool bo_is_owned;
2430 } planes[3];
2431 };
2432
2433 /* Returns the number of auxiliary buffer levels attached to an image. */
2434 static inline uint8_t
2435 anv_image_aux_levels(const struct anv_image * const image,
2436 VkImageAspectFlagBits aspect)
2437 {
2438 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2439 return image->planes[plane].aux_surface.isl.size > 0 ?
2440 image->planes[plane].aux_surface.isl.levels : 0;
2441 }
2442
2443 /* Returns the number of auxiliary buffer layers attached to an image. */
2444 static inline uint32_t
2445 anv_image_aux_layers(const struct anv_image * const image,
2446 VkImageAspectFlagBits aspect,
2447 const uint8_t miplevel)
2448 {
2449 assert(image);
2450
2451 /* The miplevel must exist in the main buffer. */
2452 assert(miplevel < image->levels);
2453
2454 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2455 /* There are no layers with auxiliary data because the miplevel has no
2456 * auxiliary data.
2457 */
2458 return 0;
2459 } else {
2460 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2461 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2462 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2463 }
2464 }
2465
2466 static inline unsigned
2467 anv_fast_clear_state_entry_size(const struct anv_device *device)
2468 {
2469 assert(device);
2470 /* Entry contents:
2471 * +--------------------------------------------+
2472 * | clear value dword(s) | needs resolve dword |
2473 * +--------------------------------------------+
2474 */
2475
2476 /* Ensure that the needs resolve dword is in fact dword-aligned to enable
2477 * GPU memcpy operations.
2478 */
2479 assert(device->isl_dev.ss.clear_value_size % 4 == 0);
2480 return device->isl_dev.ss.clear_value_size + 4;
2481 }
2482
2483 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2484 static inline bool
2485 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2486 const struct anv_image *image)
2487 {
2488 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2489 return false;
2490
2491 if (devinfo->gen < 8)
2492 return false;
2493
2494 return image->samples == 1;
2495 }
2496
2497 void
2498 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
2499 const struct anv_image *image,
2500 enum blorp_hiz_op op);
2501 void
2502 anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
2503 const struct anv_state surface_state,
2504 const struct anv_image * const image,
2505 VkImageAspectFlagBits aspect,
2506 const uint8_t level, const uint32_t layer_count,
2507 const enum blorp_fast_clear_op op);
2508
2509 void
2510 anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
2511 const struct anv_image *image,
2512 VkImageAspectFlagBits aspect,
2513 const uint32_t base_level, const uint32_t level_count,
2514 const uint32_t base_layer, uint32_t layer_count);
2515
2516 void
2517 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2518 const struct anv_image *image,
2519 uint32_t base_level, uint32_t level_count,
2520 uint32_t base_layer, uint32_t layer_count);
2521
2522 enum isl_aux_usage
2523 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2524 const struct anv_image *image,
2525 const VkImageAspectFlagBits aspect,
2526 const VkImageLayout layout);
2527
2528 /* This is defined as a macro so that it works for both
2529 * VkImageSubresourceRange and VkImageSubresourceLayers
2530 */
2531 #define anv_get_layerCount(_image, _range) \
2532 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2533 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2534
2535 static inline uint32_t
2536 anv_get_levelCount(const struct anv_image *image,
2537 const VkImageSubresourceRange *range)
2538 {
2539 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2540 image->levels - range->baseMipLevel : range->levelCount;
2541 }
2542
2543 static inline VkImageAspectFlags
2544 anv_image_expand_aspects(const struct anv_image *image,
2545 VkImageAspectFlags aspects)
2546 {
2547 /* If the underlying image has color plane aspects and
2548 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2549 * the underlying image. */
2550 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
2551 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2552 return image->aspects;
2553
2554 return aspects;
2555 }
2556
2557 static inline bool
2558 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2559 VkImageAspectFlags aspects2)
2560 {
2561 if (aspects1 == aspects2)
2562 return true;
2563
2564 /* Only 1 color aspects are compatibles. */
2565 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2566 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2567 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2568 return true;
2569
2570 return false;
2571 }
2572
2573 struct anv_image_view {
2574 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2575
2576 VkImageAspectFlags aspect_mask;
2577 VkFormat vk_format;
2578 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2579
2580 unsigned n_planes;
2581 struct {
2582 uint32_t image_plane;
2583
2584 struct isl_view isl;
2585
2586 /**
2587 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2588 * image layout of SHADER_READ_ONLY_OPTIMAL or
2589 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2590 */
2591 struct anv_surface_state optimal_sampler_surface_state;
2592
2593 /**
2594 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2595 * image layout of GENERAL.
2596 */
2597 struct anv_surface_state general_sampler_surface_state;
2598
2599 /**
2600 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2601 * states for write-only and readable, using the real format for
2602 * write-only and the lowered format for readable.
2603 */
2604 struct anv_surface_state storage_surface_state;
2605 struct anv_surface_state writeonly_storage_surface_state;
2606
2607 struct brw_image_param storage_image_param;
2608 } planes[3];
2609 };
2610
2611 enum anv_image_view_state_flags {
2612 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2613 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2614 };
2615
2616 void anv_image_fill_surface_state(struct anv_device *device,
2617 const struct anv_image *image,
2618 VkImageAspectFlagBits aspect,
2619 const struct isl_view *view,
2620 isl_surf_usage_flags_t view_usage,
2621 enum isl_aux_usage aux_usage,
2622 const union isl_color_value *clear_color,
2623 enum anv_image_view_state_flags flags,
2624 struct anv_surface_state *state_inout,
2625 struct brw_image_param *image_param_out);
2626
2627 struct anv_image_create_info {
2628 const VkImageCreateInfo *vk_info;
2629
2630 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2631 isl_tiling_flags_t isl_tiling_flags;
2632
2633 /** These flags will be added to any derived from VkImageCreateInfo. */
2634 isl_surf_usage_flags_t isl_extra_usage_flags;
2635
2636 uint32_t stride;
2637 };
2638
2639 VkResult anv_image_create(VkDevice _device,
2640 const struct anv_image_create_info *info,
2641 const VkAllocationCallbacks* alloc,
2642 VkImage *pImage);
2643
2644 #ifdef ANDROID
2645 VkResult anv_image_from_gralloc(VkDevice device_h,
2646 const VkImageCreateInfo *base_info,
2647 const VkNativeBufferANDROID *gralloc_info,
2648 const VkAllocationCallbacks *alloc,
2649 VkImage *pImage);
2650 #endif
2651
2652 const struct anv_surface *
2653 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2654 VkImageAspectFlags aspect_mask);
2655
2656 enum isl_format
2657 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2658
2659 static inline struct VkExtent3D
2660 anv_sanitize_image_extent(const VkImageType imageType,
2661 const struct VkExtent3D imageExtent)
2662 {
2663 switch (imageType) {
2664 case VK_IMAGE_TYPE_1D:
2665 return (VkExtent3D) { imageExtent.width, 1, 1 };
2666 case VK_IMAGE_TYPE_2D:
2667 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2668 case VK_IMAGE_TYPE_3D:
2669 return imageExtent;
2670 default:
2671 unreachable("invalid image type");
2672 }
2673 }
2674
2675 static inline struct VkOffset3D
2676 anv_sanitize_image_offset(const VkImageType imageType,
2677 const struct VkOffset3D imageOffset)
2678 {
2679 switch (imageType) {
2680 case VK_IMAGE_TYPE_1D:
2681 return (VkOffset3D) { imageOffset.x, 0, 0 };
2682 case VK_IMAGE_TYPE_2D:
2683 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2684 case VK_IMAGE_TYPE_3D:
2685 return imageOffset;
2686 default:
2687 unreachable("invalid image type");
2688 }
2689 }
2690
2691
2692 void anv_fill_buffer_surface_state(struct anv_device *device,
2693 struct anv_state state,
2694 enum isl_format format,
2695 uint32_t offset, uint32_t range,
2696 uint32_t stride);
2697
2698
2699 struct anv_ycbcr_conversion {
2700 const struct anv_format * format;
2701 VkSamplerYcbcrModelConversionKHR ycbcr_model;
2702 VkSamplerYcbcrRangeKHR ycbcr_range;
2703 VkComponentSwizzle mapping[4];
2704 VkChromaLocationKHR chroma_offsets[2];
2705 VkFilter chroma_filter;
2706 bool chroma_reconstruction;
2707 };
2708
2709 struct anv_sampler {
2710 uint32_t state[3][4];
2711 uint32_t n_planes;
2712 struct anv_ycbcr_conversion *conversion;
2713 };
2714
2715 struct anv_framebuffer {
2716 uint32_t width;
2717 uint32_t height;
2718 uint32_t layers;
2719
2720 uint32_t attachment_count;
2721 struct anv_image_view * attachments[0];
2722 };
2723
2724 struct anv_subpass {
2725 uint32_t attachment_count;
2726
2727 /**
2728 * A pointer to all attachment references used in this subpass.
2729 * Only valid if ::attachment_count > 0.
2730 */
2731 VkAttachmentReference * attachments;
2732 uint32_t input_count;
2733 VkAttachmentReference * input_attachments;
2734 uint32_t color_count;
2735 VkAttachmentReference * color_attachments;
2736 VkAttachmentReference * resolve_attachments;
2737
2738 VkAttachmentReference depth_stencil_attachment;
2739
2740 uint32_t view_mask;
2741
2742 /** Subpass has a depth/stencil self-dependency */
2743 bool has_ds_self_dep;
2744
2745 /** Subpass has at least one resolve attachment */
2746 bool has_resolve;
2747 };
2748
2749 static inline unsigned
2750 anv_subpass_view_count(const struct anv_subpass *subpass)
2751 {
2752 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2753 }
2754
2755 struct anv_render_pass_attachment {
2756 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2757 * its members individually.
2758 */
2759 VkFormat format;
2760 uint32_t samples;
2761 VkImageUsageFlags usage;
2762 VkAttachmentLoadOp load_op;
2763 VkAttachmentStoreOp store_op;
2764 VkAttachmentLoadOp stencil_load_op;
2765 VkImageLayout initial_layout;
2766 VkImageLayout final_layout;
2767 VkImageLayout first_subpass_layout;
2768
2769 /* The subpass id in which the attachment will be used last. */
2770 uint32_t last_subpass_idx;
2771 };
2772
2773 struct anv_render_pass {
2774 uint32_t attachment_count;
2775 uint32_t subpass_count;
2776 /* An array of subpass_count+1 flushes, one per subpass boundary */
2777 enum anv_pipe_bits * subpass_flushes;
2778 struct anv_render_pass_attachment * attachments;
2779 struct anv_subpass subpasses[0];
2780 };
2781
2782 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2783
2784 struct anv_query_pool {
2785 VkQueryType type;
2786 VkQueryPipelineStatisticFlags pipeline_statistics;
2787 /** Stride between slots, in bytes */
2788 uint32_t stride;
2789 /** Number of slots in this query pool */
2790 uint32_t slots;
2791 struct anv_bo bo;
2792 };
2793
2794 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2795 const char *name);
2796
2797 void anv_dump_image_to_ppm(struct anv_device *device,
2798 struct anv_image *image, unsigned miplevel,
2799 unsigned array_layer, VkImageAspectFlagBits aspect,
2800 const char *filename);
2801
2802 enum anv_dump_action {
2803 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2804 };
2805
2806 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2807 void anv_dump_finish(void);
2808
2809 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2810 struct anv_framebuffer *fb);
2811
2812 static inline uint32_t
2813 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2814 {
2815 /* This function must be called from within a subpass. */
2816 assert(cmd_state->pass && cmd_state->subpass);
2817
2818 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
2819
2820 /* The id of this subpass shouldn't exceed the number of subpasses in this
2821 * render pass minus 1.
2822 */
2823 assert(subpass_id < cmd_state->pass->subpass_count);
2824 return subpass_id;
2825 }
2826
2827 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2828 \
2829 static inline struct __anv_type * \
2830 __anv_type ## _from_handle(__VkType _handle) \
2831 { \
2832 return (struct __anv_type *) _handle; \
2833 } \
2834 \
2835 static inline __VkType \
2836 __anv_type ## _to_handle(struct __anv_type *_obj) \
2837 { \
2838 return (__VkType) _obj; \
2839 }
2840
2841 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2842 \
2843 static inline struct __anv_type * \
2844 __anv_type ## _from_handle(__VkType _handle) \
2845 { \
2846 return (struct __anv_type *)(uintptr_t) _handle; \
2847 } \
2848 \
2849 static inline __VkType \
2850 __anv_type ## _to_handle(struct __anv_type *_obj) \
2851 { \
2852 return (__VkType)(uintptr_t) _obj; \
2853 }
2854
2855 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2856 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2857
2858 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
2859 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
2860 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
2861 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
2862 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
2863
2864 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
2865 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
2866 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
2867 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
2868 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
2869 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
2870 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
2871 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
2872 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
2873 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
2874 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
2875 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
2876 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
2877 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
2878 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
2879 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
2880 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
2881 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
2882 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
2883 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
2884 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
2885 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_debug_report_callback, VkDebugReportCallbackEXT)
2886 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversionKHR)
2887
2888 /* Gen-specific function declarations */
2889 #ifdef genX
2890 # include "anv_genX.h"
2891 #else
2892 # define genX(x) gen7_##x
2893 # include "anv_genX.h"
2894 # undef genX
2895 # define genX(x) gen75_##x
2896 # include "anv_genX.h"
2897 # undef genX
2898 # define genX(x) gen8_##x
2899 # include "anv_genX.h"
2900 # undef genX
2901 # define genX(x) gen9_##x
2902 # include "anv_genX.h"
2903 # undef genX
2904 # define genX(x) gen10_##x
2905 # include "anv_genX.h"
2906 # undef genX
2907 #endif
2908
2909 #endif /* ANV_PRIVATE_H */