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[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53
54 /* Pre-declarations needed for WSI entrypoints */
55 struct wl_surface;
56 struct wl_display;
57 typedef struct xcb_connection_t xcb_connection_t;
58 typedef uint32_t xcb_visualid_t;
59 typedef uint32_t xcb_window_t;
60
61 struct anv_buffer;
62 struct anv_buffer_view;
63 struct anv_image_view;
64 struct anv_instance;
65 struct anv_debug_report_callback;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72 #include <vulkan/vk_android_native_buffer.h>
73
74 #include "anv_entrypoints.h"
75 #include "isl/isl.h"
76
77 #include "common/gen_debug.h"
78 #include "common/intel_log.h"
79 #include "wsi_common.h"
80
81 /* Allowing different clear colors requires us to perform a depth resolve at
82 * the end of certain render passes. This is because while slow clears store
83 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
84 * See the PRMs for examples describing when additional resolves would be
85 * necessary. To enable fast clears without requiring extra resolves, we set
86 * the clear value to a globally-defined one. We could allow different values
87 * if the user doesn't expect coherent data during or after a render passes
88 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
89 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
90 * 1.0f seems to be the only value used. The only application that doesn't set
91 * this value does so through the usage of an seemingly uninitialized clear
92 * value.
93 */
94 #define ANV_HZ_FC_VAL 1.0f
95
96 #define MAX_VBS 28
97 #define MAX_SETS 8
98 #define MAX_RTS 8
99 #define MAX_VIEWPORTS 16
100 #define MAX_SCISSORS 16
101 #define MAX_PUSH_CONSTANTS_SIZE 128
102 #define MAX_DYNAMIC_BUFFERS 16
103 #define MAX_IMAGES 8
104 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
105
106 #define ANV_SVGS_VB_INDEX MAX_VBS
107 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
108
109 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_down_npot_u32(uint32_t v, uint32_t a)
113 {
114 return v - (v % a);
115 }
116
117 static inline uint32_t
118 align_u32(uint32_t v, uint32_t a)
119 {
120 assert(a != 0 && a == (a & -a));
121 return (v + a - 1) & ~(a - 1);
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 anv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 anv_minify(uint32_t n, uint32_t levels)
148 {
149 if (unlikely(n == 0))
150 return 0;
151 else
152 return MAX2(n >> levels, 1);
153 }
154
155 static inline float
156 anv_clamp_f(float f, float min, float max)
157 {
158 assert(min < max);
159
160 if (f > max)
161 return max;
162 else if (f < min)
163 return min;
164 else
165 return f;
166 }
167
168 static inline bool
169 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
170 {
171 if (*inout_mask & clear_mask) {
172 *inout_mask &= ~clear_mask;
173 return true;
174 } else {
175 return false;
176 }
177 }
178
179 static inline union isl_color_value
180 vk_to_isl_color(VkClearColorValue color)
181 {
182 return (union isl_color_value) {
183 .u32 = {
184 color.uint32[0],
185 color.uint32[1],
186 color.uint32[2],
187 color.uint32[3],
188 },
189 };
190 }
191
192 #define for_each_bit(b, dword) \
193 for (uint32_t __dword = (dword); \
194 (b) = __builtin_ffs(__dword) - 1, __dword; \
195 __dword &= ~(1 << (b)))
196
197 #define typed_memcpy(dest, src, count) ({ \
198 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
199 memcpy((dest), (src), (count) * sizeof(*(src))); \
200 })
201
202 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
203 * to be added here in order to utilize mapping in debug/error/perf macros.
204 */
205 #define REPORT_OBJECT_TYPE(o) \
206 __builtin_choose_expr ( \
207 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
208 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
209 __builtin_choose_expr ( \
210 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
211 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
212 __builtin_choose_expr ( \
213 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
214 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
215 __builtin_choose_expr ( \
216 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
217 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
218 __builtin_choose_expr ( \
219 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
220 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
221 __builtin_choose_expr ( \
222 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
223 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
224 __builtin_choose_expr ( \
225 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
226 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
227 __builtin_choose_expr ( \
228 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
229 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
230 __builtin_choose_expr ( \
231 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
232 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
233 __builtin_choose_expr ( \
234 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
235 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
236 __builtin_choose_expr ( \
237 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
238 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
239 __builtin_choose_expr ( \
240 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
241 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
242 __builtin_choose_expr ( \
243 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
244 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
245 __builtin_choose_expr ( \
246 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
247 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
248 __builtin_choose_expr ( \
249 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
250 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
251 __builtin_choose_expr ( \
252 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
253 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
254 __builtin_choose_expr ( \
255 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
256 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
257 __builtin_choose_expr ( \
258 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
259 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
260 __builtin_choose_expr ( \
261 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
262 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
263 __builtin_choose_expr ( \
264 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
265 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
266 __builtin_choose_expr ( \
267 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
268 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
269 __builtin_choose_expr ( \
270 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
271 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
272 __builtin_choose_expr ( \
273 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
274 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
275 __builtin_choose_expr ( \
276 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
277 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
278 __builtin_choose_expr ( \
279 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
280 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
281 __builtin_choose_expr ( \
282 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
283 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
284 __builtin_choose_expr ( \
285 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
286 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
287 __builtin_choose_expr ( \
288 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
289 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
290 __builtin_choose_expr ( \
291 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
292 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
293 __builtin_choose_expr ( \
294 __builtin_types_compatible_p (__typeof (o), struct anv_debug_callback*), \
295 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
296 __builtin_choose_expr ( \
297 __builtin_types_compatible_p (__typeof (o), void*), \
298 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
299 /* The void expression results in a compile-time error \
300 when assigning the result to something. */ \
301 (void)0)))))))))))))))))))))))))))))))
302
303 /* Whenever we generate an error, pass it through this function. Useful for
304 * debugging, where we can break on it. Only call at error site, not when
305 * propagating errors. Might be useful to plug in a stack trace here.
306 */
307
308 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
309 VkDebugReportObjectTypeEXT type, VkResult error,
310 const char *file, int line, const char *format, ...);
311
312 #ifdef DEBUG
313 #define vk_error(error) __vk_errorf(NULL, NULL,\
314 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
315 error, __FILE__, __LINE__, NULL);
316 #define vk_errorf(instance, obj, error, format, ...)\
317 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
318 __FILE__, __LINE__, format, ## __VA_ARGS__);
319 #else
320 #define vk_error(error) error
321 #define vk_errorf(instance, obj, error, format, ...) error
322 #endif
323
324 /**
325 * Warn on ignored extension structs.
326 *
327 * The Vulkan spec requires us to ignore unsupported or unknown structs in
328 * a pNext chain. In debug mode, emitting warnings for ignored structs may
329 * help us discover structs that we should not have ignored.
330 *
331 *
332 * From the Vulkan 1.0.38 spec:
333 *
334 * Any component of the implementation (the loader, any enabled layers,
335 * and drivers) must skip over, without processing (other than reading the
336 * sType and pNext members) any chained structures with sType values not
337 * defined by extensions supported by that component.
338 */
339 #define anv_debug_ignored_stype(sType) \
340 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
341
342 void __anv_perf_warn(struct anv_instance *instance, const void *object,
343 VkDebugReportObjectTypeEXT type, const char *file,
344 int line, const char *format, ...)
345 anv_printflike(6, 7);
346 void anv_loge(const char *format, ...) anv_printflike(1, 2);
347 void anv_loge_v(const char *format, va_list va);
348
349 void anv_debug_report(struct anv_instance *instance,
350 VkDebugReportFlagsEXT flags,
351 VkDebugReportObjectTypeEXT object_type,
352 uint64_t handle,
353 size_t location,
354 int32_t messageCode,
355 const char* pLayerPrefix,
356 const char *pMessage);
357
358 /**
359 * Print a FINISHME message, including its source location.
360 */
361 #define anv_finishme(format, ...) \
362 do { \
363 static bool reported = false; \
364 if (!reported) { \
365 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
366 ##__VA_ARGS__); \
367 reported = true; \
368 } \
369 } while (0)
370
371 /**
372 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
373 */
374 #define anv_perf_warn(instance, obj, format, ...) \
375 do { \
376 static bool reported = false; \
377 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
378 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
379 format, ##__VA_ARGS__); \
380 reported = true; \
381 } \
382 } while (0)
383
384 /* A non-fatal assert. Useful for debugging. */
385 #ifdef DEBUG
386 #define anv_assert(x) ({ \
387 if (unlikely(!(x))) \
388 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
389 })
390 #else
391 #define anv_assert(x)
392 #endif
393
394 /* A multi-pointer allocator
395 *
396 * When copying data structures from the user (such as a render pass), it's
397 * common to need to allocate data for a bunch of different things. Instead
398 * of doing several allocations and having to handle all of the error checking
399 * that entails, it can be easier to do a single allocation. This struct
400 * helps facilitate that. The intended usage looks like this:
401 *
402 * ANV_MULTIALLOC(ma)
403 * anv_multialloc_add(&ma, &main_ptr, 1);
404 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
405 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
406 *
407 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
408 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
409 */
410 struct anv_multialloc {
411 size_t size;
412 size_t align;
413
414 uint32_t ptr_count;
415 void **ptrs[8];
416 };
417
418 #define ANV_MULTIALLOC_INIT \
419 ((struct anv_multialloc) { 0, })
420
421 #define ANV_MULTIALLOC(_name) \
422 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
423
424 __attribute__((always_inline))
425 static inline void
426 _anv_multialloc_add(struct anv_multialloc *ma,
427 void **ptr, size_t size, size_t align)
428 {
429 size_t offset = align_u64(ma->size, align);
430 ma->size = offset + size;
431 ma->align = MAX2(ma->align, align);
432
433 /* Store the offset in the pointer. */
434 *ptr = (void *)(uintptr_t)offset;
435
436 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
437 ma->ptrs[ma->ptr_count++] = ptr;
438 }
439
440 #define anv_multialloc_add_size(_ma, _ptr, _size) \
441 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
442
443 #define anv_multialloc_add(_ma, _ptr, _count) \
444 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
445
446 __attribute__((always_inline))
447 static inline void *
448 anv_multialloc_alloc(struct anv_multialloc *ma,
449 const VkAllocationCallbacks *alloc,
450 VkSystemAllocationScope scope)
451 {
452 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
453 if (!ptr)
454 return NULL;
455
456 /* Fill out each of the pointers with their final value.
457 *
458 * for (uint32_t i = 0; i < ma->ptr_count; i++)
459 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
460 *
461 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
462 * constant, GCC is incapable of figuring this out and unrolling the loop
463 * so we have to give it a little help.
464 */
465 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
466 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
467 if ((_i) < ma->ptr_count) \
468 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
469 _ANV_MULTIALLOC_UPDATE_POINTER(0);
470 _ANV_MULTIALLOC_UPDATE_POINTER(1);
471 _ANV_MULTIALLOC_UPDATE_POINTER(2);
472 _ANV_MULTIALLOC_UPDATE_POINTER(3);
473 _ANV_MULTIALLOC_UPDATE_POINTER(4);
474 _ANV_MULTIALLOC_UPDATE_POINTER(5);
475 _ANV_MULTIALLOC_UPDATE_POINTER(6);
476 _ANV_MULTIALLOC_UPDATE_POINTER(7);
477 #undef _ANV_MULTIALLOC_UPDATE_POINTER
478
479 return ptr;
480 }
481
482 __attribute__((always_inline))
483 static inline void *
484 anv_multialloc_alloc2(struct anv_multialloc *ma,
485 const VkAllocationCallbacks *parent_alloc,
486 const VkAllocationCallbacks *alloc,
487 VkSystemAllocationScope scope)
488 {
489 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
490 }
491
492 struct anv_bo {
493 uint32_t gem_handle;
494
495 /* Index into the current validation list. This is used by the
496 * validation list building alrogithm to track which buffers are already
497 * in the validation list so that we can ensure uniqueness.
498 */
499 uint32_t index;
500
501 /* Last known offset. This value is provided by the kernel when we
502 * execbuf and is used as the presumed offset for the next bunch of
503 * relocations.
504 */
505 uint64_t offset;
506
507 uint64_t size;
508 void *map;
509
510 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
511 uint32_t flags;
512 };
513
514 static inline void
515 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
516 {
517 bo->gem_handle = gem_handle;
518 bo->index = 0;
519 bo->offset = -1;
520 bo->size = size;
521 bo->map = NULL;
522 bo->flags = 0;
523 }
524
525 /* Represents a lock-free linked list of "free" things. This is used by
526 * both the block pool and the state pools. Unfortunately, in order to
527 * solve the ABA problem, we can't use a single uint32_t head.
528 */
529 union anv_free_list {
530 struct {
531 int32_t offset;
532
533 /* A simple count that is incremented every time the head changes. */
534 uint32_t count;
535 };
536 uint64_t u64;
537 };
538
539 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
540
541 struct anv_block_state {
542 union {
543 struct {
544 uint32_t next;
545 uint32_t end;
546 };
547 uint64_t u64;
548 };
549 };
550
551 struct anv_block_pool {
552 struct anv_device *device;
553
554 uint64_t bo_flags;
555
556 struct anv_bo bo;
557
558 /* The offset from the start of the bo to the "center" of the block
559 * pool. Pointers to allocated blocks are given by
560 * bo.map + center_bo_offset + offsets.
561 */
562 uint32_t center_bo_offset;
563
564 /* Current memory map of the block pool. This pointer may or may not
565 * point to the actual beginning of the block pool memory. If
566 * anv_block_pool_alloc_back has ever been called, then this pointer
567 * will point to the "center" position of the buffer and all offsets
568 * (negative or positive) given out by the block pool alloc functions
569 * will be valid relative to this pointer.
570 *
571 * In particular, map == bo.map + center_offset
572 */
573 void *map;
574 int fd;
575
576 /**
577 * Array of mmaps and gem handles owned by the block pool, reclaimed when
578 * the block pool is destroyed.
579 */
580 struct u_vector mmap_cleanups;
581
582 struct anv_block_state state;
583
584 struct anv_block_state back_state;
585 };
586
587 /* Block pools are backed by a fixed-size 1GB memfd */
588 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
589
590 /* The center of the block pool is also the middle of the memfd. This may
591 * change in the future if we decide differently for some reason.
592 */
593 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
594
595 static inline uint32_t
596 anv_block_pool_size(struct anv_block_pool *pool)
597 {
598 return pool->state.end + pool->back_state.end;
599 }
600
601 struct anv_state {
602 int32_t offset;
603 uint32_t alloc_size;
604 void *map;
605 };
606
607 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
608
609 struct anv_fixed_size_state_pool {
610 union anv_free_list free_list;
611 struct anv_block_state block;
612 };
613
614 #define ANV_MIN_STATE_SIZE_LOG2 6
615 #define ANV_MAX_STATE_SIZE_LOG2 20
616
617 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
618
619 struct anv_state_pool {
620 struct anv_block_pool block_pool;
621
622 /* The size of blocks which will be allocated from the block pool */
623 uint32_t block_size;
624
625 /** Free list for "back" allocations */
626 union anv_free_list back_alloc_free_list;
627
628 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
629 };
630
631 struct anv_state_stream_block;
632
633 struct anv_state_stream {
634 struct anv_state_pool *state_pool;
635
636 /* The size of blocks to allocate from the state pool */
637 uint32_t block_size;
638
639 /* Current block we're allocating from */
640 struct anv_state block;
641
642 /* Offset into the current block at which to allocate the next state */
643 uint32_t next;
644
645 /* List of all blocks allocated from this pool */
646 struct anv_state_stream_block *block_list;
647 };
648
649 /* The block_pool functions exported for testing only. The block pool should
650 * only be used via a state pool (see below).
651 */
652 VkResult anv_block_pool_init(struct anv_block_pool *pool,
653 struct anv_device *device,
654 uint32_t initial_size,
655 uint64_t bo_flags);
656 void anv_block_pool_finish(struct anv_block_pool *pool);
657 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
658 uint32_t block_size);
659 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
660 uint32_t block_size);
661
662 VkResult anv_state_pool_init(struct anv_state_pool *pool,
663 struct anv_device *device,
664 uint32_t block_size,
665 uint64_t bo_flags);
666 void anv_state_pool_finish(struct anv_state_pool *pool);
667 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
668 uint32_t state_size, uint32_t alignment);
669 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
670 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
671 void anv_state_stream_init(struct anv_state_stream *stream,
672 struct anv_state_pool *state_pool,
673 uint32_t block_size);
674 void anv_state_stream_finish(struct anv_state_stream *stream);
675 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
676 uint32_t size, uint32_t alignment);
677
678 /**
679 * Implements a pool of re-usable BOs. The interface is identical to that
680 * of block_pool except that each block is its own BO.
681 */
682 struct anv_bo_pool {
683 struct anv_device *device;
684
685 uint64_t bo_flags;
686
687 void *free_list[16];
688 };
689
690 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
691 uint64_t bo_flags);
692 void anv_bo_pool_finish(struct anv_bo_pool *pool);
693 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
694 uint32_t size);
695 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
696
697 struct anv_scratch_bo {
698 bool exists;
699 struct anv_bo bo;
700 };
701
702 struct anv_scratch_pool {
703 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
704 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
705 };
706
707 void anv_scratch_pool_init(struct anv_device *device,
708 struct anv_scratch_pool *pool);
709 void anv_scratch_pool_finish(struct anv_device *device,
710 struct anv_scratch_pool *pool);
711 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
712 struct anv_scratch_pool *pool,
713 gl_shader_stage stage,
714 unsigned per_thread_scratch);
715
716 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
717 struct anv_bo_cache {
718 struct hash_table *bo_map;
719 pthread_mutex_t mutex;
720 };
721
722 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
723 void anv_bo_cache_finish(struct anv_bo_cache *cache);
724 VkResult anv_bo_cache_alloc(struct anv_device *device,
725 struct anv_bo_cache *cache,
726 uint64_t size, struct anv_bo **bo);
727 VkResult anv_bo_cache_import(struct anv_device *device,
728 struct anv_bo_cache *cache,
729 int fd, struct anv_bo **bo);
730 VkResult anv_bo_cache_export(struct anv_device *device,
731 struct anv_bo_cache *cache,
732 struct anv_bo *bo_in, int *fd_out);
733 void anv_bo_cache_release(struct anv_device *device,
734 struct anv_bo_cache *cache,
735 struct anv_bo *bo);
736
737 struct anv_memory_type {
738 /* Standard bits passed on to the client */
739 VkMemoryPropertyFlags propertyFlags;
740 uint32_t heapIndex;
741
742 /* Driver-internal book-keeping */
743 VkBufferUsageFlags valid_buffer_usage;
744 };
745
746 struct anv_memory_heap {
747 /* Standard bits passed on to the client */
748 VkDeviceSize size;
749 VkMemoryHeapFlags flags;
750
751 /* Driver-internal book-keeping */
752 bool supports_48bit_addresses;
753 };
754
755 struct anv_physical_device {
756 VK_LOADER_DATA _loader_data;
757
758 struct anv_instance * instance;
759 uint32_t chipset_id;
760 char path[20];
761 const char * name;
762 struct gen_device_info info;
763 /** Amount of "GPU memory" we want to advertise
764 *
765 * Clearly, this value is bogus since Intel is a UMA architecture. On
766 * gen7 platforms, we are limited by GTT size unless we want to implement
767 * fine-grained tracking and GTT splitting. On Broadwell and above we are
768 * practically unlimited. However, we will never report more than 3/4 of
769 * the total system ram to try and avoid running out of RAM.
770 */
771 bool supports_48bit_addresses;
772 struct brw_compiler * compiler;
773 struct isl_device isl_dev;
774 int cmd_parser_version;
775 bool has_exec_async;
776 bool has_exec_fence;
777 bool has_syncobj;
778 bool has_syncobj_wait;
779
780 uint32_t eu_total;
781 uint32_t subslice_total;
782
783 struct {
784 uint32_t type_count;
785 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
786 uint32_t heap_count;
787 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
788 } memory;
789
790 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
791 uint8_t driver_uuid[VK_UUID_SIZE];
792 uint8_t device_uuid[VK_UUID_SIZE];
793
794 struct wsi_device wsi_device;
795 int local_fd;
796 };
797
798 struct anv_debug_report_callback {
799 /* Link in the 'callbacks' list in anv_instance struct. */
800 struct list_head link;
801 VkDebugReportFlagsEXT flags;
802 PFN_vkDebugReportCallbackEXT callback;
803 void * data;
804 };
805
806 struct anv_instance {
807 VK_LOADER_DATA _loader_data;
808
809 VkAllocationCallbacks alloc;
810
811 uint32_t apiVersion;
812 int physicalDeviceCount;
813 struct anv_physical_device physicalDevice;
814
815 /* VK_EXT_debug_report debug callbacks */
816 pthread_mutex_t callbacks_mutex;
817 struct list_head callbacks;
818 struct anv_debug_report_callback destroy_debug_cb;
819 };
820
821 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
822 void anv_finish_wsi(struct anv_physical_device *physical_device);
823
824 bool anv_instance_extension_supported(const char *name);
825 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
826 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
827 const char *name);
828
829 struct anv_queue {
830 VK_LOADER_DATA _loader_data;
831
832 struct anv_device * device;
833
834 struct anv_state_pool * pool;
835 };
836
837 struct anv_pipeline_cache {
838 struct anv_device * device;
839 pthread_mutex_t mutex;
840
841 struct hash_table * cache;
842 };
843
844 struct anv_pipeline_bind_map;
845
846 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
847 struct anv_device *device,
848 bool cache_enabled);
849 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
850
851 struct anv_shader_bin *
852 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
853 const void *key, uint32_t key_size);
854 struct anv_shader_bin *
855 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
856 const void *key_data, uint32_t key_size,
857 const void *kernel_data, uint32_t kernel_size,
858 const struct brw_stage_prog_data *prog_data,
859 uint32_t prog_data_size,
860 const struct anv_pipeline_bind_map *bind_map);
861
862 struct anv_device {
863 VK_LOADER_DATA _loader_data;
864
865 VkAllocationCallbacks alloc;
866
867 struct anv_instance * instance;
868 uint32_t chipset_id;
869 struct gen_device_info info;
870 struct isl_device isl_dev;
871 int context_id;
872 int fd;
873 bool can_chain_batches;
874 bool robust_buffer_access;
875
876 struct anv_bo_pool batch_bo_pool;
877
878 struct anv_bo_cache bo_cache;
879
880 struct anv_state_pool dynamic_state_pool;
881 struct anv_state_pool instruction_state_pool;
882 struct anv_state_pool surface_state_pool;
883
884 struct anv_bo workaround_bo;
885 struct anv_bo trivial_batch_bo;
886
887 struct anv_pipeline_cache blorp_shader_cache;
888 struct blorp_context blorp;
889
890 struct anv_state border_colors;
891
892 struct anv_queue queue;
893
894 struct anv_scratch_pool scratch_pool;
895
896 uint32_t default_mocs;
897
898 pthread_mutex_t mutex;
899 pthread_cond_t queue_submit;
900 bool lost;
901 };
902
903 static void inline
904 anv_state_flush(struct anv_device *device, struct anv_state state)
905 {
906 if (device->info.has_llc)
907 return;
908
909 gen_flush_range(state.map, state.alloc_size);
910 }
911
912 void anv_device_init_blorp(struct anv_device *device);
913 void anv_device_finish_blorp(struct anv_device *device);
914
915 VkResult anv_device_execbuf(struct anv_device *device,
916 struct drm_i915_gem_execbuffer2 *execbuf,
917 struct anv_bo **execbuf_bos);
918 VkResult anv_device_query_status(struct anv_device *device);
919 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
920 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
921 int64_t timeout);
922
923 void* anv_gem_mmap(struct anv_device *device,
924 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
925 void anv_gem_munmap(void *p, uint64_t size);
926 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
927 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
928 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
929 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
930 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
931 int anv_gem_execbuffer(struct anv_device *device,
932 struct drm_i915_gem_execbuffer2 *execbuf);
933 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
934 uint32_t stride, uint32_t tiling);
935 int anv_gem_create_context(struct anv_device *device);
936 int anv_gem_destroy_context(struct anv_device *device, int context);
937 int anv_gem_get_context_param(int fd, int context, uint32_t param,
938 uint64_t *value);
939 int anv_gem_get_param(int fd, uint32_t param);
940 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
941 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
942 int anv_gem_get_aperture(int fd, uint64_t *size);
943 bool anv_gem_supports_48b_addresses(int fd);
944 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
945 uint32_t *active, uint32_t *pending);
946 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
947 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
948 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
949 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
950 uint32_t read_domains, uint32_t write_domain);
951 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
952 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
953 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
954 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
955 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
956 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
957 uint32_t handle);
958 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
959 uint32_t handle, int fd);
960 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
961 bool anv_gem_supports_syncobj_wait(int fd);
962 int anv_gem_syncobj_wait(struct anv_device *device,
963 uint32_t *handles, uint32_t num_handles,
964 int64_t abs_timeout_ns, bool wait_all);
965
966 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
967
968 struct anv_reloc_list {
969 uint32_t num_relocs;
970 uint32_t array_length;
971 struct drm_i915_gem_relocation_entry * relocs;
972 struct anv_bo ** reloc_bos;
973 };
974
975 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
976 const VkAllocationCallbacks *alloc);
977 void anv_reloc_list_finish(struct anv_reloc_list *list,
978 const VkAllocationCallbacks *alloc);
979
980 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
981 const VkAllocationCallbacks *alloc,
982 uint32_t offset, struct anv_bo *target_bo,
983 uint32_t delta);
984
985 struct anv_batch_bo {
986 /* Link in the anv_cmd_buffer.owned_batch_bos list */
987 struct list_head link;
988
989 struct anv_bo bo;
990
991 /* Bytes actually consumed in this batch BO */
992 uint32_t length;
993
994 struct anv_reloc_list relocs;
995 };
996
997 struct anv_batch {
998 const VkAllocationCallbacks * alloc;
999
1000 void * start;
1001 void * end;
1002 void * next;
1003
1004 struct anv_reloc_list * relocs;
1005
1006 /* This callback is called (with the associated user data) in the event
1007 * that the batch runs out of space.
1008 */
1009 VkResult (*extend_cb)(struct anv_batch *, void *);
1010 void * user_data;
1011
1012 /**
1013 * Current error status of the command buffer. Used to track inconsistent
1014 * or incomplete command buffer states that are the consequence of run-time
1015 * errors such as out of memory scenarios. We want to track this in the
1016 * batch because the command buffer object is not visible to some parts
1017 * of the driver.
1018 */
1019 VkResult status;
1020 };
1021
1022 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1023 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1024 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1025 void *location, struct anv_bo *bo, uint32_t offset);
1026 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1027 struct anv_batch *batch);
1028
1029 static inline VkResult
1030 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1031 {
1032 assert(error != VK_SUCCESS);
1033 if (batch->status == VK_SUCCESS)
1034 batch->status = error;
1035 return batch->status;
1036 }
1037
1038 static inline bool
1039 anv_batch_has_error(struct anv_batch *batch)
1040 {
1041 return batch->status != VK_SUCCESS;
1042 }
1043
1044 struct anv_address {
1045 struct anv_bo *bo;
1046 uint32_t offset;
1047 };
1048
1049 static inline uint64_t
1050 _anv_combine_address(struct anv_batch *batch, void *location,
1051 const struct anv_address address, uint32_t delta)
1052 {
1053 if (address.bo == NULL) {
1054 return address.offset + delta;
1055 } else {
1056 assert(batch->start <= location && location < batch->end);
1057
1058 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1059 }
1060 }
1061
1062 #define __gen_address_type struct anv_address
1063 #define __gen_user_data struct anv_batch
1064 #define __gen_combine_address _anv_combine_address
1065
1066 /* Wrapper macros needed to work around preprocessor argument issues. In
1067 * particular, arguments don't get pre-evaluated if they are concatenated.
1068 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1069 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1070 * We can work around this easily enough with these helpers.
1071 */
1072 #define __anv_cmd_length(cmd) cmd ## _length
1073 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1074 #define __anv_cmd_header(cmd) cmd ## _header
1075 #define __anv_cmd_pack(cmd) cmd ## _pack
1076 #define __anv_reg_num(reg) reg ## _num
1077
1078 #define anv_pack_struct(dst, struc, ...) do { \
1079 struct struc __template = { \
1080 __VA_ARGS__ \
1081 }; \
1082 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1083 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1084 } while (0)
1085
1086 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1087 void *__dst = anv_batch_emit_dwords(batch, n); \
1088 if (__dst) { \
1089 struct cmd __template = { \
1090 __anv_cmd_header(cmd), \
1091 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1092 __VA_ARGS__ \
1093 }; \
1094 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1095 } \
1096 __dst; \
1097 })
1098
1099 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1100 do { \
1101 uint32_t *dw; \
1102 \
1103 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1104 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1105 if (!dw) \
1106 break; \
1107 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1108 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1109 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1110 } while (0)
1111
1112 #define anv_batch_emit(batch, cmd, name) \
1113 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1114 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1115 __builtin_expect(_dst != NULL, 1); \
1116 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1117 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1118 _dst = NULL; \
1119 }))
1120
1121 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1122 .GraphicsDataTypeGFDT = 0, \
1123 .LLCCacheabilityControlLLCCC = 0, \
1124 .L3CacheabilityControlL3CC = 1, \
1125 }
1126
1127 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1128 .LLCeLLCCacheabilityControlLLCCC = 0, \
1129 .L3CacheabilityControlL3CC = 1, \
1130 }
1131
1132 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1133 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1134 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1135 .AgeforQUADLRU = 0 \
1136 }
1137
1138 /* Skylake: MOCS is now an index into an array of 62 different caching
1139 * configurations programmed by the kernel.
1140 */
1141
1142 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1143 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1144 .IndextoMOCSTables = 2 \
1145 }
1146
1147 #define GEN9_MOCS_PTE { \
1148 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1149 .IndextoMOCSTables = 1 \
1150 }
1151
1152 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1153 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1154 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1155 .IndextoMOCSTables = 2 \
1156 }
1157
1158 #define GEN10_MOCS_PTE { \
1159 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1160 .IndextoMOCSTables = 1 \
1161 }
1162
1163 struct anv_device_memory {
1164 struct anv_bo * bo;
1165 struct anv_memory_type * type;
1166 VkDeviceSize map_size;
1167 void * map;
1168 };
1169
1170 /**
1171 * Header for Vertex URB Entry (VUE)
1172 */
1173 struct anv_vue_header {
1174 uint32_t Reserved;
1175 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1176 uint32_t ViewportIndex;
1177 float PointWidth;
1178 };
1179
1180 struct anv_descriptor_set_binding_layout {
1181 #ifndef NDEBUG
1182 /* The type of the descriptors in this binding */
1183 VkDescriptorType type;
1184 #endif
1185
1186 /* Number of array elements in this binding */
1187 uint16_t array_size;
1188
1189 /* Index into the flattend descriptor set */
1190 uint16_t descriptor_index;
1191
1192 /* Index into the dynamic state array for a dynamic buffer */
1193 int16_t dynamic_offset_index;
1194
1195 /* Index into the descriptor set buffer views */
1196 int16_t buffer_index;
1197
1198 struct {
1199 /* Index into the binding table for the associated surface */
1200 int16_t surface_index;
1201
1202 /* Index into the sampler table for the associated sampler */
1203 int16_t sampler_index;
1204
1205 /* Index into the image table for the associated image */
1206 int16_t image_index;
1207 } stage[MESA_SHADER_STAGES];
1208
1209 /* Immutable samplers (or NULL if no immutable samplers) */
1210 struct anv_sampler **immutable_samplers;
1211 };
1212
1213 struct anv_descriptor_set_layout {
1214 /* Number of bindings in this descriptor set */
1215 uint16_t binding_count;
1216
1217 /* Total size of the descriptor set with room for all array entries */
1218 uint16_t size;
1219
1220 /* Shader stages affected by this descriptor set */
1221 uint16_t shader_stages;
1222
1223 /* Number of buffers in this descriptor set */
1224 uint16_t buffer_count;
1225
1226 /* Number of dynamic offsets used by this descriptor set */
1227 uint16_t dynamic_offset_count;
1228
1229 /* Bindings in this descriptor set */
1230 struct anv_descriptor_set_binding_layout binding[0];
1231 };
1232
1233 struct anv_descriptor {
1234 VkDescriptorType type;
1235
1236 union {
1237 struct {
1238 VkImageLayout layout;
1239 struct anv_image_view *image_view;
1240 struct anv_sampler *sampler;
1241 };
1242
1243 struct {
1244 struct anv_buffer *buffer;
1245 uint64_t offset;
1246 uint64_t range;
1247 };
1248
1249 struct anv_buffer_view *buffer_view;
1250 };
1251 };
1252
1253 struct anv_descriptor_set {
1254 const struct anv_descriptor_set_layout *layout;
1255 uint32_t size;
1256 uint32_t buffer_count;
1257 struct anv_buffer_view *buffer_views;
1258 struct anv_descriptor descriptors[0];
1259 };
1260
1261 struct anv_buffer_view {
1262 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1263 struct anv_bo *bo;
1264 uint32_t offset; /**< Offset into bo. */
1265 uint64_t range; /**< VkBufferViewCreateInfo::range */
1266
1267 struct anv_state surface_state;
1268 struct anv_state storage_surface_state;
1269 struct anv_state writeonly_storage_surface_state;
1270
1271 struct brw_image_param storage_image_param;
1272 };
1273
1274 struct anv_push_descriptor_set {
1275 struct anv_descriptor_set set;
1276
1277 /* Put this field right behind anv_descriptor_set so it fills up the
1278 * descriptors[0] field. */
1279 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1280 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1281 };
1282
1283 struct anv_descriptor_pool {
1284 uint32_t size;
1285 uint32_t next;
1286 uint32_t free_list;
1287
1288 struct anv_state_stream surface_state_stream;
1289 void *surface_state_free_list;
1290
1291 char data[0];
1292 };
1293
1294 enum anv_descriptor_template_entry_type {
1295 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1296 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1297 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1298 };
1299
1300 struct anv_descriptor_template_entry {
1301 /* The type of descriptor in this entry */
1302 VkDescriptorType type;
1303
1304 /* Binding in the descriptor set */
1305 uint32_t binding;
1306
1307 /* Offset at which to write into the descriptor set binding */
1308 uint32_t array_element;
1309
1310 /* Number of elements to write into the descriptor set binding */
1311 uint32_t array_count;
1312
1313 /* Offset into the user provided data */
1314 size_t offset;
1315
1316 /* Stride between elements into the user provided data */
1317 size_t stride;
1318 };
1319
1320 struct anv_descriptor_update_template {
1321 /* The descriptor set this template corresponds to. This value is only
1322 * valid if the template was created with the templateType
1323 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1324 */
1325 uint8_t set;
1326
1327 /* Number of entries in this template */
1328 uint32_t entry_count;
1329
1330 /* Entries of the template */
1331 struct anv_descriptor_template_entry entries[0];
1332 };
1333
1334 size_t
1335 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1336
1337 size_t
1338 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1339
1340 void
1341 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1342 const struct gen_device_info * const devinfo,
1343 const VkDescriptorImageInfo * const info,
1344 VkDescriptorType type,
1345 uint32_t binding,
1346 uint32_t element);
1347
1348 void
1349 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1350 VkDescriptorType type,
1351 struct anv_buffer_view *buffer_view,
1352 uint32_t binding,
1353 uint32_t element);
1354
1355 void
1356 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1357 struct anv_device *device,
1358 struct anv_state_stream *alloc_stream,
1359 VkDescriptorType type,
1360 struct anv_buffer *buffer,
1361 uint32_t binding,
1362 uint32_t element,
1363 VkDeviceSize offset,
1364 VkDeviceSize range);
1365
1366 void
1367 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1368 struct anv_device *device,
1369 struct anv_state_stream *alloc_stream,
1370 const struct anv_descriptor_update_template *template,
1371 const void *data);
1372
1373 VkResult
1374 anv_descriptor_set_create(struct anv_device *device,
1375 struct anv_descriptor_pool *pool,
1376 const struct anv_descriptor_set_layout *layout,
1377 struct anv_descriptor_set **out_set);
1378
1379 void
1380 anv_descriptor_set_destroy(struct anv_device *device,
1381 struct anv_descriptor_pool *pool,
1382 struct anv_descriptor_set *set);
1383
1384 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1385
1386 struct anv_pipeline_binding {
1387 /* The descriptor set this surface corresponds to. The special value of
1388 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1389 * to a color attachment and not a regular descriptor.
1390 */
1391 uint8_t set;
1392
1393 /* Binding in the descriptor set */
1394 uint32_t binding;
1395
1396 /* Index in the binding */
1397 uint32_t index;
1398
1399 /* Plane in the binding index */
1400 uint8_t plane;
1401
1402 /* Input attachment index (relative to the subpass) */
1403 uint8_t input_attachment_index;
1404
1405 /* For a storage image, whether it is write-only */
1406 bool write_only;
1407 };
1408
1409 struct anv_pipeline_layout {
1410 struct {
1411 struct anv_descriptor_set_layout *layout;
1412 uint32_t dynamic_offset_start;
1413 } set[MAX_SETS];
1414
1415 uint32_t num_sets;
1416
1417 struct {
1418 bool has_dynamic_offsets;
1419 } stage[MESA_SHADER_STAGES];
1420
1421 unsigned char sha1[20];
1422 };
1423
1424 struct anv_buffer {
1425 struct anv_device * device;
1426 VkDeviceSize size;
1427
1428 VkBufferUsageFlags usage;
1429
1430 /* Set when bound */
1431 struct anv_bo * bo;
1432 VkDeviceSize offset;
1433 };
1434
1435 static inline uint64_t
1436 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1437 {
1438 assert(offset <= buffer->size);
1439 if (range == VK_WHOLE_SIZE) {
1440 return buffer->size - offset;
1441 } else {
1442 assert(range <= buffer->size);
1443 return range;
1444 }
1445 }
1446
1447 enum anv_cmd_dirty_bits {
1448 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1449 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1450 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1451 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1452 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1453 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1454 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1455 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1456 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1457 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1458 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1459 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1460 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1461 };
1462 typedef uint32_t anv_cmd_dirty_mask_t;
1463
1464 enum anv_pipe_bits {
1465 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1466 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1467 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1468 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1469 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1470 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1471 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1472 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1473 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1474 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1475 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1476
1477 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1478 * a flush has happened but not a CS stall. The next time we do any sort
1479 * of invalidation we need to insert a CS stall at that time. Otherwise,
1480 * we would have to CS stall on every flush which could be bad.
1481 */
1482 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1483 };
1484
1485 #define ANV_PIPE_FLUSH_BITS ( \
1486 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1487 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1488 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1489
1490 #define ANV_PIPE_STALL_BITS ( \
1491 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1492 ANV_PIPE_DEPTH_STALL_BIT | \
1493 ANV_PIPE_CS_STALL_BIT)
1494
1495 #define ANV_PIPE_INVALIDATE_BITS ( \
1496 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1497 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1498 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1499 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1500 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1501 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1502
1503 static inline enum anv_pipe_bits
1504 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1505 {
1506 enum anv_pipe_bits pipe_bits = 0;
1507
1508 unsigned b;
1509 for_each_bit(b, flags) {
1510 switch ((VkAccessFlagBits)(1 << b)) {
1511 case VK_ACCESS_SHADER_WRITE_BIT:
1512 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1513 break;
1514 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1515 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1516 break;
1517 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1518 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1519 break;
1520 case VK_ACCESS_TRANSFER_WRITE_BIT:
1521 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1522 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1523 break;
1524 default:
1525 break; /* Nothing to do */
1526 }
1527 }
1528
1529 return pipe_bits;
1530 }
1531
1532 static inline enum anv_pipe_bits
1533 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1534 {
1535 enum anv_pipe_bits pipe_bits = 0;
1536
1537 unsigned b;
1538 for_each_bit(b, flags) {
1539 switch ((VkAccessFlagBits)(1 << b)) {
1540 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1541 case VK_ACCESS_INDEX_READ_BIT:
1542 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1543 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1544 break;
1545 case VK_ACCESS_UNIFORM_READ_BIT:
1546 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1547 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1548 break;
1549 case VK_ACCESS_SHADER_READ_BIT:
1550 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1551 case VK_ACCESS_TRANSFER_READ_BIT:
1552 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1553 break;
1554 default:
1555 break; /* Nothing to do */
1556 }
1557 }
1558
1559 return pipe_bits;
1560 }
1561
1562 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1563 VK_IMAGE_ASPECT_COLOR_BIT | \
1564 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1565 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1566 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1567 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1568 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1569 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1570 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1571
1572 struct anv_vertex_binding {
1573 struct anv_buffer * buffer;
1574 VkDeviceSize offset;
1575 };
1576
1577 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1578 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1579
1580 struct anv_push_constants {
1581 /* Current allocated size of this push constants data structure.
1582 * Because a decent chunk of it may not be used (images on SKL, for
1583 * instance), we won't actually allocate the entire structure up-front.
1584 */
1585 uint32_t size;
1586
1587 /* Push constant data provided by the client through vkPushConstants */
1588 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1589
1590 /* Image data for image_load_store on pre-SKL */
1591 struct brw_image_param images[MAX_IMAGES];
1592 };
1593
1594 struct anv_dynamic_state {
1595 struct {
1596 uint32_t count;
1597 VkViewport viewports[MAX_VIEWPORTS];
1598 } viewport;
1599
1600 struct {
1601 uint32_t count;
1602 VkRect2D scissors[MAX_SCISSORS];
1603 } scissor;
1604
1605 float line_width;
1606
1607 struct {
1608 float bias;
1609 float clamp;
1610 float slope;
1611 } depth_bias;
1612
1613 float blend_constants[4];
1614
1615 struct {
1616 float min;
1617 float max;
1618 } depth_bounds;
1619
1620 struct {
1621 uint32_t front;
1622 uint32_t back;
1623 } stencil_compare_mask;
1624
1625 struct {
1626 uint32_t front;
1627 uint32_t back;
1628 } stencil_write_mask;
1629
1630 struct {
1631 uint32_t front;
1632 uint32_t back;
1633 } stencil_reference;
1634 };
1635
1636 extern const struct anv_dynamic_state default_dynamic_state;
1637
1638 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1639 const struct anv_dynamic_state *src,
1640 uint32_t copy_mask);
1641
1642 struct anv_surface_state {
1643 struct anv_state state;
1644 /** Address of the surface referred to by this state
1645 *
1646 * This address is relative to the start of the BO.
1647 */
1648 uint64_t address;
1649 /* Address of the aux surface, if any
1650 *
1651 * This field is 0 if and only if no aux surface exists.
1652 *
1653 * This address is relative to the start of the BO. On gen7, the bottom 12
1654 * bits of this address include extra aux information.
1655 */
1656 uint64_t aux_address;
1657 };
1658
1659 /**
1660 * Attachment state when recording a renderpass instance.
1661 *
1662 * The clear value is valid only if there exists a pending clear.
1663 */
1664 struct anv_attachment_state {
1665 enum isl_aux_usage aux_usage;
1666 enum isl_aux_usage input_aux_usage;
1667 struct anv_surface_state color;
1668 struct anv_surface_state input;
1669
1670 VkImageLayout current_layout;
1671 VkImageAspectFlags pending_clear_aspects;
1672 bool fast_clear;
1673 VkClearValue clear_value;
1674 bool clear_color_is_zero_one;
1675 bool clear_color_is_zero;
1676 };
1677
1678 /** State required while building cmd buffer */
1679 struct anv_cmd_state {
1680 /* PIPELINE_SELECT.PipelineSelection */
1681 uint32_t current_pipeline;
1682 const struct gen_l3_config * current_l3_config;
1683 uint32_t vb_dirty;
1684 anv_cmd_dirty_mask_t dirty;
1685 anv_cmd_dirty_mask_t compute_dirty;
1686 enum anv_pipe_bits pending_pipe_bits;
1687 uint32_t num_workgroups_offset;
1688 struct anv_bo *num_workgroups_bo;
1689 VkShaderStageFlags descriptors_dirty;
1690 VkShaderStageFlags push_constants_dirty;
1691 uint32_t scratch_size;
1692 struct anv_pipeline * pipeline;
1693 struct anv_pipeline * compute_pipeline;
1694 struct anv_framebuffer * framebuffer;
1695 struct anv_render_pass * pass;
1696 struct anv_subpass * subpass;
1697 VkRect2D render_area;
1698 uint32_t restart_index;
1699 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1700 struct anv_descriptor_set * descriptors[MAX_SETS];
1701 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1702 VkShaderStageFlags push_constant_stages;
1703 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1704 struct anv_state binding_tables[MESA_SHADER_STAGES];
1705 struct anv_state samplers[MESA_SHADER_STAGES];
1706 struct anv_dynamic_state dynamic;
1707 bool need_query_wa;
1708
1709 struct anv_push_descriptor_set * push_descriptors[MAX_SETS];
1710
1711 /**
1712 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1713 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1714 * and before invoking the secondary in ExecuteCommands.
1715 */
1716 bool pma_fix_enabled;
1717
1718 /**
1719 * Whether or not we know for certain that HiZ is enabled for the current
1720 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1721 * enabled or not, this will be false.
1722 */
1723 bool hiz_enabled;
1724
1725 /**
1726 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1727 * valid only when recording a render pass instance.
1728 */
1729 struct anv_attachment_state * attachments;
1730
1731 /**
1732 * Surface states for color render targets. These are stored in a single
1733 * flat array. For depth-stencil attachments, the surface state is simply
1734 * left blank.
1735 */
1736 struct anv_state render_pass_states;
1737
1738 /**
1739 * A null surface state of the right size to match the framebuffer. This
1740 * is one of the states in render_pass_states.
1741 */
1742 struct anv_state null_surface_state;
1743
1744 struct {
1745 struct anv_buffer * index_buffer;
1746 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1747 uint32_t index_offset;
1748 } gen7;
1749 };
1750
1751 struct anv_cmd_pool {
1752 VkAllocationCallbacks alloc;
1753 struct list_head cmd_buffers;
1754 };
1755
1756 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1757
1758 enum anv_cmd_buffer_exec_mode {
1759 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1760 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1761 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1762 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1763 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1764 };
1765
1766 struct anv_cmd_buffer {
1767 VK_LOADER_DATA _loader_data;
1768
1769 struct anv_device * device;
1770
1771 struct anv_cmd_pool * pool;
1772 struct list_head pool_link;
1773
1774 struct anv_batch batch;
1775
1776 /* Fields required for the actual chain of anv_batch_bo's.
1777 *
1778 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1779 */
1780 struct list_head batch_bos;
1781 enum anv_cmd_buffer_exec_mode exec_mode;
1782
1783 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1784 * referenced by this command buffer
1785 *
1786 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1787 */
1788 struct u_vector seen_bbos;
1789
1790 /* A vector of int32_t's for every block of binding tables.
1791 *
1792 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1793 */
1794 struct u_vector bt_block_states;
1795 uint32_t bt_next;
1796
1797 struct anv_reloc_list surface_relocs;
1798 /** Last seen surface state block pool center bo offset */
1799 uint32_t last_ss_pool_center;
1800
1801 /* Serial for tracking buffer completion */
1802 uint32_t serial;
1803
1804 /* Stream objects for storing temporary data */
1805 struct anv_state_stream surface_state_stream;
1806 struct anv_state_stream dynamic_state_stream;
1807
1808 VkCommandBufferUsageFlags usage_flags;
1809 VkCommandBufferLevel level;
1810
1811 struct anv_cmd_state state;
1812 };
1813
1814 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1815 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1816 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1817 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1818 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1819 struct anv_cmd_buffer *secondary);
1820 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1821 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1822 struct anv_cmd_buffer *cmd_buffer,
1823 const VkSemaphore *in_semaphores,
1824 uint32_t num_in_semaphores,
1825 const VkSemaphore *out_semaphores,
1826 uint32_t num_out_semaphores,
1827 VkFence fence);
1828
1829 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1830
1831 VkResult
1832 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1833 gl_shader_stage stage, uint32_t size);
1834 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1835 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1836 (offsetof(struct anv_push_constants, field) + \
1837 sizeof(cmd_buffer->state.push_constants[0]->field)))
1838
1839 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1840 const void *data, uint32_t size, uint32_t alignment);
1841 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1842 uint32_t *a, uint32_t *b,
1843 uint32_t dwords, uint32_t alignment);
1844
1845 struct anv_address
1846 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1847 struct anv_state
1848 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1849 uint32_t entries, uint32_t *state_offset);
1850 struct anv_state
1851 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1852 struct anv_state
1853 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1854 uint32_t size, uint32_t alignment);
1855
1856 VkResult
1857 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1858
1859 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1860 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1861 bool depth_clamp_enable);
1862 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1863
1864 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1865 struct anv_render_pass *pass,
1866 struct anv_framebuffer *framebuffer,
1867 const VkClearValue *clear_values);
1868
1869 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1870
1871 struct anv_state
1872 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1873 gl_shader_stage stage);
1874 struct anv_state
1875 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1876
1877 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1878 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1879
1880 const struct anv_image_view *
1881 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1882
1883 VkResult
1884 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1885 uint32_t num_entries,
1886 uint32_t *state_offset,
1887 struct anv_state *bt_state);
1888
1889 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1890
1891 enum anv_fence_type {
1892 ANV_FENCE_TYPE_NONE = 0,
1893 ANV_FENCE_TYPE_BO,
1894 ANV_FENCE_TYPE_SYNCOBJ,
1895 };
1896
1897 enum anv_bo_fence_state {
1898 /** Indicates that this is a new (or newly reset fence) */
1899 ANV_BO_FENCE_STATE_RESET,
1900
1901 /** Indicates that this fence has been submitted to the GPU but is still
1902 * (as far as we know) in use by the GPU.
1903 */
1904 ANV_BO_FENCE_STATE_SUBMITTED,
1905
1906 ANV_BO_FENCE_STATE_SIGNALED,
1907 };
1908
1909 struct anv_fence_impl {
1910 enum anv_fence_type type;
1911
1912 union {
1913 /** Fence implementation for BO fences
1914 *
1915 * These fences use a BO and a set of CPU-tracked state flags. The BO
1916 * is added to the object list of the last execbuf call in a QueueSubmit
1917 * and is marked EXEC_WRITE. The state flags track when the BO has been
1918 * submitted to the kernel. We need to do this because Vulkan lets you
1919 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1920 * will say it's idle in this case.
1921 */
1922 struct {
1923 struct anv_bo bo;
1924 enum anv_bo_fence_state state;
1925 } bo;
1926
1927 /** DRM syncobj handle for syncobj-based fences */
1928 uint32_t syncobj;
1929 };
1930 };
1931
1932 struct anv_fence {
1933 /* Permanent fence state. Every fence has some form of permanent state
1934 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
1935 * cross-process fences) or it could just be a dummy for use internally.
1936 */
1937 struct anv_fence_impl permanent;
1938
1939 /* Temporary fence state. A fence *may* have temporary state. That state
1940 * is added to the fence by an import operation and is reset back to
1941 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
1942 * state cannot be signaled because the fence must already be signaled
1943 * before the temporary state can be exported from the fence in the other
1944 * process and imported here.
1945 */
1946 struct anv_fence_impl temporary;
1947 };
1948
1949 struct anv_event {
1950 uint64_t semaphore;
1951 struct anv_state state;
1952 };
1953
1954 enum anv_semaphore_type {
1955 ANV_SEMAPHORE_TYPE_NONE = 0,
1956 ANV_SEMAPHORE_TYPE_DUMMY,
1957 ANV_SEMAPHORE_TYPE_BO,
1958 ANV_SEMAPHORE_TYPE_SYNC_FILE,
1959 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
1960 };
1961
1962 struct anv_semaphore_impl {
1963 enum anv_semaphore_type type;
1964
1965 union {
1966 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1967 * This BO will be added to the object list on any execbuf2 calls for
1968 * which this semaphore is used as a wait or signal fence. When used as
1969 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1970 */
1971 struct anv_bo *bo;
1972
1973 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
1974 * If the semaphore is in the unsignaled state due to either just being
1975 * created or because it has been used for a wait, fd will be -1.
1976 */
1977 int fd;
1978
1979 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
1980 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
1981 * import so we don't need to bother with a userspace cache.
1982 */
1983 uint32_t syncobj;
1984 };
1985 };
1986
1987 struct anv_semaphore {
1988 /* Permanent semaphore state. Every semaphore has some form of permanent
1989 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1990 * (for cross-process semaphores0 or it could just be a dummy for use
1991 * internally.
1992 */
1993 struct anv_semaphore_impl permanent;
1994
1995 /* Temporary semaphore state. A semaphore *may* have temporary state.
1996 * That state is added to the semaphore by an import operation and is reset
1997 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1998 * semaphore with temporary state cannot be signaled because the semaphore
1999 * must already be signaled before the temporary state can be exported from
2000 * the semaphore in the other process and imported here.
2001 */
2002 struct anv_semaphore_impl temporary;
2003 };
2004
2005 void anv_semaphore_reset_temporary(struct anv_device *device,
2006 struct anv_semaphore *semaphore);
2007
2008 struct anv_shader_module {
2009 unsigned char sha1[20];
2010 uint32_t size;
2011 char data[0];
2012 };
2013
2014 static inline gl_shader_stage
2015 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2016 {
2017 assert(__builtin_popcount(vk_stage) == 1);
2018 return ffs(vk_stage) - 1;
2019 }
2020
2021 static inline VkShaderStageFlagBits
2022 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2023 {
2024 return (1 << mesa_stage);
2025 }
2026
2027 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2028
2029 #define anv_foreach_stage(stage, stage_bits) \
2030 for (gl_shader_stage stage, \
2031 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2032 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2033 __tmp &= ~(1 << (stage)))
2034
2035 struct anv_pipeline_bind_map {
2036 uint32_t surface_count;
2037 uint32_t sampler_count;
2038 uint32_t image_count;
2039
2040 struct anv_pipeline_binding * surface_to_descriptor;
2041 struct anv_pipeline_binding * sampler_to_descriptor;
2042 };
2043
2044 struct anv_shader_bin_key {
2045 uint32_t size;
2046 uint8_t data[0];
2047 };
2048
2049 struct anv_shader_bin {
2050 uint32_t ref_cnt;
2051
2052 const struct anv_shader_bin_key *key;
2053
2054 struct anv_state kernel;
2055 uint32_t kernel_size;
2056
2057 const struct brw_stage_prog_data *prog_data;
2058 uint32_t prog_data_size;
2059
2060 struct anv_pipeline_bind_map bind_map;
2061 };
2062
2063 struct anv_shader_bin *
2064 anv_shader_bin_create(struct anv_device *device,
2065 const void *key, uint32_t key_size,
2066 const void *kernel, uint32_t kernel_size,
2067 const struct brw_stage_prog_data *prog_data,
2068 uint32_t prog_data_size, const void *prog_data_param,
2069 const struct anv_pipeline_bind_map *bind_map);
2070
2071 void
2072 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2073
2074 static inline void
2075 anv_shader_bin_ref(struct anv_shader_bin *shader)
2076 {
2077 assert(shader && shader->ref_cnt >= 1);
2078 p_atomic_inc(&shader->ref_cnt);
2079 }
2080
2081 static inline void
2082 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2083 {
2084 assert(shader && shader->ref_cnt >= 1);
2085 if (p_atomic_dec_zero(&shader->ref_cnt))
2086 anv_shader_bin_destroy(device, shader);
2087 }
2088
2089 struct anv_pipeline {
2090 struct anv_device * device;
2091 struct anv_batch batch;
2092 uint32_t batch_data[512];
2093 struct anv_reloc_list batch_relocs;
2094 uint32_t dynamic_state_mask;
2095 struct anv_dynamic_state dynamic_state;
2096
2097 struct anv_subpass * subpass;
2098 struct anv_pipeline_layout * layout;
2099
2100 bool needs_data_cache;
2101
2102 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2103
2104 struct {
2105 const struct gen_l3_config * l3_config;
2106 uint32_t total_size;
2107 } urb;
2108
2109 VkShaderStageFlags active_stages;
2110 struct anv_state blend_state;
2111
2112 uint32_t vb_used;
2113 uint32_t binding_stride[MAX_VBS];
2114 bool instancing_enable[MAX_VBS];
2115 bool primitive_restart;
2116 uint32_t topology;
2117
2118 uint32_t cs_right_mask;
2119
2120 bool writes_depth;
2121 bool depth_test_enable;
2122 bool writes_stencil;
2123 bool stencil_test_enable;
2124 bool depth_clamp_enable;
2125 bool sample_shading_enable;
2126 bool kill_pixel;
2127
2128 struct {
2129 uint32_t sf[7];
2130 uint32_t depth_stencil_state[3];
2131 } gen7;
2132
2133 struct {
2134 uint32_t sf[4];
2135 uint32_t raster[5];
2136 uint32_t wm_depth_stencil[3];
2137 } gen8;
2138
2139 struct {
2140 uint32_t wm_depth_stencil[4];
2141 } gen9;
2142
2143 uint32_t interface_descriptor_data[8];
2144 };
2145
2146 static inline bool
2147 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2148 gl_shader_stage stage)
2149 {
2150 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2151 }
2152
2153 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2154 static inline const struct brw_##prefix##_prog_data * \
2155 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2156 { \
2157 if (anv_pipeline_has_stage(pipeline, stage)) { \
2158 return (const struct brw_##prefix##_prog_data *) \
2159 pipeline->shaders[stage]->prog_data; \
2160 } else { \
2161 return NULL; \
2162 } \
2163 }
2164
2165 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2166 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2167 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2168 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2169 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2170 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2171
2172 static inline const struct brw_vue_prog_data *
2173 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2174 {
2175 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2176 return &get_gs_prog_data(pipeline)->base;
2177 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2178 return &get_tes_prog_data(pipeline)->base;
2179 else
2180 return &get_vs_prog_data(pipeline)->base;
2181 }
2182
2183 VkResult
2184 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2185 struct anv_pipeline_cache *cache,
2186 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2187 const VkAllocationCallbacks *alloc);
2188
2189 VkResult
2190 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2191 struct anv_pipeline_cache *cache,
2192 const VkComputePipelineCreateInfo *info,
2193 struct anv_shader_module *module,
2194 const char *entrypoint,
2195 const VkSpecializationInfo *spec_info);
2196
2197 struct anv_format_plane {
2198 enum isl_format isl_format:16;
2199 struct isl_swizzle swizzle;
2200
2201 /* Whether this plane contains chroma channels */
2202 bool has_chroma;
2203
2204 /* For downscaling of YUV planes */
2205 uint8_t denominator_scales[2];
2206
2207 /* How to map sampled ycbcr planes to a single 4 component element. */
2208 struct isl_swizzle ycbcr_swizzle;
2209 };
2210
2211
2212 struct anv_format {
2213 struct anv_format_plane planes[3];
2214 uint8_t n_planes;
2215 bool can_ycbcr;
2216 };
2217
2218 static inline uint32_t
2219 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2220 VkImageAspectFlags aspect_mask)
2221 {
2222 switch (aspect_mask) {
2223 case VK_IMAGE_ASPECT_COLOR_BIT:
2224 case VK_IMAGE_ASPECT_DEPTH_BIT:
2225 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
2226 return 0;
2227 case VK_IMAGE_ASPECT_STENCIL_BIT:
2228 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2229 return 0;
2230 /* Fall-through */
2231 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
2232 return 1;
2233 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
2234 return 2;
2235 default:
2236 /* Purposefully assert with depth/stencil aspects. */
2237 unreachable("invalid image aspect");
2238 }
2239 }
2240
2241 static inline uint32_t
2242 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2243 {
2244 uint32_t planes = 0;
2245
2246 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2247 VK_IMAGE_ASPECT_DEPTH_BIT |
2248 VK_IMAGE_ASPECT_STENCIL_BIT |
2249 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR))
2250 planes++;
2251 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT_KHR)
2252 planes++;
2253 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
2254 planes++;
2255
2256 return planes;
2257 }
2258
2259 static inline VkImageAspectFlags
2260 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2261 uint32_t plane)
2262 {
2263 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2264 if (_mesa_bitcount(image_aspects) > 1)
2265 return VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << plane;
2266 return VK_IMAGE_ASPECT_COLOR_BIT;
2267 }
2268 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2269 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2270 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2271 return VK_IMAGE_ASPECT_STENCIL_BIT;
2272 }
2273
2274 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2275 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2276
2277 const struct anv_format *
2278 anv_get_format(VkFormat format);
2279
2280 static inline uint32_t
2281 anv_get_format_planes(VkFormat vk_format)
2282 {
2283 const struct anv_format *format = anv_get_format(vk_format);
2284
2285 return format != NULL ? format->n_planes : 0;
2286 }
2287
2288 struct anv_format_plane
2289 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2290 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2291
2292 static inline enum isl_format
2293 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2294 VkImageAspectFlags aspect, VkImageTiling tiling)
2295 {
2296 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2297 }
2298
2299 static inline struct isl_swizzle
2300 anv_swizzle_for_render(struct isl_swizzle swizzle)
2301 {
2302 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2303 * RGB as RGBA for texturing
2304 */
2305 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2306 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2307
2308 /* But it doesn't matter what we render to that channel */
2309 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2310
2311 return swizzle;
2312 }
2313
2314 void
2315 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2316
2317 /**
2318 * Subsurface of an anv_image.
2319 */
2320 struct anv_surface {
2321 /** Valid only if isl_surf::size > 0. */
2322 struct isl_surf isl;
2323
2324 /**
2325 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2326 */
2327 uint32_t offset;
2328 };
2329
2330 struct anv_image {
2331 VkImageType type;
2332 /* The original VkFormat provided by the client. This may not match any
2333 * of the actual surface formats.
2334 */
2335 VkFormat vk_format;
2336 const struct anv_format *format;
2337
2338 VkImageAspectFlags aspects;
2339 VkExtent3D extent;
2340 uint32_t levels;
2341 uint32_t array_size;
2342 uint32_t samples; /**< VkImageCreateInfo::samples */
2343 uint32_t n_planes;
2344 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2345 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2346
2347 VkDeviceSize size;
2348 uint32_t alignment;
2349
2350 /* Whether the image is made of several underlying buffer objects rather a
2351 * single one with different offsets.
2352 */
2353 bool disjoint;
2354
2355 /**
2356 * Image subsurfaces
2357 *
2358 * For each foo, anv_image::planes[x].surface is valid if and only if
2359 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2360 * to figure the number associated with a given aspect.
2361 *
2362 * The hardware requires that the depth buffer and stencil buffer be
2363 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2364 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2365 * allocate the depth and stencil buffers as separate surfaces in the same
2366 * bo.
2367 *
2368 * Memory layout :
2369 *
2370 * -----------------------
2371 * | surface0 | /|\
2372 * ----------------------- |
2373 * | shadow surface0 | |
2374 * ----------------------- | Plane 0
2375 * | aux surface0 | |
2376 * ----------------------- |
2377 * | fast clear colors0 | \|/
2378 * -----------------------
2379 * | surface1 | /|\
2380 * ----------------------- |
2381 * | shadow surface1 | |
2382 * ----------------------- | Plane 1
2383 * | aux surface1 | |
2384 * ----------------------- |
2385 * | fast clear colors1 | \|/
2386 * -----------------------
2387 * | ... |
2388 * | |
2389 * -----------------------
2390 */
2391 struct {
2392 /**
2393 * Offset of the entire plane (whenever the image is disjoint this is
2394 * set to 0).
2395 */
2396 uint32_t offset;
2397
2398 VkDeviceSize size;
2399 uint32_t alignment;
2400
2401 struct anv_surface surface;
2402
2403 /**
2404 * A surface which shadows the main surface and may have different
2405 * tiling. This is used for sampling using a tiling that isn't supported
2406 * for other operations.
2407 */
2408 struct anv_surface shadow_surface;
2409
2410 /**
2411 * For color images, this is the aux usage for this image when not used
2412 * as a color attachment.
2413 *
2414 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2415 * image has a HiZ buffer.
2416 */
2417 enum isl_aux_usage aux_usage;
2418
2419 struct anv_surface aux_surface;
2420
2421 /**
2422 * Offset of the fast clear state (used to compute the
2423 * fast_clear_state_offset of the following planes).
2424 */
2425 uint32_t fast_clear_state_offset;
2426
2427 /**
2428 * BO associated with this plane, set when bound.
2429 */
2430 struct anv_bo *bo;
2431 VkDeviceSize bo_offset;
2432
2433 /**
2434 * When destroying the image, also free the bo.
2435 * */
2436 bool bo_is_owned;
2437 } planes[3];
2438 };
2439
2440 /* Returns the number of auxiliary buffer levels attached to an image. */
2441 static inline uint8_t
2442 anv_image_aux_levels(const struct anv_image * const image,
2443 VkImageAspectFlagBits aspect)
2444 {
2445 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2446 return image->planes[plane].aux_surface.isl.size > 0 ?
2447 image->planes[plane].aux_surface.isl.levels : 0;
2448 }
2449
2450 /* Returns the number of auxiliary buffer layers attached to an image. */
2451 static inline uint32_t
2452 anv_image_aux_layers(const struct anv_image * const image,
2453 VkImageAspectFlagBits aspect,
2454 const uint8_t miplevel)
2455 {
2456 assert(image);
2457
2458 /* The miplevel must exist in the main buffer. */
2459 assert(miplevel < image->levels);
2460
2461 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2462 /* There are no layers with auxiliary data because the miplevel has no
2463 * auxiliary data.
2464 */
2465 return 0;
2466 } else {
2467 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2468 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2469 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2470 }
2471 }
2472
2473 static inline unsigned
2474 anv_fast_clear_state_entry_size(const struct anv_device *device)
2475 {
2476 assert(device);
2477 /* Entry contents:
2478 * +--------------------------------------------+
2479 * | clear value dword(s) | needs resolve dword |
2480 * +--------------------------------------------+
2481 */
2482
2483 /* Ensure that the needs resolve dword is in fact dword-aligned to enable
2484 * GPU memcpy operations.
2485 */
2486 assert(device->isl_dev.ss.clear_value_size % 4 == 0);
2487 return device->isl_dev.ss.clear_value_size + 4;
2488 }
2489
2490 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2491 static inline bool
2492 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2493 const struct anv_image *image)
2494 {
2495 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2496 return false;
2497
2498 if (devinfo->gen < 8)
2499 return false;
2500
2501 return image->samples == 1;
2502 }
2503
2504 void
2505 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
2506 const struct anv_image *image,
2507 enum blorp_hiz_op op);
2508 void
2509 anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
2510 const struct anv_state surface_state,
2511 const struct anv_image * const image,
2512 VkImageAspectFlagBits aspect,
2513 const uint8_t level, const uint32_t layer_count,
2514 const enum blorp_fast_clear_op op);
2515
2516 void
2517 anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
2518 const struct anv_image *image,
2519 VkImageAspectFlagBits aspect,
2520 const uint32_t base_level, const uint32_t level_count,
2521 const uint32_t base_layer, uint32_t layer_count);
2522
2523 void
2524 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2525 const struct anv_image *image,
2526 uint32_t base_level, uint32_t level_count,
2527 uint32_t base_layer, uint32_t layer_count);
2528
2529 enum isl_aux_usage
2530 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2531 const struct anv_image *image,
2532 const VkImageAspectFlagBits aspect,
2533 const VkImageLayout layout);
2534
2535 /* This is defined as a macro so that it works for both
2536 * VkImageSubresourceRange and VkImageSubresourceLayers
2537 */
2538 #define anv_get_layerCount(_image, _range) \
2539 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2540 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2541
2542 static inline uint32_t
2543 anv_get_levelCount(const struct anv_image *image,
2544 const VkImageSubresourceRange *range)
2545 {
2546 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2547 image->levels - range->baseMipLevel : range->levelCount;
2548 }
2549
2550 static inline VkImageAspectFlags
2551 anv_image_expand_aspects(const struct anv_image *image,
2552 VkImageAspectFlags aspects)
2553 {
2554 /* If the underlying image has color plane aspects and
2555 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2556 * the underlying image. */
2557 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
2558 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2559 return image->aspects;
2560
2561 return aspects;
2562 }
2563
2564 static inline bool
2565 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2566 VkImageAspectFlags aspects2)
2567 {
2568 if (aspects1 == aspects2)
2569 return true;
2570
2571 /* Only 1 color aspects are compatibles. */
2572 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2573 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2574 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2575 return true;
2576
2577 return false;
2578 }
2579
2580 struct anv_image_view {
2581 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2582
2583 VkImageAspectFlags aspect_mask;
2584 VkFormat vk_format;
2585 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2586
2587 unsigned n_planes;
2588 struct {
2589 uint32_t image_plane;
2590
2591 struct isl_view isl;
2592
2593 /**
2594 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2595 * image layout of SHADER_READ_ONLY_OPTIMAL or
2596 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2597 */
2598 struct anv_surface_state optimal_sampler_surface_state;
2599
2600 /**
2601 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2602 * image layout of GENERAL.
2603 */
2604 struct anv_surface_state general_sampler_surface_state;
2605
2606 /**
2607 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2608 * states for write-only and readable, using the real format for
2609 * write-only and the lowered format for readable.
2610 */
2611 struct anv_surface_state storage_surface_state;
2612 struct anv_surface_state writeonly_storage_surface_state;
2613
2614 struct brw_image_param storage_image_param;
2615 } planes[3];
2616 };
2617
2618 enum anv_image_view_state_flags {
2619 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2620 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2621 };
2622
2623 void anv_image_fill_surface_state(struct anv_device *device,
2624 const struct anv_image *image,
2625 VkImageAspectFlagBits aspect,
2626 const struct isl_view *view,
2627 isl_surf_usage_flags_t view_usage,
2628 enum isl_aux_usage aux_usage,
2629 const union isl_color_value *clear_color,
2630 enum anv_image_view_state_flags flags,
2631 struct anv_surface_state *state_inout,
2632 struct brw_image_param *image_param_out);
2633
2634 struct anv_image_create_info {
2635 const VkImageCreateInfo *vk_info;
2636
2637 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2638 isl_tiling_flags_t isl_tiling_flags;
2639
2640 /** These flags will be added to any derived from VkImageCreateInfo. */
2641 isl_surf_usage_flags_t isl_extra_usage_flags;
2642
2643 uint32_t stride;
2644 };
2645
2646 VkResult anv_image_create(VkDevice _device,
2647 const struct anv_image_create_info *info,
2648 const VkAllocationCallbacks* alloc,
2649 VkImage *pImage);
2650
2651 #ifdef ANDROID
2652 VkResult anv_image_from_gralloc(VkDevice device_h,
2653 const VkImageCreateInfo *base_info,
2654 const VkNativeBufferANDROID *gralloc_info,
2655 const VkAllocationCallbacks *alloc,
2656 VkImage *pImage);
2657 #endif
2658
2659 const struct anv_surface *
2660 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2661 VkImageAspectFlags aspect_mask);
2662
2663 enum isl_format
2664 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2665
2666 static inline struct VkExtent3D
2667 anv_sanitize_image_extent(const VkImageType imageType,
2668 const struct VkExtent3D imageExtent)
2669 {
2670 switch (imageType) {
2671 case VK_IMAGE_TYPE_1D:
2672 return (VkExtent3D) { imageExtent.width, 1, 1 };
2673 case VK_IMAGE_TYPE_2D:
2674 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2675 case VK_IMAGE_TYPE_3D:
2676 return imageExtent;
2677 default:
2678 unreachable("invalid image type");
2679 }
2680 }
2681
2682 static inline struct VkOffset3D
2683 anv_sanitize_image_offset(const VkImageType imageType,
2684 const struct VkOffset3D imageOffset)
2685 {
2686 switch (imageType) {
2687 case VK_IMAGE_TYPE_1D:
2688 return (VkOffset3D) { imageOffset.x, 0, 0 };
2689 case VK_IMAGE_TYPE_2D:
2690 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2691 case VK_IMAGE_TYPE_3D:
2692 return imageOffset;
2693 default:
2694 unreachable("invalid image type");
2695 }
2696 }
2697
2698
2699 void anv_fill_buffer_surface_state(struct anv_device *device,
2700 struct anv_state state,
2701 enum isl_format format,
2702 uint32_t offset, uint32_t range,
2703 uint32_t stride);
2704
2705
2706 struct anv_ycbcr_conversion {
2707 const struct anv_format * format;
2708 VkSamplerYcbcrModelConversionKHR ycbcr_model;
2709 VkSamplerYcbcrRangeKHR ycbcr_range;
2710 VkComponentSwizzle mapping[4];
2711 VkChromaLocationKHR chroma_offsets[2];
2712 VkFilter chroma_filter;
2713 bool chroma_reconstruction;
2714 };
2715
2716 struct anv_sampler {
2717 uint32_t state[3][4];
2718 uint32_t n_planes;
2719 struct anv_ycbcr_conversion *conversion;
2720 };
2721
2722 struct anv_framebuffer {
2723 uint32_t width;
2724 uint32_t height;
2725 uint32_t layers;
2726
2727 uint32_t attachment_count;
2728 struct anv_image_view * attachments[0];
2729 };
2730
2731 struct anv_subpass {
2732 uint32_t attachment_count;
2733
2734 /**
2735 * A pointer to all attachment references used in this subpass.
2736 * Only valid if ::attachment_count > 0.
2737 */
2738 VkAttachmentReference * attachments;
2739 uint32_t input_count;
2740 VkAttachmentReference * input_attachments;
2741 uint32_t color_count;
2742 VkAttachmentReference * color_attachments;
2743 VkAttachmentReference * resolve_attachments;
2744
2745 VkAttachmentReference depth_stencil_attachment;
2746
2747 uint32_t view_mask;
2748
2749 /** Subpass has a depth/stencil self-dependency */
2750 bool has_ds_self_dep;
2751
2752 /** Subpass has at least one resolve attachment */
2753 bool has_resolve;
2754 };
2755
2756 static inline unsigned
2757 anv_subpass_view_count(const struct anv_subpass *subpass)
2758 {
2759 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2760 }
2761
2762 struct anv_render_pass_attachment {
2763 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2764 * its members individually.
2765 */
2766 VkFormat format;
2767 uint32_t samples;
2768 VkImageUsageFlags usage;
2769 VkAttachmentLoadOp load_op;
2770 VkAttachmentStoreOp store_op;
2771 VkAttachmentLoadOp stencil_load_op;
2772 VkImageLayout initial_layout;
2773 VkImageLayout final_layout;
2774 VkImageLayout first_subpass_layout;
2775
2776 /* The subpass id in which the attachment will be used last. */
2777 uint32_t last_subpass_idx;
2778 };
2779
2780 struct anv_render_pass {
2781 uint32_t attachment_count;
2782 uint32_t subpass_count;
2783 /* An array of subpass_count+1 flushes, one per subpass boundary */
2784 enum anv_pipe_bits * subpass_flushes;
2785 struct anv_render_pass_attachment * attachments;
2786 struct anv_subpass subpasses[0];
2787 };
2788
2789 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2790
2791 struct anv_query_pool {
2792 VkQueryType type;
2793 VkQueryPipelineStatisticFlags pipeline_statistics;
2794 /** Stride between slots, in bytes */
2795 uint32_t stride;
2796 /** Number of slots in this query pool */
2797 uint32_t slots;
2798 struct anv_bo bo;
2799 };
2800
2801 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2802 const char *name);
2803
2804 void anv_dump_image_to_ppm(struct anv_device *device,
2805 struct anv_image *image, unsigned miplevel,
2806 unsigned array_layer, VkImageAspectFlagBits aspect,
2807 const char *filename);
2808
2809 enum anv_dump_action {
2810 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2811 };
2812
2813 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2814 void anv_dump_finish(void);
2815
2816 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2817 struct anv_framebuffer *fb);
2818
2819 static inline uint32_t
2820 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2821 {
2822 /* This function must be called from within a subpass. */
2823 assert(cmd_state->pass && cmd_state->subpass);
2824
2825 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
2826
2827 /* The id of this subpass shouldn't exceed the number of subpasses in this
2828 * render pass minus 1.
2829 */
2830 assert(subpass_id < cmd_state->pass->subpass_count);
2831 return subpass_id;
2832 }
2833
2834 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2835 \
2836 static inline struct __anv_type * \
2837 __anv_type ## _from_handle(__VkType _handle) \
2838 { \
2839 return (struct __anv_type *) _handle; \
2840 } \
2841 \
2842 static inline __VkType \
2843 __anv_type ## _to_handle(struct __anv_type *_obj) \
2844 { \
2845 return (__VkType) _obj; \
2846 }
2847
2848 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2849 \
2850 static inline struct __anv_type * \
2851 __anv_type ## _from_handle(__VkType _handle) \
2852 { \
2853 return (struct __anv_type *)(uintptr_t) _handle; \
2854 } \
2855 \
2856 static inline __VkType \
2857 __anv_type ## _to_handle(struct __anv_type *_obj) \
2858 { \
2859 return (__VkType)(uintptr_t) _obj; \
2860 }
2861
2862 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2863 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2864
2865 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
2866 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
2867 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
2868 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
2869 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
2870
2871 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
2872 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
2873 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
2874 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
2875 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
2876 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
2877 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
2878 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
2879 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
2880 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
2881 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
2882 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
2883 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
2884 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
2885 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
2886 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
2887 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
2888 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
2889 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
2890 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
2891 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
2892 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_debug_report_callback, VkDebugReportCallbackEXT)
2893 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversionKHR)
2894
2895 /* Gen-specific function declarations */
2896 #ifdef genX
2897 # include "anv_genX.h"
2898 #else
2899 # define genX(x) gen7_##x
2900 # include "anv_genX.h"
2901 # undef genX
2902 # define genX(x) gen75_##x
2903 # include "anv_genX.h"
2904 # undef genX
2905 # define genX(x) gen8_##x
2906 # include "anv_genX.h"
2907 # undef genX
2908 # define genX(x) gen9_##x
2909 # include "anv_genX.h"
2910 # undef genX
2911 # define genX(x) gen10_##x
2912 # include "anv_genX.h"
2913 # undef genX
2914 #endif
2915
2916 #endif /* ANV_PRIVATE_H */