2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/bitset.h"
53 #include "util/macros.h"
54 #include "util/hash_table.h"
55 #include "util/list.h"
56 #include "util/sparse_array.h"
57 #include "util/u_atomic.h"
58 #include "util/u_vector.h"
59 #include "util/u_math.h"
61 #include "util/xmlconfig.h"
63 #include "vk_debug_report.h"
65 /* Pre-declarations needed for WSI entrypoints */
68 typedef struct xcb_connection_t xcb_connection_t
;
69 typedef uint32_t xcb_visualid_t
;
70 typedef uint32_t xcb_window_t
;
74 struct anv_buffer_view
;
75 struct anv_image_view
;
78 struct gen_aux_map_context
;
80 struct gen_perf_config
;
82 #include <vulkan/vulkan.h>
83 #include <vulkan/vulkan_intel.h>
84 #include <vulkan/vk_icd.h>
86 #include "anv_android.h"
87 #include "anv_entrypoints.h"
88 #include "anv_extensions.h"
91 #include "dev/gen_debug.h"
92 #include "common/intel_log.h"
93 #include "wsi_common.h"
95 #define NSEC_PER_SEC 1000000000ull
97 /* anv Virtual Memory Layout
98 * =========================
100 * When the anv driver is determining the virtual graphics addresses of memory
101 * objects itself using the softpin mechanism, the following memory ranges
104 * Three special considerations to notice:
106 * (1) the dynamic state pool is located within the same 4 GiB as the low
107 * heap. This is to work around a VF cache issue described in a comment in
108 * anv_physical_device_init_heaps.
110 * (2) the binding table pool is located at lower addresses than the surface
111 * state pool, within a 4 GiB range. This allows surface state base addresses
112 * to cover both binding tables (16 bit offsets) and surface states (32 bit
115 * (3) the last 4 GiB of the address space is withheld from the high
116 * heap. Various hardware units will read past the end of an object for
117 * various reasons. This healthy margin prevents reads from wrapping around
120 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
121 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
122 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
123 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
124 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
125 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
126 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
127 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
128 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
129 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
130 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
132 #define LOW_HEAP_SIZE \
133 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
134 #define DYNAMIC_STATE_POOL_SIZE \
135 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
136 #define BINDING_TABLE_POOL_SIZE \
137 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
138 #define SURFACE_STATE_POOL_SIZE \
139 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
140 #define INSTRUCTION_STATE_POOL_SIZE \
141 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
143 /* Allowing different clear colors requires us to perform a depth resolve at
144 * the end of certain render passes. This is because while slow clears store
145 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
146 * See the PRMs for examples describing when additional resolves would be
147 * necessary. To enable fast clears without requiring extra resolves, we set
148 * the clear value to a globally-defined one. We could allow different values
149 * if the user doesn't expect coherent data during or after a render passes
150 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
151 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
152 * 1.0f seems to be the only value used. The only application that doesn't set
153 * this value does so through the usage of an seemingly uninitialized clear
156 #define ANV_HZ_FC_VAL 1.0f
159 #define MAX_XFB_BUFFERS 4
160 #define MAX_XFB_STREAMS 4
163 #define MAX_VIEWPORTS 16
164 #define MAX_SCISSORS 16
165 #define MAX_PUSH_CONSTANTS_SIZE 128
166 #define MAX_DYNAMIC_BUFFERS 16
167 #define MAX_IMAGES 64
168 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
169 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
170 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
172 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
174 * "The surface state model is used when a Binding Table Index (specified
175 * in the message descriptor) of less than 240 is specified. In this model,
176 * the Binding Table Index is used to index into the binding table, and the
177 * binding table entry contains a pointer to the SURFACE_STATE."
179 * Binding table values above 240 are used for various things in the hardware
180 * such as stateless, stateless with incoherent cache, SLM, and bindless.
182 #define MAX_BINDING_TABLE_SIZE 240
184 /* The kernel relocation API has a limitation of a 32-bit delta value
185 * applied to the address before it is written which, in spite of it being
186 * unsigned, is treated as signed . Because of the way that this maps to
187 * the Vulkan API, we cannot handle an offset into a buffer that does not
188 * fit into a signed 32 bits. The only mechanism we have for dealing with
189 * this at the moment is to limit all VkDeviceMemory objects to a maximum
190 * of 2GB each. The Vulkan spec allows us to do this:
192 * "Some platforms may have a limit on the maximum size of a single
193 * allocation. For example, certain systems may fail to create
194 * allocations with a size greater than or equal to 4GB. Such a limit is
195 * implementation-dependent, and if such a failure occurs then the error
196 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
198 * We don't use vk_error here because it's not an error so much as an
199 * indication to the application that the allocation is too large.
201 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
203 #define ANV_SVGS_VB_INDEX MAX_VBS
204 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
206 /* We reserve this MI ALU register for the purpose of handling predication.
207 * Other code which uses the MI ALU should leave it alone.
209 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
211 /* For gen12 we set the streamout buffers using 4 separate commands
212 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
213 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
214 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
215 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
216 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
217 * 3DSTATE_SO_BUFFER_INDEX_0.
219 #define SO_BUFFER_INDEX_0_CMD 0x60
220 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
222 static inline uint32_t
223 align_down_npot_u32(uint32_t v
, uint32_t a
)
228 static inline uint32_t
229 align_u32(uint32_t v
, uint32_t a
)
231 assert(a
!= 0 && a
== (a
& -a
));
232 return (v
+ a
- 1) & ~(a
- 1);
235 static inline uint64_t
236 align_u64(uint64_t v
, uint64_t a
)
238 assert(a
!= 0 && a
== (a
& -a
));
239 return (v
+ a
- 1) & ~(a
- 1);
242 static inline int32_t
243 align_i32(int32_t v
, int32_t a
)
245 assert(a
!= 0 && a
== (a
& -a
));
246 return (v
+ a
- 1) & ~(a
- 1);
249 /** Alignment must be a power of 2. */
251 anv_is_aligned(uintmax_t n
, uintmax_t a
)
253 assert(a
== (a
& -a
));
254 return (n
& (a
- 1)) == 0;
257 static inline uint32_t
258 anv_minify(uint32_t n
, uint32_t levels
)
260 if (unlikely(n
== 0))
263 return MAX2(n
>> levels
, 1);
267 anv_clamp_f(float f
, float min
, float max
)
280 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
282 if (*inout_mask
& clear_mask
) {
283 *inout_mask
&= ~clear_mask
;
290 static inline union isl_color_value
291 vk_to_isl_color(VkClearColorValue color
)
293 return (union isl_color_value
) {
303 #define for_each_bit(b, dword) \
304 for (uint32_t __dword = (dword); \
305 (b) = __builtin_ffs(__dword) - 1, __dword; \
306 __dword &= ~(1 << (b)))
308 #define typed_memcpy(dest, src, count) ({ \
309 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
310 memcpy((dest), (src), (count) * sizeof(*(src))); \
313 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
314 * to be added here in order to utilize mapping in debug/error/perf macros.
316 #define REPORT_OBJECT_TYPE(o) \
317 __builtin_choose_expr ( \
318 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
319 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
320 __builtin_choose_expr ( \
321 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
322 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
323 __builtin_choose_expr ( \
324 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
325 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
326 __builtin_choose_expr ( \
327 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
328 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
329 __builtin_choose_expr ( \
330 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
331 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
332 __builtin_choose_expr ( \
333 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
334 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
335 __builtin_choose_expr ( \
336 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
337 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
338 __builtin_choose_expr ( \
339 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
340 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
407 __builtin_choose_expr ( \
408 __builtin_types_compatible_p (__typeof (o), void*), \
409 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
410 /* The void expression results in a compile-time error \
411 when assigning the result to something. */ \
412 (void)0)))))))))))))))))))))))))))))))
414 /* Whenever we generate an error, pass it through this function. Useful for
415 * debugging, where we can break on it. Only call at error site, not when
416 * propagating errors. Might be useful to plug in a stack trace here.
419 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
420 VkDebugReportObjectTypeEXT type
, VkResult error
,
421 const char *file
, int line
, const char *format
,
424 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
425 VkDebugReportObjectTypeEXT type
, VkResult error
,
426 const char *file
, int line
, const char *format
, ...)
427 anv_printflike(7, 8);
430 #define vk_error(error) __vk_errorf(NULL, NULL,\
431 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
432 error, __FILE__, __LINE__, NULL)
433 #define vk_errorv(instance, obj, error, format, args)\
434 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
435 __FILE__, __LINE__, format, args)
436 #define vk_errorf(instance, obj, error, format, ...)\
437 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
438 __FILE__, __LINE__, format, ## __VA_ARGS__)
440 #define vk_error(error) error
441 #define vk_errorf(instance, obj, error, format, ...) error
445 * Warn on ignored extension structs.
447 * The Vulkan spec requires us to ignore unsupported or unknown structs in
448 * a pNext chain. In debug mode, emitting warnings for ignored structs may
449 * help us discover structs that we should not have ignored.
452 * From the Vulkan 1.0.38 spec:
454 * Any component of the implementation (the loader, any enabled layers,
455 * and drivers) must skip over, without processing (other than reading the
456 * sType and pNext members) any chained structures with sType values not
457 * defined by extensions supported by that component.
459 #define anv_debug_ignored_stype(sType) \
460 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
462 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
463 VkDebugReportObjectTypeEXT type
, const char *file
,
464 int line
, const char *format
, ...)
465 anv_printflike(6, 7);
466 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
467 void anv_loge_v(const char *format
, va_list va
);
470 * Print a FINISHME message, including its source location.
472 #define anv_finishme(format, ...) \
474 static bool reported = false; \
476 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
483 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
485 #define anv_perf_warn(instance, obj, format, ...) \
487 static bool reported = false; \
488 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
489 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
490 format, ##__VA_ARGS__); \
495 /* A non-fatal assert. Useful for debugging. */
497 #define anv_assert(x) ({ \
498 if (unlikely(!(x))) \
499 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
502 #define anv_assert(x)
505 /* A multi-pointer allocator
507 * When copying data structures from the user (such as a render pass), it's
508 * common to need to allocate data for a bunch of different things. Instead
509 * of doing several allocations and having to handle all of the error checking
510 * that entails, it can be easier to do a single allocation. This struct
511 * helps facilitate that. The intended usage looks like this:
514 * anv_multialloc_add(&ma, &main_ptr, 1);
515 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
516 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
518 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
519 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
521 struct anv_multialloc
{
529 #define ANV_MULTIALLOC_INIT \
530 ((struct anv_multialloc) { 0, })
532 #define ANV_MULTIALLOC(_name) \
533 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
535 __attribute__((always_inline
))
537 _anv_multialloc_add(struct anv_multialloc
*ma
,
538 void **ptr
, size_t size
, size_t align
)
540 size_t offset
= align_u64(ma
->size
, align
);
541 ma
->size
= offset
+ size
;
542 ma
->align
= MAX2(ma
->align
, align
);
544 /* Store the offset in the pointer. */
545 *ptr
= (void *)(uintptr_t)offset
;
547 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
548 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
551 #define anv_multialloc_add_size(_ma, _ptr, _size) \
552 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
554 #define anv_multialloc_add(_ma, _ptr, _count) \
555 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
557 __attribute__((always_inline
))
559 anv_multialloc_alloc(struct anv_multialloc
*ma
,
560 const VkAllocationCallbacks
*alloc
,
561 VkSystemAllocationScope scope
)
563 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
567 /* Fill out each of the pointers with their final value.
569 * for (uint32_t i = 0; i < ma->ptr_count; i++)
570 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
572 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
573 * constant, GCC is incapable of figuring this out and unrolling the loop
574 * so we have to give it a little help.
576 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
577 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
578 if ((_i) < ma->ptr_count) \
579 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
580 _ANV_MULTIALLOC_UPDATE_POINTER(0);
581 _ANV_MULTIALLOC_UPDATE_POINTER(1);
582 _ANV_MULTIALLOC_UPDATE_POINTER(2);
583 _ANV_MULTIALLOC_UPDATE_POINTER(3);
584 _ANV_MULTIALLOC_UPDATE_POINTER(4);
585 _ANV_MULTIALLOC_UPDATE_POINTER(5);
586 _ANV_MULTIALLOC_UPDATE_POINTER(6);
587 _ANV_MULTIALLOC_UPDATE_POINTER(7);
588 #undef _ANV_MULTIALLOC_UPDATE_POINTER
593 __attribute__((always_inline
))
595 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
596 const VkAllocationCallbacks
*parent_alloc
,
597 const VkAllocationCallbacks
*alloc
,
598 VkSystemAllocationScope scope
)
600 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
608 /* Index into the current validation list. This is used by the
609 * validation list building alrogithm to track which buffers are already
610 * in the validation list so that we can ensure uniqueness.
614 /* Index for use with util_sparse_array_free_list */
617 /* Last known offset. This value is provided by the kernel when we
618 * execbuf and is used as the presumed offset for the next bunch of
625 /* Map for internally mapped BOs.
627 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
631 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
634 /** True if this BO may be shared with other processes */
637 /** True if this BO is a wrapper
639 * When set to true, none of the fields in this BO are meaningful except
640 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
641 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
642 * is set in the physical device.
646 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
647 bool has_fixed_address
:1;
649 /** True if this BO wraps a host pointer */
650 bool from_host_ptr
:1;
653 static inline struct anv_bo
*
654 anv_bo_unwrap(struct anv_bo
*bo
)
656 while (bo
->is_wrapper
)
661 /* Represents a lock-free linked list of "free" things. This is used by
662 * both the block pool and the state pools. Unfortunately, in order to
663 * solve the ABA problem, we can't use a single uint32_t head.
665 union anv_free_list
{
669 /* A simple count that is incremented every time the head changes. */
672 /* Make sure it's aligned to 64 bits. This will make atomic operations
673 * faster on 32 bit platforms.
675 uint64_t u64
__attribute__ ((aligned (8)));
678 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
680 struct anv_block_state
{
686 /* Make sure it's aligned to 64 bits. This will make atomic operations
687 * faster on 32 bit platforms.
689 uint64_t u64
__attribute__ ((aligned (8)));
693 #define anv_block_pool_foreach_bo(bo, pool) \
694 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
695 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
698 #define ANV_MAX_BLOCK_POOL_BOS 20
700 struct anv_block_pool
{
701 struct anv_device
*device
;
704 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
705 * around the actual BO so that we grow the pool after the wrapper BO has
706 * been put in a relocation list. This is only used in the non-softpin
709 struct anv_bo wrapper_bo
;
711 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
717 /* The address where the start of the pool is pinned. The various bos that
718 * are created as the pool grows will have addresses in the range
719 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
721 uint64_t start_address
;
723 /* The offset from the start of the bo to the "center" of the block
724 * pool. Pointers to allocated blocks are given by
725 * bo.map + center_bo_offset + offsets.
727 uint32_t center_bo_offset
;
729 /* Current memory map of the block pool. This pointer may or may not
730 * point to the actual beginning of the block pool memory. If
731 * anv_block_pool_alloc_back has ever been called, then this pointer
732 * will point to the "center" position of the buffer and all offsets
733 * (negative or positive) given out by the block pool alloc functions
734 * will be valid relative to this pointer.
736 * In particular, map == bo.map + center_offset
738 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
739 * since it will handle the softpin case as well, where this points to NULL.
745 * Array of mmaps and gem handles owned by the block pool, reclaimed when
746 * the block pool is destroyed.
748 struct u_vector mmap_cleanups
;
750 struct anv_block_state state
;
752 struct anv_block_state back_state
;
755 /* Block pools are backed by a fixed-size 1GB memfd */
756 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
758 /* The center of the block pool is also the middle of the memfd. This may
759 * change in the future if we decide differently for some reason.
761 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
763 static inline uint32_t
764 anv_block_pool_size(struct anv_block_pool
*pool
)
766 return pool
->state
.end
+ pool
->back_state
.end
;
776 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
778 struct anv_fixed_size_state_pool
{
779 union anv_free_list free_list
;
780 struct anv_block_state block
;
783 #define ANV_MIN_STATE_SIZE_LOG2 6
784 #define ANV_MAX_STATE_SIZE_LOG2 21
786 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
788 struct anv_free_entry
{
790 struct anv_state state
;
793 struct anv_state_table
{
794 struct anv_device
*device
;
796 struct anv_free_entry
*map
;
798 struct anv_block_state state
;
799 struct u_vector cleanups
;
802 struct anv_state_pool
{
803 struct anv_block_pool block_pool
;
805 struct anv_state_table table
;
807 /* The size of blocks which will be allocated from the block pool */
810 /** Free list for "back" allocations */
811 union anv_free_list back_alloc_free_list
;
813 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
816 struct anv_state_stream_block
;
818 struct anv_state_stream
{
819 struct anv_state_pool
*state_pool
;
821 /* The size of blocks to allocate from the state pool */
824 /* Current block we're allocating from */
825 struct anv_state block
;
827 /* Offset into the current block at which to allocate the next state */
830 /* List of all blocks allocated from this pool */
831 struct anv_state_stream_block
*block_list
;
834 /* The block_pool functions exported for testing only. The block pool should
835 * only be used via a state pool (see below).
837 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
838 struct anv_device
*device
,
839 uint64_t start_address
,
840 uint32_t initial_size
);
841 void anv_block_pool_finish(struct anv_block_pool
*pool
);
842 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
843 uint32_t block_size
, uint32_t *padding
);
844 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
845 uint32_t block_size
);
846 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
848 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
849 struct anv_device
*device
,
850 uint64_t start_address
,
851 uint32_t block_size
);
852 void anv_state_pool_finish(struct anv_state_pool
*pool
);
853 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
854 uint32_t state_size
, uint32_t alignment
);
855 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
856 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
857 void anv_state_stream_init(struct anv_state_stream
*stream
,
858 struct anv_state_pool
*state_pool
,
859 uint32_t block_size
);
860 void anv_state_stream_finish(struct anv_state_stream
*stream
);
861 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
862 uint32_t size
, uint32_t alignment
);
864 VkResult
anv_state_table_init(struct anv_state_table
*table
,
865 struct anv_device
*device
,
866 uint32_t initial_entries
);
867 void anv_state_table_finish(struct anv_state_table
*table
);
868 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
870 void anv_free_list_push(union anv_free_list
*list
,
871 struct anv_state_table
*table
,
872 uint32_t idx
, uint32_t count
);
873 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
874 struct anv_state_table
*table
);
877 static inline struct anv_state
*
878 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
880 return &table
->map
[idx
].state
;
883 * Implements a pool of re-usable BOs. The interface is identical to that
884 * of block_pool except that each block is its own BO.
887 struct anv_device
*device
;
891 struct util_sparse_array_free_list free_list
[16];
894 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
896 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
897 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
898 struct anv_bo
**bo_out
);
899 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
901 struct anv_scratch_pool
{
902 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
903 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
906 void anv_scratch_pool_init(struct anv_device
*device
,
907 struct anv_scratch_pool
*pool
);
908 void anv_scratch_pool_finish(struct anv_device
*device
,
909 struct anv_scratch_pool
*pool
);
910 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
911 struct anv_scratch_pool
*pool
,
912 gl_shader_stage stage
,
913 unsigned per_thread_scratch
);
915 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
916 struct anv_bo_cache
{
917 struct util_sparse_array bo_map
;
918 pthread_mutex_t mutex
;
921 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
922 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
924 struct anv_memory_type
{
925 /* Standard bits passed on to the client */
926 VkMemoryPropertyFlags propertyFlags
;
929 /* Driver-internal book-keeping */
930 VkBufferUsageFlags valid_buffer_usage
;
933 struct anv_memory_heap
{
934 /* Standard bits passed on to the client */
936 VkMemoryHeapFlags flags
;
938 /* Driver-internal book-keeping */
941 bool supports_48bit_addresses
;
945 struct anv_physical_device
{
946 VK_LOADER_DATA _loader_data
;
948 struct anv_instance
* instance
;
959 struct gen_device_info info
;
960 /** Amount of "GPU memory" we want to advertise
962 * Clearly, this value is bogus since Intel is a UMA architecture. On
963 * gen7 platforms, we are limited by GTT size unless we want to implement
964 * fine-grained tracking and GTT splitting. On Broadwell and above we are
965 * practically unlimited. However, we will never report more than 3/4 of
966 * the total system ram to try and avoid running out of RAM.
968 bool supports_48bit_addresses
;
969 struct brw_compiler
* compiler
;
970 struct isl_device isl_dev
;
971 struct gen_perf_config
* perf
;
972 int cmd_parser_version
;
974 bool has_exec_capture
;
977 bool has_syncobj_wait
;
978 bool has_context_priority
;
980 bool has_context_isolation
;
981 bool has_mem_available
;
982 bool always_use_bindless
;
984 /** True if we can access buffers using A64 messages */
985 bool has_a64_buffer_access
;
986 /** True if we can use bindless access for images */
987 bool has_bindless_images
;
988 /** True if we can use bindless access for samplers */
989 bool has_bindless_samplers
;
991 struct anv_device_extension_table supported_extensions
;
992 struct anv_physical_device_dispatch_table dispatch
;
995 uint32_t subslice_total
;
999 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1000 uint32_t heap_count
;
1001 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1004 uint8_t driver_build_sha1
[20];
1005 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1006 uint8_t driver_uuid
[VK_UUID_SIZE
];
1007 uint8_t device_uuid
[VK_UUID_SIZE
];
1009 struct disk_cache
* disk_cache
;
1011 struct wsi_device wsi_device
;
1016 struct anv_app_info
{
1017 const char* app_name
;
1018 uint32_t app_version
;
1019 const char* engine_name
;
1020 uint32_t engine_version
;
1021 uint32_t api_version
;
1024 struct anv_instance
{
1025 VK_LOADER_DATA _loader_data
;
1027 VkAllocationCallbacks alloc
;
1029 struct anv_app_info app_info
;
1031 struct anv_instance_extension_table enabled_extensions
;
1032 struct anv_instance_dispatch_table dispatch
;
1033 struct anv_device_dispatch_table device_dispatch
;
1035 int physicalDeviceCount
;
1036 struct anv_physical_device physicalDevice
;
1038 bool pipeline_cache_enabled
;
1040 struct vk_debug_report_instance debug_report_callbacks
;
1042 struct driOptionCache dri_options
;
1043 struct driOptionCache available_dri_options
;
1046 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1047 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1049 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1050 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1054 VK_LOADER_DATA _loader_data
;
1056 struct anv_device
* device
;
1058 VkDeviceQueueCreateFlags flags
;
1061 struct anv_pipeline_cache
{
1062 struct anv_device
* device
;
1063 pthread_mutex_t mutex
;
1065 struct hash_table
* nir_cache
;
1067 struct hash_table
* cache
;
1070 struct nir_xfb_info
;
1071 struct anv_pipeline_bind_map
;
1073 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1074 struct anv_device
*device
,
1075 bool cache_enabled
);
1076 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1078 struct anv_shader_bin
*
1079 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1080 const void *key
, uint32_t key_size
);
1081 struct anv_shader_bin
*
1082 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1083 const void *key_data
, uint32_t key_size
,
1084 const void *kernel_data
, uint32_t kernel_size
,
1085 const void *constant_data
,
1086 uint32_t constant_data_size
,
1087 const struct brw_stage_prog_data
*prog_data
,
1088 uint32_t prog_data_size
,
1089 const struct brw_compile_stats
*stats
,
1091 const struct nir_xfb_info
*xfb_info
,
1092 const struct anv_pipeline_bind_map
*bind_map
);
1094 struct anv_shader_bin
*
1095 anv_device_search_for_kernel(struct anv_device
*device
,
1096 struct anv_pipeline_cache
*cache
,
1097 const void *key_data
, uint32_t key_size
,
1098 bool *user_cache_bit
);
1100 struct anv_shader_bin
*
1101 anv_device_upload_kernel(struct anv_device
*device
,
1102 struct anv_pipeline_cache
*cache
,
1103 const void *key_data
, uint32_t key_size
,
1104 const void *kernel_data
, uint32_t kernel_size
,
1105 const void *constant_data
,
1106 uint32_t constant_data_size
,
1107 const struct brw_stage_prog_data
*prog_data
,
1108 uint32_t prog_data_size
,
1109 const struct brw_compile_stats
*stats
,
1111 const struct nir_xfb_info
*xfb_info
,
1112 const struct anv_pipeline_bind_map
*bind_map
);
1115 struct nir_shader_compiler_options
;
1118 anv_device_search_for_nir(struct anv_device
*device
,
1119 struct anv_pipeline_cache
*cache
,
1120 const struct nir_shader_compiler_options
*nir_options
,
1121 unsigned char sha1_key
[20],
1125 anv_device_upload_nir(struct anv_device
*device
,
1126 struct anv_pipeline_cache
*cache
,
1127 const struct nir_shader
*nir
,
1128 unsigned char sha1_key
[20]);
1131 VK_LOADER_DATA _loader_data
;
1133 VkAllocationCallbacks alloc
;
1135 struct anv_instance
* instance
;
1136 uint32_t chipset_id
;
1138 struct gen_device_info info
;
1139 struct isl_device isl_dev
;
1142 bool can_chain_batches
;
1143 bool robust_buffer_access
;
1144 struct anv_device_extension_table enabled_extensions
;
1145 struct anv_device_dispatch_table dispatch
;
1147 pthread_mutex_t vma_mutex
;
1148 struct util_vma_heap vma_lo
;
1149 struct util_vma_heap vma_hi
;
1150 uint64_t vma_lo_available
;
1151 uint64_t vma_hi_available
;
1153 /** List of all anv_device_memory objects */
1154 struct list_head memory_objects
;
1156 struct anv_bo_pool batch_bo_pool
;
1158 struct anv_bo_cache bo_cache
;
1160 struct anv_state_pool dynamic_state_pool
;
1161 struct anv_state_pool instruction_state_pool
;
1162 struct anv_state_pool binding_table_pool
;
1163 struct anv_state_pool surface_state_pool
;
1165 struct anv_bo
* workaround_bo
;
1166 struct anv_bo
* trivial_batch_bo
;
1167 struct anv_bo
* hiz_clear_bo
;
1169 struct anv_pipeline_cache default_pipeline_cache
;
1170 struct blorp_context blorp
;
1172 struct anv_state border_colors
;
1174 struct anv_state slice_hash
;
1176 struct anv_queue queue
;
1178 struct anv_scratch_pool scratch_pool
;
1180 uint32_t default_mocs
;
1181 uint32_t external_mocs
;
1183 pthread_mutex_t mutex
;
1184 pthread_cond_t queue_submit
;
1187 struct gen_batch_decode_ctx decoder_ctx
;
1189 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1190 * the cmd_buffer's list.
1192 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1194 int perf_fd
; /* -1 if no opened */
1195 uint64_t perf_metric
; /* 0 if unset */
1197 struct gen_aux_map_context
*aux_map_ctx
;
1200 static inline struct anv_state_pool
*
1201 anv_binding_table_pool(struct anv_device
*device
)
1203 if (device
->instance
->physicalDevice
.use_softpin
)
1204 return &device
->binding_table_pool
;
1206 return &device
->surface_state_pool
;
1209 static inline struct anv_state
1210 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1211 if (device
->instance
->physicalDevice
.use_softpin
)
1212 return anv_state_pool_alloc(&device
->binding_table_pool
,
1213 device
->binding_table_pool
.block_size
, 0);
1215 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1219 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1220 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1223 static inline uint32_t
1224 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1226 if (bo
->is_external
)
1227 return device
->external_mocs
;
1229 return device
->default_mocs
;
1232 void anv_device_init_blorp(struct anv_device
*device
);
1233 void anv_device_finish_blorp(struct anv_device
*device
);
1235 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1236 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1237 const char *file
, int line
,
1238 const char *msg
, ...)
1239 anv_printflike(4, 5);
1240 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1241 const char *file
, int line
,
1242 const char *msg
, ...)
1243 anv_printflike(4, 5);
1244 #define anv_device_set_lost(dev, ...) \
1245 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1246 #define anv_queue_set_lost(queue, ...) \
1247 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1250 anv_device_is_lost(struct anv_device
*device
)
1252 return unlikely(p_atomic_read(&device
->_lost
));
1255 VkResult
anv_device_query_status(struct anv_device
*device
);
1258 enum anv_bo_alloc_flags
{
1259 /** Specifies that the BO must have a 32-bit address
1261 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1263 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1265 /** Specifies that the BO may be shared externally */
1266 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1268 /** Specifies that the BO should be mapped */
1269 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1271 /** Specifies that the BO should be snooped so we get coherency */
1272 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1274 /** Specifies that the BO should be captured in error states */
1275 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1277 /** Specifies that the BO will have an address assigned by the caller */
1278 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1280 /** Enables implicit synchronization on the BO
1282 * This is the opposite of EXEC_OBJECT_ASYNC.
1284 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1286 /** Enables implicit synchronization on the BO
1288 * This is equivalent to EXEC_OBJECT_WRITE.
1290 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1293 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1294 enum anv_bo_alloc_flags alloc_flags
,
1295 struct anv_bo
**bo
);
1296 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1297 void *host_ptr
, uint32_t size
,
1298 enum anv_bo_alloc_flags alloc_flags
,
1299 struct anv_bo
**bo_out
);
1300 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1301 enum anv_bo_alloc_flags alloc_flags
,
1302 struct anv_bo
**bo
);
1303 VkResult
anv_device_export_bo(struct anv_device
*device
,
1304 struct anv_bo
*bo
, int *fd_out
);
1305 void anv_device_release_bo(struct anv_device
*device
,
1308 static inline struct anv_bo
*
1309 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1311 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1314 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1315 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1318 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1319 void anv_queue_finish(struct anv_queue
*queue
);
1321 VkResult
anv_queue_execbuf(struct anv_queue
*queue
,
1322 struct drm_i915_gem_execbuffer2
*execbuf
,
1323 struct anv_bo
**execbuf_bos
);
1324 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1325 struct anv_batch
*batch
);
1327 uint64_t anv_gettime_ns(void);
1328 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1330 void* anv_gem_mmap(struct anv_device
*device
,
1331 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1332 void anv_gem_munmap(void *p
, uint64_t size
);
1333 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1334 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1335 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1336 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1337 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1338 int anv_gem_execbuffer(struct anv_device
*device
,
1339 struct drm_i915_gem_execbuffer2
*execbuf
);
1340 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1341 uint32_t stride
, uint32_t tiling
);
1342 int anv_gem_create_context(struct anv_device
*device
);
1343 bool anv_gem_has_context_priority(int fd
);
1344 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1345 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1347 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1349 int anv_gem_get_param(int fd
, uint32_t param
);
1350 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1351 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1352 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1353 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1354 uint32_t *active
, uint32_t *pending
);
1355 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1356 int anv_gem_reg_read(struct anv_device
*device
,
1357 uint32_t offset
, uint64_t *result
);
1358 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1359 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1360 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1361 uint32_t read_domains
, uint32_t write_domain
);
1362 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1363 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1364 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1365 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1366 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1367 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1369 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1370 uint32_t handle
, int fd
);
1371 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1372 bool anv_gem_supports_syncobj_wait(int fd
);
1373 int anv_gem_syncobj_wait(struct anv_device
*device
,
1374 uint32_t *handles
, uint32_t num_handles
,
1375 int64_t abs_timeout_ns
, bool wait_all
);
1377 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1378 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1380 struct anv_reloc_list
{
1381 uint32_t num_relocs
;
1382 uint32_t array_length
;
1383 struct drm_i915_gem_relocation_entry
* relocs
;
1384 struct anv_bo
** reloc_bos
;
1389 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1390 const VkAllocationCallbacks
*alloc
);
1391 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1392 const VkAllocationCallbacks
*alloc
);
1394 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1395 const VkAllocationCallbacks
*alloc
,
1396 uint32_t offset
, struct anv_bo
*target_bo
,
1397 uint32_t delta
, uint64_t *address_u64_out
);
1399 struct anv_batch_bo
{
1400 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1401 struct list_head link
;
1405 /* Bytes actually consumed in this batch BO */
1408 struct anv_reloc_list relocs
;
1412 const VkAllocationCallbacks
* alloc
;
1418 struct anv_reloc_list
* relocs
;
1420 /* This callback is called (with the associated user data) in the event
1421 * that the batch runs out of space.
1423 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1427 * Current error status of the command buffer. Used to track inconsistent
1428 * or incomplete command buffer states that are the consequence of run-time
1429 * errors such as out of memory scenarios. We want to track this in the
1430 * batch because the command buffer object is not visible to some parts
1436 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1437 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1438 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1439 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1441 static inline VkResult
1442 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1444 assert(error
!= VK_SUCCESS
);
1445 if (batch
->status
== VK_SUCCESS
)
1446 batch
->status
= error
;
1447 return batch
->status
;
1451 anv_batch_has_error(struct anv_batch
*batch
)
1453 return batch
->status
!= VK_SUCCESS
;
1456 struct anv_address
{
1461 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1464 anv_address_is_null(struct anv_address addr
)
1466 return addr
.bo
== NULL
&& addr
.offset
== 0;
1469 static inline uint64_t
1470 anv_address_physical(struct anv_address addr
)
1472 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1473 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1475 return gen_canonical_address(addr
.offset
);
1478 static inline struct anv_address
1479 anv_address_add(struct anv_address addr
, uint64_t offset
)
1481 addr
.offset
+= offset
;
1486 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1488 unsigned reloc_size
= 0;
1489 if (device
->info
.gen
>= 8) {
1490 reloc_size
= sizeof(uint64_t);
1491 *(uint64_t *)p
= gen_canonical_address(v
);
1493 reloc_size
= sizeof(uint32_t);
1497 if (flush
&& !device
->info
.has_llc
)
1498 gen_flush_range(p
, reloc_size
);
1501 static inline uint64_t
1502 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1503 const struct anv_address address
, uint32_t delta
)
1505 if (address
.bo
== NULL
) {
1506 return address
.offset
+ delta
;
1508 assert(batch
->start
<= location
&& location
< batch
->end
);
1510 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1514 #define __gen_address_type struct anv_address
1515 #define __gen_user_data struct anv_batch
1516 #define __gen_combine_address _anv_combine_address
1518 /* Wrapper macros needed to work around preprocessor argument issues. In
1519 * particular, arguments don't get pre-evaluated if they are concatenated.
1520 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1521 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1522 * We can work around this easily enough with these helpers.
1524 #define __anv_cmd_length(cmd) cmd ## _length
1525 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1526 #define __anv_cmd_header(cmd) cmd ## _header
1527 #define __anv_cmd_pack(cmd) cmd ## _pack
1528 #define __anv_reg_num(reg) reg ## _num
1530 #define anv_pack_struct(dst, struc, ...) do { \
1531 struct struc __template = { \
1534 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1535 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1538 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1539 void *__dst = anv_batch_emit_dwords(batch, n); \
1541 struct cmd __template = { \
1542 __anv_cmd_header(cmd), \
1543 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1546 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1551 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1555 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1556 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1559 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1560 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1561 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1564 #define anv_batch_emit(batch, cmd, name) \
1565 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1566 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1567 __builtin_expect(_dst != NULL, 1); \
1568 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1569 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1573 /* MEMORY_OBJECT_CONTROL_STATE:
1574 * .GraphicsDataTypeGFDT = 0,
1575 * .LLCCacheabilityControlLLCCC = 0,
1576 * .L3CacheabilityControlL3CC = 1,
1580 /* MEMORY_OBJECT_CONTROL_STATE:
1581 * .LLCeLLCCacheabilityControlLLCCC = 0,
1582 * .L3CacheabilityControlL3CC = 1,
1584 #define GEN75_MOCS 1
1586 /* MEMORY_OBJECT_CONTROL_STATE:
1587 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1588 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1589 * .AgeforQUADLRU = 0
1591 #define GEN8_MOCS 0x78
1593 /* MEMORY_OBJECT_CONTROL_STATE:
1594 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1595 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1596 * .AgeforQUADLRU = 0
1598 #define GEN8_EXTERNAL_MOCS 0x18
1600 /* Skylake: MOCS is now an index into an array of 62 different caching
1601 * configurations programmed by the kernel.
1604 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1605 #define GEN9_MOCS (2 << 1)
1607 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1608 #define GEN9_EXTERNAL_MOCS (1 << 1)
1610 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1611 #define GEN10_MOCS GEN9_MOCS
1612 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1614 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1615 #define GEN11_MOCS GEN9_MOCS
1616 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1618 /* TigerLake MOCS */
1619 #define GEN12_MOCS GEN9_MOCS
1620 /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
1621 #define GEN12_EXTERNAL_MOCS (3 << 1)
1623 struct anv_device_memory
{
1624 struct list_head link
;
1627 struct anv_memory_type
* type
;
1628 VkDeviceSize map_size
;
1631 /* If set, we are holding reference to AHardwareBuffer
1632 * which we must release when memory is freed.
1634 struct AHardwareBuffer
* ahw
;
1636 /* If set, this memory comes from a host pointer. */
1641 * Header for Vertex URB Entry (VUE)
1643 struct anv_vue_header
{
1645 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1646 uint32_t ViewportIndex
;
1650 /** Struct representing a sampled image descriptor
1652 * This descriptor layout is used for sampled images, bare sampler, and
1653 * combined image/sampler descriptors.
1655 struct anv_sampled_image_descriptor
{
1656 /** Bindless image handle
1658 * This is expected to already be shifted such that the 20-bit
1659 * SURFACE_STATE table index is in the top 20 bits.
1663 /** Bindless sampler handle
1665 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1666 * to the dynamic state base address.
1671 struct anv_texture_swizzle_descriptor
{
1674 * See also nir_intrinsic_channel_select_intel
1678 /** Unused padding to ensure the struct is a multiple of 64 bits */
1682 /** Struct representing a storage image descriptor */
1683 struct anv_storage_image_descriptor
{
1684 /** Bindless image handles
1686 * These are expected to already be shifted such that the 20-bit
1687 * SURFACE_STATE table index is in the top 20 bits.
1689 uint32_t read_write
;
1690 uint32_t write_only
;
1693 /** Struct representing a address/range descriptor
1695 * The fields of this struct correspond directly to the data layout of
1696 * nir_address_format_64bit_bounded_global addresses. The last field is the
1697 * offset in the NIR address so it must be zero so that when you load the
1698 * descriptor you get a pointer to the start of the range.
1700 struct anv_address_range_descriptor
{
1706 enum anv_descriptor_data
{
1707 /** The descriptor contains a BTI reference to a surface state */
1708 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1709 /** The descriptor contains a BTI reference to a sampler state */
1710 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1711 /** The descriptor contains an actual buffer view */
1712 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1713 /** The descriptor contains auxiliary image layout data */
1714 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1715 /** The descriptor contains auxiliary image layout data */
1716 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1717 /** anv_address_range_descriptor with a buffer address and range */
1718 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1719 /** Bindless surface handle */
1720 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1721 /** Storage image handles */
1722 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1723 /** Storage image handles */
1724 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1727 struct anv_descriptor_set_binding_layout
{
1729 /* The type of the descriptors in this binding */
1730 VkDescriptorType type
;
1733 /* Flags provided when this binding was created */
1734 VkDescriptorBindingFlagsEXT flags
;
1736 /* Bitfield representing the type of data this descriptor contains */
1737 enum anv_descriptor_data data
;
1739 /* Maximum number of YCbCr texture/sampler planes */
1740 uint8_t max_plane_count
;
1742 /* Number of array elements in this binding (or size in bytes for inline
1745 uint16_t array_size
;
1747 /* Index into the flattend descriptor set */
1748 uint16_t descriptor_index
;
1750 /* Index into the dynamic state array for a dynamic buffer */
1751 int16_t dynamic_offset_index
;
1753 /* Index into the descriptor set buffer views */
1754 int16_t buffer_view_index
;
1756 /* Offset into the descriptor buffer where this descriptor lives */
1757 uint32_t descriptor_offset
;
1759 /* Immutable samplers (or NULL if no immutable samplers) */
1760 struct anv_sampler
**immutable_samplers
;
1763 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1765 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1766 VkDescriptorType type
);
1768 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1769 const struct anv_descriptor_set_binding_layout
*binding
,
1772 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1773 const struct anv_descriptor_set_binding_layout
*binding
,
1776 struct anv_descriptor_set_layout
{
1777 /* Descriptor set layouts can be destroyed at almost any time */
1780 /* Number of bindings in this descriptor set */
1781 uint16_t binding_count
;
1783 /* Total size of the descriptor set with room for all array entries */
1786 /* Shader stages affected by this descriptor set */
1787 uint16_t shader_stages
;
1789 /* Number of buffer views in this descriptor set */
1790 uint16_t buffer_view_count
;
1792 /* Number of dynamic offsets used by this descriptor set */
1793 uint16_t dynamic_offset_count
;
1795 /* Size of the descriptor buffer for this descriptor set */
1796 uint32_t descriptor_buffer_size
;
1798 /* Bindings in this descriptor set */
1799 struct anv_descriptor_set_binding_layout binding
[0];
1803 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1805 assert(layout
&& layout
->ref_cnt
>= 1);
1806 p_atomic_inc(&layout
->ref_cnt
);
1810 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1811 struct anv_descriptor_set_layout
*layout
)
1813 assert(layout
&& layout
->ref_cnt
>= 1);
1814 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1815 vk_free(&device
->alloc
, layout
);
1818 struct anv_descriptor
{
1819 VkDescriptorType type
;
1823 VkImageLayout layout
;
1824 struct anv_image_view
*image_view
;
1825 struct anv_sampler
*sampler
;
1829 struct anv_buffer
*buffer
;
1834 struct anv_buffer_view
*buffer_view
;
1838 struct anv_descriptor_set
{
1839 struct anv_descriptor_pool
*pool
;
1840 struct anv_descriptor_set_layout
*layout
;
1843 /* State relative to anv_descriptor_pool::bo */
1844 struct anv_state desc_mem
;
1845 /* Surface state for the descriptor buffer */
1846 struct anv_state desc_surface_state
;
1848 uint32_t buffer_view_count
;
1849 struct anv_buffer_view
*buffer_views
;
1851 /* Link to descriptor pool's desc_sets list . */
1852 struct list_head pool_link
;
1854 struct anv_descriptor descriptors
[0];
1857 struct anv_buffer_view
{
1858 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1859 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1861 struct anv_address address
;
1863 struct anv_state surface_state
;
1864 struct anv_state storage_surface_state
;
1865 struct anv_state writeonly_storage_surface_state
;
1867 struct brw_image_param storage_image_param
;
1870 struct anv_push_descriptor_set
{
1871 struct anv_descriptor_set set
;
1873 /* Put this field right behind anv_descriptor_set so it fills up the
1874 * descriptors[0] field. */
1875 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1877 /** True if the descriptor set buffer has been referenced by a draw or
1880 bool set_used_on_gpu
;
1882 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1885 struct anv_descriptor_pool
{
1891 struct util_vma_heap bo_heap
;
1893 struct anv_state_stream surface_state_stream
;
1894 void *surface_state_free_list
;
1896 struct list_head desc_sets
;
1901 enum anv_descriptor_template_entry_type
{
1902 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1903 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1904 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1907 struct anv_descriptor_template_entry
{
1908 /* The type of descriptor in this entry */
1909 VkDescriptorType type
;
1911 /* Binding in the descriptor set */
1914 /* Offset at which to write into the descriptor set binding */
1915 uint32_t array_element
;
1917 /* Number of elements to write into the descriptor set binding */
1918 uint32_t array_count
;
1920 /* Offset into the user provided data */
1923 /* Stride between elements into the user provided data */
1927 struct anv_descriptor_update_template
{
1928 VkPipelineBindPoint bind_point
;
1930 /* The descriptor set this template corresponds to. This value is only
1931 * valid if the template was created with the templateType
1932 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1936 /* Number of entries in this template */
1937 uint32_t entry_count
;
1939 /* Entries of the template */
1940 struct anv_descriptor_template_entry entries
[0];
1944 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1947 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1948 struct anv_descriptor_set
*set
,
1949 const VkDescriptorImageInfo
* const info
,
1950 VkDescriptorType type
,
1955 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1956 struct anv_descriptor_set
*set
,
1957 VkDescriptorType type
,
1958 struct anv_buffer_view
*buffer_view
,
1963 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1964 struct anv_descriptor_set
*set
,
1965 struct anv_state_stream
*alloc_stream
,
1966 VkDescriptorType type
,
1967 struct anv_buffer
*buffer
,
1970 VkDeviceSize offset
,
1971 VkDeviceSize range
);
1973 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1974 struct anv_descriptor_set
*set
,
1981 anv_descriptor_set_write_template(struct anv_device
*device
,
1982 struct anv_descriptor_set
*set
,
1983 struct anv_state_stream
*alloc_stream
,
1984 const struct anv_descriptor_update_template
*template,
1988 anv_descriptor_set_create(struct anv_device
*device
,
1989 struct anv_descriptor_pool
*pool
,
1990 struct anv_descriptor_set_layout
*layout
,
1991 struct anv_descriptor_set
**out_set
);
1994 anv_descriptor_set_destroy(struct anv_device
*device
,
1995 struct anv_descriptor_pool
*pool
,
1996 struct anv_descriptor_set
*set
);
1998 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
1999 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2000 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2001 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2003 struct anv_pipeline_binding
{
2004 /* The descriptor set this surface corresponds to. The special value of
2005 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
2006 * to a color attachment and not a regular descriptor.
2010 /* Binding in the descriptor set */
2013 /* Index in the binding */
2016 /* Plane in the binding index */
2019 /* Input attachment index (relative to the subpass) */
2020 uint8_t input_attachment_index
;
2022 /* For a storage image, whether it is write-only */
2026 struct anv_pipeline_layout
{
2028 struct anv_descriptor_set_layout
*layout
;
2029 uint32_t dynamic_offset_start
;
2034 unsigned char sha1
[20];
2038 struct anv_device
* device
;
2041 VkBufferUsageFlags usage
;
2043 /* Set when bound */
2044 struct anv_address address
;
2047 static inline uint64_t
2048 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2050 assert(offset
<= buffer
->size
);
2051 if (range
== VK_WHOLE_SIZE
) {
2052 return buffer
->size
- offset
;
2054 assert(range
+ offset
>= range
);
2055 assert(range
+ offset
<= buffer
->size
);
2060 enum anv_cmd_dirty_bits
{
2061 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2062 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2063 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2064 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2065 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2066 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2067 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2068 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2069 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2070 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2071 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2072 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2073 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2074 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2076 typedef uint32_t anv_cmd_dirty_mask_t
;
2078 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2079 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2080 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2081 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2082 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2083 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2084 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2085 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2086 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2087 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2088 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2090 static inline enum anv_cmd_dirty_bits
2091 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2094 case VK_DYNAMIC_STATE_VIEWPORT
:
2095 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2096 case VK_DYNAMIC_STATE_SCISSOR
:
2097 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2098 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2099 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2100 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2101 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2102 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2103 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2104 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2105 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2106 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2107 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2108 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2109 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2110 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2111 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2112 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2113 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2115 assert(!"Unsupported dynamic state");
2121 enum anv_pipe_bits
{
2122 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2123 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2124 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2125 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2126 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2127 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2128 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2129 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2130 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2131 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2132 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2133 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2135 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2136 * a flush has happened but not a CS stall. The next time we do any sort
2137 * of invalidation we need to insert a CS stall at that time. Otherwise,
2138 * we would have to CS stall on every flush which could be bad.
2140 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2142 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2143 * target operations related to transfer commands with VkBuffer as
2144 * destination are ongoing. Some operations like copies on the command
2145 * streamer might need to be aware of this to trigger the appropriate stall
2146 * before they can proceed with the copy.
2148 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2151 #define ANV_PIPE_FLUSH_BITS ( \
2152 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2153 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2154 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2155 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2157 #define ANV_PIPE_STALL_BITS ( \
2158 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2159 ANV_PIPE_DEPTH_STALL_BIT | \
2160 ANV_PIPE_CS_STALL_BIT)
2162 #define ANV_PIPE_INVALIDATE_BITS ( \
2163 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2164 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2165 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2166 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2167 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2168 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2170 static inline enum anv_pipe_bits
2171 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2173 enum anv_pipe_bits pipe_bits
= 0;
2176 for_each_bit(b
, flags
) {
2177 switch ((VkAccessFlagBits
)(1 << b
)) {
2178 case VK_ACCESS_SHADER_WRITE_BIT
:
2179 /* We're transitioning a buffer that was previously used as write
2180 * destination through the data port. To make its content available
2181 * to future operations, flush the data cache.
2183 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2185 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2186 /* We're transitioning a buffer that was previously used as render
2187 * target. To make its content available to future operations, flush
2188 * the render target cache.
2190 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2192 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2193 /* We're transitioning a buffer that was previously used as depth
2194 * buffer. To make its content available to future operations, flush
2197 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2199 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2200 /* We're transitioning a buffer that was previously used as a
2201 * transfer write destination. Generic write operations include color
2202 * & depth operations as well as buffer operations like :
2203 * - vkCmdClearColorImage()
2204 * - vkCmdClearDepthStencilImage()
2205 * - vkCmdBlitImage()
2206 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2208 * Most of these operations are implemented using Blorp which writes
2209 * through the render target, so flush that cache to make it visible
2210 * to future operations. And for depth related operations we also
2211 * need to flush the depth cache.
2213 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2214 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2216 case VK_ACCESS_MEMORY_WRITE_BIT
:
2217 /* We're transitioning a buffer for generic write operations. Flush
2220 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2223 break; /* Nothing to do */
2230 static inline enum anv_pipe_bits
2231 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2233 enum anv_pipe_bits pipe_bits
= 0;
2236 for_each_bit(b
, flags
) {
2237 switch ((VkAccessFlagBits
)(1 << b
)) {
2238 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2239 /* Indirect draw commands take a buffer as input that we're going to
2240 * read from the command streamer to load some of the HW registers
2241 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2242 * command streamer stall so that all the cache flushes have
2243 * completed before the command streamer loads from memory.
2245 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2246 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2247 * through a vertex buffer, so invalidate that cache.
2249 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2250 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2251 * UBO from the buffer, so we need to invalidate constant cache.
2253 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2255 case VK_ACCESS_INDEX_READ_BIT
:
2256 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2257 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2258 * commands, so we invalidate the VF cache to make sure there is no
2259 * stale data when we start rendering.
2261 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2263 case VK_ACCESS_UNIFORM_READ_BIT
:
2264 /* We transitioning a buffer to be used as uniform data. Because
2265 * uniform is accessed through the data port & sampler, we need to
2266 * invalidate the texture cache (sampler) & constant cache (data
2267 * port) to avoid stale data.
2269 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2270 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2272 case VK_ACCESS_SHADER_READ_BIT
:
2273 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2274 case VK_ACCESS_TRANSFER_READ_BIT
:
2275 /* Transitioning a buffer to be read through the sampler, so
2276 * invalidate the texture cache, we don't want any stale data.
2278 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2280 case VK_ACCESS_MEMORY_READ_BIT
:
2281 /* Transitioning a buffer for generic read, invalidate all the
2284 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2286 case VK_ACCESS_MEMORY_WRITE_BIT
:
2287 /* Generic write, make sure all previously written things land in
2290 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2292 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2293 /* Transitioning a buffer for conditional rendering. We'll load the
2294 * content of this buffer into HW registers using the command
2295 * streamer, so we need to stall the command streamer to make sure
2296 * any in-flight flush operations have completed.
2298 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2301 break; /* Nothing to do */
2308 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2309 VK_IMAGE_ASPECT_COLOR_BIT | \
2310 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2311 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2312 VK_IMAGE_ASPECT_PLANE_2_BIT)
2313 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2314 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2315 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2316 VK_IMAGE_ASPECT_PLANE_2_BIT)
2318 struct anv_vertex_binding
{
2319 struct anv_buffer
* buffer
;
2320 VkDeviceSize offset
;
2323 struct anv_xfb_binding
{
2324 struct anv_buffer
* buffer
;
2325 VkDeviceSize offset
;
2329 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
2330 #define ANV_PARAM_IS_PUSH(param) ((uint32_t)(param) >> 16 == 1)
2331 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2333 #define ANV_PARAM_DYN_OFFSET(offset) ((2 << 16) | (uint32_t)(offset))
2334 #define ANV_PARAM_IS_DYN_OFFSET(param) ((uint32_t)(param) >> 16 == 2)
2335 #define ANV_PARAM_DYN_OFFSET_IDX(param) ((param) & 0xffff)
2337 struct anv_push_constants
{
2338 /* Push constant data provided by the client through vkPushConstants */
2339 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2341 /* Used for vkCmdDispatchBase */
2342 uint32_t base_work_group_id
[3];
2345 struct anv_dynamic_state
{
2348 VkViewport viewports
[MAX_VIEWPORTS
];
2353 VkRect2D scissors
[MAX_SCISSORS
];
2364 float blend_constants
[4];
2374 } stencil_compare_mask
;
2379 } stencil_write_mask
;
2384 } stencil_reference
;
2392 extern const struct anv_dynamic_state default_dynamic_state
;
2394 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2395 const struct anv_dynamic_state
*src
,
2396 uint32_t copy_mask
);
2398 struct anv_surface_state
{
2399 struct anv_state state
;
2400 /** Address of the surface referred to by this state
2402 * This address is relative to the start of the BO.
2404 struct anv_address address
;
2405 /* Address of the aux surface, if any
2407 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2409 * With the exception of gen8, the bottom 12 bits of this address' offset
2410 * include extra aux information.
2412 struct anv_address aux_address
;
2413 /* Address of the clear color, if any
2415 * This address is relative to the start of the BO.
2417 struct anv_address clear_address
;
2421 * Attachment state when recording a renderpass instance.
2423 * The clear value is valid only if there exists a pending clear.
2425 struct anv_attachment_state
{
2426 enum isl_aux_usage aux_usage
;
2427 enum isl_aux_usage input_aux_usage
;
2428 struct anv_surface_state color
;
2429 struct anv_surface_state input
;
2431 VkImageLayout current_layout
;
2432 VkImageLayout current_stencil_layout
;
2433 VkImageAspectFlags pending_clear_aspects
;
2434 VkImageAspectFlags pending_load_aspects
;
2436 VkClearValue clear_value
;
2437 bool clear_color_is_zero_one
;
2438 bool clear_color_is_zero
;
2440 /* When multiview is active, attachments with a renderpass clear
2441 * operation have their respective layers cleared on the first
2442 * subpass that uses them, and only in that subpass. We keep track
2443 * of this using a bitfield to indicate which layers of an attachment
2444 * have not been cleared yet when multiview is active.
2446 uint32_t pending_clear_views
;
2447 struct anv_image_view
* image_view
;
2450 /** State tracking for particular pipeline bind point
2452 * This struct is the base struct for anv_cmd_graphics_state and
2453 * anv_cmd_compute_state. These are used to track state which is bound to a
2454 * particular type of pipeline. Generic state that applies per-stage such as
2455 * binding table offsets and push constants is tracked generically with a
2456 * per-stage array in anv_cmd_state.
2458 struct anv_cmd_pipeline_state
{
2459 struct anv_pipeline
*pipeline
;
2460 struct anv_pipeline_layout
*layout
;
2462 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2463 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2465 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2468 /** State tracking for graphics pipeline
2470 * This has anv_cmd_pipeline_state as a base struct to track things which get
2471 * bound to a graphics pipeline. Along with general pipeline bind point state
2472 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2473 * state which is graphics-specific.
2475 struct anv_cmd_graphics_state
{
2476 struct anv_cmd_pipeline_state base
;
2478 anv_cmd_dirty_mask_t dirty
;
2481 struct anv_dynamic_state dynamic
;
2484 struct anv_buffer
*index_buffer
;
2485 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2486 uint32_t index_offset
;
2490 /** State tracking for compute pipeline
2492 * This has anv_cmd_pipeline_state as a base struct to track things which get
2493 * bound to a compute pipeline. Along with general pipeline bind point state
2494 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2495 * state which is compute-specific.
2497 struct anv_cmd_compute_state
{
2498 struct anv_cmd_pipeline_state base
;
2500 bool pipeline_dirty
;
2502 struct anv_address num_workgroups
;
2505 /** State required while building cmd buffer */
2506 struct anv_cmd_state
{
2507 /* PIPELINE_SELECT.PipelineSelection */
2508 uint32_t current_pipeline
;
2509 const struct gen_l3_config
* current_l3_config
;
2510 uint32_t last_aux_map_state
;
2512 struct anv_cmd_graphics_state gfx
;
2513 struct anv_cmd_compute_state compute
;
2515 enum anv_pipe_bits pending_pipe_bits
;
2516 VkShaderStageFlags descriptors_dirty
;
2517 VkShaderStageFlags push_constants_dirty
;
2519 struct anv_framebuffer
* framebuffer
;
2520 struct anv_render_pass
* pass
;
2521 struct anv_subpass
* subpass
;
2522 VkRect2D render_area
;
2523 uint32_t restart_index
;
2524 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2526 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2527 VkShaderStageFlags push_constant_stages
;
2528 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2529 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2530 struct anv_state samplers
[MESA_SHADER_STAGES
];
2533 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2534 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2535 * and before invoking the secondary in ExecuteCommands.
2537 bool pma_fix_enabled
;
2540 * Whether or not we know for certain that HiZ is enabled for the current
2541 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2542 * enabled or not, this will be false.
2546 bool conditional_render_enabled
;
2549 * Last rendering scale argument provided to
2550 * genX(cmd_buffer_emit_hashing_mode)().
2552 unsigned current_hash_scale
;
2555 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2556 * valid only when recording a render pass instance.
2558 struct anv_attachment_state
* attachments
;
2561 * Surface states for color render targets. These are stored in a single
2562 * flat array. For depth-stencil attachments, the surface state is simply
2565 struct anv_state render_pass_states
;
2568 * A null surface state of the right size to match the framebuffer. This
2569 * is one of the states in render_pass_states.
2571 struct anv_state null_surface_state
;
2574 struct anv_cmd_pool
{
2575 VkAllocationCallbacks alloc
;
2576 struct list_head cmd_buffers
;
2579 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2581 enum anv_cmd_buffer_exec_mode
{
2582 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2583 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2584 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2585 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2586 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2589 struct anv_cmd_buffer
{
2590 VK_LOADER_DATA _loader_data
;
2592 struct anv_device
* device
;
2594 struct anv_cmd_pool
* pool
;
2595 struct list_head pool_link
;
2597 struct anv_batch batch
;
2599 /* Fields required for the actual chain of anv_batch_bo's.
2601 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2603 struct list_head batch_bos
;
2604 enum anv_cmd_buffer_exec_mode exec_mode
;
2606 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2607 * referenced by this command buffer
2609 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2611 struct u_vector seen_bbos
;
2613 /* A vector of int32_t's for every block of binding tables.
2615 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2617 struct u_vector bt_block_states
;
2620 struct anv_reloc_list surface_relocs
;
2621 /** Last seen surface state block pool center bo offset */
2622 uint32_t last_ss_pool_center
;
2624 /* Serial for tracking buffer completion */
2627 /* Stream objects for storing temporary data */
2628 struct anv_state_stream surface_state_stream
;
2629 struct anv_state_stream dynamic_state_stream
;
2631 VkCommandBufferUsageFlags usage_flags
;
2632 VkCommandBufferLevel level
;
2634 struct anv_cmd_state state
;
2636 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2637 uint64_t intel_perf_marker
;
2640 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2641 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2642 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2643 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2644 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2645 struct anv_cmd_buffer
*secondary
);
2646 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2647 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
2648 struct anv_cmd_buffer
*cmd_buffer
,
2649 const VkSemaphore
*in_semaphores
,
2650 uint32_t num_in_semaphores
,
2651 const VkSemaphore
*out_semaphores
,
2652 uint32_t num_out_semaphores
,
2655 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2657 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2658 const void *data
, uint32_t size
, uint32_t alignment
);
2659 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2660 uint32_t *a
, uint32_t *b
,
2661 uint32_t dwords
, uint32_t alignment
);
2664 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2666 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2667 uint32_t entries
, uint32_t *state_offset
);
2669 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2671 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2672 uint32_t size
, uint32_t alignment
);
2675 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2677 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2678 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2679 bool depth_clamp_enable
);
2680 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2682 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2683 struct anv_render_pass
*pass
,
2684 struct anv_framebuffer
*framebuffer
,
2685 const VkClearValue
*clear_values
);
2687 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2690 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2691 gl_shader_stage stage
);
2693 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2695 const struct anv_image_view
*
2696 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2699 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2700 uint32_t num_entries
,
2701 uint32_t *state_offset
,
2702 struct anv_state
*bt_state
);
2704 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2706 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2708 enum anv_fence_type
{
2709 ANV_FENCE_TYPE_NONE
= 0,
2711 ANV_FENCE_TYPE_SYNCOBJ
,
2715 enum anv_bo_fence_state
{
2716 /** Indicates that this is a new (or newly reset fence) */
2717 ANV_BO_FENCE_STATE_RESET
,
2719 /** Indicates that this fence has been submitted to the GPU but is still
2720 * (as far as we know) in use by the GPU.
2722 ANV_BO_FENCE_STATE_SUBMITTED
,
2724 ANV_BO_FENCE_STATE_SIGNALED
,
2727 struct anv_fence_impl
{
2728 enum anv_fence_type type
;
2731 /** Fence implementation for BO fences
2733 * These fences use a BO and a set of CPU-tracked state flags. The BO
2734 * is added to the object list of the last execbuf call in a QueueSubmit
2735 * and is marked EXEC_WRITE. The state flags track when the BO has been
2736 * submitted to the kernel. We need to do this because Vulkan lets you
2737 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2738 * will say it's idle in this case.
2742 enum anv_bo_fence_state state
;
2745 /** DRM syncobj handle for syncobj-based fences */
2749 struct wsi_fence
*fence_wsi
;
2754 /* Permanent fence state. Every fence has some form of permanent state
2755 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2756 * cross-process fences) or it could just be a dummy for use internally.
2758 struct anv_fence_impl permanent
;
2760 /* Temporary fence state. A fence *may* have temporary state. That state
2761 * is added to the fence by an import operation and is reset back to
2762 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2763 * state cannot be signaled because the fence must already be signaled
2764 * before the temporary state can be exported from the fence in the other
2765 * process and imported here.
2767 struct anv_fence_impl temporary
;
2772 struct anv_state state
;
2775 enum anv_semaphore_type
{
2776 ANV_SEMAPHORE_TYPE_NONE
= 0,
2777 ANV_SEMAPHORE_TYPE_DUMMY
,
2778 ANV_SEMAPHORE_TYPE_BO
,
2779 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2780 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2783 struct anv_semaphore_impl
{
2784 enum anv_semaphore_type type
;
2787 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2788 * This BO will be added to the object list on any execbuf2 calls for
2789 * which this semaphore is used as a wait or signal fence. When used as
2790 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2794 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2795 * If the semaphore is in the unsignaled state due to either just being
2796 * created or because it has been used for a wait, fd will be -1.
2800 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2801 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2802 * import so we don't need to bother with a userspace cache.
2808 struct anv_semaphore
{
2809 /* Permanent semaphore state. Every semaphore has some form of permanent
2810 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2811 * (for cross-process semaphores0 or it could just be a dummy for use
2814 struct anv_semaphore_impl permanent
;
2816 /* Temporary semaphore state. A semaphore *may* have temporary state.
2817 * That state is added to the semaphore by an import operation and is reset
2818 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2819 * semaphore with temporary state cannot be signaled because the semaphore
2820 * must already be signaled before the temporary state can be exported from
2821 * the semaphore in the other process and imported here.
2823 struct anv_semaphore_impl temporary
;
2826 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2827 struct anv_semaphore
*semaphore
);
2829 struct anv_shader_module
{
2830 unsigned char sha1
[20];
2835 static inline gl_shader_stage
2836 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2838 assert(__builtin_popcount(vk_stage
) == 1);
2839 return ffs(vk_stage
) - 1;
2842 static inline VkShaderStageFlagBits
2843 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2845 return (1 << mesa_stage
);
2848 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2850 #define anv_foreach_stage(stage, stage_bits) \
2851 for (gl_shader_stage stage, \
2852 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2853 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2854 __tmp &= ~(1 << (stage)))
2856 struct anv_pipeline_bind_map
{
2857 uint32_t surface_count
;
2858 uint32_t sampler_count
;
2860 struct anv_pipeline_binding
* surface_to_descriptor
;
2861 struct anv_pipeline_binding
* sampler_to_descriptor
;
2864 struct anv_shader_bin_key
{
2869 struct anv_shader_bin
{
2872 const struct anv_shader_bin_key
*key
;
2874 struct anv_state kernel
;
2875 uint32_t kernel_size
;
2877 struct anv_state constant_data
;
2878 uint32_t constant_data_size
;
2880 const struct brw_stage_prog_data
*prog_data
;
2881 uint32_t prog_data_size
;
2883 struct brw_compile_stats stats
[3];
2886 struct nir_xfb_info
*xfb_info
;
2888 struct anv_pipeline_bind_map bind_map
;
2891 struct anv_shader_bin
*
2892 anv_shader_bin_create(struct anv_device
*device
,
2893 const void *key
, uint32_t key_size
,
2894 const void *kernel
, uint32_t kernel_size
,
2895 const void *constant_data
, uint32_t constant_data_size
,
2896 const struct brw_stage_prog_data
*prog_data
,
2897 uint32_t prog_data_size
, const void *prog_data_param
,
2898 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
2899 const struct nir_xfb_info
*xfb_info
,
2900 const struct anv_pipeline_bind_map
*bind_map
);
2903 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2906 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2908 assert(shader
&& shader
->ref_cnt
>= 1);
2909 p_atomic_inc(&shader
->ref_cnt
);
2913 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2915 assert(shader
&& shader
->ref_cnt
>= 1);
2916 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2917 anv_shader_bin_destroy(device
, shader
);
2920 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
2921 #define MAX_PIPELINE_EXECUTABLES 7
2923 struct anv_pipeline_executable
{
2924 gl_shader_stage stage
;
2926 struct brw_compile_stats stats
;
2932 struct anv_pipeline
{
2933 struct anv_device
* device
;
2934 struct anv_batch batch
;
2935 uint32_t batch_data
[512];
2936 struct anv_reloc_list batch_relocs
;
2937 anv_cmd_dirty_mask_t dynamic_state_mask
;
2938 struct anv_dynamic_state dynamic_state
;
2942 VkPipelineCreateFlags flags
;
2943 struct anv_subpass
* subpass
;
2945 bool needs_data_cache
;
2947 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2949 uint32_t num_executables
;
2950 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
2953 const struct gen_l3_config
* l3_config
;
2954 uint32_t total_size
;
2957 VkShaderStageFlags active_stages
;
2958 struct anv_state blend_state
;
2961 struct anv_pipeline_vertex_binding
{
2964 uint32_t instance_divisor
;
2969 bool primitive_restart
;
2972 uint32_t cs_right_mask
;
2975 bool depth_test_enable
;
2976 bool writes_stencil
;
2977 bool stencil_test_enable
;
2978 bool depth_clamp_enable
;
2979 bool depth_clip_enable
;
2980 bool sample_shading_enable
;
2982 bool depth_bounds_test_enable
;
2986 uint32_t depth_stencil_state
[3];
2992 uint32_t wm_depth_stencil
[3];
2996 uint32_t wm_depth_stencil
[4];
2999 uint32_t interface_descriptor_data
[8];
3003 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
3004 gl_shader_stage stage
)
3006 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3009 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
3010 static inline const struct brw_##prefix##_prog_data * \
3011 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
3013 if (anv_pipeline_has_stage(pipeline, stage)) { \
3014 return (const struct brw_##prefix##_prog_data *) \
3015 pipeline->shaders[stage]->prog_data; \
3021 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3022 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3023 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3024 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3025 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3026 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
3028 static inline const struct brw_vue_prog_data
*
3029 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
3031 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3032 return &get_gs_prog_data(pipeline
)->base
;
3033 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3034 return &get_tes_prog_data(pipeline
)->base
;
3036 return &get_vs_prog_data(pipeline
)->base
;
3040 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
3041 struct anv_pipeline_cache
*cache
,
3042 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3043 const VkAllocationCallbacks
*alloc
);
3046 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
3047 struct anv_pipeline_cache
*cache
,
3048 const VkComputePipelineCreateInfo
*info
,
3049 const struct anv_shader_module
*module
,
3050 const char *entrypoint
,
3051 const VkSpecializationInfo
*spec_info
);
3053 struct anv_format_plane
{
3054 enum isl_format isl_format
:16;
3055 struct isl_swizzle swizzle
;
3057 /* Whether this plane contains chroma channels */
3060 /* For downscaling of YUV planes */
3061 uint8_t denominator_scales
[2];
3063 /* How to map sampled ycbcr planes to a single 4 component element. */
3064 struct isl_swizzle ycbcr_swizzle
;
3066 /* What aspect is associated to this plane */
3067 VkImageAspectFlags aspect
;
3072 struct anv_format_plane planes
[3];
3078 static inline uint32_t
3079 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3080 VkImageAspectFlags aspect_mask
)
3082 switch (aspect_mask
) {
3083 case VK_IMAGE_ASPECT_COLOR_BIT
:
3084 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3085 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3087 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3088 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3091 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3093 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3096 /* Purposefully assert with depth/stencil aspects. */
3097 unreachable("invalid image aspect");
3101 static inline VkImageAspectFlags
3102 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3105 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3106 if (util_bitcount(image_aspects
) > 1)
3107 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3108 return VK_IMAGE_ASPECT_COLOR_BIT
;
3110 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3111 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3112 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3113 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3116 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3117 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3119 const struct anv_format
*
3120 anv_get_format(VkFormat format
);
3122 static inline uint32_t
3123 anv_get_format_planes(VkFormat vk_format
)
3125 const struct anv_format
*format
= anv_get_format(vk_format
);
3127 return format
!= NULL
? format
->n_planes
: 0;
3130 struct anv_format_plane
3131 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3132 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3134 static inline enum isl_format
3135 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3136 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3138 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3141 static inline struct isl_swizzle
3142 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3144 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3145 * RGB as RGBA for texturing
3147 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3148 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3150 /* But it doesn't matter what we render to that channel */
3151 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3157 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3160 * Subsurface of an anv_image.
3162 struct anv_surface
{
3163 /** Valid only if isl_surf::size_B > 0. */
3164 struct isl_surf isl
;
3167 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3173 VkImageType type
; /**< VkImageCreateInfo::imageType */
3174 /* The original VkFormat provided by the client. This may not match any
3175 * of the actual surface formats.
3178 const struct anv_format
*format
;
3180 VkImageAspectFlags aspects
;
3183 uint32_t array_size
;
3184 uint32_t samples
; /**< VkImageCreateInfo::samples */
3186 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3187 VkImageUsageFlags stencil_usage
;
3188 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3189 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3191 /** True if this is needs to be bound to an appropriately tiled BO.
3193 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3194 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3195 * we require a dedicated allocation so that we can know to allocate a
3198 bool needs_set_tiling
;
3201 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3202 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3204 uint64_t drm_format_mod
;
3209 /* Whether the image is made of several underlying buffer objects rather a
3210 * single one with different offsets.
3214 /* All the formats that can be used when creating views of this image
3215 * are CCS_E compatible.
3217 bool ccs_e_compatible
;
3219 /* Image was created with external format. */
3220 bool external_format
;
3225 * For each foo, anv_image::planes[x].surface is valid if and only if
3226 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3227 * to figure the number associated with a given aspect.
3229 * The hardware requires that the depth buffer and stencil buffer be
3230 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3231 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3232 * allocate the depth and stencil buffers as separate surfaces in the same
3237 * -----------------------
3239 * ----------------------- |
3240 * | shadow surface0 | |
3241 * ----------------------- | Plane 0
3242 * | aux surface0 | |
3243 * ----------------------- |
3244 * | fast clear colors0 | \|/
3245 * -----------------------
3247 * ----------------------- |
3248 * | shadow surface1 | |
3249 * ----------------------- | Plane 1
3250 * | aux surface1 | |
3251 * ----------------------- |
3252 * | fast clear colors1 | \|/
3253 * -----------------------
3256 * -----------------------
3260 * Offset of the entire plane (whenever the image is disjoint this is
3268 struct anv_surface surface
;
3271 * A surface which shadows the main surface and may have different
3272 * tiling. This is used for sampling using a tiling that isn't supported
3273 * for other operations.
3275 struct anv_surface shadow_surface
;
3278 * For color images, this is the aux usage for this image when not used
3279 * as a color attachment.
3281 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3282 * image has a HiZ buffer.
3284 enum isl_aux_usage aux_usage
;
3286 struct anv_surface aux_surface
;
3289 * Offset of the fast clear state (used to compute the
3290 * fast_clear_state_offset of the following planes).
3292 uint32_t fast_clear_state_offset
;
3295 * BO associated with this plane, set when bound.
3297 struct anv_address address
;
3300 * Address of the main surface used to fill the aux map table. This is
3301 * used at destruction of the image since the Vulkan spec does not
3302 * guarantee that the address.bo field we still be valid at destruction.
3304 uint64_t aux_map_surface_address
;
3307 * When destroying the image, also free the bo.
3313 /* The ordering of this enum is important */
3314 enum anv_fast_clear_type
{
3315 /** Image does not have/support any fast-clear blocks */
3316 ANV_FAST_CLEAR_NONE
= 0,
3317 /** Image has/supports fast-clear but only to the default value */
3318 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3319 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3320 ANV_FAST_CLEAR_ANY
= 2,
3323 /* Returns the number of auxiliary buffer levels attached to an image. */
3324 static inline uint8_t
3325 anv_image_aux_levels(const struct anv_image
* const image
,
3326 VkImageAspectFlagBits aspect
)
3328 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3330 /* The Gen12 CCS aux surface is represented with only one level. */
3331 const uint8_t aux_logical_levels
=
3332 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3333 image
->planes
[plane
].surface
.isl
.levels
:
3334 image
->planes
[plane
].aux_surface
.isl
.levels
;
3336 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3337 aux_logical_levels
: 0;
3340 /* Returns the number of auxiliary buffer layers attached to an image. */
3341 static inline uint32_t
3342 anv_image_aux_layers(const struct anv_image
* const image
,
3343 VkImageAspectFlagBits aspect
,
3344 const uint8_t miplevel
)
3348 /* The miplevel must exist in the main buffer. */
3349 assert(miplevel
< image
->levels
);
3351 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3352 /* There are no layers with auxiliary data because the miplevel has no
3357 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3359 /* The Gen12 CCS aux surface is represented with only one layer. */
3360 const struct isl_extent4d
*aux_logical_level0_px
=
3361 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3362 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3363 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3365 return MAX2(aux_logical_level0_px
->array_len
,
3366 aux_logical_level0_px
->depth
>> miplevel
);
3370 static inline struct anv_address
3371 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3372 const struct anv_image
*image
,
3373 VkImageAspectFlagBits aspect
)
3375 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3377 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3378 return anv_address_add(image
->planes
[plane
].address
,
3379 image
->planes
[plane
].fast_clear_state_offset
);
3382 static inline struct anv_address
3383 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3384 const struct anv_image
*image
,
3385 VkImageAspectFlagBits aspect
)
3387 struct anv_address addr
=
3388 anv_image_get_clear_color_addr(device
, image
, aspect
);
3390 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3391 device
->isl_dev
.ss
.clear_color_state_size
:
3392 device
->isl_dev
.ss
.clear_value_size
;
3393 return anv_address_add(addr
, clear_color_state_size
);
3396 static inline struct anv_address
3397 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3398 const struct anv_image
*image
,
3399 VkImageAspectFlagBits aspect
,
3400 uint32_t level
, uint32_t array_layer
)
3402 assert(level
< anv_image_aux_levels(image
, aspect
));
3403 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3404 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3405 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3407 struct anv_address addr
=
3408 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3409 addr
.offset
+= 4; /* Go past the fast clear type */
3411 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3412 for (uint32_t l
= 0; l
< level
; l
++)
3413 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3415 addr
.offset
+= level
* image
->array_size
* 4;
3417 addr
.offset
+= array_layer
* 4;
3419 assert(addr
.offset
<
3420 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3424 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3426 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3427 const struct anv_image
*image
)
3429 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3432 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3433 * struct. There's documentation which suggests that this feature actually
3434 * reduces performance on BDW, but it has only been observed to help so
3435 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3436 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3438 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3441 return image
->samples
== 1;
3445 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3446 const struct anv_image
*image
,
3449 return device
->info
.has_aux_map
&&
3450 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3454 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3455 const struct anv_image
*image
,
3456 VkImageAspectFlagBits aspect
,
3457 enum isl_aux_usage aux_usage
,
3459 uint32_t base_layer
,
3460 uint32_t layer_count
);
3463 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3464 const struct anv_image
*image
,
3465 VkImageAspectFlagBits aspect
,
3466 enum isl_aux_usage aux_usage
,
3467 enum isl_format format
, struct isl_swizzle swizzle
,
3468 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3469 VkRect2D area
, union isl_color_value clear_color
);
3471 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3472 const struct anv_image
*image
,
3473 VkImageAspectFlags aspects
,
3474 enum isl_aux_usage depth_aux_usage
,
3476 uint32_t base_layer
, uint32_t layer_count
,
3478 float depth_value
, uint8_t stencil_value
);
3480 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3481 const struct anv_image
*src_image
,
3482 enum isl_aux_usage src_aux_usage
,
3483 uint32_t src_level
, uint32_t src_base_layer
,
3484 const struct anv_image
*dst_image
,
3485 enum isl_aux_usage dst_aux_usage
,
3486 uint32_t dst_level
, uint32_t dst_base_layer
,
3487 VkImageAspectFlagBits aspect
,
3488 uint32_t src_x
, uint32_t src_y
,
3489 uint32_t dst_x
, uint32_t dst_y
,
3490 uint32_t width
, uint32_t height
,
3491 uint32_t layer_count
,
3492 enum blorp_filter filter
);
3494 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3495 const struct anv_image
*image
,
3496 VkImageAspectFlagBits aspect
, uint32_t level
,
3497 uint32_t base_layer
, uint32_t layer_count
,
3498 enum isl_aux_op hiz_op
);
3500 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3501 const struct anv_image
*image
,
3502 VkImageAspectFlags aspects
,
3504 uint32_t base_layer
, uint32_t layer_count
,
3505 VkRect2D area
, uint8_t stencil_value
);
3507 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3508 const struct anv_image
*image
,
3509 enum isl_format format
,
3510 VkImageAspectFlagBits aspect
,
3511 uint32_t base_layer
, uint32_t layer_count
,
3512 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3515 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3516 const struct anv_image
*image
,
3517 enum isl_format format
,
3518 VkImageAspectFlagBits aspect
, uint32_t level
,
3519 uint32_t base_layer
, uint32_t layer_count
,
3520 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3524 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3525 const struct anv_image
*image
,
3526 VkImageAspectFlagBits aspect
,
3527 uint32_t base_level
, uint32_t level_count
,
3528 uint32_t base_layer
, uint32_t layer_count
);
3531 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3532 const struct anv_image
*image
,
3533 const VkImageAspectFlagBits aspect
,
3534 const VkImageLayout layout
);
3536 enum anv_fast_clear_type
3537 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3538 const struct anv_image
* const image
,
3539 const VkImageAspectFlagBits aspect
,
3540 const VkImageLayout layout
);
3542 /* This is defined as a macro so that it works for both
3543 * VkImageSubresourceRange and VkImageSubresourceLayers
3545 #define anv_get_layerCount(_image, _range) \
3546 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3547 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3549 static inline uint32_t
3550 anv_get_levelCount(const struct anv_image
*image
,
3551 const VkImageSubresourceRange
*range
)
3553 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3554 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3557 static inline VkImageAspectFlags
3558 anv_image_expand_aspects(const struct anv_image
*image
,
3559 VkImageAspectFlags aspects
)
3561 /* If the underlying image has color plane aspects and
3562 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3563 * the underlying image. */
3564 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3565 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3566 return image
->aspects
;
3572 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3573 VkImageAspectFlags aspects2
)
3575 if (aspects1
== aspects2
)
3578 /* Only 1 color aspects are compatibles. */
3579 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3580 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3581 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3587 struct anv_image_view
{
3588 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3590 VkImageAspectFlags aspect_mask
;
3592 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3596 uint32_t image_plane
;
3598 struct isl_view isl
;
3601 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3602 * image layout of SHADER_READ_ONLY_OPTIMAL or
3603 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3605 struct anv_surface_state optimal_sampler_surface_state
;
3608 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3609 * image layout of GENERAL.
3611 struct anv_surface_state general_sampler_surface_state
;
3614 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3615 * states for write-only and readable, using the real format for
3616 * write-only and the lowered format for readable.
3618 struct anv_surface_state storage_surface_state
;
3619 struct anv_surface_state writeonly_storage_surface_state
;
3621 struct brw_image_param storage_image_param
;
3625 enum anv_image_view_state_flags
{
3626 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3627 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3630 void anv_image_fill_surface_state(struct anv_device
*device
,
3631 const struct anv_image
*image
,
3632 VkImageAspectFlagBits aspect
,
3633 const struct isl_view
*view
,
3634 isl_surf_usage_flags_t view_usage
,
3635 enum isl_aux_usage aux_usage
,
3636 const union isl_color_value
*clear_color
,
3637 enum anv_image_view_state_flags flags
,
3638 struct anv_surface_state
*state_inout
,
3639 struct brw_image_param
*image_param_out
);
3641 struct anv_image_create_info
{
3642 const VkImageCreateInfo
*vk_info
;
3644 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3645 isl_tiling_flags_t isl_tiling_flags
;
3647 /** These flags will be added to any derived from VkImageCreateInfo. */
3648 isl_surf_usage_flags_t isl_extra_usage_flags
;
3651 bool external_format
;
3654 VkResult
anv_image_create(VkDevice _device
,
3655 const struct anv_image_create_info
*info
,
3656 const VkAllocationCallbacks
* alloc
,
3659 const struct anv_surface
*
3660 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3661 VkImageAspectFlags aspect_mask
);
3664 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3666 static inline struct VkExtent3D
3667 anv_sanitize_image_extent(const VkImageType imageType
,
3668 const struct VkExtent3D imageExtent
)
3670 switch (imageType
) {
3671 case VK_IMAGE_TYPE_1D
:
3672 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3673 case VK_IMAGE_TYPE_2D
:
3674 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3675 case VK_IMAGE_TYPE_3D
:
3678 unreachable("invalid image type");
3682 static inline struct VkOffset3D
3683 anv_sanitize_image_offset(const VkImageType imageType
,
3684 const struct VkOffset3D imageOffset
)
3686 switch (imageType
) {
3687 case VK_IMAGE_TYPE_1D
:
3688 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3689 case VK_IMAGE_TYPE_2D
:
3690 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3691 case VK_IMAGE_TYPE_3D
:
3694 unreachable("invalid image type");
3698 VkFormatFeatureFlags
3699 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3701 const struct anv_format
*anv_format
,
3702 VkImageTiling vk_tiling
);
3704 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3705 struct anv_state state
,
3706 enum isl_format format
,
3707 struct anv_address address
,
3708 uint32_t range
, uint32_t stride
);
3711 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3712 const struct anv_attachment_state
*att_state
,
3713 const struct anv_image_view
*iview
)
3715 const struct isl_format_layout
*view_fmtl
=
3716 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3718 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3719 if (view_fmtl->channels.c.bits) \
3720 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3722 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3723 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3724 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3725 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3727 #undef COPY_CLEAR_COLOR_CHANNEL
3731 struct anv_ycbcr_conversion
{
3732 const struct anv_format
* format
;
3733 VkSamplerYcbcrModelConversion ycbcr_model
;
3734 VkSamplerYcbcrRange ycbcr_range
;
3735 VkComponentSwizzle mapping
[4];
3736 VkChromaLocation chroma_offsets
[2];
3737 VkFilter chroma_filter
;
3738 bool chroma_reconstruction
;
3741 struct anv_sampler
{
3742 uint32_t state
[3][4];
3744 struct anv_ycbcr_conversion
*conversion
;
3746 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3747 * and with a 32-byte stride for use as bindless samplers.
3749 struct anv_state bindless_state
;
3752 struct anv_framebuffer
{
3757 uint32_t attachment_count
;
3758 struct anv_image_view
* attachments
[0];
3761 struct anv_subpass_attachment
{
3762 VkImageUsageFlagBits usage
;
3763 uint32_t attachment
;
3764 VkImageLayout layout
;
3766 /* Used only with attachment containing stencil data. */
3767 VkImageLayout stencil_layout
;
3770 struct anv_subpass
{
3771 uint32_t attachment_count
;
3774 * A pointer to all attachment references used in this subpass.
3775 * Only valid if ::attachment_count > 0.
3777 struct anv_subpass_attachment
* attachments
;
3778 uint32_t input_count
;
3779 struct anv_subpass_attachment
* input_attachments
;
3780 uint32_t color_count
;
3781 struct anv_subpass_attachment
* color_attachments
;
3782 struct anv_subpass_attachment
* resolve_attachments
;
3784 struct anv_subpass_attachment
* depth_stencil_attachment
;
3785 struct anv_subpass_attachment
* ds_resolve_attachment
;
3786 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3787 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3791 /** Subpass has a depth/stencil self-dependency */
3792 bool has_ds_self_dep
;
3794 /** Subpass has at least one color resolve attachment */
3795 bool has_color_resolve
;
3798 static inline unsigned
3799 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3801 return MAX2(1, util_bitcount(subpass
->view_mask
));
3804 struct anv_render_pass_attachment
{
3805 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3806 * its members individually.
3810 VkImageUsageFlags usage
;
3811 VkAttachmentLoadOp load_op
;
3812 VkAttachmentStoreOp store_op
;
3813 VkAttachmentLoadOp stencil_load_op
;
3814 VkImageLayout initial_layout
;
3815 VkImageLayout final_layout
;
3816 VkImageLayout first_subpass_layout
;
3818 VkImageLayout stencil_initial_layout
;
3819 VkImageLayout stencil_final_layout
;
3821 /* The subpass id in which the attachment will be used last. */
3822 uint32_t last_subpass_idx
;
3825 struct anv_render_pass
{
3826 uint32_t attachment_count
;
3827 uint32_t subpass_count
;
3828 /* An array of subpass_count+1 flushes, one per subpass boundary */
3829 enum anv_pipe_bits
* subpass_flushes
;
3830 struct anv_render_pass_attachment
* attachments
;
3831 struct anv_subpass subpasses
[0];
3834 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3836 struct anv_query_pool
{
3838 VkQueryPipelineStatisticFlags pipeline_statistics
;
3839 /** Stride between slots, in bytes */
3841 /** Number of slots in this query pool */
3846 int anv_get_instance_entrypoint_index(const char *name
);
3847 int anv_get_device_entrypoint_index(const char *name
);
3848 int anv_get_physical_device_entrypoint_index(const char *name
);
3850 const char *anv_get_instance_entry_name(int index
);
3851 const char *anv_get_physical_device_entry_name(int index
);
3852 const char *anv_get_device_entry_name(int index
);
3855 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3856 const struct anv_instance_extension_table
*instance
);
3858 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3859 const struct anv_instance_extension_table
*instance
);
3861 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3862 const struct anv_instance_extension_table
*instance
,
3863 const struct anv_device_extension_table
*device
);
3865 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3868 void anv_dump_image_to_ppm(struct anv_device
*device
,
3869 struct anv_image
*image
, unsigned miplevel
,
3870 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3871 const char *filename
);
3873 enum anv_dump_action
{
3874 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3877 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3878 void anv_dump_finish(void);
3880 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
3882 static inline uint32_t
3883 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3885 /* This function must be called from within a subpass. */
3886 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3888 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3890 /* The id of this subpass shouldn't exceed the number of subpasses in this
3891 * render pass minus 1.
3893 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3897 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
3898 void anv_device_perf_init(struct anv_device
*device
);
3900 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3902 static inline struct __anv_type * \
3903 __anv_type ## _from_handle(__VkType _handle) \
3905 return (struct __anv_type *) _handle; \
3908 static inline __VkType \
3909 __anv_type ## _to_handle(struct __anv_type *_obj) \
3911 return (__VkType) _obj; \
3914 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3916 static inline struct __anv_type * \
3917 __anv_type ## _from_handle(__VkType _handle) \
3919 return (struct __anv_type *)(uintptr_t) _handle; \
3922 static inline __VkType \
3923 __anv_type ## _to_handle(struct __anv_type *_obj) \
3925 return (__VkType)(uintptr_t) _obj; \
3928 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3929 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3931 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3932 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3933 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3934 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3935 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3937 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3938 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3939 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3940 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3941 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3942 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3943 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3944 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3945 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3946 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3947 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3948 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3949 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3950 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3951 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3952 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3953 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3954 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3955 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3956 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3957 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3958 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3959 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3961 /* Gen-specific function declarations */
3963 # include "anv_genX.h"
3965 # define genX(x) gen7_##x
3966 # include "anv_genX.h"
3968 # define genX(x) gen75_##x
3969 # include "anv_genX.h"
3971 # define genX(x) gen8_##x
3972 # include "anv_genX.h"
3974 # define genX(x) gen9_##x
3975 # include "anv_genX.h"
3977 # define genX(x) gen10_##x
3978 # include "anv_genX.h"
3980 # define genX(x) gen11_##x
3981 # include "anv_genX.h"
3983 # define genX(x) gen12_##x
3984 # include "anv_genX.h"
3988 #endif /* ANV_PRIVATE_H */