2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "compiler/brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
52 /* Pre-declarations needed for WSI entrypoints */
55 typedef struct xcb_connection_t xcb_connection_t
;
56 typedef uint32_t xcb_visualid_t
;
57 typedef uint32_t xcb_window_t
;
60 struct anv_buffer_view
;
61 struct anv_image_view
;
65 #include <vulkan/vulkan.h>
66 #include <vulkan/vulkan_intel.h>
67 #include <vulkan/vk_icd.h>
69 #include "anv_entrypoints.h"
72 #include "common/gen_debug.h"
73 #include "wsi_common.h"
75 /* Allowing different clear colors requires us to perform a depth resolve at
76 * the end of certain render passes. This is because while slow clears store
77 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
78 * See the PRMs for examples describing when additional resolves would be
79 * necessary. To enable fast clears without requiring extra resolves, we set
80 * the clear value to a globally-defined one. We could allow different values
81 * if the user doesn't expect coherent data during or after a render passes
82 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
83 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
84 * 1.0f seems to be the only value used. The only application that doesn't set
85 * this value does so through the usage of an seemingly uninitialized clear
88 #define ANV_HZ_FC_VAL 1.0f
93 #define MAX_VIEWPORTS 16
94 #define MAX_SCISSORS 16
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_DYNAMIC_BUFFERS 16
98 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
100 #define ANV_SVGS_VB_INDEX MAX_VBS
101 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
103 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
105 static inline uint32_t
106 align_down_npot_u32(uint32_t v
, uint32_t a
)
111 static inline uint32_t
112 align_u32(uint32_t v
, uint32_t a
)
114 assert(a
!= 0 && a
== (a
& -a
));
115 return (v
+ a
- 1) & ~(a
- 1);
118 static inline uint64_t
119 align_u64(uint64_t v
, uint64_t a
)
121 assert(a
!= 0 && a
== (a
& -a
));
122 return (v
+ a
- 1) & ~(a
- 1);
125 static inline int32_t
126 align_i32(int32_t v
, int32_t a
)
128 assert(a
!= 0 && a
== (a
& -a
));
129 return (v
+ a
- 1) & ~(a
- 1);
132 /** Alignment must be a power of 2. */
134 anv_is_aligned(uintmax_t n
, uintmax_t a
)
136 assert(a
== (a
& -a
));
137 return (n
& (a
- 1)) == 0;
140 static inline uint32_t
141 anv_minify(uint32_t n
, uint32_t levels
)
143 if (unlikely(n
== 0))
146 return MAX2(n
>> levels
, 1);
150 anv_clamp_f(float f
, float min
, float max
)
163 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
165 if (*inout_mask
& clear_mask
) {
166 *inout_mask
&= ~clear_mask
;
173 static inline union isl_color_value
174 vk_to_isl_color(VkClearColorValue color
)
176 return (union isl_color_value
) {
186 #define for_each_bit(b, dword) \
187 for (uint32_t __dword = (dword); \
188 (b) = __builtin_ffs(__dword) - 1, __dword; \
189 __dword &= ~(1 << (b)))
191 #define typed_memcpy(dest, src, count) ({ \
192 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
193 memcpy((dest), (src), (count) * sizeof(*(src))); \
196 /* Whenever we generate an error, pass it through this function. Useful for
197 * debugging, where we can break on it. Only call at error site, not when
198 * propagating errors. Might be useful to plug in a stack trace here.
201 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
204 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
205 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
206 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
208 #define vk_error(error) error
209 #define vk_errorf(error, format, ...) error
210 #define anv_debug(format, ...)
214 * Warn on ignored extension structs.
216 * The Vulkan spec requires us to ignore unsupported or unknown structs in
217 * a pNext chain. In debug mode, emitting warnings for ignored structs may
218 * help us discover structs that we should not have ignored.
221 * From the Vulkan 1.0.38 spec:
223 * Any component of the implementation (the loader, any enabled layers,
224 * and drivers) must skip over, without processing (other than reading the
225 * sType and pNext members) any chained structures with sType values not
226 * defined by extensions supported by that component.
228 #define anv_debug_ignored_stype(sType) \
229 anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType))
231 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
232 anv_printflike(3, 4);
233 void __anv_perf_warn(const char *file
, int line
, const char *format
, ...)
234 anv_printflike(3, 4);
235 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
236 void anv_loge_v(const char *format
, va_list va
);
239 * Print a FINISHME message, including its source location.
241 #define anv_finishme(format, ...) \
243 static bool reported = false; \
245 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
251 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
253 #define anv_perf_warn(format, ...) \
255 static bool reported = false; \
256 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
257 __anv_perf_warn(__FILE__, __LINE__, format, ##__VA_ARGS__); \
262 /* A non-fatal assert. Useful for debugging. */
264 #define anv_assert(x) ({ \
265 if (unlikely(!(x))) \
266 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
269 #define anv_assert(x)
273 * A dynamically growable, circular buffer. Elements are added at head and
274 * removed from tail. head and tail are free-running uint32_t indices and we
275 * only compute the modulo with size when accessing the array. This way,
276 * number of bytes in the queue is always head - tail, even in case of
283 /* Index into the current validation list. This is used by the
284 * validation list building alrogithm to track which buffers are already
285 * in the validation list so that we can ensure uniqueness.
289 /* Last known offset. This value is provided by the kernel when we
290 * execbuf and is used as the presumed offset for the next bunch of
298 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
303 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
305 bo
->gem_handle
= gem_handle
;
313 /* Represents a lock-free linked list of "free" things. This is used by
314 * both the block pool and the state pools. Unfortunately, in order to
315 * solve the ABA problem, we can't use a single uint32_t head.
317 union anv_free_list
{
321 /* A simple count that is incremented every time the head changes. */
327 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
329 struct anv_block_state
{
339 struct anv_block_pool
{
340 struct anv_device
*device
;
344 /* The offset from the start of the bo to the "center" of the block
345 * pool. Pointers to allocated blocks are given by
346 * bo.map + center_bo_offset + offsets.
348 uint32_t center_bo_offset
;
350 /* Current memory map of the block pool. This pointer may or may not
351 * point to the actual beginning of the block pool memory. If
352 * anv_block_pool_alloc_back has ever been called, then this pointer
353 * will point to the "center" position of the buffer and all offsets
354 * (negative or positive) given out by the block pool alloc functions
355 * will be valid relative to this pointer.
357 * In particular, map == bo.map + center_offset
363 * Array of mmaps and gem handles owned by the block pool, reclaimed when
364 * the block pool is destroyed.
366 struct u_vector mmap_cleanups
;
370 union anv_free_list free_list
;
371 struct anv_block_state state
;
373 union anv_free_list back_free_list
;
374 struct anv_block_state back_state
;
377 /* Block pools are backed by a fixed-size 1GB memfd */
378 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
380 /* The center of the block pool is also the middle of the memfd. This may
381 * change in the future if we decide differently for some reason.
383 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
385 static inline uint32_t
386 anv_block_pool_size(struct anv_block_pool
*pool
)
388 return pool
->state
.end
+ pool
->back_state
.end
;
397 struct anv_fixed_size_state_pool
{
399 union anv_free_list free_list
;
400 struct anv_block_state block
;
403 #define ANV_MIN_STATE_SIZE_LOG2 6
404 #define ANV_MAX_STATE_SIZE_LOG2 20
406 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
408 struct anv_state_pool
{
409 struct anv_block_pool
*block_pool
;
410 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
413 struct anv_state_stream_block
;
415 struct anv_state_stream
{
416 struct anv_block_pool
*block_pool
;
418 /* The current working block */
419 struct anv_state_stream_block
*block
;
421 /* Offset at which the current block starts */
423 /* Offset at which to allocate the next state */
425 /* Offset at which the current block ends */
429 #define CACHELINE_SIZE 64
430 #define CACHELINE_MASK 63
433 anv_clflush_range(void *start
, size_t size
)
435 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
436 void *end
= start
+ size
;
439 __builtin_ia32_clflush(p
);
445 anv_flush_range(void *start
, size_t size
)
447 __builtin_ia32_mfence();
448 anv_clflush_range(start
, size
);
452 anv_invalidate_range(void *start
, size_t size
)
454 anv_clflush_range(start
, size
);
455 __builtin_ia32_mfence();
458 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
459 struct anv_device
*device
, uint32_t block_size
);
460 void anv_block_pool_finish(struct anv_block_pool
*pool
);
461 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
);
462 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
);
463 void anv_block_pool_free(struct anv_block_pool
*pool
, int32_t offset
);
464 void anv_state_pool_init(struct anv_state_pool
*pool
,
465 struct anv_block_pool
*block_pool
);
466 void anv_state_pool_finish(struct anv_state_pool
*pool
);
467 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
468 size_t state_size
, size_t alignment
);
469 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
470 void anv_state_stream_init(struct anv_state_stream
*stream
,
471 struct anv_block_pool
*block_pool
);
472 void anv_state_stream_finish(struct anv_state_stream
*stream
);
473 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
474 uint32_t size
, uint32_t alignment
);
477 * Implements a pool of re-usable BOs. The interface is identical to that
478 * of block_pool except that each block is its own BO.
481 struct anv_device
*device
;
486 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
487 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
488 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
490 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
492 struct anv_scratch_bo
{
497 struct anv_scratch_pool
{
498 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
499 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
502 void anv_scratch_pool_init(struct anv_device
*device
,
503 struct anv_scratch_pool
*pool
);
504 void anv_scratch_pool_finish(struct anv_device
*device
,
505 struct anv_scratch_pool
*pool
);
506 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
507 struct anv_scratch_pool
*pool
,
508 gl_shader_stage stage
,
509 unsigned per_thread_scratch
);
511 struct anv_physical_device
{
512 VK_LOADER_DATA _loader_data
;
514 struct anv_instance
* instance
;
518 struct gen_device_info info
;
519 /** Amount of "GPU memory" we want to advertise
521 * Clearly, this value is bogus since Intel is a UMA architecture. On
522 * gen7 platforms, we are limited by GTT size unless we want to implement
523 * fine-grained tracking and GTT splitting. On Broadwell and above we are
524 * practically unlimited. However, we will never report more than 3/4 of
525 * the total system ram to try and avoid running out of RAM.
528 bool supports_48bit_addresses
;
529 struct brw_compiler
* compiler
;
530 struct isl_device isl_dev
;
531 int cmd_parser_version
;
534 uint32_t subslice_total
;
536 uint8_t uuid
[VK_UUID_SIZE
];
538 struct wsi_device wsi_device
;
542 struct anv_instance
{
543 VK_LOADER_DATA _loader_data
;
545 VkAllocationCallbacks alloc
;
548 int physicalDeviceCount
;
549 struct anv_physical_device physicalDevice
;
552 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
553 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
556 VK_LOADER_DATA _loader_data
;
558 struct anv_device
* device
;
560 struct anv_state_pool
* pool
;
563 struct anv_pipeline_cache
{
564 struct anv_device
* device
;
565 pthread_mutex_t mutex
;
567 struct hash_table
* cache
;
570 struct anv_pipeline_bind_map
;
572 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
573 struct anv_device
*device
,
575 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
577 struct anv_shader_bin
*
578 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
579 const void *key
, uint32_t key_size
);
580 struct anv_shader_bin
*
581 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
582 const void *key_data
, uint32_t key_size
,
583 const void *kernel_data
, uint32_t kernel_size
,
584 const struct brw_stage_prog_data
*prog_data
,
585 uint32_t prog_data_size
,
586 const struct anv_pipeline_bind_map
*bind_map
);
589 VK_LOADER_DATA _loader_data
;
591 VkAllocationCallbacks alloc
;
593 struct anv_instance
* instance
;
595 struct gen_device_info info
;
596 struct isl_device isl_dev
;
599 bool can_chain_batches
;
600 bool robust_buffer_access
;
602 struct anv_bo_pool batch_bo_pool
;
604 struct anv_block_pool dynamic_state_block_pool
;
605 struct anv_state_pool dynamic_state_pool
;
607 struct anv_block_pool instruction_block_pool
;
608 struct anv_state_pool instruction_state_pool
;
610 struct anv_block_pool surface_state_block_pool
;
611 struct anv_state_pool surface_state_pool
;
613 struct anv_bo workaround_bo
;
615 struct anv_pipeline_cache blorp_shader_cache
;
616 struct blorp_context blorp
;
618 struct anv_state border_colors
;
620 struct anv_queue queue
;
622 struct anv_scratch_pool scratch_pool
;
624 uint32_t default_mocs
;
626 pthread_mutex_t mutex
;
627 pthread_cond_t queue_submit
;
632 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
634 if (device
->info
.has_llc
)
637 anv_flush_range(state
.map
, state
.alloc_size
);
640 void anv_device_init_blorp(struct anv_device
*device
);
641 void anv_device_finish_blorp(struct anv_device
*device
);
643 VkResult
anv_device_execbuf(struct anv_device
*device
,
644 struct drm_i915_gem_execbuffer2
*execbuf
,
645 struct anv_bo
**execbuf_bos
);
646 VkResult
anv_device_query_status(struct anv_device
*device
);
647 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
650 void* anv_gem_mmap(struct anv_device
*device
,
651 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
652 void anv_gem_munmap(void *p
, uint64_t size
);
653 uint32_t anv_gem_create(struct anv_device
*device
, size_t size
);
654 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
655 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
656 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
657 int anv_gem_execbuffer(struct anv_device
*device
,
658 struct drm_i915_gem_execbuffer2
*execbuf
);
659 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
660 uint32_t stride
, uint32_t tiling
);
661 int anv_gem_create_context(struct anv_device
*device
);
662 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
663 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
665 int anv_gem_get_param(int fd
, uint32_t param
);
666 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
667 int anv_gem_get_aperture(int fd
, uint64_t *size
);
668 bool anv_gem_supports_48b_addresses(int fd
);
669 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
670 uint32_t *active
, uint32_t *pending
);
671 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
672 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
673 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
674 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
675 uint32_t read_domains
, uint32_t write_domain
);
677 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
679 struct anv_reloc_list
{
682 struct drm_i915_gem_relocation_entry
* relocs
;
683 struct anv_bo
** reloc_bos
;
686 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
687 const VkAllocationCallbacks
*alloc
);
688 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
689 const VkAllocationCallbacks
*alloc
);
691 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
692 const VkAllocationCallbacks
*alloc
,
693 uint32_t offset
, struct anv_bo
*target_bo
,
696 struct anv_batch_bo
{
697 /* Link in the anv_cmd_buffer.owned_batch_bos list */
698 struct list_head link
;
702 /* Bytes actually consumed in this batch BO */
705 struct anv_reloc_list relocs
;
709 const VkAllocationCallbacks
* alloc
;
715 struct anv_reloc_list
* relocs
;
717 /* This callback is called (with the associated user data) in the event
718 * that the batch runs out of space.
720 VkResult (*extend_cb
)(struct anv_batch
*, void *);
724 * Current error status of the command buffer. Used to track inconsistent
725 * or incomplete command buffer states that are the consequence of run-time
726 * errors such as out of memory scenarios. We want to track this in the
727 * batch because the command buffer object is not visible to some parts
733 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
734 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
735 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
736 void *location
, struct anv_bo
*bo
, uint32_t offset
);
737 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
738 struct anv_batch
*batch
);
740 static inline VkResult
741 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
743 assert(error
!= VK_SUCCESS
);
744 if (batch
->status
== VK_SUCCESS
)
745 batch
->status
= error
;
746 return batch
->status
;
750 anv_batch_has_error(struct anv_batch
*batch
)
752 return batch
->status
!= VK_SUCCESS
;
760 static inline uint64_t
761 _anv_combine_address(struct anv_batch
*batch
, void *location
,
762 const struct anv_address address
, uint32_t delta
)
764 if (address
.bo
== NULL
) {
765 return address
.offset
+ delta
;
767 assert(batch
->start
<= location
&& location
< batch
->end
);
769 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
773 #define __gen_address_type struct anv_address
774 #define __gen_user_data struct anv_batch
775 #define __gen_combine_address _anv_combine_address
777 /* Wrapper macros needed to work around preprocessor argument issues. In
778 * particular, arguments don't get pre-evaluated if they are concatenated.
779 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
780 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
781 * We can work around this easily enough with these helpers.
783 #define __anv_cmd_length(cmd) cmd ## _length
784 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
785 #define __anv_cmd_header(cmd) cmd ## _header
786 #define __anv_cmd_pack(cmd) cmd ## _pack
787 #define __anv_reg_num(reg) reg ## _num
789 #define anv_pack_struct(dst, struc, ...) do { \
790 struct struc __template = { \
793 __anv_cmd_pack(struc)(NULL, dst, &__template); \
794 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
797 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
798 void *__dst = anv_batch_emit_dwords(batch, n); \
800 struct cmd __template = { \
801 __anv_cmd_header(cmd), \
802 .DWordLength = n - __anv_cmd_length_bias(cmd), \
805 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
810 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
814 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
815 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
818 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
819 dw[i] = (dwords0)[i] | (dwords1)[i]; \
820 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
823 #define anv_batch_emit(batch, cmd, name) \
824 for (struct cmd name = { __anv_cmd_header(cmd) }, \
825 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
826 __builtin_expect(_dst != NULL, 1); \
827 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
828 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
832 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
833 .GraphicsDataTypeGFDT = 0, \
834 .LLCCacheabilityControlLLCCC = 0, \
835 .L3CacheabilityControlL3CC = 1, \
838 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
839 .LLCeLLCCacheabilityControlLLCCC = 0, \
840 .L3CacheabilityControlL3CC = 1, \
843 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
844 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
845 .TargetCache = L3DefertoPATforLLCeLLCselection, \
849 /* Skylake: MOCS is now an index into an array of 62 different caching
850 * configurations programmed by the kernel.
853 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
854 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
855 .IndextoMOCSTables = 2 \
858 #define GEN9_MOCS_PTE { \
859 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
860 .IndextoMOCSTables = 1 \
863 struct anv_device_memory
{
866 VkDeviceSize map_size
;
871 * Header for Vertex URB Entry (VUE)
873 struct anv_vue_header
{
875 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
876 uint32_t ViewportIndex
;
880 struct anv_descriptor_set_binding_layout
{
882 /* The type of the descriptors in this binding */
883 VkDescriptorType type
;
886 /* Number of array elements in this binding */
889 /* Index into the flattend descriptor set */
890 uint16_t descriptor_index
;
892 /* Index into the dynamic state array for a dynamic buffer */
893 int16_t dynamic_offset_index
;
895 /* Index into the descriptor set buffer views */
896 int16_t buffer_index
;
899 /* Index into the binding table for the associated surface */
900 int16_t surface_index
;
902 /* Index into the sampler table for the associated sampler */
903 int16_t sampler_index
;
905 /* Index into the image table for the associated image */
907 } stage
[MESA_SHADER_STAGES
];
909 /* Immutable samplers (or NULL if no immutable samplers) */
910 struct anv_sampler
**immutable_samplers
;
913 struct anv_descriptor_set_layout
{
914 /* Number of bindings in this descriptor set */
915 uint16_t binding_count
;
917 /* Total size of the descriptor set with room for all array entries */
920 /* Shader stages affected by this descriptor set */
921 uint16_t shader_stages
;
923 /* Number of buffers in this descriptor set */
924 uint16_t buffer_count
;
926 /* Number of dynamic offsets used by this descriptor set */
927 uint16_t dynamic_offset_count
;
929 /* Bindings in this descriptor set */
930 struct anv_descriptor_set_binding_layout binding
[0];
933 struct anv_descriptor
{
934 VkDescriptorType type
;
938 struct anv_image_view
*image_view
;
939 struct anv_sampler
*sampler
;
941 /* Used to determine whether or not we need the surface state to have
942 * the auxiliary buffer enabled.
944 enum isl_aux_usage aux_usage
;
948 struct anv_buffer
*buffer
;
953 struct anv_buffer_view
*buffer_view
;
957 struct anv_descriptor_set
{
958 const struct anv_descriptor_set_layout
*layout
;
960 uint32_t buffer_count
;
961 struct anv_buffer_view
*buffer_views
;
962 struct anv_descriptor descriptors
[0];
965 struct anv_buffer_view
{
966 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
968 uint32_t offset
; /**< Offset into bo. */
969 uint64_t range
; /**< VkBufferViewCreateInfo::range */
971 struct anv_state surface_state
;
972 struct anv_state storage_surface_state
;
973 struct anv_state writeonly_storage_surface_state
;
975 struct brw_image_param storage_image_param
;
978 struct anv_push_descriptor_set
{
979 struct anv_descriptor_set set
;
981 /* Put this field right behind anv_descriptor_set so it fills up the
982 * descriptors[0] field. */
983 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
985 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
988 struct anv_descriptor_pool
{
993 struct anv_state_stream surface_state_stream
;
994 void *surface_state_free_list
;
999 enum anv_descriptor_template_entry_type
{
1000 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1001 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1002 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1005 struct anv_descriptor_template_entry
{
1006 /* The type of descriptor in this entry */
1007 VkDescriptorType type
;
1009 /* Binding in the descriptor set */
1012 /* Offset at which to write into the descriptor set binding */
1013 uint32_t array_element
;
1015 /* Number of elements to write into the descriptor set binding */
1016 uint32_t array_count
;
1018 /* Offset into the user provided data */
1021 /* Stride between elements into the user provided data */
1025 struct anv_descriptor_update_template
{
1026 /* The descriptor set this template corresponds to. This value is only
1027 * valid if the template was created with the templateType
1028 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1032 /* Number of entries in this template */
1033 uint32_t entry_count
;
1035 /* Entries of the template */
1036 struct anv_descriptor_template_entry entries
[0];
1040 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1043 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1044 const struct gen_device_info
* const devinfo
,
1045 const VkDescriptorImageInfo
* const info
,
1046 VkDescriptorType type
,
1051 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1052 VkDescriptorType type
,
1053 struct anv_buffer_view
*buffer_view
,
1058 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1059 struct anv_device
*device
,
1060 struct anv_state_stream
*alloc_stream
,
1061 VkDescriptorType type
,
1062 struct anv_buffer
*buffer
,
1065 VkDeviceSize offset
,
1066 VkDeviceSize range
);
1069 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1070 struct anv_device
*device
,
1071 struct anv_state_stream
*alloc_stream
,
1072 const struct anv_descriptor_update_template
*template,
1076 anv_descriptor_set_create(struct anv_device
*device
,
1077 struct anv_descriptor_pool
*pool
,
1078 const struct anv_descriptor_set_layout
*layout
,
1079 struct anv_descriptor_set
**out_set
);
1082 anv_descriptor_set_destroy(struct anv_device
*device
,
1083 struct anv_descriptor_pool
*pool
,
1084 struct anv_descriptor_set
*set
);
1086 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1088 struct anv_pipeline_binding
{
1089 /* The descriptor set this surface corresponds to. The special value of
1090 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1091 * to a color attachment and not a regular descriptor.
1095 /* Binding in the descriptor set */
1098 /* Index in the binding */
1101 /* Input attachment index (relative to the subpass) */
1102 uint8_t input_attachment_index
;
1104 /* For a storage image, whether it is write-only */
1108 struct anv_pipeline_layout
{
1110 struct anv_descriptor_set_layout
*layout
;
1111 uint32_t dynamic_offset_start
;
1117 bool has_dynamic_offsets
;
1118 } stage
[MESA_SHADER_STAGES
];
1120 unsigned char sha1
[20];
1124 struct anv_device
* device
;
1127 VkBufferUsageFlags usage
;
1129 /* Set when bound */
1131 VkDeviceSize offset
;
1134 static inline uint64_t
1135 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1137 assert(offset
<= buffer
->size
);
1138 if (range
== VK_WHOLE_SIZE
) {
1139 return buffer
->size
- offset
;
1141 assert(range
<= buffer
->size
);
1146 enum anv_cmd_dirty_bits
{
1147 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1148 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1149 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1150 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1151 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1152 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1153 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1154 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1155 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1156 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1157 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1158 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1159 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1161 typedef uint32_t anv_cmd_dirty_mask_t
;
1163 enum anv_pipe_bits
{
1164 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1165 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1166 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1167 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1168 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1169 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1170 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1171 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1172 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1173 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1174 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1176 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1177 * a flush has happened but not a CS stall. The next time we do any sort
1178 * of invalidation we need to insert a CS stall at that time. Otherwise,
1179 * we would have to CS stall on every flush which could be bad.
1181 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1184 #define ANV_PIPE_FLUSH_BITS ( \
1185 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1186 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1187 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1189 #define ANV_PIPE_STALL_BITS ( \
1190 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1191 ANV_PIPE_DEPTH_STALL_BIT | \
1192 ANV_PIPE_CS_STALL_BIT)
1194 #define ANV_PIPE_INVALIDATE_BITS ( \
1195 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1196 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1197 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1198 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1199 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1200 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1202 struct anv_vertex_binding
{
1203 struct anv_buffer
* buffer
;
1204 VkDeviceSize offset
;
1207 struct anv_push_constants
{
1208 /* Current allocated size of this push constants data structure.
1209 * Because a decent chunk of it may not be used (images on SKL, for
1210 * instance), we won't actually allocate the entire structure up-front.
1214 /* Push constant data provided by the client through vkPushConstants */
1215 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1217 /* Our hardware only provides zero-based vertex and instance id so, in
1218 * order to satisfy the vulkan requirements, we may have to push one or
1219 * both of these into the shader.
1221 uint32_t base_vertex
;
1222 uint32_t base_instance
;
1224 /* Image data for image_load_store on pre-SKL */
1225 struct brw_image_param images
[MAX_IMAGES
];
1228 struct anv_dynamic_state
{
1231 VkViewport viewports
[MAX_VIEWPORTS
];
1236 VkRect2D scissors
[MAX_SCISSORS
];
1247 float blend_constants
[4];
1257 } stencil_compare_mask
;
1262 } stencil_write_mask
;
1267 } stencil_reference
;
1270 extern const struct anv_dynamic_state default_dynamic_state
;
1272 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1273 const struct anv_dynamic_state
*src
,
1274 uint32_t copy_mask
);
1277 * Attachment state when recording a renderpass instance.
1279 * The clear value is valid only if there exists a pending clear.
1281 struct anv_attachment_state
{
1282 enum isl_aux_usage aux_usage
;
1283 enum isl_aux_usage input_aux_usage
;
1284 struct anv_state color_rt_state
;
1285 struct anv_state input_att_state
;
1287 VkImageLayout current_layout
;
1288 VkImageAspectFlags pending_clear_aspects
;
1290 VkClearValue clear_value
;
1291 bool clear_color_is_zero_one
;
1294 /** State required while building cmd buffer */
1295 struct anv_cmd_state
{
1296 /* PIPELINE_SELECT.PipelineSelection */
1297 uint32_t current_pipeline
;
1298 const struct gen_l3_config
* current_l3_config
;
1300 anv_cmd_dirty_mask_t dirty
;
1301 anv_cmd_dirty_mask_t compute_dirty
;
1302 enum anv_pipe_bits pending_pipe_bits
;
1303 uint32_t num_workgroups_offset
;
1304 struct anv_bo
*num_workgroups_bo
;
1305 VkShaderStageFlags descriptors_dirty
;
1306 VkShaderStageFlags push_constants_dirty
;
1307 uint32_t scratch_size
;
1308 struct anv_pipeline
* pipeline
;
1309 struct anv_pipeline
* compute_pipeline
;
1310 struct anv_framebuffer
* framebuffer
;
1311 struct anv_render_pass
* pass
;
1312 struct anv_subpass
* subpass
;
1313 VkRect2D render_area
;
1314 uint32_t restart_index
;
1315 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1316 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1317 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
1318 VkShaderStageFlags push_constant_stages
;
1319 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1320 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1321 struct anv_state samplers
[MESA_SHADER_STAGES
];
1322 struct anv_dynamic_state dynamic
;
1325 struct anv_push_descriptor_set push_descriptor
;
1328 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1329 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1330 * and before invoking the secondary in ExecuteCommands.
1332 bool pma_fix_enabled
;
1335 * Whether or not we know for certain that HiZ is enabled for the current
1336 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1337 * enabled or not, this will be false.
1342 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1343 * valid only when recording a render pass instance.
1345 struct anv_attachment_state
* attachments
;
1348 * Surface states for color render targets. These are stored in a single
1349 * flat array. For depth-stencil attachments, the surface state is simply
1352 struct anv_state render_pass_states
;
1355 * A null surface state of the right size to match the framebuffer. This
1356 * is one of the states in render_pass_states.
1358 struct anv_state null_surface_state
;
1361 struct anv_buffer
* index_buffer
;
1362 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1363 uint32_t index_offset
;
1367 struct anv_cmd_pool
{
1368 VkAllocationCallbacks alloc
;
1369 struct list_head cmd_buffers
;
1372 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1374 enum anv_cmd_buffer_exec_mode
{
1375 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1376 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1377 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1378 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1379 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1382 struct anv_cmd_buffer
{
1383 VK_LOADER_DATA _loader_data
;
1385 struct anv_device
* device
;
1387 struct anv_cmd_pool
* pool
;
1388 struct list_head pool_link
;
1390 struct anv_batch batch
;
1392 /* Fields required for the actual chain of anv_batch_bo's.
1394 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1396 struct list_head batch_bos
;
1397 enum anv_cmd_buffer_exec_mode exec_mode
;
1399 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1400 * referenced by this command buffer
1402 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1404 struct u_vector seen_bbos
;
1406 /* A vector of int32_t's for every block of binding tables.
1408 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1410 struct u_vector bt_blocks
;
1413 struct anv_reloc_list surface_relocs
;
1414 /** Last seen surface state block pool center bo offset */
1415 uint32_t last_ss_pool_center
;
1417 /* Serial for tracking buffer completion */
1420 /* Stream objects for storing temporary data */
1421 struct anv_state_stream surface_state_stream
;
1422 struct anv_state_stream dynamic_state_stream
;
1424 VkCommandBufferUsageFlags usage_flags
;
1425 VkCommandBufferLevel level
;
1427 struct anv_cmd_state state
;
1430 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1431 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1432 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1433 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1434 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1435 struct anv_cmd_buffer
*secondary
);
1436 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1437 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1438 struct anv_cmd_buffer
*cmd_buffer
);
1440 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1443 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1444 gl_shader_stage stage
, uint32_t size
);
1445 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1446 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1447 (offsetof(struct anv_push_constants, field) + \
1448 sizeof(cmd_buffer->state.push_constants[0]->field)))
1450 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1451 const void *data
, uint32_t size
, uint32_t alignment
);
1452 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1453 uint32_t *a
, uint32_t *b
,
1454 uint32_t dwords
, uint32_t alignment
);
1457 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1459 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1460 uint32_t entries
, uint32_t *state_offset
);
1462 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1464 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1465 uint32_t size
, uint32_t alignment
);
1468 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1470 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1471 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1472 bool depth_clamp_enable
);
1473 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1475 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1476 struct anv_render_pass
*pass
,
1477 struct anv_framebuffer
*framebuffer
,
1478 const VkClearValue
*clear_values
);
1480 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1483 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1484 gl_shader_stage stage
);
1486 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1488 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1489 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1491 const struct anv_image_view
*
1492 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1495 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1496 uint32_t num_entries
,
1497 uint32_t *state_offset
,
1498 struct anv_state
*bt_state
);
1500 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1502 enum anv_fence_state
{
1503 /** Indicates that this is a new (or newly reset fence) */
1504 ANV_FENCE_STATE_RESET
,
1506 /** Indicates that this fence has been submitted to the GPU but is still
1507 * (as far as we know) in use by the GPU.
1509 ANV_FENCE_STATE_SUBMITTED
,
1511 ANV_FENCE_STATE_SIGNALED
,
1516 struct drm_i915_gem_execbuffer2 execbuf
;
1517 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1518 enum anv_fence_state state
;
1523 struct anv_state state
;
1526 struct anv_shader_module
{
1527 unsigned char sha1
[20];
1532 void anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
1533 struct anv_shader_module
*module
,
1534 const char *entrypoint
,
1535 const struct anv_pipeline_layout
*pipeline_layout
,
1536 const VkSpecializationInfo
*spec_info
);
1538 static inline gl_shader_stage
1539 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1541 assert(__builtin_popcount(vk_stage
) == 1);
1542 return ffs(vk_stage
) - 1;
1545 static inline VkShaderStageFlagBits
1546 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1548 return (1 << mesa_stage
);
1551 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1553 #define anv_foreach_stage(stage, stage_bits) \
1554 for (gl_shader_stage stage, \
1555 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1556 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1557 __tmp &= ~(1 << (stage)))
1559 struct anv_pipeline_bind_map
{
1560 uint32_t surface_count
;
1561 uint32_t sampler_count
;
1562 uint32_t image_count
;
1564 struct anv_pipeline_binding
* surface_to_descriptor
;
1565 struct anv_pipeline_binding
* sampler_to_descriptor
;
1568 struct anv_shader_bin_key
{
1573 struct anv_shader_bin
{
1576 const struct anv_shader_bin_key
*key
;
1578 struct anv_state kernel
;
1579 uint32_t kernel_size
;
1581 const struct brw_stage_prog_data
*prog_data
;
1582 uint32_t prog_data_size
;
1584 struct anv_pipeline_bind_map bind_map
;
1586 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1589 struct anv_shader_bin
*
1590 anv_shader_bin_create(struct anv_device
*device
,
1591 const void *key
, uint32_t key_size
,
1592 const void *kernel
, uint32_t kernel_size
,
1593 const struct brw_stage_prog_data
*prog_data
,
1594 uint32_t prog_data_size
, const void *prog_data_param
,
1595 const struct anv_pipeline_bind_map
*bind_map
);
1598 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1601 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1603 assert(shader
&& shader
->ref_cnt
>= 1);
1604 __sync_fetch_and_add(&shader
->ref_cnt
, 1);
1608 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1610 assert(shader
&& shader
->ref_cnt
>= 1);
1611 if (__sync_fetch_and_add(&shader
->ref_cnt
, -1) == 1)
1612 anv_shader_bin_destroy(device
, shader
);
1615 struct anv_pipeline
{
1616 struct anv_device
* device
;
1617 struct anv_batch batch
;
1618 uint32_t batch_data
[512];
1619 struct anv_reloc_list batch_relocs
;
1620 uint32_t dynamic_state_mask
;
1621 struct anv_dynamic_state dynamic_state
;
1623 struct anv_pipeline_layout
* layout
;
1625 bool needs_data_cache
;
1627 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1630 const struct gen_l3_config
* l3_config
;
1631 uint32_t total_size
;
1634 VkShaderStageFlags active_stages
;
1635 struct anv_state blend_state
;
1638 uint32_t binding_stride
[MAX_VBS
];
1639 bool instancing_enable
[MAX_VBS
];
1640 bool primitive_restart
;
1643 uint32_t cs_right_mask
;
1646 bool depth_test_enable
;
1647 bool writes_stencil
;
1648 bool stencil_test_enable
;
1649 bool depth_clamp_enable
;
1650 bool sample_shading_enable
;
1655 uint32_t depth_stencil_state
[3];
1661 uint32_t wm_depth_stencil
[3];
1665 uint32_t wm_depth_stencil
[4];
1668 uint32_t interface_descriptor_data
[8];
1672 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1673 gl_shader_stage stage
)
1675 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1678 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1679 static inline const struct brw_##prefix##_prog_data * \
1680 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1682 if (anv_pipeline_has_stage(pipeline, stage)) { \
1683 return (const struct brw_##prefix##_prog_data *) \
1684 pipeline->shaders[stage]->prog_data; \
1690 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1691 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
1692 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
1693 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1694 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1695 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1697 static inline const struct brw_vue_prog_data
*
1698 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
1700 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1701 return &get_gs_prog_data(pipeline
)->base
;
1702 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1703 return &get_tes_prog_data(pipeline
)->base
;
1705 return &get_vs_prog_data(pipeline
)->base
;
1709 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1710 struct anv_pipeline_cache
*cache
,
1711 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1712 const VkAllocationCallbacks
*alloc
);
1715 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1716 struct anv_pipeline_cache
*cache
,
1717 const VkComputePipelineCreateInfo
*info
,
1718 struct anv_shader_module
*module
,
1719 const char *entrypoint
,
1720 const VkSpecializationInfo
*spec_info
);
1723 enum isl_format isl_format
:16;
1724 struct isl_swizzle swizzle
;
1728 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1729 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1731 static inline enum isl_format
1732 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1733 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1735 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1738 static inline struct isl_swizzle
1739 anv_swizzle_for_render(struct isl_swizzle swizzle
)
1741 /* Sometimes the swizzle will have alpha map to one. We do this to fake
1742 * RGB as RGBA for texturing
1744 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
1745 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
1747 /* But it doesn't matter what we render to that channel */
1748 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
1754 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
1757 * Subsurface of an anv_image.
1759 struct anv_surface
{
1760 /** Valid only if isl_surf::size > 0. */
1761 struct isl_surf isl
;
1764 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1771 /* The original VkFormat provided by the client. This may not match any
1772 * of the actual surface formats.
1775 VkImageAspectFlags aspects
;
1778 uint32_t array_size
;
1779 uint32_t samples
; /**< VkImageCreateInfo::samples */
1780 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1781 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1786 /* Set when bound */
1788 VkDeviceSize offset
;
1793 * For each foo, anv_image::foo_surface is valid if and only if
1794 * anv_image::aspects has a foo aspect.
1796 * The hardware requires that the depth buffer and stencil buffer be
1797 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1798 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1799 * allocate the depth and stencil buffers as separate surfaces in the same
1803 struct anv_surface color_surface
;
1806 struct anv_surface depth_surface
;
1807 struct anv_surface stencil_surface
;
1812 * For color images, this is the aux usage for this image when not used as a
1815 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
1818 enum isl_aux_usage aux_usage
;
1820 struct anv_surface aux_surface
;
1823 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
1825 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
1826 const VkImageAspectFlags aspect_mask
,
1827 const uint32_t samples
)
1829 /* Validate the inputs. */
1830 assert(devinfo
&& aspect_mask
&& samples
);
1831 return devinfo
->gen
>= 8 && (aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1836 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
1837 const struct anv_image
*image
,
1838 enum blorp_hiz_op op
);
1841 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
1842 const struct anv_image
*image
,
1843 const VkImageAspectFlags aspects
,
1844 const VkImageLayout layout
);
1846 /* This is defined as a macro so that it works for both
1847 * VkImageSubresourceRange and VkImageSubresourceLayers
1849 #define anv_get_layerCount(_image, _range) \
1850 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
1851 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
1853 static inline uint32_t
1854 anv_get_levelCount(const struct anv_image
*image
,
1855 const VkImageSubresourceRange
*range
)
1857 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1858 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1862 struct anv_image_view
{
1863 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
1865 uint32_t offset
; /**< Offset into bo. */
1867 struct isl_view isl
;
1869 VkImageAspectFlags aspect_mask
;
1871 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1873 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1874 struct anv_state sampler_surface_state
;
1877 * RENDER_SURFACE_STATE when using image as a sampler surface with the
1878 * auxiliary buffer disabled.
1880 struct anv_state no_aux_sampler_surface_state
;
1883 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
1884 * for write-only and readable, using the real format for write-only and the
1885 * lowered format for readable.
1887 struct anv_state storage_surface_state
;
1888 struct anv_state writeonly_storage_surface_state
;
1890 struct brw_image_param storage_image_param
;
1893 struct anv_image_create_info
{
1894 const VkImageCreateInfo
*vk_info
;
1896 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1897 isl_tiling_flags_t isl_tiling_flags
;
1902 VkResult
anv_image_create(VkDevice _device
,
1903 const struct anv_image_create_info
*info
,
1904 const VkAllocationCallbacks
* alloc
,
1907 const struct anv_surface
*
1908 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1909 VkImageAspectFlags aspect_mask
);
1912 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
1914 static inline struct VkExtent3D
1915 anv_sanitize_image_extent(const VkImageType imageType
,
1916 const struct VkExtent3D imageExtent
)
1918 switch (imageType
) {
1919 case VK_IMAGE_TYPE_1D
:
1920 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1921 case VK_IMAGE_TYPE_2D
:
1922 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1923 case VK_IMAGE_TYPE_3D
:
1926 unreachable("invalid image type");
1930 static inline struct VkOffset3D
1931 anv_sanitize_image_offset(const VkImageType imageType
,
1932 const struct VkOffset3D imageOffset
)
1934 switch (imageType
) {
1935 case VK_IMAGE_TYPE_1D
:
1936 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1937 case VK_IMAGE_TYPE_2D
:
1938 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1939 case VK_IMAGE_TYPE_3D
:
1942 unreachable("invalid image type");
1947 void anv_fill_buffer_surface_state(struct anv_device
*device
,
1948 struct anv_state state
,
1949 enum isl_format format
,
1950 uint32_t offset
, uint32_t range
,
1953 void anv_image_view_fill_image_param(struct anv_device
*device
,
1954 struct anv_image_view
*view
,
1955 struct brw_image_param
*param
);
1956 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
1957 struct anv_buffer_view
*view
,
1958 struct brw_image_param
*param
);
1960 struct anv_sampler
{
1964 struct anv_framebuffer
{
1969 uint32_t attachment_count
;
1970 struct anv_image_view
* attachments
[0];
1973 struct anv_subpass
{
1974 uint32_t attachment_count
;
1977 * A pointer to all attachment references used in this subpass.
1978 * Only valid if ::attachment_count > 0.
1980 VkAttachmentReference
* attachments
;
1981 uint32_t input_count
;
1982 VkAttachmentReference
* input_attachments
;
1983 uint32_t color_count
;
1984 VkAttachmentReference
* color_attachments
;
1985 VkAttachmentReference
* resolve_attachments
;
1987 VkAttachmentReference depth_stencil_attachment
;
1989 /** Subpass has a depth/stencil self-dependency */
1990 bool has_ds_self_dep
;
1992 /** Subpass has at least one resolve attachment */
1996 enum anv_subpass_usage
{
1997 ANV_SUBPASS_USAGE_DRAW
= (1 << 0),
1998 ANV_SUBPASS_USAGE_INPUT
= (1 << 1),
1999 ANV_SUBPASS_USAGE_RESOLVE_SRC
= (1 << 2),
2000 ANV_SUBPASS_USAGE_RESOLVE_DST
= (1 << 3),
2003 struct anv_render_pass_attachment
{
2004 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2005 * its members individually.
2009 VkImageUsageFlags usage
;
2010 VkAttachmentLoadOp load_op
;
2011 VkAttachmentStoreOp store_op
;
2012 VkAttachmentLoadOp stencil_load_op
;
2013 VkImageLayout initial_layout
;
2014 VkImageLayout final_layout
;
2016 /* An array, indexed by subpass id, of how the attachment will be used. */
2017 enum anv_subpass_usage
* subpass_usage
;
2019 /* The subpass id in which the attachment will be used last. */
2020 uint32_t last_subpass_idx
;
2023 struct anv_render_pass
{
2024 uint32_t attachment_count
;
2025 uint32_t subpass_count
;
2026 VkAttachmentReference
* subpass_attachments
;
2027 enum anv_subpass_usage
* subpass_usages
;
2028 struct anv_render_pass_attachment
* attachments
;
2029 struct anv_subpass subpasses
[0];
2032 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2034 struct anv_query_pool
{
2036 VkQueryPipelineStatisticFlags pipeline_statistics
;
2037 /** Stride between slots, in bytes */
2039 /** Number of slots in this query pool */
2044 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
2047 void anv_dump_image_to_ppm(struct anv_device
*device
,
2048 struct anv_image
*image
, unsigned miplevel
,
2049 unsigned array_layer
, VkImageAspectFlagBits aspect
,
2050 const char *filename
);
2052 enum anv_dump_action
{
2053 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
2056 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
2057 void anv_dump_finish(void);
2059 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
2060 struct anv_framebuffer
*fb
);
2062 static inline uint32_t
2063 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
2065 /* This function must be called from within a subpass. */
2066 assert(cmd_state
->pass
&& cmd_state
->subpass
);
2068 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
2070 /* The id of this subpass shouldn't exceed the number of subpasses in this
2071 * render pass minus 1.
2073 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
2077 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2079 static inline struct __anv_type * \
2080 __anv_type ## _from_handle(__VkType _handle) \
2082 return (struct __anv_type *) _handle; \
2085 static inline __VkType \
2086 __anv_type ## _to_handle(struct __anv_type *_obj) \
2088 return (__VkType) _obj; \
2091 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2093 static inline struct __anv_type * \
2094 __anv_type ## _from_handle(__VkType _handle) \
2096 return (struct __anv_type *)(uintptr_t) _handle; \
2099 static inline __VkType \
2100 __anv_type ## _to_handle(struct __anv_type *_obj) \
2102 return (__VkType)(uintptr_t) _obj; \
2105 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2106 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2108 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
2109 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
2110 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
2111 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
2112 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
2114 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
2115 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
2116 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
2117 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
2118 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
2119 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
2120 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
2121 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
2122 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
2123 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
2124 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
2125 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
2126 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
2127 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
2128 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
2129 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
2130 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
2131 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
2132 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
2133 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
2135 /* Gen-specific function declarations */
2137 # include "anv_genX.h"
2139 # define genX(x) gen7_##x
2140 # include "anv_genX.h"
2142 # define genX(x) gen75_##x
2143 # include "anv_genX.h"
2145 # define genX(x) gen8_##x
2146 # include "anv_genX.h"
2148 # define genX(x) gen9_##x
2149 # include "anv_genX.h"
2153 #endif /* ANV_PRIVATE_H */