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anv/entrypoints: Split entrypoint index lookup into its own function
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 /* Pre-declarations needed for WSI entrypoints */
56 struct wl_surface;
57 struct wl_display;
58 typedef struct xcb_connection_t xcb_connection_t;
59 typedef uint32_t xcb_visualid_t;
60 typedef uint32_t xcb_window_t;
61
62 struct anv_buffer;
63 struct anv_buffer_view;
64 struct anv_image_view;
65 struct anv_instance;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72 #include <vulkan/vk_android_native_buffer.h>
73
74 #include "anv_entrypoints.h"
75 #include "anv_extensions.h"
76 #include "isl/isl.h"
77
78 #include "common/gen_debug.h"
79 #include "common/intel_log.h"
80 #include "wsi_common.h"
81
82 /* Allowing different clear colors requires us to perform a depth resolve at
83 * the end of certain render passes. This is because while slow clears store
84 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
85 * See the PRMs for examples describing when additional resolves would be
86 * necessary. To enable fast clears without requiring extra resolves, we set
87 * the clear value to a globally-defined one. We could allow different values
88 * if the user doesn't expect coherent data during or after a render passes
89 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
90 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
91 * 1.0f seems to be the only value used. The only application that doesn't set
92 * this value does so through the usage of an seemingly uninitialized clear
93 * value.
94 */
95 #define ANV_HZ_FC_VAL 1.0f
96
97 #define MAX_VBS 28
98 #define MAX_SETS 8
99 #define MAX_RTS 8
100 #define MAX_VIEWPORTS 16
101 #define MAX_SCISSORS 16
102 #define MAX_PUSH_CONSTANTS_SIZE 128
103 #define MAX_DYNAMIC_BUFFERS 16
104 #define MAX_IMAGES 8
105 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
106
107 #define ANV_SVGS_VB_INDEX MAX_VBS
108 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
109
110 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
111
112 static inline uint32_t
113 align_down_npot_u32(uint32_t v, uint32_t a)
114 {
115 return v - (v % a);
116 }
117
118 static inline uint32_t
119 align_u32(uint32_t v, uint32_t a)
120 {
121 assert(a != 0 && a == (a & -a));
122 return (v + a - 1) & ~(a - 1);
123 }
124
125 static inline uint64_t
126 align_u64(uint64_t v, uint64_t a)
127 {
128 assert(a != 0 && a == (a & -a));
129 return (v + a - 1) & ~(a - 1);
130 }
131
132 static inline int32_t
133 align_i32(int32_t v, int32_t a)
134 {
135 assert(a != 0 && a == (a & -a));
136 return (v + a - 1) & ~(a - 1);
137 }
138
139 /** Alignment must be a power of 2. */
140 static inline bool
141 anv_is_aligned(uintmax_t n, uintmax_t a)
142 {
143 assert(a == (a & -a));
144 return (n & (a - 1)) == 0;
145 }
146
147 static inline uint32_t
148 anv_minify(uint32_t n, uint32_t levels)
149 {
150 if (unlikely(n == 0))
151 return 0;
152 else
153 return MAX2(n >> levels, 1);
154 }
155
156 static inline float
157 anv_clamp_f(float f, float min, float max)
158 {
159 assert(min < max);
160
161 if (f > max)
162 return max;
163 else if (f < min)
164 return min;
165 else
166 return f;
167 }
168
169 static inline bool
170 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
171 {
172 if (*inout_mask & clear_mask) {
173 *inout_mask &= ~clear_mask;
174 return true;
175 } else {
176 return false;
177 }
178 }
179
180 static inline union isl_color_value
181 vk_to_isl_color(VkClearColorValue color)
182 {
183 return (union isl_color_value) {
184 .u32 = {
185 color.uint32[0],
186 color.uint32[1],
187 color.uint32[2],
188 color.uint32[3],
189 },
190 };
191 }
192
193 #define for_each_bit(b, dword) \
194 for (uint32_t __dword = (dword); \
195 (b) = __builtin_ffs(__dword) - 1, __dword; \
196 __dword &= ~(1 << (b)))
197
198 #define typed_memcpy(dest, src, count) ({ \
199 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
200 memcpy((dest), (src), (count) * sizeof(*(src))); \
201 })
202
203 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
204 * to be added here in order to utilize mapping in debug/error/perf macros.
205 */
206 #define REPORT_OBJECT_TYPE(o) \
207 __builtin_choose_expr ( \
208 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
209 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
210 __builtin_choose_expr ( \
211 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
212 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
213 __builtin_choose_expr ( \
214 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
215 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
216 __builtin_choose_expr ( \
217 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
218 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
219 __builtin_choose_expr ( \
220 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
221 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
222 __builtin_choose_expr ( \
223 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
224 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
225 __builtin_choose_expr ( \
226 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
227 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
228 __builtin_choose_expr ( \
229 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
230 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
231 __builtin_choose_expr ( \
232 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
233 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
234 __builtin_choose_expr ( \
235 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
236 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
237 __builtin_choose_expr ( \
238 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
239 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
240 __builtin_choose_expr ( \
241 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
242 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
243 __builtin_choose_expr ( \
244 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
245 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
246 __builtin_choose_expr ( \
247 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
248 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
249 __builtin_choose_expr ( \
250 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
251 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
252 __builtin_choose_expr ( \
253 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
254 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
255 __builtin_choose_expr ( \
256 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
257 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
258 __builtin_choose_expr ( \
259 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
260 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
261 __builtin_choose_expr ( \
262 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
263 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
264 __builtin_choose_expr ( \
265 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
266 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
267 __builtin_choose_expr ( \
268 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
269 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
270 __builtin_choose_expr ( \
271 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
272 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
273 __builtin_choose_expr ( \
274 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
275 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
276 __builtin_choose_expr ( \
277 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
278 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
279 __builtin_choose_expr ( \
280 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
281 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
282 __builtin_choose_expr ( \
283 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
284 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
285 __builtin_choose_expr ( \
286 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
287 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
288 __builtin_choose_expr ( \
289 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
290 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
291 __builtin_choose_expr ( \
292 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
293 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
294 __builtin_choose_expr ( \
295 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
296 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
297 __builtin_choose_expr ( \
298 __builtin_types_compatible_p (__typeof (o), void*), \
299 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
300 /* The void expression results in a compile-time error \
301 when assigning the result to something. */ \
302 (void)0)))))))))))))))))))))))))))))))
303
304 /* Whenever we generate an error, pass it through this function. Useful for
305 * debugging, where we can break on it. Only call at error site, not when
306 * propagating errors. Might be useful to plug in a stack trace here.
307 */
308
309 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
310 VkDebugReportObjectTypeEXT type, VkResult error,
311 const char *file, int line, const char *format, ...);
312
313 #ifdef DEBUG
314 #define vk_error(error) __vk_errorf(NULL, NULL,\
315 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
316 error, __FILE__, __LINE__, NULL);
317 #define vk_errorf(instance, obj, error, format, ...)\
318 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
319 __FILE__, __LINE__, format, ## __VA_ARGS__);
320 #else
321 #define vk_error(error) error
322 #define vk_errorf(instance, obj, error, format, ...) error
323 #endif
324
325 /**
326 * Warn on ignored extension structs.
327 *
328 * The Vulkan spec requires us to ignore unsupported or unknown structs in
329 * a pNext chain. In debug mode, emitting warnings for ignored structs may
330 * help us discover structs that we should not have ignored.
331 *
332 *
333 * From the Vulkan 1.0.38 spec:
334 *
335 * Any component of the implementation (the loader, any enabled layers,
336 * and drivers) must skip over, without processing (other than reading the
337 * sType and pNext members) any chained structures with sType values not
338 * defined by extensions supported by that component.
339 */
340 #define anv_debug_ignored_stype(sType) \
341 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
342
343 void __anv_perf_warn(struct anv_instance *instance, const void *object,
344 VkDebugReportObjectTypeEXT type, const char *file,
345 int line, const char *format, ...)
346 anv_printflike(6, 7);
347 void anv_loge(const char *format, ...) anv_printflike(1, 2);
348 void anv_loge_v(const char *format, va_list va);
349
350 /**
351 * Print a FINISHME message, including its source location.
352 */
353 #define anv_finishme(format, ...) \
354 do { \
355 static bool reported = false; \
356 if (!reported) { \
357 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
358 ##__VA_ARGS__); \
359 reported = true; \
360 } \
361 } while (0)
362
363 /**
364 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
365 */
366 #define anv_perf_warn(instance, obj, format, ...) \
367 do { \
368 static bool reported = false; \
369 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
370 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
371 format, ##__VA_ARGS__); \
372 reported = true; \
373 } \
374 } while (0)
375
376 /* A non-fatal assert. Useful for debugging. */
377 #ifdef DEBUG
378 #define anv_assert(x) ({ \
379 if (unlikely(!(x))) \
380 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
381 })
382 #else
383 #define anv_assert(x)
384 #endif
385
386 /* A multi-pointer allocator
387 *
388 * When copying data structures from the user (such as a render pass), it's
389 * common to need to allocate data for a bunch of different things. Instead
390 * of doing several allocations and having to handle all of the error checking
391 * that entails, it can be easier to do a single allocation. This struct
392 * helps facilitate that. The intended usage looks like this:
393 *
394 * ANV_MULTIALLOC(ma)
395 * anv_multialloc_add(&ma, &main_ptr, 1);
396 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
397 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
398 *
399 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
400 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
401 */
402 struct anv_multialloc {
403 size_t size;
404 size_t align;
405
406 uint32_t ptr_count;
407 void **ptrs[8];
408 };
409
410 #define ANV_MULTIALLOC_INIT \
411 ((struct anv_multialloc) { 0, })
412
413 #define ANV_MULTIALLOC(_name) \
414 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
415
416 __attribute__((always_inline))
417 static inline void
418 _anv_multialloc_add(struct anv_multialloc *ma,
419 void **ptr, size_t size, size_t align)
420 {
421 size_t offset = align_u64(ma->size, align);
422 ma->size = offset + size;
423 ma->align = MAX2(ma->align, align);
424
425 /* Store the offset in the pointer. */
426 *ptr = (void *)(uintptr_t)offset;
427
428 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
429 ma->ptrs[ma->ptr_count++] = ptr;
430 }
431
432 #define anv_multialloc_add_size(_ma, _ptr, _size) \
433 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
434
435 #define anv_multialloc_add(_ma, _ptr, _count) \
436 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
437
438 __attribute__((always_inline))
439 static inline void *
440 anv_multialloc_alloc(struct anv_multialloc *ma,
441 const VkAllocationCallbacks *alloc,
442 VkSystemAllocationScope scope)
443 {
444 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
445 if (!ptr)
446 return NULL;
447
448 /* Fill out each of the pointers with their final value.
449 *
450 * for (uint32_t i = 0; i < ma->ptr_count; i++)
451 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
452 *
453 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
454 * constant, GCC is incapable of figuring this out and unrolling the loop
455 * so we have to give it a little help.
456 */
457 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
458 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
459 if ((_i) < ma->ptr_count) \
460 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
461 _ANV_MULTIALLOC_UPDATE_POINTER(0);
462 _ANV_MULTIALLOC_UPDATE_POINTER(1);
463 _ANV_MULTIALLOC_UPDATE_POINTER(2);
464 _ANV_MULTIALLOC_UPDATE_POINTER(3);
465 _ANV_MULTIALLOC_UPDATE_POINTER(4);
466 _ANV_MULTIALLOC_UPDATE_POINTER(5);
467 _ANV_MULTIALLOC_UPDATE_POINTER(6);
468 _ANV_MULTIALLOC_UPDATE_POINTER(7);
469 #undef _ANV_MULTIALLOC_UPDATE_POINTER
470
471 return ptr;
472 }
473
474 __attribute__((always_inline))
475 static inline void *
476 anv_multialloc_alloc2(struct anv_multialloc *ma,
477 const VkAllocationCallbacks *parent_alloc,
478 const VkAllocationCallbacks *alloc,
479 VkSystemAllocationScope scope)
480 {
481 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
482 }
483
484 struct anv_bo {
485 uint32_t gem_handle;
486
487 /* Index into the current validation list. This is used by the
488 * validation list building alrogithm to track which buffers are already
489 * in the validation list so that we can ensure uniqueness.
490 */
491 uint32_t index;
492
493 /* Last known offset. This value is provided by the kernel when we
494 * execbuf and is used as the presumed offset for the next bunch of
495 * relocations.
496 */
497 uint64_t offset;
498
499 uint64_t size;
500 void *map;
501
502 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
503 uint32_t flags;
504 };
505
506 static inline void
507 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
508 {
509 bo->gem_handle = gem_handle;
510 bo->index = 0;
511 bo->offset = -1;
512 bo->size = size;
513 bo->map = NULL;
514 bo->flags = 0;
515 }
516
517 /* Represents a lock-free linked list of "free" things. This is used by
518 * both the block pool and the state pools. Unfortunately, in order to
519 * solve the ABA problem, we can't use a single uint32_t head.
520 */
521 union anv_free_list {
522 struct {
523 int32_t offset;
524
525 /* A simple count that is incremented every time the head changes. */
526 uint32_t count;
527 };
528 uint64_t u64;
529 };
530
531 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
532
533 struct anv_block_state {
534 union {
535 struct {
536 uint32_t next;
537 uint32_t end;
538 };
539 uint64_t u64;
540 };
541 };
542
543 struct anv_block_pool {
544 struct anv_device *device;
545
546 uint64_t bo_flags;
547
548 struct anv_bo bo;
549
550 /* The offset from the start of the bo to the "center" of the block
551 * pool. Pointers to allocated blocks are given by
552 * bo.map + center_bo_offset + offsets.
553 */
554 uint32_t center_bo_offset;
555
556 /* Current memory map of the block pool. This pointer may or may not
557 * point to the actual beginning of the block pool memory. If
558 * anv_block_pool_alloc_back has ever been called, then this pointer
559 * will point to the "center" position of the buffer and all offsets
560 * (negative or positive) given out by the block pool alloc functions
561 * will be valid relative to this pointer.
562 *
563 * In particular, map == bo.map + center_offset
564 */
565 void *map;
566 int fd;
567
568 /**
569 * Array of mmaps and gem handles owned by the block pool, reclaimed when
570 * the block pool is destroyed.
571 */
572 struct u_vector mmap_cleanups;
573
574 struct anv_block_state state;
575
576 struct anv_block_state back_state;
577 };
578
579 /* Block pools are backed by a fixed-size 1GB memfd */
580 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
581
582 /* The center of the block pool is also the middle of the memfd. This may
583 * change in the future if we decide differently for some reason.
584 */
585 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
586
587 static inline uint32_t
588 anv_block_pool_size(struct anv_block_pool *pool)
589 {
590 return pool->state.end + pool->back_state.end;
591 }
592
593 struct anv_state {
594 int32_t offset;
595 uint32_t alloc_size;
596 void *map;
597 };
598
599 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
600
601 struct anv_fixed_size_state_pool {
602 union anv_free_list free_list;
603 struct anv_block_state block;
604 };
605
606 #define ANV_MIN_STATE_SIZE_LOG2 6
607 #define ANV_MAX_STATE_SIZE_LOG2 20
608
609 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
610
611 struct anv_state_pool {
612 struct anv_block_pool block_pool;
613
614 /* The size of blocks which will be allocated from the block pool */
615 uint32_t block_size;
616
617 /** Free list for "back" allocations */
618 union anv_free_list back_alloc_free_list;
619
620 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
621 };
622
623 struct anv_state_stream_block;
624
625 struct anv_state_stream {
626 struct anv_state_pool *state_pool;
627
628 /* The size of blocks to allocate from the state pool */
629 uint32_t block_size;
630
631 /* Current block we're allocating from */
632 struct anv_state block;
633
634 /* Offset into the current block at which to allocate the next state */
635 uint32_t next;
636
637 /* List of all blocks allocated from this pool */
638 struct anv_state_stream_block *block_list;
639 };
640
641 /* The block_pool functions exported for testing only. The block pool should
642 * only be used via a state pool (see below).
643 */
644 VkResult anv_block_pool_init(struct anv_block_pool *pool,
645 struct anv_device *device,
646 uint32_t initial_size,
647 uint64_t bo_flags);
648 void anv_block_pool_finish(struct anv_block_pool *pool);
649 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
650 uint32_t block_size);
651 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
652 uint32_t block_size);
653
654 VkResult anv_state_pool_init(struct anv_state_pool *pool,
655 struct anv_device *device,
656 uint32_t block_size,
657 uint64_t bo_flags);
658 void anv_state_pool_finish(struct anv_state_pool *pool);
659 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
660 uint32_t state_size, uint32_t alignment);
661 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
662 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
663 void anv_state_stream_init(struct anv_state_stream *stream,
664 struct anv_state_pool *state_pool,
665 uint32_t block_size);
666 void anv_state_stream_finish(struct anv_state_stream *stream);
667 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
668 uint32_t size, uint32_t alignment);
669
670 /**
671 * Implements a pool of re-usable BOs. The interface is identical to that
672 * of block_pool except that each block is its own BO.
673 */
674 struct anv_bo_pool {
675 struct anv_device *device;
676
677 uint64_t bo_flags;
678
679 void *free_list[16];
680 };
681
682 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
683 uint64_t bo_flags);
684 void anv_bo_pool_finish(struct anv_bo_pool *pool);
685 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
686 uint32_t size);
687 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
688
689 struct anv_scratch_bo {
690 bool exists;
691 struct anv_bo bo;
692 };
693
694 struct anv_scratch_pool {
695 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
696 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
697 };
698
699 void anv_scratch_pool_init(struct anv_device *device,
700 struct anv_scratch_pool *pool);
701 void anv_scratch_pool_finish(struct anv_device *device,
702 struct anv_scratch_pool *pool);
703 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
704 struct anv_scratch_pool *pool,
705 gl_shader_stage stage,
706 unsigned per_thread_scratch);
707
708 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
709 struct anv_bo_cache {
710 struct hash_table *bo_map;
711 pthread_mutex_t mutex;
712 };
713
714 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
715 void anv_bo_cache_finish(struct anv_bo_cache *cache);
716 VkResult anv_bo_cache_alloc(struct anv_device *device,
717 struct anv_bo_cache *cache,
718 uint64_t size, struct anv_bo **bo);
719 VkResult anv_bo_cache_import(struct anv_device *device,
720 struct anv_bo_cache *cache,
721 int fd, struct anv_bo **bo);
722 VkResult anv_bo_cache_export(struct anv_device *device,
723 struct anv_bo_cache *cache,
724 struct anv_bo *bo_in, int *fd_out);
725 void anv_bo_cache_release(struct anv_device *device,
726 struct anv_bo_cache *cache,
727 struct anv_bo *bo);
728
729 struct anv_memory_type {
730 /* Standard bits passed on to the client */
731 VkMemoryPropertyFlags propertyFlags;
732 uint32_t heapIndex;
733
734 /* Driver-internal book-keeping */
735 VkBufferUsageFlags valid_buffer_usage;
736 };
737
738 struct anv_memory_heap {
739 /* Standard bits passed on to the client */
740 VkDeviceSize size;
741 VkMemoryHeapFlags flags;
742
743 /* Driver-internal book-keeping */
744 bool supports_48bit_addresses;
745 };
746
747 struct anv_physical_device {
748 VK_LOADER_DATA _loader_data;
749
750 struct anv_instance * instance;
751 uint32_t chipset_id;
752 char path[20];
753 const char * name;
754 struct gen_device_info info;
755 /** Amount of "GPU memory" we want to advertise
756 *
757 * Clearly, this value is bogus since Intel is a UMA architecture. On
758 * gen7 platforms, we are limited by GTT size unless we want to implement
759 * fine-grained tracking and GTT splitting. On Broadwell and above we are
760 * practically unlimited. However, we will never report more than 3/4 of
761 * the total system ram to try and avoid running out of RAM.
762 */
763 bool supports_48bit_addresses;
764 struct brw_compiler * compiler;
765 struct isl_device isl_dev;
766 int cmd_parser_version;
767 bool has_exec_async;
768 bool has_exec_capture;
769 bool has_exec_fence;
770 bool has_syncobj;
771 bool has_syncobj_wait;
772
773 struct anv_device_extension_table supported_extensions;
774
775 uint32_t eu_total;
776 uint32_t subslice_total;
777
778 struct {
779 uint32_t type_count;
780 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
781 uint32_t heap_count;
782 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
783 } memory;
784
785 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
786 uint8_t driver_uuid[VK_UUID_SIZE];
787 uint8_t device_uuid[VK_UUID_SIZE];
788
789 struct wsi_device wsi_device;
790 int local_fd;
791 };
792
793 struct anv_instance {
794 VK_LOADER_DATA _loader_data;
795
796 VkAllocationCallbacks alloc;
797
798 uint32_t apiVersion;
799 struct anv_instance_extension_table enabled_extensions;
800
801 int physicalDeviceCount;
802 struct anv_physical_device physicalDevice;
803
804 struct vk_debug_report_instance debug_report_callbacks;
805 };
806
807 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
808 void anv_finish_wsi(struct anv_physical_device *physical_device);
809
810 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
811 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
812 const char *name);
813
814 struct anv_queue {
815 VK_LOADER_DATA _loader_data;
816
817 struct anv_device * device;
818
819 struct anv_state_pool * pool;
820 };
821
822 struct anv_pipeline_cache {
823 struct anv_device * device;
824 pthread_mutex_t mutex;
825
826 struct hash_table * cache;
827 };
828
829 struct anv_pipeline_bind_map;
830
831 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
832 struct anv_device *device,
833 bool cache_enabled);
834 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
835
836 struct anv_shader_bin *
837 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
838 const void *key, uint32_t key_size);
839 struct anv_shader_bin *
840 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
841 const void *key_data, uint32_t key_size,
842 const void *kernel_data, uint32_t kernel_size,
843 const struct brw_stage_prog_data *prog_data,
844 uint32_t prog_data_size,
845 const struct anv_pipeline_bind_map *bind_map);
846
847 struct anv_device {
848 VK_LOADER_DATA _loader_data;
849
850 VkAllocationCallbacks alloc;
851
852 struct anv_instance * instance;
853 uint32_t chipset_id;
854 struct gen_device_info info;
855 struct isl_device isl_dev;
856 int context_id;
857 int fd;
858 bool can_chain_batches;
859 bool robust_buffer_access;
860 struct anv_device_extension_table enabled_extensions;
861
862 struct anv_bo_pool batch_bo_pool;
863
864 struct anv_bo_cache bo_cache;
865
866 struct anv_state_pool dynamic_state_pool;
867 struct anv_state_pool instruction_state_pool;
868 struct anv_state_pool surface_state_pool;
869
870 struct anv_bo workaround_bo;
871 struct anv_bo trivial_batch_bo;
872
873 struct anv_pipeline_cache blorp_shader_cache;
874 struct blorp_context blorp;
875
876 struct anv_state border_colors;
877
878 struct anv_queue queue;
879
880 struct anv_scratch_pool scratch_pool;
881
882 uint32_t default_mocs;
883
884 pthread_mutex_t mutex;
885 pthread_cond_t queue_submit;
886 bool lost;
887 };
888
889 static void inline
890 anv_state_flush(struct anv_device *device, struct anv_state state)
891 {
892 if (device->info.has_llc)
893 return;
894
895 gen_flush_range(state.map, state.alloc_size);
896 }
897
898 void anv_device_init_blorp(struct anv_device *device);
899 void anv_device_finish_blorp(struct anv_device *device);
900
901 VkResult anv_device_execbuf(struct anv_device *device,
902 struct drm_i915_gem_execbuffer2 *execbuf,
903 struct anv_bo **execbuf_bos);
904 VkResult anv_device_query_status(struct anv_device *device);
905 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
906 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
907 int64_t timeout);
908
909 void* anv_gem_mmap(struct anv_device *device,
910 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
911 void anv_gem_munmap(void *p, uint64_t size);
912 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
913 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
914 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
915 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
916 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
917 int anv_gem_execbuffer(struct anv_device *device,
918 struct drm_i915_gem_execbuffer2 *execbuf);
919 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
920 uint32_t stride, uint32_t tiling);
921 int anv_gem_create_context(struct anv_device *device);
922 int anv_gem_destroy_context(struct anv_device *device, int context);
923 int anv_gem_get_context_param(int fd, int context, uint32_t param,
924 uint64_t *value);
925 int anv_gem_get_param(int fd, uint32_t param);
926 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
927 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
928 int anv_gem_get_aperture(int fd, uint64_t *size);
929 bool anv_gem_supports_48b_addresses(int fd);
930 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
931 uint32_t *active, uint32_t *pending);
932 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
933 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
934 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
935 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
936 uint32_t read_domains, uint32_t write_domain);
937 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
938 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
939 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
940 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
941 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
942 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
943 uint32_t handle);
944 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
945 uint32_t handle, int fd);
946 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
947 bool anv_gem_supports_syncobj_wait(int fd);
948 int anv_gem_syncobj_wait(struct anv_device *device,
949 uint32_t *handles, uint32_t num_handles,
950 int64_t abs_timeout_ns, bool wait_all);
951
952 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
953
954 struct anv_reloc_list {
955 uint32_t num_relocs;
956 uint32_t array_length;
957 struct drm_i915_gem_relocation_entry * relocs;
958 struct anv_bo ** reloc_bos;
959 };
960
961 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
962 const VkAllocationCallbacks *alloc);
963 void anv_reloc_list_finish(struct anv_reloc_list *list,
964 const VkAllocationCallbacks *alloc);
965
966 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
967 const VkAllocationCallbacks *alloc,
968 uint32_t offset, struct anv_bo *target_bo,
969 uint32_t delta);
970
971 struct anv_batch_bo {
972 /* Link in the anv_cmd_buffer.owned_batch_bos list */
973 struct list_head link;
974
975 struct anv_bo bo;
976
977 /* Bytes actually consumed in this batch BO */
978 uint32_t length;
979
980 struct anv_reloc_list relocs;
981 };
982
983 struct anv_batch {
984 const VkAllocationCallbacks * alloc;
985
986 void * start;
987 void * end;
988 void * next;
989
990 struct anv_reloc_list * relocs;
991
992 /* This callback is called (with the associated user data) in the event
993 * that the batch runs out of space.
994 */
995 VkResult (*extend_cb)(struct anv_batch *, void *);
996 void * user_data;
997
998 /**
999 * Current error status of the command buffer. Used to track inconsistent
1000 * or incomplete command buffer states that are the consequence of run-time
1001 * errors such as out of memory scenarios. We want to track this in the
1002 * batch because the command buffer object is not visible to some parts
1003 * of the driver.
1004 */
1005 VkResult status;
1006 };
1007
1008 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1009 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1010 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1011 void *location, struct anv_bo *bo, uint32_t offset);
1012 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1013 struct anv_batch *batch);
1014
1015 static inline VkResult
1016 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1017 {
1018 assert(error != VK_SUCCESS);
1019 if (batch->status == VK_SUCCESS)
1020 batch->status = error;
1021 return batch->status;
1022 }
1023
1024 static inline bool
1025 anv_batch_has_error(struct anv_batch *batch)
1026 {
1027 return batch->status != VK_SUCCESS;
1028 }
1029
1030 struct anv_address {
1031 struct anv_bo *bo;
1032 uint32_t offset;
1033 };
1034
1035 static inline uint64_t
1036 _anv_combine_address(struct anv_batch *batch, void *location,
1037 const struct anv_address address, uint32_t delta)
1038 {
1039 if (address.bo == NULL) {
1040 return address.offset + delta;
1041 } else {
1042 assert(batch->start <= location && location < batch->end);
1043
1044 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1045 }
1046 }
1047
1048 #define __gen_address_type struct anv_address
1049 #define __gen_user_data struct anv_batch
1050 #define __gen_combine_address _anv_combine_address
1051
1052 /* Wrapper macros needed to work around preprocessor argument issues. In
1053 * particular, arguments don't get pre-evaluated if they are concatenated.
1054 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1055 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1056 * We can work around this easily enough with these helpers.
1057 */
1058 #define __anv_cmd_length(cmd) cmd ## _length
1059 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1060 #define __anv_cmd_header(cmd) cmd ## _header
1061 #define __anv_cmd_pack(cmd) cmd ## _pack
1062 #define __anv_reg_num(reg) reg ## _num
1063
1064 #define anv_pack_struct(dst, struc, ...) do { \
1065 struct struc __template = { \
1066 __VA_ARGS__ \
1067 }; \
1068 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1069 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1070 } while (0)
1071
1072 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1073 void *__dst = anv_batch_emit_dwords(batch, n); \
1074 if (__dst) { \
1075 struct cmd __template = { \
1076 __anv_cmd_header(cmd), \
1077 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1078 __VA_ARGS__ \
1079 }; \
1080 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1081 } \
1082 __dst; \
1083 })
1084
1085 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1086 do { \
1087 uint32_t *dw; \
1088 \
1089 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1090 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1091 if (!dw) \
1092 break; \
1093 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1094 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1095 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1096 } while (0)
1097
1098 #define anv_batch_emit(batch, cmd, name) \
1099 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1100 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1101 __builtin_expect(_dst != NULL, 1); \
1102 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1103 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1104 _dst = NULL; \
1105 }))
1106
1107 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1108 .GraphicsDataTypeGFDT = 0, \
1109 .LLCCacheabilityControlLLCCC = 0, \
1110 .L3CacheabilityControlL3CC = 1, \
1111 }
1112
1113 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1114 .LLCeLLCCacheabilityControlLLCCC = 0, \
1115 .L3CacheabilityControlL3CC = 1, \
1116 }
1117
1118 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1119 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1120 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1121 .AgeforQUADLRU = 0 \
1122 }
1123
1124 /* Skylake: MOCS is now an index into an array of 62 different caching
1125 * configurations programmed by the kernel.
1126 */
1127
1128 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1129 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1130 .IndextoMOCSTables = 2 \
1131 }
1132
1133 #define GEN9_MOCS_PTE { \
1134 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1135 .IndextoMOCSTables = 1 \
1136 }
1137
1138 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1139 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1140 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1141 .IndextoMOCSTables = 2 \
1142 }
1143
1144 #define GEN10_MOCS_PTE { \
1145 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1146 .IndextoMOCSTables = 1 \
1147 }
1148
1149 struct anv_device_memory {
1150 struct anv_bo * bo;
1151 struct anv_memory_type * type;
1152 VkDeviceSize map_size;
1153 void * map;
1154 };
1155
1156 /**
1157 * Header for Vertex URB Entry (VUE)
1158 */
1159 struct anv_vue_header {
1160 uint32_t Reserved;
1161 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1162 uint32_t ViewportIndex;
1163 float PointWidth;
1164 };
1165
1166 struct anv_descriptor_set_binding_layout {
1167 #ifndef NDEBUG
1168 /* The type of the descriptors in this binding */
1169 VkDescriptorType type;
1170 #endif
1171
1172 /* Number of array elements in this binding */
1173 uint16_t array_size;
1174
1175 /* Index into the flattend descriptor set */
1176 uint16_t descriptor_index;
1177
1178 /* Index into the dynamic state array for a dynamic buffer */
1179 int16_t dynamic_offset_index;
1180
1181 /* Index into the descriptor set buffer views */
1182 int16_t buffer_index;
1183
1184 struct {
1185 /* Index into the binding table for the associated surface */
1186 int16_t surface_index;
1187
1188 /* Index into the sampler table for the associated sampler */
1189 int16_t sampler_index;
1190
1191 /* Index into the image table for the associated image */
1192 int16_t image_index;
1193 } stage[MESA_SHADER_STAGES];
1194
1195 /* Immutable samplers (or NULL if no immutable samplers) */
1196 struct anv_sampler **immutable_samplers;
1197 };
1198
1199 struct anv_descriptor_set_layout {
1200 /* Number of bindings in this descriptor set */
1201 uint16_t binding_count;
1202
1203 /* Total size of the descriptor set with room for all array entries */
1204 uint16_t size;
1205
1206 /* Shader stages affected by this descriptor set */
1207 uint16_t shader_stages;
1208
1209 /* Number of buffers in this descriptor set */
1210 uint16_t buffer_count;
1211
1212 /* Number of dynamic offsets used by this descriptor set */
1213 uint16_t dynamic_offset_count;
1214
1215 /* Bindings in this descriptor set */
1216 struct anv_descriptor_set_binding_layout binding[0];
1217 };
1218
1219 struct anv_descriptor {
1220 VkDescriptorType type;
1221
1222 union {
1223 struct {
1224 VkImageLayout layout;
1225 struct anv_image_view *image_view;
1226 struct anv_sampler *sampler;
1227 };
1228
1229 struct {
1230 struct anv_buffer *buffer;
1231 uint64_t offset;
1232 uint64_t range;
1233 };
1234
1235 struct anv_buffer_view *buffer_view;
1236 };
1237 };
1238
1239 struct anv_descriptor_set {
1240 const struct anv_descriptor_set_layout *layout;
1241 uint32_t size;
1242 uint32_t buffer_count;
1243 struct anv_buffer_view *buffer_views;
1244 struct anv_descriptor descriptors[0];
1245 };
1246
1247 struct anv_buffer_view {
1248 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1249 struct anv_bo *bo;
1250 uint32_t offset; /**< Offset into bo. */
1251 uint64_t range; /**< VkBufferViewCreateInfo::range */
1252
1253 struct anv_state surface_state;
1254 struct anv_state storage_surface_state;
1255 struct anv_state writeonly_storage_surface_state;
1256
1257 struct brw_image_param storage_image_param;
1258 };
1259
1260 struct anv_push_descriptor_set {
1261 struct anv_descriptor_set set;
1262
1263 /* Put this field right behind anv_descriptor_set so it fills up the
1264 * descriptors[0] field. */
1265 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1266 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1267 };
1268
1269 struct anv_descriptor_pool {
1270 uint32_t size;
1271 uint32_t next;
1272 uint32_t free_list;
1273
1274 struct anv_state_stream surface_state_stream;
1275 void *surface_state_free_list;
1276
1277 char data[0];
1278 };
1279
1280 enum anv_descriptor_template_entry_type {
1281 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1282 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1283 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1284 };
1285
1286 struct anv_descriptor_template_entry {
1287 /* The type of descriptor in this entry */
1288 VkDescriptorType type;
1289
1290 /* Binding in the descriptor set */
1291 uint32_t binding;
1292
1293 /* Offset at which to write into the descriptor set binding */
1294 uint32_t array_element;
1295
1296 /* Number of elements to write into the descriptor set binding */
1297 uint32_t array_count;
1298
1299 /* Offset into the user provided data */
1300 size_t offset;
1301
1302 /* Stride between elements into the user provided data */
1303 size_t stride;
1304 };
1305
1306 struct anv_descriptor_update_template {
1307 /* The descriptor set this template corresponds to. This value is only
1308 * valid if the template was created with the templateType
1309 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1310 */
1311 uint8_t set;
1312
1313 /* Number of entries in this template */
1314 uint32_t entry_count;
1315
1316 /* Entries of the template */
1317 struct anv_descriptor_template_entry entries[0];
1318 };
1319
1320 size_t
1321 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1322
1323 size_t
1324 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1325
1326 void
1327 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1328 const struct gen_device_info * const devinfo,
1329 const VkDescriptorImageInfo * const info,
1330 VkDescriptorType type,
1331 uint32_t binding,
1332 uint32_t element);
1333
1334 void
1335 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1336 VkDescriptorType type,
1337 struct anv_buffer_view *buffer_view,
1338 uint32_t binding,
1339 uint32_t element);
1340
1341 void
1342 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1343 struct anv_device *device,
1344 struct anv_state_stream *alloc_stream,
1345 VkDescriptorType type,
1346 struct anv_buffer *buffer,
1347 uint32_t binding,
1348 uint32_t element,
1349 VkDeviceSize offset,
1350 VkDeviceSize range);
1351
1352 void
1353 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1354 struct anv_device *device,
1355 struct anv_state_stream *alloc_stream,
1356 const struct anv_descriptor_update_template *template,
1357 const void *data);
1358
1359 VkResult
1360 anv_descriptor_set_create(struct anv_device *device,
1361 struct anv_descriptor_pool *pool,
1362 const struct anv_descriptor_set_layout *layout,
1363 struct anv_descriptor_set **out_set);
1364
1365 void
1366 anv_descriptor_set_destroy(struct anv_device *device,
1367 struct anv_descriptor_pool *pool,
1368 struct anv_descriptor_set *set);
1369
1370 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1371
1372 struct anv_pipeline_binding {
1373 /* The descriptor set this surface corresponds to. The special value of
1374 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1375 * to a color attachment and not a regular descriptor.
1376 */
1377 uint8_t set;
1378
1379 /* Binding in the descriptor set */
1380 uint32_t binding;
1381
1382 /* Index in the binding */
1383 uint32_t index;
1384
1385 /* Plane in the binding index */
1386 uint8_t plane;
1387
1388 /* Input attachment index (relative to the subpass) */
1389 uint8_t input_attachment_index;
1390
1391 /* For a storage image, whether it is write-only */
1392 bool write_only;
1393 };
1394
1395 struct anv_pipeline_layout {
1396 struct {
1397 struct anv_descriptor_set_layout *layout;
1398 uint32_t dynamic_offset_start;
1399 } set[MAX_SETS];
1400
1401 uint32_t num_sets;
1402
1403 struct {
1404 bool has_dynamic_offsets;
1405 } stage[MESA_SHADER_STAGES];
1406
1407 unsigned char sha1[20];
1408 };
1409
1410 struct anv_buffer {
1411 struct anv_device * device;
1412 VkDeviceSize size;
1413
1414 VkBufferUsageFlags usage;
1415
1416 /* Set when bound */
1417 struct anv_bo * bo;
1418 VkDeviceSize offset;
1419 };
1420
1421 static inline uint64_t
1422 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1423 {
1424 assert(offset <= buffer->size);
1425 if (range == VK_WHOLE_SIZE) {
1426 return buffer->size - offset;
1427 } else {
1428 assert(range <= buffer->size);
1429 return range;
1430 }
1431 }
1432
1433 enum anv_cmd_dirty_bits {
1434 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1435 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1436 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1437 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1438 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1439 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1440 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1441 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1442 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1443 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1444 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1445 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1446 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1447 };
1448 typedef uint32_t anv_cmd_dirty_mask_t;
1449
1450 enum anv_pipe_bits {
1451 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1452 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1453 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1454 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1455 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1456 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1457 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1458 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1459 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1460 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1461 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1462
1463 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1464 * a flush has happened but not a CS stall. The next time we do any sort
1465 * of invalidation we need to insert a CS stall at that time. Otherwise,
1466 * we would have to CS stall on every flush which could be bad.
1467 */
1468 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1469 };
1470
1471 #define ANV_PIPE_FLUSH_BITS ( \
1472 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1473 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1474 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1475
1476 #define ANV_PIPE_STALL_BITS ( \
1477 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1478 ANV_PIPE_DEPTH_STALL_BIT | \
1479 ANV_PIPE_CS_STALL_BIT)
1480
1481 #define ANV_PIPE_INVALIDATE_BITS ( \
1482 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1483 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1484 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1485 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1486 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1487 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1488
1489 static inline enum anv_pipe_bits
1490 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1491 {
1492 enum anv_pipe_bits pipe_bits = 0;
1493
1494 unsigned b;
1495 for_each_bit(b, flags) {
1496 switch ((VkAccessFlagBits)(1 << b)) {
1497 case VK_ACCESS_SHADER_WRITE_BIT:
1498 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1499 break;
1500 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1501 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1502 break;
1503 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1504 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1505 break;
1506 case VK_ACCESS_TRANSFER_WRITE_BIT:
1507 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1508 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1509 break;
1510 default:
1511 break; /* Nothing to do */
1512 }
1513 }
1514
1515 return pipe_bits;
1516 }
1517
1518 static inline enum anv_pipe_bits
1519 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1520 {
1521 enum anv_pipe_bits pipe_bits = 0;
1522
1523 unsigned b;
1524 for_each_bit(b, flags) {
1525 switch ((VkAccessFlagBits)(1 << b)) {
1526 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1527 case VK_ACCESS_INDEX_READ_BIT:
1528 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1529 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1530 break;
1531 case VK_ACCESS_UNIFORM_READ_BIT:
1532 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1533 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1534 break;
1535 case VK_ACCESS_SHADER_READ_BIT:
1536 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1537 case VK_ACCESS_TRANSFER_READ_BIT:
1538 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1539 break;
1540 default:
1541 break; /* Nothing to do */
1542 }
1543 }
1544
1545 return pipe_bits;
1546 }
1547
1548 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1549 VK_IMAGE_ASPECT_COLOR_BIT | \
1550 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1551 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1552 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1553 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1554 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1555 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1556 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1557
1558 struct anv_vertex_binding {
1559 struct anv_buffer * buffer;
1560 VkDeviceSize offset;
1561 };
1562
1563 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1564 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1565
1566 struct anv_push_constants {
1567 /* Current allocated size of this push constants data structure.
1568 * Because a decent chunk of it may not be used (images on SKL, for
1569 * instance), we won't actually allocate the entire structure up-front.
1570 */
1571 uint32_t size;
1572
1573 /* Push constant data provided by the client through vkPushConstants */
1574 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1575
1576 /* Image data for image_load_store on pre-SKL */
1577 struct brw_image_param images[MAX_IMAGES];
1578 };
1579
1580 struct anv_dynamic_state {
1581 struct {
1582 uint32_t count;
1583 VkViewport viewports[MAX_VIEWPORTS];
1584 } viewport;
1585
1586 struct {
1587 uint32_t count;
1588 VkRect2D scissors[MAX_SCISSORS];
1589 } scissor;
1590
1591 float line_width;
1592
1593 struct {
1594 float bias;
1595 float clamp;
1596 float slope;
1597 } depth_bias;
1598
1599 float blend_constants[4];
1600
1601 struct {
1602 float min;
1603 float max;
1604 } depth_bounds;
1605
1606 struct {
1607 uint32_t front;
1608 uint32_t back;
1609 } stencil_compare_mask;
1610
1611 struct {
1612 uint32_t front;
1613 uint32_t back;
1614 } stencil_write_mask;
1615
1616 struct {
1617 uint32_t front;
1618 uint32_t back;
1619 } stencil_reference;
1620 };
1621
1622 extern const struct anv_dynamic_state default_dynamic_state;
1623
1624 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1625 const struct anv_dynamic_state *src,
1626 uint32_t copy_mask);
1627
1628 struct anv_surface_state {
1629 struct anv_state state;
1630 /** Address of the surface referred to by this state
1631 *
1632 * This address is relative to the start of the BO.
1633 */
1634 uint64_t address;
1635 /* Address of the aux surface, if any
1636 *
1637 * This field is 0 if and only if no aux surface exists.
1638 *
1639 * This address is relative to the start of the BO. On gen7, the bottom 12
1640 * bits of this address include extra aux information.
1641 */
1642 uint64_t aux_address;
1643 };
1644
1645 /**
1646 * Attachment state when recording a renderpass instance.
1647 *
1648 * The clear value is valid only if there exists a pending clear.
1649 */
1650 struct anv_attachment_state {
1651 enum isl_aux_usage aux_usage;
1652 enum isl_aux_usage input_aux_usage;
1653 struct anv_surface_state color;
1654 struct anv_surface_state input;
1655
1656 VkImageLayout current_layout;
1657 VkImageAspectFlags pending_clear_aspects;
1658 bool fast_clear;
1659 VkClearValue clear_value;
1660 bool clear_color_is_zero_one;
1661 bool clear_color_is_zero;
1662 };
1663
1664 /** State required while building cmd buffer */
1665 struct anv_cmd_state {
1666 /* PIPELINE_SELECT.PipelineSelection */
1667 uint32_t current_pipeline;
1668 const struct gen_l3_config * current_l3_config;
1669 uint32_t vb_dirty;
1670 anv_cmd_dirty_mask_t dirty;
1671 anv_cmd_dirty_mask_t compute_dirty;
1672 enum anv_pipe_bits pending_pipe_bits;
1673 uint32_t num_workgroups_offset;
1674 struct anv_bo *num_workgroups_bo;
1675 VkShaderStageFlags descriptors_dirty;
1676 VkShaderStageFlags push_constants_dirty;
1677 uint32_t scratch_size;
1678 struct anv_pipeline * pipeline;
1679 struct anv_pipeline * compute_pipeline;
1680 struct anv_framebuffer * framebuffer;
1681 struct anv_render_pass * pass;
1682 struct anv_subpass * subpass;
1683 VkRect2D render_area;
1684 uint32_t restart_index;
1685 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1686 struct anv_descriptor_set * descriptors[MAX_SETS];
1687 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1688 VkShaderStageFlags push_constant_stages;
1689 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1690 struct anv_state binding_tables[MESA_SHADER_STAGES];
1691 struct anv_state samplers[MESA_SHADER_STAGES];
1692 struct anv_dynamic_state dynamic;
1693 bool need_query_wa;
1694
1695 struct anv_push_descriptor_set * push_descriptors[MAX_SETS];
1696
1697 /**
1698 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1699 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1700 * and before invoking the secondary in ExecuteCommands.
1701 */
1702 bool pma_fix_enabled;
1703
1704 /**
1705 * Whether or not we know for certain that HiZ is enabled for the current
1706 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1707 * enabled or not, this will be false.
1708 */
1709 bool hiz_enabled;
1710
1711 /**
1712 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1713 * valid only when recording a render pass instance.
1714 */
1715 struct anv_attachment_state * attachments;
1716
1717 /**
1718 * Surface states for color render targets. These are stored in a single
1719 * flat array. For depth-stencil attachments, the surface state is simply
1720 * left blank.
1721 */
1722 struct anv_state render_pass_states;
1723
1724 /**
1725 * A null surface state of the right size to match the framebuffer. This
1726 * is one of the states in render_pass_states.
1727 */
1728 struct anv_state null_surface_state;
1729
1730 struct {
1731 struct anv_buffer * index_buffer;
1732 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1733 uint32_t index_offset;
1734 } gen7;
1735 };
1736
1737 struct anv_cmd_pool {
1738 VkAllocationCallbacks alloc;
1739 struct list_head cmd_buffers;
1740 };
1741
1742 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1743
1744 enum anv_cmd_buffer_exec_mode {
1745 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1746 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1747 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1748 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1749 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1750 };
1751
1752 struct anv_cmd_buffer {
1753 VK_LOADER_DATA _loader_data;
1754
1755 struct anv_device * device;
1756
1757 struct anv_cmd_pool * pool;
1758 struct list_head pool_link;
1759
1760 struct anv_batch batch;
1761
1762 /* Fields required for the actual chain of anv_batch_bo's.
1763 *
1764 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1765 */
1766 struct list_head batch_bos;
1767 enum anv_cmd_buffer_exec_mode exec_mode;
1768
1769 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1770 * referenced by this command buffer
1771 *
1772 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1773 */
1774 struct u_vector seen_bbos;
1775
1776 /* A vector of int32_t's for every block of binding tables.
1777 *
1778 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1779 */
1780 struct u_vector bt_block_states;
1781 uint32_t bt_next;
1782
1783 struct anv_reloc_list surface_relocs;
1784 /** Last seen surface state block pool center bo offset */
1785 uint32_t last_ss_pool_center;
1786
1787 /* Serial for tracking buffer completion */
1788 uint32_t serial;
1789
1790 /* Stream objects for storing temporary data */
1791 struct anv_state_stream surface_state_stream;
1792 struct anv_state_stream dynamic_state_stream;
1793
1794 VkCommandBufferUsageFlags usage_flags;
1795 VkCommandBufferLevel level;
1796
1797 struct anv_cmd_state state;
1798 };
1799
1800 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1801 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1802 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1803 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1804 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1805 struct anv_cmd_buffer *secondary);
1806 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1807 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1808 struct anv_cmd_buffer *cmd_buffer,
1809 const VkSemaphore *in_semaphores,
1810 uint32_t num_in_semaphores,
1811 const VkSemaphore *out_semaphores,
1812 uint32_t num_out_semaphores,
1813 VkFence fence);
1814
1815 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1816
1817 VkResult
1818 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1819 gl_shader_stage stage, uint32_t size);
1820 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1821 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1822 (offsetof(struct anv_push_constants, field) + \
1823 sizeof(cmd_buffer->state.push_constants[0]->field)))
1824
1825 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1826 const void *data, uint32_t size, uint32_t alignment);
1827 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1828 uint32_t *a, uint32_t *b,
1829 uint32_t dwords, uint32_t alignment);
1830
1831 struct anv_address
1832 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1833 struct anv_state
1834 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1835 uint32_t entries, uint32_t *state_offset);
1836 struct anv_state
1837 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1838 struct anv_state
1839 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1840 uint32_t size, uint32_t alignment);
1841
1842 VkResult
1843 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1844
1845 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1846 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1847 bool depth_clamp_enable);
1848 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1849
1850 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1851 struct anv_render_pass *pass,
1852 struct anv_framebuffer *framebuffer,
1853 const VkClearValue *clear_values);
1854
1855 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1856
1857 struct anv_state
1858 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1859 gl_shader_stage stage);
1860 struct anv_state
1861 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1862
1863 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1864 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1865
1866 const struct anv_image_view *
1867 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1868
1869 VkResult
1870 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1871 uint32_t num_entries,
1872 uint32_t *state_offset,
1873 struct anv_state *bt_state);
1874
1875 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1876
1877 enum anv_fence_type {
1878 ANV_FENCE_TYPE_NONE = 0,
1879 ANV_FENCE_TYPE_BO,
1880 ANV_FENCE_TYPE_SYNCOBJ,
1881 };
1882
1883 enum anv_bo_fence_state {
1884 /** Indicates that this is a new (or newly reset fence) */
1885 ANV_BO_FENCE_STATE_RESET,
1886
1887 /** Indicates that this fence has been submitted to the GPU but is still
1888 * (as far as we know) in use by the GPU.
1889 */
1890 ANV_BO_FENCE_STATE_SUBMITTED,
1891
1892 ANV_BO_FENCE_STATE_SIGNALED,
1893 };
1894
1895 struct anv_fence_impl {
1896 enum anv_fence_type type;
1897
1898 union {
1899 /** Fence implementation for BO fences
1900 *
1901 * These fences use a BO and a set of CPU-tracked state flags. The BO
1902 * is added to the object list of the last execbuf call in a QueueSubmit
1903 * and is marked EXEC_WRITE. The state flags track when the BO has been
1904 * submitted to the kernel. We need to do this because Vulkan lets you
1905 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1906 * will say it's idle in this case.
1907 */
1908 struct {
1909 struct anv_bo bo;
1910 enum anv_bo_fence_state state;
1911 } bo;
1912
1913 /** DRM syncobj handle for syncobj-based fences */
1914 uint32_t syncobj;
1915 };
1916 };
1917
1918 struct anv_fence {
1919 /* Permanent fence state. Every fence has some form of permanent state
1920 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
1921 * cross-process fences) or it could just be a dummy for use internally.
1922 */
1923 struct anv_fence_impl permanent;
1924
1925 /* Temporary fence state. A fence *may* have temporary state. That state
1926 * is added to the fence by an import operation and is reset back to
1927 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
1928 * state cannot be signaled because the fence must already be signaled
1929 * before the temporary state can be exported from the fence in the other
1930 * process and imported here.
1931 */
1932 struct anv_fence_impl temporary;
1933 };
1934
1935 struct anv_event {
1936 uint64_t semaphore;
1937 struct anv_state state;
1938 };
1939
1940 enum anv_semaphore_type {
1941 ANV_SEMAPHORE_TYPE_NONE = 0,
1942 ANV_SEMAPHORE_TYPE_DUMMY,
1943 ANV_SEMAPHORE_TYPE_BO,
1944 ANV_SEMAPHORE_TYPE_SYNC_FILE,
1945 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
1946 };
1947
1948 struct anv_semaphore_impl {
1949 enum anv_semaphore_type type;
1950
1951 union {
1952 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1953 * This BO will be added to the object list on any execbuf2 calls for
1954 * which this semaphore is used as a wait or signal fence. When used as
1955 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1956 */
1957 struct anv_bo *bo;
1958
1959 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
1960 * If the semaphore is in the unsignaled state due to either just being
1961 * created or because it has been used for a wait, fd will be -1.
1962 */
1963 int fd;
1964
1965 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
1966 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
1967 * import so we don't need to bother with a userspace cache.
1968 */
1969 uint32_t syncobj;
1970 };
1971 };
1972
1973 struct anv_semaphore {
1974 /* Permanent semaphore state. Every semaphore has some form of permanent
1975 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1976 * (for cross-process semaphores0 or it could just be a dummy for use
1977 * internally.
1978 */
1979 struct anv_semaphore_impl permanent;
1980
1981 /* Temporary semaphore state. A semaphore *may* have temporary state.
1982 * That state is added to the semaphore by an import operation and is reset
1983 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1984 * semaphore with temporary state cannot be signaled because the semaphore
1985 * must already be signaled before the temporary state can be exported from
1986 * the semaphore in the other process and imported here.
1987 */
1988 struct anv_semaphore_impl temporary;
1989 };
1990
1991 void anv_semaphore_reset_temporary(struct anv_device *device,
1992 struct anv_semaphore *semaphore);
1993
1994 struct anv_shader_module {
1995 unsigned char sha1[20];
1996 uint32_t size;
1997 char data[0];
1998 };
1999
2000 static inline gl_shader_stage
2001 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2002 {
2003 assert(__builtin_popcount(vk_stage) == 1);
2004 return ffs(vk_stage) - 1;
2005 }
2006
2007 static inline VkShaderStageFlagBits
2008 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2009 {
2010 return (1 << mesa_stage);
2011 }
2012
2013 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2014
2015 #define anv_foreach_stage(stage, stage_bits) \
2016 for (gl_shader_stage stage, \
2017 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2018 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2019 __tmp &= ~(1 << (stage)))
2020
2021 struct anv_pipeline_bind_map {
2022 uint32_t surface_count;
2023 uint32_t sampler_count;
2024 uint32_t image_count;
2025
2026 struct anv_pipeline_binding * surface_to_descriptor;
2027 struct anv_pipeline_binding * sampler_to_descriptor;
2028 };
2029
2030 struct anv_shader_bin_key {
2031 uint32_t size;
2032 uint8_t data[0];
2033 };
2034
2035 struct anv_shader_bin {
2036 uint32_t ref_cnt;
2037
2038 const struct anv_shader_bin_key *key;
2039
2040 struct anv_state kernel;
2041 uint32_t kernel_size;
2042
2043 const struct brw_stage_prog_data *prog_data;
2044 uint32_t prog_data_size;
2045
2046 struct anv_pipeline_bind_map bind_map;
2047 };
2048
2049 struct anv_shader_bin *
2050 anv_shader_bin_create(struct anv_device *device,
2051 const void *key, uint32_t key_size,
2052 const void *kernel, uint32_t kernel_size,
2053 const struct brw_stage_prog_data *prog_data,
2054 uint32_t prog_data_size, const void *prog_data_param,
2055 const struct anv_pipeline_bind_map *bind_map);
2056
2057 void
2058 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2059
2060 static inline void
2061 anv_shader_bin_ref(struct anv_shader_bin *shader)
2062 {
2063 assert(shader && shader->ref_cnt >= 1);
2064 p_atomic_inc(&shader->ref_cnt);
2065 }
2066
2067 static inline void
2068 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2069 {
2070 assert(shader && shader->ref_cnt >= 1);
2071 if (p_atomic_dec_zero(&shader->ref_cnt))
2072 anv_shader_bin_destroy(device, shader);
2073 }
2074
2075 struct anv_pipeline {
2076 struct anv_device * device;
2077 struct anv_batch batch;
2078 uint32_t batch_data[512];
2079 struct anv_reloc_list batch_relocs;
2080 uint32_t dynamic_state_mask;
2081 struct anv_dynamic_state dynamic_state;
2082
2083 struct anv_subpass * subpass;
2084 struct anv_pipeline_layout * layout;
2085
2086 bool needs_data_cache;
2087
2088 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2089
2090 struct {
2091 const struct gen_l3_config * l3_config;
2092 uint32_t total_size;
2093 } urb;
2094
2095 VkShaderStageFlags active_stages;
2096 struct anv_state blend_state;
2097
2098 uint32_t vb_used;
2099 uint32_t binding_stride[MAX_VBS];
2100 bool instancing_enable[MAX_VBS];
2101 bool primitive_restart;
2102 uint32_t topology;
2103
2104 uint32_t cs_right_mask;
2105
2106 bool writes_depth;
2107 bool depth_test_enable;
2108 bool writes_stencil;
2109 bool stencil_test_enable;
2110 bool depth_clamp_enable;
2111 bool sample_shading_enable;
2112 bool kill_pixel;
2113
2114 struct {
2115 uint32_t sf[7];
2116 uint32_t depth_stencil_state[3];
2117 } gen7;
2118
2119 struct {
2120 uint32_t sf[4];
2121 uint32_t raster[5];
2122 uint32_t wm_depth_stencil[3];
2123 } gen8;
2124
2125 struct {
2126 uint32_t wm_depth_stencil[4];
2127 } gen9;
2128
2129 uint32_t interface_descriptor_data[8];
2130 };
2131
2132 static inline bool
2133 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2134 gl_shader_stage stage)
2135 {
2136 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2137 }
2138
2139 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2140 static inline const struct brw_##prefix##_prog_data * \
2141 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2142 { \
2143 if (anv_pipeline_has_stage(pipeline, stage)) { \
2144 return (const struct brw_##prefix##_prog_data *) \
2145 pipeline->shaders[stage]->prog_data; \
2146 } else { \
2147 return NULL; \
2148 } \
2149 }
2150
2151 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2152 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2153 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2154 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2155 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2156 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2157
2158 static inline const struct brw_vue_prog_data *
2159 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2160 {
2161 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2162 return &get_gs_prog_data(pipeline)->base;
2163 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2164 return &get_tes_prog_data(pipeline)->base;
2165 else
2166 return &get_vs_prog_data(pipeline)->base;
2167 }
2168
2169 VkResult
2170 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2171 struct anv_pipeline_cache *cache,
2172 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2173 const VkAllocationCallbacks *alloc);
2174
2175 VkResult
2176 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2177 struct anv_pipeline_cache *cache,
2178 const VkComputePipelineCreateInfo *info,
2179 struct anv_shader_module *module,
2180 const char *entrypoint,
2181 const VkSpecializationInfo *spec_info);
2182
2183 struct anv_format_plane {
2184 enum isl_format isl_format:16;
2185 struct isl_swizzle swizzle;
2186
2187 /* Whether this plane contains chroma channels */
2188 bool has_chroma;
2189
2190 /* For downscaling of YUV planes */
2191 uint8_t denominator_scales[2];
2192
2193 /* How to map sampled ycbcr planes to a single 4 component element. */
2194 struct isl_swizzle ycbcr_swizzle;
2195 };
2196
2197
2198 struct anv_format {
2199 struct anv_format_plane planes[3];
2200 uint8_t n_planes;
2201 bool can_ycbcr;
2202 };
2203
2204 static inline uint32_t
2205 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2206 VkImageAspectFlags aspect_mask)
2207 {
2208 switch (aspect_mask) {
2209 case VK_IMAGE_ASPECT_COLOR_BIT:
2210 case VK_IMAGE_ASPECT_DEPTH_BIT:
2211 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
2212 return 0;
2213 case VK_IMAGE_ASPECT_STENCIL_BIT:
2214 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2215 return 0;
2216 /* Fall-through */
2217 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
2218 return 1;
2219 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
2220 return 2;
2221 default:
2222 /* Purposefully assert with depth/stencil aspects. */
2223 unreachable("invalid image aspect");
2224 }
2225 }
2226
2227 static inline uint32_t
2228 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2229 {
2230 uint32_t planes = 0;
2231
2232 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2233 VK_IMAGE_ASPECT_DEPTH_BIT |
2234 VK_IMAGE_ASPECT_STENCIL_BIT |
2235 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR))
2236 planes++;
2237 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT_KHR)
2238 planes++;
2239 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
2240 planes++;
2241
2242 return planes;
2243 }
2244
2245 static inline VkImageAspectFlags
2246 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2247 uint32_t plane)
2248 {
2249 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2250 if (_mesa_bitcount(image_aspects) > 1)
2251 return VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << plane;
2252 return VK_IMAGE_ASPECT_COLOR_BIT;
2253 }
2254 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2255 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2256 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2257 return VK_IMAGE_ASPECT_STENCIL_BIT;
2258 }
2259
2260 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2261 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2262
2263 const struct anv_format *
2264 anv_get_format(VkFormat format);
2265
2266 static inline uint32_t
2267 anv_get_format_planes(VkFormat vk_format)
2268 {
2269 const struct anv_format *format = anv_get_format(vk_format);
2270
2271 return format != NULL ? format->n_planes : 0;
2272 }
2273
2274 struct anv_format_plane
2275 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2276 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2277
2278 static inline enum isl_format
2279 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2280 VkImageAspectFlags aspect, VkImageTiling tiling)
2281 {
2282 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2283 }
2284
2285 static inline struct isl_swizzle
2286 anv_swizzle_for_render(struct isl_swizzle swizzle)
2287 {
2288 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2289 * RGB as RGBA for texturing
2290 */
2291 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2292 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2293
2294 /* But it doesn't matter what we render to that channel */
2295 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2296
2297 return swizzle;
2298 }
2299
2300 void
2301 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2302
2303 /**
2304 * Subsurface of an anv_image.
2305 */
2306 struct anv_surface {
2307 /** Valid only if isl_surf::size > 0. */
2308 struct isl_surf isl;
2309
2310 /**
2311 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2312 */
2313 uint32_t offset;
2314 };
2315
2316 struct anv_image {
2317 VkImageType type;
2318 /* The original VkFormat provided by the client. This may not match any
2319 * of the actual surface formats.
2320 */
2321 VkFormat vk_format;
2322 const struct anv_format *format;
2323
2324 VkImageAspectFlags aspects;
2325 VkExtent3D extent;
2326 uint32_t levels;
2327 uint32_t array_size;
2328 uint32_t samples; /**< VkImageCreateInfo::samples */
2329 uint32_t n_planes;
2330 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2331 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2332
2333 /**
2334 * DRM format modifier for this image or DRM_FORMAT_MOD_INVALID.
2335 */
2336 uint64_t drm_format_mod;
2337
2338 VkDeviceSize size;
2339 uint32_t alignment;
2340
2341 /* Whether the image is made of several underlying buffer objects rather a
2342 * single one with different offsets.
2343 */
2344 bool disjoint;
2345
2346 /**
2347 * Image subsurfaces
2348 *
2349 * For each foo, anv_image::planes[x].surface is valid if and only if
2350 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2351 * to figure the number associated with a given aspect.
2352 *
2353 * The hardware requires that the depth buffer and stencil buffer be
2354 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2355 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2356 * allocate the depth and stencil buffers as separate surfaces in the same
2357 * bo.
2358 *
2359 * Memory layout :
2360 *
2361 * -----------------------
2362 * | surface0 | /|\
2363 * ----------------------- |
2364 * | shadow surface0 | |
2365 * ----------------------- | Plane 0
2366 * | aux surface0 | |
2367 * ----------------------- |
2368 * | fast clear colors0 | \|/
2369 * -----------------------
2370 * | surface1 | /|\
2371 * ----------------------- |
2372 * | shadow surface1 | |
2373 * ----------------------- | Plane 1
2374 * | aux surface1 | |
2375 * ----------------------- |
2376 * | fast clear colors1 | \|/
2377 * -----------------------
2378 * | ... |
2379 * | |
2380 * -----------------------
2381 */
2382 struct {
2383 /**
2384 * Offset of the entire plane (whenever the image is disjoint this is
2385 * set to 0).
2386 */
2387 uint32_t offset;
2388
2389 VkDeviceSize size;
2390 uint32_t alignment;
2391
2392 struct anv_surface surface;
2393
2394 /**
2395 * A surface which shadows the main surface and may have different
2396 * tiling. This is used for sampling using a tiling that isn't supported
2397 * for other operations.
2398 */
2399 struct anv_surface shadow_surface;
2400
2401 /**
2402 * For color images, this is the aux usage for this image when not used
2403 * as a color attachment.
2404 *
2405 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2406 * image has a HiZ buffer.
2407 */
2408 enum isl_aux_usage aux_usage;
2409
2410 struct anv_surface aux_surface;
2411
2412 /**
2413 * Offset of the fast clear state (used to compute the
2414 * fast_clear_state_offset of the following planes).
2415 */
2416 uint32_t fast_clear_state_offset;
2417
2418 /**
2419 * BO associated with this plane, set when bound.
2420 */
2421 struct anv_bo *bo;
2422 VkDeviceSize bo_offset;
2423
2424 /**
2425 * When destroying the image, also free the bo.
2426 * */
2427 bool bo_is_owned;
2428 } planes[3];
2429 };
2430
2431 /* Returns the number of auxiliary buffer levels attached to an image. */
2432 static inline uint8_t
2433 anv_image_aux_levels(const struct anv_image * const image,
2434 VkImageAspectFlagBits aspect)
2435 {
2436 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2437 return image->planes[plane].aux_surface.isl.size > 0 ?
2438 image->planes[plane].aux_surface.isl.levels : 0;
2439 }
2440
2441 /* Returns the number of auxiliary buffer layers attached to an image. */
2442 static inline uint32_t
2443 anv_image_aux_layers(const struct anv_image * const image,
2444 VkImageAspectFlagBits aspect,
2445 const uint8_t miplevel)
2446 {
2447 assert(image);
2448
2449 /* The miplevel must exist in the main buffer. */
2450 assert(miplevel < image->levels);
2451
2452 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2453 /* There are no layers with auxiliary data because the miplevel has no
2454 * auxiliary data.
2455 */
2456 return 0;
2457 } else {
2458 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2459 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2460 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2461 }
2462 }
2463
2464 static inline unsigned
2465 anv_fast_clear_state_entry_size(const struct anv_device *device)
2466 {
2467 assert(device);
2468 /* Entry contents:
2469 * +--------------------------------------------+
2470 * | clear value dword(s) | needs resolve dword |
2471 * +--------------------------------------------+
2472 */
2473
2474 /* Ensure that the needs resolve dword is in fact dword-aligned to enable
2475 * GPU memcpy operations.
2476 */
2477 assert(device->isl_dev.ss.clear_value_size % 4 == 0);
2478 return device->isl_dev.ss.clear_value_size + 4;
2479 }
2480
2481 static inline struct anv_address
2482 anv_image_get_clear_color_addr(const struct anv_device *device,
2483 const struct anv_image *image,
2484 VkImageAspectFlagBits aspect,
2485 unsigned level)
2486 {
2487 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2488 return (struct anv_address) {
2489 .bo = image->planes[plane].bo,
2490 .offset = image->planes[plane].bo_offset +
2491 image->planes[plane].fast_clear_state_offset +
2492 anv_fast_clear_state_entry_size(device) * level,
2493 };
2494 }
2495
2496 static inline struct anv_address
2497 anv_image_get_needs_resolve_addr(const struct anv_device *device,
2498 const struct anv_image *image,
2499 VkImageAspectFlagBits aspect,
2500 unsigned level)
2501 {
2502 struct anv_address addr =
2503 anv_image_get_clear_color_addr(device, image, aspect, level);
2504 addr.offset += device->isl_dev.ss.clear_value_size;
2505 return addr;
2506 }
2507
2508 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2509 static inline bool
2510 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2511 const struct anv_image *image)
2512 {
2513 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2514 return false;
2515
2516 if (devinfo->gen < 8)
2517 return false;
2518
2519 return image->samples == 1;
2520 }
2521
2522 void
2523 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
2524 const struct anv_image *image,
2525 enum blorp_hiz_op op);
2526 void
2527 anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
2528 const struct anv_image * const image,
2529 VkImageAspectFlagBits aspect,
2530 const uint8_t level,
2531 const uint32_t start_layer, const uint32_t layer_count,
2532 const enum blorp_fast_clear_op op);
2533
2534 void
2535 anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
2536 const struct anv_image *image,
2537 VkImageAspectFlagBits aspect,
2538 const uint32_t base_level, const uint32_t level_count,
2539 const uint32_t base_layer, uint32_t layer_count);
2540
2541 void
2542 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2543 const struct anv_image *image,
2544 uint32_t base_level, uint32_t level_count,
2545 uint32_t base_layer, uint32_t layer_count);
2546
2547 enum isl_aux_usage
2548 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2549 const struct anv_image *image,
2550 const VkImageAspectFlagBits aspect,
2551 const VkImageLayout layout);
2552
2553 /* This is defined as a macro so that it works for both
2554 * VkImageSubresourceRange and VkImageSubresourceLayers
2555 */
2556 #define anv_get_layerCount(_image, _range) \
2557 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2558 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2559
2560 static inline uint32_t
2561 anv_get_levelCount(const struct anv_image *image,
2562 const VkImageSubresourceRange *range)
2563 {
2564 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2565 image->levels - range->baseMipLevel : range->levelCount;
2566 }
2567
2568 static inline VkImageAspectFlags
2569 anv_image_expand_aspects(const struct anv_image *image,
2570 VkImageAspectFlags aspects)
2571 {
2572 /* If the underlying image has color plane aspects and
2573 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2574 * the underlying image. */
2575 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
2576 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2577 return image->aspects;
2578
2579 return aspects;
2580 }
2581
2582 static inline bool
2583 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2584 VkImageAspectFlags aspects2)
2585 {
2586 if (aspects1 == aspects2)
2587 return true;
2588
2589 /* Only 1 color aspects are compatibles. */
2590 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2591 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2592 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2593 return true;
2594
2595 return false;
2596 }
2597
2598 struct anv_image_view {
2599 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2600
2601 VkImageAspectFlags aspect_mask;
2602 VkFormat vk_format;
2603 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2604
2605 unsigned n_planes;
2606 struct {
2607 uint32_t image_plane;
2608
2609 struct isl_view isl;
2610
2611 /**
2612 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2613 * image layout of SHADER_READ_ONLY_OPTIMAL or
2614 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2615 */
2616 struct anv_surface_state optimal_sampler_surface_state;
2617
2618 /**
2619 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2620 * image layout of GENERAL.
2621 */
2622 struct anv_surface_state general_sampler_surface_state;
2623
2624 /**
2625 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2626 * states for write-only and readable, using the real format for
2627 * write-only and the lowered format for readable.
2628 */
2629 struct anv_surface_state storage_surface_state;
2630 struct anv_surface_state writeonly_storage_surface_state;
2631
2632 struct brw_image_param storage_image_param;
2633 } planes[3];
2634 };
2635
2636 enum anv_image_view_state_flags {
2637 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2638 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2639 };
2640
2641 void anv_image_fill_surface_state(struct anv_device *device,
2642 const struct anv_image *image,
2643 VkImageAspectFlagBits aspect,
2644 const struct isl_view *view,
2645 isl_surf_usage_flags_t view_usage,
2646 enum isl_aux_usage aux_usage,
2647 const union isl_color_value *clear_color,
2648 enum anv_image_view_state_flags flags,
2649 struct anv_surface_state *state_inout,
2650 struct brw_image_param *image_param_out);
2651
2652 struct anv_image_create_info {
2653 const VkImageCreateInfo *vk_info;
2654
2655 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2656 isl_tiling_flags_t isl_tiling_flags;
2657
2658 /** These flags will be added to any derived from VkImageCreateInfo. */
2659 isl_surf_usage_flags_t isl_extra_usage_flags;
2660
2661 uint32_t stride;
2662 };
2663
2664 VkResult anv_image_create(VkDevice _device,
2665 const struct anv_image_create_info *info,
2666 const VkAllocationCallbacks* alloc,
2667 VkImage *pImage);
2668
2669 #ifdef ANDROID
2670 VkResult anv_image_from_gralloc(VkDevice device_h,
2671 const VkImageCreateInfo *base_info,
2672 const VkNativeBufferANDROID *gralloc_info,
2673 const VkAllocationCallbacks *alloc,
2674 VkImage *pImage);
2675 #endif
2676
2677 const struct anv_surface *
2678 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2679 VkImageAspectFlags aspect_mask);
2680
2681 enum isl_format
2682 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2683
2684 static inline struct VkExtent3D
2685 anv_sanitize_image_extent(const VkImageType imageType,
2686 const struct VkExtent3D imageExtent)
2687 {
2688 switch (imageType) {
2689 case VK_IMAGE_TYPE_1D:
2690 return (VkExtent3D) { imageExtent.width, 1, 1 };
2691 case VK_IMAGE_TYPE_2D:
2692 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2693 case VK_IMAGE_TYPE_3D:
2694 return imageExtent;
2695 default:
2696 unreachable("invalid image type");
2697 }
2698 }
2699
2700 static inline struct VkOffset3D
2701 anv_sanitize_image_offset(const VkImageType imageType,
2702 const struct VkOffset3D imageOffset)
2703 {
2704 switch (imageType) {
2705 case VK_IMAGE_TYPE_1D:
2706 return (VkOffset3D) { imageOffset.x, 0, 0 };
2707 case VK_IMAGE_TYPE_2D:
2708 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2709 case VK_IMAGE_TYPE_3D:
2710 return imageOffset;
2711 default:
2712 unreachable("invalid image type");
2713 }
2714 }
2715
2716
2717 void anv_fill_buffer_surface_state(struct anv_device *device,
2718 struct anv_state state,
2719 enum isl_format format,
2720 uint32_t offset, uint32_t range,
2721 uint32_t stride);
2722
2723
2724 struct anv_ycbcr_conversion {
2725 const struct anv_format * format;
2726 VkSamplerYcbcrModelConversionKHR ycbcr_model;
2727 VkSamplerYcbcrRangeKHR ycbcr_range;
2728 VkComponentSwizzle mapping[4];
2729 VkChromaLocationKHR chroma_offsets[2];
2730 VkFilter chroma_filter;
2731 bool chroma_reconstruction;
2732 };
2733
2734 struct anv_sampler {
2735 uint32_t state[3][4];
2736 uint32_t n_planes;
2737 struct anv_ycbcr_conversion *conversion;
2738 };
2739
2740 struct anv_framebuffer {
2741 uint32_t width;
2742 uint32_t height;
2743 uint32_t layers;
2744
2745 uint32_t attachment_count;
2746 struct anv_image_view * attachments[0];
2747 };
2748
2749 struct anv_subpass {
2750 uint32_t attachment_count;
2751
2752 /**
2753 * A pointer to all attachment references used in this subpass.
2754 * Only valid if ::attachment_count > 0.
2755 */
2756 VkAttachmentReference * attachments;
2757 uint32_t input_count;
2758 VkAttachmentReference * input_attachments;
2759 uint32_t color_count;
2760 VkAttachmentReference * color_attachments;
2761 VkAttachmentReference * resolve_attachments;
2762
2763 VkAttachmentReference depth_stencil_attachment;
2764
2765 uint32_t view_mask;
2766
2767 /** Subpass has a depth/stencil self-dependency */
2768 bool has_ds_self_dep;
2769
2770 /** Subpass has at least one resolve attachment */
2771 bool has_resolve;
2772 };
2773
2774 static inline unsigned
2775 anv_subpass_view_count(const struct anv_subpass *subpass)
2776 {
2777 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2778 }
2779
2780 struct anv_render_pass_attachment {
2781 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2782 * its members individually.
2783 */
2784 VkFormat format;
2785 uint32_t samples;
2786 VkImageUsageFlags usage;
2787 VkAttachmentLoadOp load_op;
2788 VkAttachmentStoreOp store_op;
2789 VkAttachmentLoadOp stencil_load_op;
2790 VkImageLayout initial_layout;
2791 VkImageLayout final_layout;
2792 VkImageLayout first_subpass_layout;
2793
2794 /* The subpass id in which the attachment will be used last. */
2795 uint32_t last_subpass_idx;
2796 };
2797
2798 struct anv_render_pass {
2799 uint32_t attachment_count;
2800 uint32_t subpass_count;
2801 /* An array of subpass_count+1 flushes, one per subpass boundary */
2802 enum anv_pipe_bits * subpass_flushes;
2803 struct anv_render_pass_attachment * attachments;
2804 struct anv_subpass subpasses[0];
2805 };
2806
2807 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2808
2809 struct anv_query_pool {
2810 VkQueryType type;
2811 VkQueryPipelineStatisticFlags pipeline_statistics;
2812 /** Stride between slots, in bytes */
2813 uint32_t stride;
2814 /** Number of slots in this query pool */
2815 uint32_t slots;
2816 struct anv_bo bo;
2817 };
2818
2819 int anv_get_entrypoint_index(const char *name);
2820
2821 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2822 const char *name);
2823
2824 void anv_dump_image_to_ppm(struct anv_device *device,
2825 struct anv_image *image, unsigned miplevel,
2826 unsigned array_layer, VkImageAspectFlagBits aspect,
2827 const char *filename);
2828
2829 enum anv_dump_action {
2830 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2831 };
2832
2833 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2834 void anv_dump_finish(void);
2835
2836 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2837 struct anv_framebuffer *fb);
2838
2839 static inline uint32_t
2840 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2841 {
2842 /* This function must be called from within a subpass. */
2843 assert(cmd_state->pass && cmd_state->subpass);
2844
2845 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
2846
2847 /* The id of this subpass shouldn't exceed the number of subpasses in this
2848 * render pass minus 1.
2849 */
2850 assert(subpass_id < cmd_state->pass->subpass_count);
2851 return subpass_id;
2852 }
2853
2854 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2855 \
2856 static inline struct __anv_type * \
2857 __anv_type ## _from_handle(__VkType _handle) \
2858 { \
2859 return (struct __anv_type *) _handle; \
2860 } \
2861 \
2862 static inline __VkType \
2863 __anv_type ## _to_handle(struct __anv_type *_obj) \
2864 { \
2865 return (__VkType) _obj; \
2866 }
2867
2868 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2869 \
2870 static inline struct __anv_type * \
2871 __anv_type ## _from_handle(__VkType _handle) \
2872 { \
2873 return (struct __anv_type *)(uintptr_t) _handle; \
2874 } \
2875 \
2876 static inline __VkType \
2877 __anv_type ## _to_handle(struct __anv_type *_obj) \
2878 { \
2879 return (__VkType)(uintptr_t) _obj; \
2880 }
2881
2882 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2883 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2884
2885 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
2886 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
2887 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
2888 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
2889 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
2890
2891 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
2892 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
2893 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
2894 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
2895 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
2896 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
2897 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
2898 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
2899 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
2900 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
2901 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
2902 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
2903 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
2904 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
2905 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
2906 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
2907 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
2908 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
2909 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
2910 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
2911 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
2912 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback, VkDebugReportCallbackEXT)
2913 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversionKHR)
2914
2915 /* Gen-specific function declarations */
2916 #ifdef genX
2917 # include "anv_genX.h"
2918 #else
2919 # define genX(x) gen7_##x
2920 # include "anv_genX.h"
2921 # undef genX
2922 # define genX(x) gen75_##x
2923 # include "anv_genX.h"
2924 # undef genX
2925 # define genX(x) gen8_##x
2926 # include "anv_genX.h"
2927 # undef genX
2928 # define genX(x) gen9_##x
2929 # include "anv_genX.h"
2930 # undef genX
2931 # define genX(x) gen10_##x
2932 # include "anv_genX.h"
2933 # undef genX
2934 #endif
2935
2936 #endif /* ANV_PRIVATE_H */