anv: For pinned BOs, skip relocations, but track bo usage
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_gem.h"
46 #include "dev/gen_device_info.h"
47 #include "blorp/blorp.h"
48 #include "compiler/brw_compiler.h"
49 #include "util/macros.h"
50 #include "util/hash_table.h"
51 #include "util/list.h"
52 #include "util/set.h"
53 #include "util/u_atomic.h"
54 #include "util/u_vector.h"
55 #include "util/vma.h"
56 #include "vk_alloc.h"
57 #include "vk_debug_report.h"
58
59 /* Pre-declarations needed for WSI entrypoints */
60 struct wl_surface;
61 struct wl_display;
62 typedef struct xcb_connection_t xcb_connection_t;
63 typedef uint32_t xcb_visualid_t;
64 typedef uint32_t xcb_window_t;
65
66 struct anv_buffer;
67 struct anv_buffer_view;
68 struct anv_image_view;
69 struct anv_instance;
70
71 struct gen_l3_config;
72
73 #include <vulkan/vulkan.h>
74 #include <vulkan/vulkan_intel.h>
75 #include <vulkan/vk_icd.h>
76 #include <vulkan/vk_android_native_buffer.h>
77
78 #include "anv_entrypoints.h"
79 #include "anv_extensions.h"
80 #include "isl/isl.h"
81
82 #include "common/gen_debug.h"
83 #include "common/intel_log.h"
84 #include "wsi_common.h"
85
86 /* anv Virtual Memory Layout
87 * =========================
88 *
89 * When the anv driver is determining the virtual graphics addresses of memory
90 * objects itself using the softpin mechanism, the following memory ranges
91 * will be used.
92 *
93 * Three special considerations to notice:
94 *
95 * (1) the dynamic state pool is located within the same 4 GiB as the low
96 * heap. This is to work around a VF cache issue described in a comment in
97 * anv_physical_device_init_heaps.
98 *
99 * (2) the binding table pool is located at lower addresses than the surface
100 * state pool, within a 4 GiB range. This allows surface state base addresses
101 * to cover both binding tables (16 bit offsets) and surface states (32 bit
102 * offsets).
103 *
104 * (3) the last 4 GiB of the address space is withheld from the high
105 * heap. Various hardware units will read past the end of an object for
106 * various reasons. This healthy margin prevents reads from wrapping around
107 * 48-bit addresses.
108 */
109 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
110 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
111 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
112 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
113 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
114 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
115 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
116 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
117 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
118 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
119 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
120 #define HIGH_HEAP_MAX_ADDRESS 0xfffeffffffffULL
121
122 #define LOW_HEAP_SIZE \
123 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
124 #define HIGH_HEAP_SIZE \
125 (HIGH_HEAP_MAX_ADDRESS - HIGH_HEAP_MIN_ADDRESS + 1)
126 #define DYNAMIC_STATE_POOL_SIZE \
127 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
128 #define BINDING_TABLE_POOL_SIZE \
129 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
130 #define SURFACE_STATE_POOL_SIZE \
131 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
132 #define INSTRUCTION_STATE_POOL_SIZE \
133 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
134
135 /* Allowing different clear colors requires us to perform a depth resolve at
136 * the end of certain render passes. This is because while slow clears store
137 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
138 * See the PRMs for examples describing when additional resolves would be
139 * necessary. To enable fast clears without requiring extra resolves, we set
140 * the clear value to a globally-defined one. We could allow different values
141 * if the user doesn't expect coherent data during or after a render passes
142 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
143 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
144 * 1.0f seems to be the only value used. The only application that doesn't set
145 * this value does so through the usage of an seemingly uninitialized clear
146 * value.
147 */
148 #define ANV_HZ_FC_VAL 1.0f
149
150 #define MAX_VBS 28
151 #define MAX_SETS 8
152 #define MAX_RTS 8
153 #define MAX_VIEWPORTS 16
154 #define MAX_SCISSORS 16
155 #define MAX_PUSH_CONSTANTS_SIZE 128
156 #define MAX_DYNAMIC_BUFFERS 16
157 #define MAX_IMAGES 8
158 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
159
160 /* The kernel relocation API has a limitation of a 32-bit delta value
161 * applied to the address before it is written which, in spite of it being
162 * unsigned, is treated as signed . Because of the way that this maps to
163 * the Vulkan API, we cannot handle an offset into a buffer that does not
164 * fit into a signed 32 bits. The only mechanism we have for dealing with
165 * this at the moment is to limit all VkDeviceMemory objects to a maximum
166 * of 2GB each. The Vulkan spec allows us to do this:
167 *
168 * "Some platforms may have a limit on the maximum size of a single
169 * allocation. For example, certain systems may fail to create
170 * allocations with a size greater than or equal to 4GB. Such a limit is
171 * implementation-dependent, and if such a failure occurs then the error
172 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
173 *
174 * We don't use vk_error here because it's not an error so much as an
175 * indication to the application that the allocation is too large.
176 */
177 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
178
179 #define ANV_SVGS_VB_INDEX MAX_VBS
180 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
181
182 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
183
184 static inline uint32_t
185 align_down_npot_u32(uint32_t v, uint32_t a)
186 {
187 return v - (v % a);
188 }
189
190 static inline uint32_t
191 align_u32(uint32_t v, uint32_t a)
192 {
193 assert(a != 0 && a == (a & -a));
194 return (v + a - 1) & ~(a - 1);
195 }
196
197 static inline uint64_t
198 align_u64(uint64_t v, uint64_t a)
199 {
200 assert(a != 0 && a == (a & -a));
201 return (v + a - 1) & ~(a - 1);
202 }
203
204 static inline int32_t
205 align_i32(int32_t v, int32_t a)
206 {
207 assert(a != 0 && a == (a & -a));
208 return (v + a - 1) & ~(a - 1);
209 }
210
211 /** Alignment must be a power of 2. */
212 static inline bool
213 anv_is_aligned(uintmax_t n, uintmax_t a)
214 {
215 assert(a == (a & -a));
216 return (n & (a - 1)) == 0;
217 }
218
219 static inline uint32_t
220 anv_minify(uint32_t n, uint32_t levels)
221 {
222 if (unlikely(n == 0))
223 return 0;
224 else
225 return MAX2(n >> levels, 1);
226 }
227
228 static inline float
229 anv_clamp_f(float f, float min, float max)
230 {
231 assert(min < max);
232
233 if (f > max)
234 return max;
235 else if (f < min)
236 return min;
237 else
238 return f;
239 }
240
241 static inline bool
242 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
243 {
244 if (*inout_mask & clear_mask) {
245 *inout_mask &= ~clear_mask;
246 return true;
247 } else {
248 return false;
249 }
250 }
251
252 static inline union isl_color_value
253 vk_to_isl_color(VkClearColorValue color)
254 {
255 return (union isl_color_value) {
256 .u32 = {
257 color.uint32[0],
258 color.uint32[1],
259 color.uint32[2],
260 color.uint32[3],
261 },
262 };
263 }
264
265 #define for_each_bit(b, dword) \
266 for (uint32_t __dword = (dword); \
267 (b) = __builtin_ffs(__dword) - 1, __dword; \
268 __dword &= ~(1 << (b)))
269
270 #define typed_memcpy(dest, src, count) ({ \
271 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
272 memcpy((dest), (src), (count) * sizeof(*(src))); \
273 })
274
275 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
276 * to be added here in order to utilize mapping in debug/error/perf macros.
277 */
278 #define REPORT_OBJECT_TYPE(o) \
279 __builtin_choose_expr ( \
280 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
281 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
282 __builtin_choose_expr ( \
283 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
284 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
285 __builtin_choose_expr ( \
286 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
287 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
288 __builtin_choose_expr ( \
289 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
290 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
291 __builtin_choose_expr ( \
292 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
293 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
294 __builtin_choose_expr ( \
295 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
296 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
297 __builtin_choose_expr ( \
298 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
299 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
300 __builtin_choose_expr ( \
301 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
302 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
303 __builtin_choose_expr ( \
304 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
305 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
306 __builtin_choose_expr ( \
307 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
308 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
309 __builtin_choose_expr ( \
310 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
311 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
312 __builtin_choose_expr ( \
313 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
314 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
315 __builtin_choose_expr ( \
316 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
317 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
318 __builtin_choose_expr ( \
319 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
320 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
321 __builtin_choose_expr ( \
322 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
323 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
324 __builtin_choose_expr ( \
325 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
326 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
327 __builtin_choose_expr ( \
328 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
329 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
330 __builtin_choose_expr ( \
331 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
332 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
333 __builtin_choose_expr ( \
334 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
335 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
336 __builtin_choose_expr ( \
337 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
338 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
339 __builtin_choose_expr ( \
340 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
341 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
342 __builtin_choose_expr ( \
343 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
344 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
345 __builtin_choose_expr ( \
346 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
347 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
348 __builtin_choose_expr ( \
349 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
350 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
351 __builtin_choose_expr ( \
352 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
353 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
354 __builtin_choose_expr ( \
355 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
356 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
357 __builtin_choose_expr ( \
358 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
359 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
360 __builtin_choose_expr ( \
361 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
362 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
363 __builtin_choose_expr ( \
364 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
365 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
366 __builtin_choose_expr ( \
367 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
368 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
369 __builtin_choose_expr ( \
370 __builtin_types_compatible_p (__typeof (o), void*), \
371 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
372 /* The void expression results in a compile-time error \
373 when assigning the result to something. */ \
374 (void)0)))))))))))))))))))))))))))))))
375
376 /* Whenever we generate an error, pass it through this function. Useful for
377 * debugging, where we can break on it. Only call at error site, not when
378 * propagating errors. Might be useful to plug in a stack trace here.
379 */
380
381 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
382 VkDebugReportObjectTypeEXT type, VkResult error,
383 const char *file, int line, const char *format, ...);
384
385 #ifdef DEBUG
386 #define vk_error(error) __vk_errorf(NULL, NULL,\
387 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
388 error, __FILE__, __LINE__, NULL)
389 #define vk_errorf(instance, obj, error, format, ...)\
390 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
391 __FILE__, __LINE__, format, ## __VA_ARGS__)
392 #else
393 #define vk_error(error) error
394 #define vk_errorf(instance, obj, error, format, ...) error
395 #endif
396
397 /**
398 * Warn on ignored extension structs.
399 *
400 * The Vulkan spec requires us to ignore unsupported or unknown structs in
401 * a pNext chain. In debug mode, emitting warnings for ignored structs may
402 * help us discover structs that we should not have ignored.
403 *
404 *
405 * From the Vulkan 1.0.38 spec:
406 *
407 * Any component of the implementation (the loader, any enabled layers,
408 * and drivers) must skip over, without processing (other than reading the
409 * sType and pNext members) any chained structures with sType values not
410 * defined by extensions supported by that component.
411 */
412 #define anv_debug_ignored_stype(sType) \
413 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
414
415 void __anv_perf_warn(struct anv_instance *instance, const void *object,
416 VkDebugReportObjectTypeEXT type, const char *file,
417 int line, const char *format, ...)
418 anv_printflike(6, 7);
419 void anv_loge(const char *format, ...) anv_printflike(1, 2);
420 void anv_loge_v(const char *format, va_list va);
421
422 /**
423 * Print a FINISHME message, including its source location.
424 */
425 #define anv_finishme(format, ...) \
426 do { \
427 static bool reported = false; \
428 if (!reported) { \
429 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
430 ##__VA_ARGS__); \
431 reported = true; \
432 } \
433 } while (0)
434
435 /**
436 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
437 */
438 #define anv_perf_warn(instance, obj, format, ...) \
439 do { \
440 static bool reported = false; \
441 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
442 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
443 format, ##__VA_ARGS__); \
444 reported = true; \
445 } \
446 } while (0)
447
448 /* A non-fatal assert. Useful for debugging. */
449 #ifdef DEBUG
450 #define anv_assert(x) ({ \
451 if (unlikely(!(x))) \
452 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
453 })
454 #else
455 #define anv_assert(x)
456 #endif
457
458 /* A multi-pointer allocator
459 *
460 * When copying data structures from the user (such as a render pass), it's
461 * common to need to allocate data for a bunch of different things. Instead
462 * of doing several allocations and having to handle all of the error checking
463 * that entails, it can be easier to do a single allocation. This struct
464 * helps facilitate that. The intended usage looks like this:
465 *
466 * ANV_MULTIALLOC(ma)
467 * anv_multialloc_add(&ma, &main_ptr, 1);
468 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
469 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
470 *
471 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
472 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
473 */
474 struct anv_multialloc {
475 size_t size;
476 size_t align;
477
478 uint32_t ptr_count;
479 void **ptrs[8];
480 };
481
482 #define ANV_MULTIALLOC_INIT \
483 ((struct anv_multialloc) { 0, })
484
485 #define ANV_MULTIALLOC(_name) \
486 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
487
488 __attribute__((always_inline))
489 static inline void
490 _anv_multialloc_add(struct anv_multialloc *ma,
491 void **ptr, size_t size, size_t align)
492 {
493 size_t offset = align_u64(ma->size, align);
494 ma->size = offset + size;
495 ma->align = MAX2(ma->align, align);
496
497 /* Store the offset in the pointer. */
498 *ptr = (void *)(uintptr_t)offset;
499
500 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
501 ma->ptrs[ma->ptr_count++] = ptr;
502 }
503
504 #define anv_multialloc_add_size(_ma, _ptr, _size) \
505 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
506
507 #define anv_multialloc_add(_ma, _ptr, _count) \
508 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
509
510 __attribute__((always_inline))
511 static inline void *
512 anv_multialloc_alloc(struct anv_multialloc *ma,
513 const VkAllocationCallbacks *alloc,
514 VkSystemAllocationScope scope)
515 {
516 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
517 if (!ptr)
518 return NULL;
519
520 /* Fill out each of the pointers with their final value.
521 *
522 * for (uint32_t i = 0; i < ma->ptr_count; i++)
523 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
524 *
525 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
526 * constant, GCC is incapable of figuring this out and unrolling the loop
527 * so we have to give it a little help.
528 */
529 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
530 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
531 if ((_i) < ma->ptr_count) \
532 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
533 _ANV_MULTIALLOC_UPDATE_POINTER(0);
534 _ANV_MULTIALLOC_UPDATE_POINTER(1);
535 _ANV_MULTIALLOC_UPDATE_POINTER(2);
536 _ANV_MULTIALLOC_UPDATE_POINTER(3);
537 _ANV_MULTIALLOC_UPDATE_POINTER(4);
538 _ANV_MULTIALLOC_UPDATE_POINTER(5);
539 _ANV_MULTIALLOC_UPDATE_POINTER(6);
540 _ANV_MULTIALLOC_UPDATE_POINTER(7);
541 #undef _ANV_MULTIALLOC_UPDATE_POINTER
542
543 return ptr;
544 }
545
546 __attribute__((always_inline))
547 static inline void *
548 anv_multialloc_alloc2(struct anv_multialloc *ma,
549 const VkAllocationCallbacks *parent_alloc,
550 const VkAllocationCallbacks *alloc,
551 VkSystemAllocationScope scope)
552 {
553 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
554 }
555
556 struct anv_bo {
557 uint32_t gem_handle;
558
559 /* Index into the current validation list. This is used by the
560 * validation list building alrogithm to track which buffers are already
561 * in the validation list so that we can ensure uniqueness.
562 */
563 uint32_t index;
564
565 /* Last known offset. This value is provided by the kernel when we
566 * execbuf and is used as the presumed offset for the next bunch of
567 * relocations.
568 */
569 uint64_t offset;
570
571 uint64_t size;
572 void *map;
573
574 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
575 uint32_t flags;
576 };
577
578 static inline void
579 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
580 {
581 bo->gem_handle = gem_handle;
582 bo->index = 0;
583 bo->offset = -1;
584 bo->size = size;
585 bo->map = NULL;
586 bo->flags = 0;
587 }
588
589 /* Represents a lock-free linked list of "free" things. This is used by
590 * both the block pool and the state pools. Unfortunately, in order to
591 * solve the ABA problem, we can't use a single uint32_t head.
592 */
593 union anv_free_list {
594 struct {
595 int32_t offset;
596
597 /* A simple count that is incremented every time the head changes. */
598 uint32_t count;
599 };
600 uint64_t u64;
601 };
602
603 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
604
605 struct anv_block_state {
606 union {
607 struct {
608 uint32_t next;
609 uint32_t end;
610 };
611 uint64_t u64;
612 };
613 };
614
615 struct anv_block_pool {
616 struct anv_device *device;
617
618 uint64_t bo_flags;
619
620 struct anv_bo bo;
621
622 /* The address where the start of the pool is pinned. The various bos that
623 * are created as the pool grows will have addresses in the range
624 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
625 */
626 uint64_t start_address;
627
628 /* The offset from the start of the bo to the "center" of the block
629 * pool. Pointers to allocated blocks are given by
630 * bo.map + center_bo_offset + offsets.
631 */
632 uint32_t center_bo_offset;
633
634 /* Current memory map of the block pool. This pointer may or may not
635 * point to the actual beginning of the block pool memory. If
636 * anv_block_pool_alloc_back has ever been called, then this pointer
637 * will point to the "center" position of the buffer and all offsets
638 * (negative or positive) given out by the block pool alloc functions
639 * will be valid relative to this pointer.
640 *
641 * In particular, map == bo.map + center_offset
642 */
643 void *map;
644 int fd;
645
646 /**
647 * Array of mmaps and gem handles owned by the block pool, reclaimed when
648 * the block pool is destroyed.
649 */
650 struct u_vector mmap_cleanups;
651
652 struct anv_block_state state;
653
654 struct anv_block_state back_state;
655 };
656
657 /* Block pools are backed by a fixed-size 1GB memfd */
658 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
659
660 /* The center of the block pool is also the middle of the memfd. This may
661 * change in the future if we decide differently for some reason.
662 */
663 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
664
665 static inline uint32_t
666 anv_block_pool_size(struct anv_block_pool *pool)
667 {
668 return pool->state.end + pool->back_state.end;
669 }
670
671 struct anv_state {
672 int32_t offset;
673 uint32_t alloc_size;
674 void *map;
675 };
676
677 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
678
679 struct anv_fixed_size_state_pool {
680 union anv_free_list free_list;
681 struct anv_block_state block;
682 };
683
684 #define ANV_MIN_STATE_SIZE_LOG2 6
685 #define ANV_MAX_STATE_SIZE_LOG2 20
686
687 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
688
689 struct anv_state_pool {
690 struct anv_block_pool block_pool;
691
692 /* The size of blocks which will be allocated from the block pool */
693 uint32_t block_size;
694
695 /** Free list for "back" allocations */
696 union anv_free_list back_alloc_free_list;
697
698 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
699 };
700
701 struct anv_state_stream_block;
702
703 struct anv_state_stream {
704 struct anv_state_pool *state_pool;
705
706 /* The size of blocks to allocate from the state pool */
707 uint32_t block_size;
708
709 /* Current block we're allocating from */
710 struct anv_state block;
711
712 /* Offset into the current block at which to allocate the next state */
713 uint32_t next;
714
715 /* List of all blocks allocated from this pool */
716 struct anv_state_stream_block *block_list;
717 };
718
719 /* The block_pool functions exported for testing only. The block pool should
720 * only be used via a state pool (see below).
721 */
722 VkResult anv_block_pool_init(struct anv_block_pool *pool,
723 struct anv_device *device,
724 uint64_t start_address,
725 uint32_t initial_size,
726 uint64_t bo_flags);
727 void anv_block_pool_finish(struct anv_block_pool *pool);
728 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
729 uint32_t block_size);
730 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
731 uint32_t block_size);
732
733 VkResult anv_state_pool_init(struct anv_state_pool *pool,
734 struct anv_device *device,
735 uint64_t start_address,
736 uint32_t block_size,
737 uint64_t bo_flags);
738 void anv_state_pool_finish(struct anv_state_pool *pool);
739 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
740 uint32_t state_size, uint32_t alignment);
741 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
742 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
743 void anv_state_stream_init(struct anv_state_stream *stream,
744 struct anv_state_pool *state_pool,
745 uint32_t block_size);
746 void anv_state_stream_finish(struct anv_state_stream *stream);
747 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
748 uint32_t size, uint32_t alignment);
749
750 /**
751 * Implements a pool of re-usable BOs. The interface is identical to that
752 * of block_pool except that each block is its own BO.
753 */
754 struct anv_bo_pool {
755 struct anv_device *device;
756
757 uint64_t bo_flags;
758
759 void *free_list[16];
760 };
761
762 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
763 uint64_t bo_flags);
764 void anv_bo_pool_finish(struct anv_bo_pool *pool);
765 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
766 uint32_t size);
767 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
768
769 struct anv_scratch_bo {
770 bool exists;
771 struct anv_bo bo;
772 };
773
774 struct anv_scratch_pool {
775 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
776 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
777 };
778
779 void anv_scratch_pool_init(struct anv_device *device,
780 struct anv_scratch_pool *pool);
781 void anv_scratch_pool_finish(struct anv_device *device,
782 struct anv_scratch_pool *pool);
783 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
784 struct anv_scratch_pool *pool,
785 gl_shader_stage stage,
786 unsigned per_thread_scratch);
787
788 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
789 struct anv_bo_cache {
790 struct hash_table *bo_map;
791 pthread_mutex_t mutex;
792 };
793
794 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
795 void anv_bo_cache_finish(struct anv_bo_cache *cache);
796 VkResult anv_bo_cache_alloc(struct anv_device *device,
797 struct anv_bo_cache *cache,
798 uint64_t size, struct anv_bo **bo);
799 VkResult anv_bo_cache_import(struct anv_device *device,
800 struct anv_bo_cache *cache,
801 int fd, struct anv_bo **bo);
802 VkResult anv_bo_cache_export(struct anv_device *device,
803 struct anv_bo_cache *cache,
804 struct anv_bo *bo_in, int *fd_out);
805 void anv_bo_cache_release(struct anv_device *device,
806 struct anv_bo_cache *cache,
807 struct anv_bo *bo);
808
809 struct anv_memory_type {
810 /* Standard bits passed on to the client */
811 VkMemoryPropertyFlags propertyFlags;
812 uint32_t heapIndex;
813
814 /* Driver-internal book-keeping */
815 VkBufferUsageFlags valid_buffer_usage;
816 };
817
818 struct anv_memory_heap {
819 /* Standard bits passed on to the client */
820 VkDeviceSize size;
821 VkMemoryHeapFlags flags;
822
823 /* Driver-internal book-keeping */
824 bool supports_48bit_addresses;
825 };
826
827 struct anv_physical_device {
828 VK_LOADER_DATA _loader_data;
829
830 struct anv_instance * instance;
831 uint32_t chipset_id;
832 bool no_hw;
833 char path[20];
834 const char * name;
835 struct gen_device_info info;
836 /** Amount of "GPU memory" we want to advertise
837 *
838 * Clearly, this value is bogus since Intel is a UMA architecture. On
839 * gen7 platforms, we are limited by GTT size unless we want to implement
840 * fine-grained tracking and GTT splitting. On Broadwell and above we are
841 * practically unlimited. However, we will never report more than 3/4 of
842 * the total system ram to try and avoid running out of RAM.
843 */
844 bool supports_48bit_addresses;
845 struct brw_compiler * compiler;
846 struct isl_device isl_dev;
847 int cmd_parser_version;
848 bool has_exec_async;
849 bool has_exec_capture;
850 bool has_exec_fence;
851 bool has_syncobj;
852 bool has_syncobj_wait;
853 bool has_context_priority;
854 bool use_softpin;
855
856 struct anv_device_extension_table supported_extensions;
857
858 uint32_t eu_total;
859 uint32_t subslice_total;
860
861 struct {
862 uint32_t type_count;
863 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
864 uint32_t heap_count;
865 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
866 } memory;
867
868 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
869 uint8_t driver_uuid[VK_UUID_SIZE];
870 uint8_t device_uuid[VK_UUID_SIZE];
871
872 struct wsi_device wsi_device;
873 int local_fd;
874 };
875
876 struct anv_instance {
877 VK_LOADER_DATA _loader_data;
878
879 VkAllocationCallbacks alloc;
880
881 uint32_t apiVersion;
882 struct anv_instance_extension_table enabled_extensions;
883 struct anv_dispatch_table dispatch;
884
885 int physicalDeviceCount;
886 struct anv_physical_device physicalDevice;
887
888 struct vk_debug_report_instance debug_report_callbacks;
889 };
890
891 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
892 void anv_finish_wsi(struct anv_physical_device *physical_device);
893
894 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
895 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
896 const char *name);
897
898 struct anv_queue {
899 VK_LOADER_DATA _loader_data;
900
901 struct anv_device * device;
902
903 VkDeviceQueueCreateFlags flags;
904 };
905
906 struct anv_pipeline_cache {
907 struct anv_device * device;
908 pthread_mutex_t mutex;
909
910 struct hash_table * cache;
911 };
912
913 struct anv_pipeline_bind_map;
914
915 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
916 struct anv_device *device,
917 bool cache_enabled);
918 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
919
920 struct anv_shader_bin *
921 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
922 const void *key, uint32_t key_size);
923 struct anv_shader_bin *
924 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
925 const void *key_data, uint32_t key_size,
926 const void *kernel_data, uint32_t kernel_size,
927 const struct brw_stage_prog_data *prog_data,
928 uint32_t prog_data_size,
929 const struct anv_pipeline_bind_map *bind_map);
930
931 struct anv_device {
932 VK_LOADER_DATA _loader_data;
933
934 VkAllocationCallbacks alloc;
935
936 struct anv_instance * instance;
937 uint32_t chipset_id;
938 bool no_hw;
939 struct gen_device_info info;
940 struct isl_device isl_dev;
941 int context_id;
942 int fd;
943 bool can_chain_batches;
944 bool robust_buffer_access;
945 struct anv_device_extension_table enabled_extensions;
946 struct anv_dispatch_table dispatch;
947
948 pthread_mutex_t vma_mutex;
949 struct util_vma_heap vma_lo;
950 struct util_vma_heap vma_hi;
951 uint64_t vma_lo_available;
952 uint64_t vma_hi_available;
953
954 struct anv_bo_pool batch_bo_pool;
955
956 struct anv_bo_cache bo_cache;
957
958 struct anv_state_pool dynamic_state_pool;
959 struct anv_state_pool instruction_state_pool;
960 struct anv_state_pool binding_table_pool;
961 struct anv_state_pool surface_state_pool;
962
963 struct anv_bo workaround_bo;
964 struct anv_bo trivial_batch_bo;
965 struct anv_bo hiz_clear_bo;
966
967 struct anv_pipeline_cache blorp_shader_cache;
968 struct blorp_context blorp;
969
970 struct anv_state border_colors;
971
972 struct anv_queue queue;
973
974 struct anv_scratch_pool scratch_pool;
975
976 uint32_t default_mocs;
977
978 pthread_mutex_t mutex;
979 pthread_cond_t queue_submit;
980 bool lost;
981 };
982
983 static inline struct anv_state_pool *
984 anv_binding_table_pool(struct anv_device *device)
985 {
986 if (device->instance->physicalDevice.use_softpin)
987 return &device->binding_table_pool;
988 else
989 return &device->surface_state_pool;
990 }
991
992 static inline struct anv_state
993 anv_binding_table_pool_alloc(struct anv_device *device) {
994 if (device->instance->physicalDevice.use_softpin)
995 return anv_state_pool_alloc(&device->binding_table_pool,
996 device->binding_table_pool.block_size, 0);
997 else
998 return anv_state_pool_alloc_back(&device->surface_state_pool);
999 }
1000
1001 static inline void
1002 anv_binding_table_pool_free(struct anv_device *device, struct anv_state state) {
1003 anv_state_pool_free(anv_binding_table_pool(device), state);
1004 }
1005
1006 static void inline
1007 anv_state_flush(struct anv_device *device, struct anv_state state)
1008 {
1009 if (device->info.has_llc)
1010 return;
1011
1012 gen_flush_range(state.map, state.alloc_size);
1013 }
1014
1015 void anv_device_init_blorp(struct anv_device *device);
1016 void anv_device_finish_blorp(struct anv_device *device);
1017
1018 VkResult anv_device_execbuf(struct anv_device *device,
1019 struct drm_i915_gem_execbuffer2 *execbuf,
1020 struct anv_bo **execbuf_bos);
1021 VkResult anv_device_query_status(struct anv_device *device);
1022 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
1023 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
1024 int64_t timeout);
1025
1026 void* anv_gem_mmap(struct anv_device *device,
1027 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
1028 void anv_gem_munmap(void *p, uint64_t size);
1029 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
1030 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
1031 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
1032 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
1033 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
1034 int anv_gem_execbuffer(struct anv_device *device,
1035 struct drm_i915_gem_execbuffer2 *execbuf);
1036 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
1037 uint32_t stride, uint32_t tiling);
1038 int anv_gem_create_context(struct anv_device *device);
1039 bool anv_gem_has_context_priority(int fd);
1040 int anv_gem_destroy_context(struct anv_device *device, int context);
1041 int anv_gem_set_context_param(int fd, int context, uint32_t param,
1042 uint64_t value);
1043 int anv_gem_get_context_param(int fd, int context, uint32_t param,
1044 uint64_t *value);
1045 int anv_gem_get_param(int fd, uint32_t param);
1046 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
1047 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
1048 int anv_gem_get_aperture(int fd, uint64_t *size);
1049 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
1050 uint32_t *active, uint32_t *pending);
1051 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
1052 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
1053 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
1054 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
1055 uint32_t read_domains, uint32_t write_domain);
1056 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
1057 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
1058 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
1059 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
1060 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
1061 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
1062 uint32_t handle);
1063 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
1064 uint32_t handle, int fd);
1065 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
1066 bool anv_gem_supports_syncobj_wait(int fd);
1067 int anv_gem_syncobj_wait(struct anv_device *device,
1068 uint32_t *handles, uint32_t num_handles,
1069 int64_t abs_timeout_ns, bool wait_all);
1070
1071 bool anv_vma_alloc(struct anv_device *device, struct anv_bo *bo);
1072 void anv_vma_free(struct anv_device *device, struct anv_bo *bo);
1073
1074 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
1075
1076 struct anv_reloc_list {
1077 uint32_t num_relocs;
1078 uint32_t array_length;
1079 struct drm_i915_gem_relocation_entry * relocs;
1080 struct anv_bo ** reloc_bos;
1081 struct set * deps;
1082 };
1083
1084 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
1085 const VkAllocationCallbacks *alloc);
1086 void anv_reloc_list_finish(struct anv_reloc_list *list,
1087 const VkAllocationCallbacks *alloc);
1088
1089 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
1090 const VkAllocationCallbacks *alloc,
1091 uint32_t offset, struct anv_bo *target_bo,
1092 uint32_t delta);
1093
1094 struct anv_batch_bo {
1095 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1096 struct list_head link;
1097
1098 struct anv_bo bo;
1099
1100 /* Bytes actually consumed in this batch BO */
1101 uint32_t length;
1102
1103 struct anv_reloc_list relocs;
1104 };
1105
1106 struct anv_batch {
1107 const VkAllocationCallbacks * alloc;
1108
1109 void * start;
1110 void * end;
1111 void * next;
1112
1113 struct anv_reloc_list * relocs;
1114
1115 /* This callback is called (with the associated user data) in the event
1116 * that the batch runs out of space.
1117 */
1118 VkResult (*extend_cb)(struct anv_batch *, void *);
1119 void * user_data;
1120
1121 /**
1122 * Current error status of the command buffer. Used to track inconsistent
1123 * or incomplete command buffer states that are the consequence of run-time
1124 * errors such as out of memory scenarios. We want to track this in the
1125 * batch because the command buffer object is not visible to some parts
1126 * of the driver.
1127 */
1128 VkResult status;
1129 };
1130
1131 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1132 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1133 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1134 void *location, struct anv_bo *bo, uint32_t offset);
1135 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1136 struct anv_batch *batch);
1137
1138 static inline VkResult
1139 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1140 {
1141 assert(error != VK_SUCCESS);
1142 if (batch->status == VK_SUCCESS)
1143 batch->status = error;
1144 return batch->status;
1145 }
1146
1147 static inline bool
1148 anv_batch_has_error(struct anv_batch *batch)
1149 {
1150 return batch->status != VK_SUCCESS;
1151 }
1152
1153 struct anv_address {
1154 struct anv_bo *bo;
1155 uint32_t offset;
1156 };
1157
1158 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1159
1160 static inline bool
1161 anv_address_is_null(struct anv_address addr)
1162 {
1163 return addr.bo == NULL && addr.offset == 0;
1164 }
1165
1166 static inline uint64_t
1167 anv_address_physical(struct anv_address addr)
1168 {
1169 if (addr.bo && (addr.bo->flags & EXEC_OBJECT_PINNED))
1170 return gen_canonical_address(addr.bo->offset + addr.offset);
1171 else
1172 return gen_canonical_address(addr.offset);
1173 }
1174
1175 static inline struct anv_address
1176 anv_address_add(struct anv_address addr, uint64_t offset)
1177 {
1178 addr.offset += offset;
1179 return addr;
1180 }
1181
1182 static inline void
1183 write_reloc(const struct anv_device *device, void *p, uint64_t v, bool flush)
1184 {
1185 unsigned reloc_size = 0;
1186 if (device->info.gen >= 8) {
1187 reloc_size = sizeof(uint64_t);
1188 *(uint64_t *)p = gen_canonical_address(v);
1189 } else {
1190 reloc_size = sizeof(uint32_t);
1191 *(uint32_t *)p = v;
1192 }
1193
1194 if (flush && !device->info.has_llc)
1195 gen_flush_range(p, reloc_size);
1196 }
1197
1198 static inline uint64_t
1199 _anv_combine_address(struct anv_batch *batch, void *location,
1200 const struct anv_address address, uint32_t delta)
1201 {
1202 if (address.bo == NULL) {
1203 return address.offset + delta;
1204 } else {
1205 assert(batch->start <= location && location < batch->end);
1206
1207 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1208 }
1209 }
1210
1211 #define __gen_address_type struct anv_address
1212 #define __gen_user_data struct anv_batch
1213 #define __gen_combine_address _anv_combine_address
1214
1215 /* Wrapper macros needed to work around preprocessor argument issues. In
1216 * particular, arguments don't get pre-evaluated if they are concatenated.
1217 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1218 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1219 * We can work around this easily enough with these helpers.
1220 */
1221 #define __anv_cmd_length(cmd) cmd ## _length
1222 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1223 #define __anv_cmd_header(cmd) cmd ## _header
1224 #define __anv_cmd_pack(cmd) cmd ## _pack
1225 #define __anv_reg_num(reg) reg ## _num
1226
1227 #define anv_pack_struct(dst, struc, ...) do { \
1228 struct struc __template = { \
1229 __VA_ARGS__ \
1230 }; \
1231 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1232 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1233 } while (0)
1234
1235 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1236 void *__dst = anv_batch_emit_dwords(batch, n); \
1237 if (__dst) { \
1238 struct cmd __template = { \
1239 __anv_cmd_header(cmd), \
1240 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1241 __VA_ARGS__ \
1242 }; \
1243 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1244 } \
1245 __dst; \
1246 })
1247
1248 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1249 do { \
1250 uint32_t *dw; \
1251 \
1252 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1253 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1254 if (!dw) \
1255 break; \
1256 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1257 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1258 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1259 } while (0)
1260
1261 #define anv_batch_emit(batch, cmd, name) \
1262 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1263 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1264 __builtin_expect(_dst != NULL, 1); \
1265 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1266 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1267 _dst = NULL; \
1268 }))
1269
1270 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1271 .GraphicsDataTypeGFDT = 0, \
1272 .LLCCacheabilityControlLLCCC = 0, \
1273 .L3CacheabilityControlL3CC = 1, \
1274 }
1275
1276 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1277 .LLCeLLCCacheabilityControlLLCCC = 0, \
1278 .L3CacheabilityControlL3CC = 1, \
1279 }
1280
1281 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1282 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1283 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1284 .AgeforQUADLRU = 0 \
1285 }
1286
1287 /* Skylake: MOCS is now an index into an array of 62 different caching
1288 * configurations programmed by the kernel.
1289 */
1290
1291 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1292 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1293 .IndextoMOCSTables = 2 \
1294 }
1295
1296 #define GEN9_MOCS_PTE { \
1297 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1298 .IndextoMOCSTables = 1 \
1299 }
1300
1301 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1302 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1303 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1304 .IndextoMOCSTables = 2 \
1305 }
1306
1307 #define GEN10_MOCS_PTE { \
1308 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1309 .IndextoMOCSTables = 1 \
1310 }
1311
1312 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1313 #define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1314 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1315 .IndextoMOCSTables = 2 \
1316 }
1317
1318 #define GEN11_MOCS_PTE { \
1319 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1320 .IndextoMOCSTables = 1 \
1321 }
1322
1323 struct anv_device_memory {
1324 struct anv_bo * bo;
1325 struct anv_memory_type * type;
1326 VkDeviceSize map_size;
1327 void * map;
1328 };
1329
1330 /**
1331 * Header for Vertex URB Entry (VUE)
1332 */
1333 struct anv_vue_header {
1334 uint32_t Reserved;
1335 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1336 uint32_t ViewportIndex;
1337 float PointWidth;
1338 };
1339
1340 struct anv_descriptor_set_binding_layout {
1341 #ifndef NDEBUG
1342 /* The type of the descriptors in this binding */
1343 VkDescriptorType type;
1344 #endif
1345
1346 /* Number of array elements in this binding */
1347 uint16_t array_size;
1348
1349 /* Index into the flattend descriptor set */
1350 uint16_t descriptor_index;
1351
1352 /* Index into the dynamic state array for a dynamic buffer */
1353 int16_t dynamic_offset_index;
1354
1355 /* Index into the descriptor set buffer views */
1356 int16_t buffer_index;
1357
1358 struct {
1359 /* Index into the binding table for the associated surface */
1360 int16_t surface_index;
1361
1362 /* Index into the sampler table for the associated sampler */
1363 int16_t sampler_index;
1364
1365 /* Index into the image table for the associated image */
1366 int16_t image_index;
1367 } stage[MESA_SHADER_STAGES];
1368
1369 /* Immutable samplers (or NULL if no immutable samplers) */
1370 struct anv_sampler **immutable_samplers;
1371 };
1372
1373 struct anv_descriptor_set_layout {
1374 /* Descriptor set layouts can be destroyed at almost any time */
1375 uint32_t ref_cnt;
1376
1377 /* Number of bindings in this descriptor set */
1378 uint16_t binding_count;
1379
1380 /* Total size of the descriptor set with room for all array entries */
1381 uint16_t size;
1382
1383 /* Shader stages affected by this descriptor set */
1384 uint16_t shader_stages;
1385
1386 /* Number of buffers in this descriptor set */
1387 uint16_t buffer_count;
1388
1389 /* Number of dynamic offsets used by this descriptor set */
1390 uint16_t dynamic_offset_count;
1391
1392 /* Bindings in this descriptor set */
1393 struct anv_descriptor_set_binding_layout binding[0];
1394 };
1395
1396 static inline void
1397 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
1398 {
1399 assert(layout && layout->ref_cnt >= 1);
1400 p_atomic_inc(&layout->ref_cnt);
1401 }
1402
1403 static inline void
1404 anv_descriptor_set_layout_unref(struct anv_device *device,
1405 struct anv_descriptor_set_layout *layout)
1406 {
1407 assert(layout && layout->ref_cnt >= 1);
1408 if (p_atomic_dec_zero(&layout->ref_cnt))
1409 vk_free(&device->alloc, layout);
1410 }
1411
1412 struct anv_descriptor {
1413 VkDescriptorType type;
1414
1415 union {
1416 struct {
1417 VkImageLayout layout;
1418 struct anv_image_view *image_view;
1419 struct anv_sampler *sampler;
1420 };
1421
1422 struct {
1423 struct anv_buffer *buffer;
1424 uint64_t offset;
1425 uint64_t range;
1426 };
1427
1428 struct anv_buffer_view *buffer_view;
1429 };
1430 };
1431
1432 struct anv_descriptor_set {
1433 struct anv_descriptor_set_layout *layout;
1434 uint32_t size;
1435 uint32_t buffer_count;
1436 struct anv_buffer_view *buffer_views;
1437 struct anv_descriptor descriptors[0];
1438 };
1439
1440 struct anv_buffer_view {
1441 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1442 uint64_t range; /**< VkBufferViewCreateInfo::range */
1443
1444 struct anv_address address;
1445
1446 struct anv_state surface_state;
1447 struct anv_state storage_surface_state;
1448 struct anv_state writeonly_storage_surface_state;
1449
1450 struct brw_image_param storage_image_param;
1451 };
1452
1453 struct anv_push_descriptor_set {
1454 struct anv_descriptor_set set;
1455
1456 /* Put this field right behind anv_descriptor_set so it fills up the
1457 * descriptors[0] field. */
1458 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1459 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1460 };
1461
1462 struct anv_descriptor_pool {
1463 uint32_t size;
1464 uint32_t next;
1465 uint32_t free_list;
1466
1467 struct anv_state_stream surface_state_stream;
1468 void *surface_state_free_list;
1469
1470 char data[0];
1471 };
1472
1473 enum anv_descriptor_template_entry_type {
1474 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1475 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1476 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1477 };
1478
1479 struct anv_descriptor_template_entry {
1480 /* The type of descriptor in this entry */
1481 VkDescriptorType type;
1482
1483 /* Binding in the descriptor set */
1484 uint32_t binding;
1485
1486 /* Offset at which to write into the descriptor set binding */
1487 uint32_t array_element;
1488
1489 /* Number of elements to write into the descriptor set binding */
1490 uint32_t array_count;
1491
1492 /* Offset into the user provided data */
1493 size_t offset;
1494
1495 /* Stride between elements into the user provided data */
1496 size_t stride;
1497 };
1498
1499 struct anv_descriptor_update_template {
1500 VkPipelineBindPoint bind_point;
1501
1502 /* The descriptor set this template corresponds to. This value is only
1503 * valid if the template was created with the templateType
1504 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1505 */
1506 uint8_t set;
1507
1508 /* Number of entries in this template */
1509 uint32_t entry_count;
1510
1511 /* Entries of the template */
1512 struct anv_descriptor_template_entry entries[0];
1513 };
1514
1515 size_t
1516 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1517
1518 size_t
1519 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1520
1521 void
1522 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1523 const struct gen_device_info * const devinfo,
1524 const VkDescriptorImageInfo * const info,
1525 VkDescriptorType type,
1526 uint32_t binding,
1527 uint32_t element);
1528
1529 void
1530 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1531 VkDescriptorType type,
1532 struct anv_buffer_view *buffer_view,
1533 uint32_t binding,
1534 uint32_t element);
1535
1536 void
1537 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1538 struct anv_device *device,
1539 struct anv_state_stream *alloc_stream,
1540 VkDescriptorType type,
1541 struct anv_buffer *buffer,
1542 uint32_t binding,
1543 uint32_t element,
1544 VkDeviceSize offset,
1545 VkDeviceSize range);
1546
1547 void
1548 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1549 struct anv_device *device,
1550 struct anv_state_stream *alloc_stream,
1551 const struct anv_descriptor_update_template *template,
1552 const void *data);
1553
1554 VkResult
1555 anv_descriptor_set_create(struct anv_device *device,
1556 struct anv_descriptor_pool *pool,
1557 struct anv_descriptor_set_layout *layout,
1558 struct anv_descriptor_set **out_set);
1559
1560 void
1561 anv_descriptor_set_destroy(struct anv_device *device,
1562 struct anv_descriptor_pool *pool,
1563 struct anv_descriptor_set *set);
1564
1565 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1566
1567 struct anv_pipeline_binding {
1568 /* The descriptor set this surface corresponds to. The special value of
1569 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1570 * to a color attachment and not a regular descriptor.
1571 */
1572 uint8_t set;
1573
1574 /* Binding in the descriptor set */
1575 uint32_t binding;
1576
1577 /* Index in the binding */
1578 uint32_t index;
1579
1580 /* Plane in the binding index */
1581 uint8_t plane;
1582
1583 /* Input attachment index (relative to the subpass) */
1584 uint8_t input_attachment_index;
1585
1586 /* For a storage image, whether it is write-only */
1587 bool write_only;
1588 };
1589
1590 struct anv_pipeline_layout {
1591 struct {
1592 struct anv_descriptor_set_layout *layout;
1593 uint32_t dynamic_offset_start;
1594 } set[MAX_SETS];
1595
1596 uint32_t num_sets;
1597
1598 struct {
1599 bool has_dynamic_offsets;
1600 } stage[MESA_SHADER_STAGES];
1601
1602 unsigned char sha1[20];
1603 };
1604
1605 struct anv_buffer {
1606 struct anv_device * device;
1607 VkDeviceSize size;
1608
1609 VkBufferUsageFlags usage;
1610
1611 /* Set when bound */
1612 struct anv_address address;
1613 };
1614
1615 static inline uint64_t
1616 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1617 {
1618 assert(offset <= buffer->size);
1619 if (range == VK_WHOLE_SIZE) {
1620 return buffer->size - offset;
1621 } else {
1622 assert(range <= buffer->size);
1623 return range;
1624 }
1625 }
1626
1627 enum anv_cmd_dirty_bits {
1628 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1629 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1630 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1631 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1632 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1633 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1634 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1635 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1636 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1637 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1638 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1639 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1640 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1641 };
1642 typedef uint32_t anv_cmd_dirty_mask_t;
1643
1644 enum anv_pipe_bits {
1645 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1646 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1647 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1648 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1649 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1650 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1651 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1652 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1653 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1654 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1655 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1656
1657 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1658 * a flush has happened but not a CS stall. The next time we do any sort
1659 * of invalidation we need to insert a CS stall at that time. Otherwise,
1660 * we would have to CS stall on every flush which could be bad.
1661 */
1662 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1663 };
1664
1665 #define ANV_PIPE_FLUSH_BITS ( \
1666 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1667 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1668 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1669
1670 #define ANV_PIPE_STALL_BITS ( \
1671 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1672 ANV_PIPE_DEPTH_STALL_BIT | \
1673 ANV_PIPE_CS_STALL_BIT)
1674
1675 #define ANV_PIPE_INVALIDATE_BITS ( \
1676 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1677 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1678 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1679 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1680 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1681 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1682
1683 static inline enum anv_pipe_bits
1684 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1685 {
1686 enum anv_pipe_bits pipe_bits = 0;
1687
1688 unsigned b;
1689 for_each_bit(b, flags) {
1690 switch ((VkAccessFlagBits)(1 << b)) {
1691 case VK_ACCESS_SHADER_WRITE_BIT:
1692 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1693 break;
1694 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1695 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1696 break;
1697 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1698 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1699 break;
1700 case VK_ACCESS_TRANSFER_WRITE_BIT:
1701 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1702 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1703 break;
1704 default:
1705 break; /* Nothing to do */
1706 }
1707 }
1708
1709 return pipe_bits;
1710 }
1711
1712 static inline enum anv_pipe_bits
1713 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1714 {
1715 enum anv_pipe_bits pipe_bits = 0;
1716
1717 unsigned b;
1718 for_each_bit(b, flags) {
1719 switch ((VkAccessFlagBits)(1 << b)) {
1720 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1721 case VK_ACCESS_INDEX_READ_BIT:
1722 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1723 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1724 break;
1725 case VK_ACCESS_UNIFORM_READ_BIT:
1726 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1727 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1728 break;
1729 case VK_ACCESS_SHADER_READ_BIT:
1730 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1731 case VK_ACCESS_TRANSFER_READ_BIT:
1732 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1733 break;
1734 default:
1735 break; /* Nothing to do */
1736 }
1737 }
1738
1739 return pipe_bits;
1740 }
1741
1742 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1743 VK_IMAGE_ASPECT_COLOR_BIT | \
1744 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1745 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1746 VK_IMAGE_ASPECT_PLANE_2_BIT)
1747 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1748 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1749 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1750 VK_IMAGE_ASPECT_PLANE_2_BIT)
1751
1752 struct anv_vertex_binding {
1753 struct anv_buffer * buffer;
1754 VkDeviceSize offset;
1755 };
1756
1757 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1758 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1759
1760 struct anv_push_constants {
1761 /* Current allocated size of this push constants data structure.
1762 * Because a decent chunk of it may not be used (images on SKL, for
1763 * instance), we won't actually allocate the entire structure up-front.
1764 */
1765 uint32_t size;
1766
1767 /* Push constant data provided by the client through vkPushConstants */
1768 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1769
1770 /* Used for vkCmdDispatchBase */
1771 uint32_t base_work_group_id[3];
1772
1773 /* Image data for image_load_store on pre-SKL */
1774 struct brw_image_param images[MAX_IMAGES];
1775 };
1776
1777 struct anv_dynamic_state {
1778 struct {
1779 uint32_t count;
1780 VkViewport viewports[MAX_VIEWPORTS];
1781 } viewport;
1782
1783 struct {
1784 uint32_t count;
1785 VkRect2D scissors[MAX_SCISSORS];
1786 } scissor;
1787
1788 float line_width;
1789
1790 struct {
1791 float bias;
1792 float clamp;
1793 float slope;
1794 } depth_bias;
1795
1796 float blend_constants[4];
1797
1798 struct {
1799 float min;
1800 float max;
1801 } depth_bounds;
1802
1803 struct {
1804 uint32_t front;
1805 uint32_t back;
1806 } stencil_compare_mask;
1807
1808 struct {
1809 uint32_t front;
1810 uint32_t back;
1811 } stencil_write_mask;
1812
1813 struct {
1814 uint32_t front;
1815 uint32_t back;
1816 } stencil_reference;
1817 };
1818
1819 extern const struct anv_dynamic_state default_dynamic_state;
1820
1821 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1822 const struct anv_dynamic_state *src,
1823 uint32_t copy_mask);
1824
1825 struct anv_surface_state {
1826 struct anv_state state;
1827 /** Address of the surface referred to by this state
1828 *
1829 * This address is relative to the start of the BO.
1830 */
1831 struct anv_address address;
1832 /* Address of the aux surface, if any
1833 *
1834 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
1835 *
1836 * With the exception of gen8, the bottom 12 bits of this address' offset
1837 * include extra aux information.
1838 */
1839 struct anv_address aux_address;
1840 /* Address of the clear color, if any
1841 *
1842 * This address is relative to the start of the BO.
1843 */
1844 struct anv_address clear_address;
1845 };
1846
1847 /**
1848 * Attachment state when recording a renderpass instance.
1849 *
1850 * The clear value is valid only if there exists a pending clear.
1851 */
1852 struct anv_attachment_state {
1853 enum isl_aux_usage aux_usage;
1854 enum isl_aux_usage input_aux_usage;
1855 struct anv_surface_state color;
1856 struct anv_surface_state input;
1857
1858 VkImageLayout current_layout;
1859 VkImageAspectFlags pending_clear_aspects;
1860 VkImageAspectFlags pending_load_aspects;
1861 bool fast_clear;
1862 VkClearValue clear_value;
1863 bool clear_color_is_zero_one;
1864 bool clear_color_is_zero;
1865
1866 /* When multiview is active, attachments with a renderpass clear
1867 * operation have their respective layers cleared on the first
1868 * subpass that uses them, and only in that subpass. We keep track
1869 * of this using a bitfield to indicate which layers of an attachment
1870 * have not been cleared yet when multiview is active.
1871 */
1872 uint32_t pending_clear_views;
1873 };
1874
1875 /** State tracking for particular pipeline bind point
1876 *
1877 * This struct is the base struct for anv_cmd_graphics_state and
1878 * anv_cmd_compute_state. These are used to track state which is bound to a
1879 * particular type of pipeline. Generic state that applies per-stage such as
1880 * binding table offsets and push constants is tracked generically with a
1881 * per-stage array in anv_cmd_state.
1882 */
1883 struct anv_cmd_pipeline_state {
1884 struct anv_pipeline *pipeline;
1885 struct anv_pipeline_layout *layout;
1886
1887 struct anv_descriptor_set *descriptors[MAX_SETS];
1888 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1889
1890 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
1891 };
1892
1893 /** State tracking for graphics pipeline
1894 *
1895 * This has anv_cmd_pipeline_state as a base struct to track things which get
1896 * bound to a graphics pipeline. Along with general pipeline bind point state
1897 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1898 * state which is graphics-specific.
1899 */
1900 struct anv_cmd_graphics_state {
1901 struct anv_cmd_pipeline_state base;
1902
1903 anv_cmd_dirty_mask_t dirty;
1904 uint32_t vb_dirty;
1905
1906 struct anv_dynamic_state dynamic;
1907
1908 struct {
1909 struct anv_buffer *index_buffer;
1910 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1911 uint32_t index_offset;
1912 } gen7;
1913 };
1914
1915 /** State tracking for compute pipeline
1916 *
1917 * This has anv_cmd_pipeline_state as a base struct to track things which get
1918 * bound to a compute pipeline. Along with general pipeline bind point state
1919 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1920 * state which is compute-specific.
1921 */
1922 struct anv_cmd_compute_state {
1923 struct anv_cmd_pipeline_state base;
1924
1925 bool pipeline_dirty;
1926
1927 struct anv_address num_workgroups;
1928 };
1929
1930 /** State required while building cmd buffer */
1931 struct anv_cmd_state {
1932 /* PIPELINE_SELECT.PipelineSelection */
1933 uint32_t current_pipeline;
1934 const struct gen_l3_config * current_l3_config;
1935
1936 struct anv_cmd_graphics_state gfx;
1937 struct anv_cmd_compute_state compute;
1938
1939 enum anv_pipe_bits pending_pipe_bits;
1940 VkShaderStageFlags descriptors_dirty;
1941 VkShaderStageFlags push_constants_dirty;
1942
1943 struct anv_framebuffer * framebuffer;
1944 struct anv_render_pass * pass;
1945 struct anv_subpass * subpass;
1946 VkRect2D render_area;
1947 uint32_t restart_index;
1948 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1949 VkShaderStageFlags push_constant_stages;
1950 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1951 struct anv_state binding_tables[MESA_SHADER_STAGES];
1952 struct anv_state samplers[MESA_SHADER_STAGES];
1953
1954 /**
1955 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1956 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1957 * and before invoking the secondary in ExecuteCommands.
1958 */
1959 bool pma_fix_enabled;
1960
1961 /**
1962 * Whether or not we know for certain that HiZ is enabled for the current
1963 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1964 * enabled or not, this will be false.
1965 */
1966 bool hiz_enabled;
1967
1968 /**
1969 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1970 * valid only when recording a render pass instance.
1971 */
1972 struct anv_attachment_state * attachments;
1973
1974 /**
1975 * Surface states for color render targets. These are stored in a single
1976 * flat array. For depth-stencil attachments, the surface state is simply
1977 * left blank.
1978 */
1979 struct anv_state render_pass_states;
1980
1981 /**
1982 * A null surface state of the right size to match the framebuffer. This
1983 * is one of the states in render_pass_states.
1984 */
1985 struct anv_state null_surface_state;
1986 };
1987
1988 struct anv_cmd_pool {
1989 VkAllocationCallbacks alloc;
1990 struct list_head cmd_buffers;
1991 };
1992
1993 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1994
1995 enum anv_cmd_buffer_exec_mode {
1996 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1997 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1998 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1999 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
2000 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
2001 };
2002
2003 struct anv_cmd_buffer {
2004 VK_LOADER_DATA _loader_data;
2005
2006 struct anv_device * device;
2007
2008 struct anv_cmd_pool * pool;
2009 struct list_head pool_link;
2010
2011 struct anv_batch batch;
2012
2013 /* Fields required for the actual chain of anv_batch_bo's.
2014 *
2015 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2016 */
2017 struct list_head batch_bos;
2018 enum anv_cmd_buffer_exec_mode exec_mode;
2019
2020 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2021 * referenced by this command buffer
2022 *
2023 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2024 */
2025 struct u_vector seen_bbos;
2026
2027 /* A vector of int32_t's for every block of binding tables.
2028 *
2029 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2030 */
2031 struct u_vector bt_block_states;
2032 uint32_t bt_next;
2033
2034 struct anv_reloc_list surface_relocs;
2035 /** Last seen surface state block pool center bo offset */
2036 uint32_t last_ss_pool_center;
2037
2038 /* Serial for tracking buffer completion */
2039 uint32_t serial;
2040
2041 /* Stream objects for storing temporary data */
2042 struct anv_state_stream surface_state_stream;
2043 struct anv_state_stream dynamic_state_stream;
2044
2045 VkCommandBufferUsageFlags usage_flags;
2046 VkCommandBufferLevel level;
2047
2048 struct anv_cmd_state state;
2049 };
2050
2051 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2052 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2053 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2054 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
2055 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
2056 struct anv_cmd_buffer *secondary);
2057 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
2058 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
2059 struct anv_cmd_buffer *cmd_buffer,
2060 const VkSemaphore *in_semaphores,
2061 uint32_t num_in_semaphores,
2062 const VkSemaphore *out_semaphores,
2063 uint32_t num_out_semaphores,
2064 VkFence fence);
2065
2066 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
2067
2068 VkResult
2069 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
2070 gl_shader_stage stage, uint32_t size);
2071 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
2072 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
2073 (offsetof(struct anv_push_constants, field) + \
2074 sizeof(cmd_buffer->state.push_constants[0]->field)))
2075
2076 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
2077 const void *data, uint32_t size, uint32_t alignment);
2078 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
2079 uint32_t *a, uint32_t *b,
2080 uint32_t dwords, uint32_t alignment);
2081
2082 struct anv_address
2083 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
2084 struct anv_state
2085 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
2086 uint32_t entries, uint32_t *state_offset);
2087 struct anv_state
2088 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
2089 struct anv_state
2090 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
2091 uint32_t size, uint32_t alignment);
2092
2093 VkResult
2094 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
2095
2096 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
2097 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
2098 bool depth_clamp_enable);
2099 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
2100
2101 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
2102 struct anv_render_pass *pass,
2103 struct anv_framebuffer *framebuffer,
2104 const VkClearValue *clear_values);
2105
2106 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
2107
2108 struct anv_state
2109 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
2110 gl_shader_stage stage);
2111 struct anv_state
2112 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
2113
2114 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
2115
2116 const struct anv_image_view *
2117 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
2118
2119 VkResult
2120 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
2121 uint32_t num_entries,
2122 uint32_t *state_offset,
2123 struct anv_state *bt_state);
2124
2125 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
2126
2127 enum anv_fence_type {
2128 ANV_FENCE_TYPE_NONE = 0,
2129 ANV_FENCE_TYPE_BO,
2130 ANV_FENCE_TYPE_SYNCOBJ,
2131 };
2132
2133 enum anv_bo_fence_state {
2134 /** Indicates that this is a new (or newly reset fence) */
2135 ANV_BO_FENCE_STATE_RESET,
2136
2137 /** Indicates that this fence has been submitted to the GPU but is still
2138 * (as far as we know) in use by the GPU.
2139 */
2140 ANV_BO_FENCE_STATE_SUBMITTED,
2141
2142 ANV_BO_FENCE_STATE_SIGNALED,
2143 };
2144
2145 struct anv_fence_impl {
2146 enum anv_fence_type type;
2147
2148 union {
2149 /** Fence implementation for BO fences
2150 *
2151 * These fences use a BO and a set of CPU-tracked state flags. The BO
2152 * is added to the object list of the last execbuf call in a QueueSubmit
2153 * and is marked EXEC_WRITE. The state flags track when the BO has been
2154 * submitted to the kernel. We need to do this because Vulkan lets you
2155 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2156 * will say it's idle in this case.
2157 */
2158 struct {
2159 struct anv_bo bo;
2160 enum anv_bo_fence_state state;
2161 } bo;
2162
2163 /** DRM syncobj handle for syncobj-based fences */
2164 uint32_t syncobj;
2165 };
2166 };
2167
2168 struct anv_fence {
2169 /* Permanent fence state. Every fence has some form of permanent state
2170 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2171 * cross-process fences) or it could just be a dummy for use internally.
2172 */
2173 struct anv_fence_impl permanent;
2174
2175 /* Temporary fence state. A fence *may* have temporary state. That state
2176 * is added to the fence by an import operation and is reset back to
2177 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2178 * state cannot be signaled because the fence must already be signaled
2179 * before the temporary state can be exported from the fence in the other
2180 * process and imported here.
2181 */
2182 struct anv_fence_impl temporary;
2183 };
2184
2185 struct anv_event {
2186 uint64_t semaphore;
2187 struct anv_state state;
2188 };
2189
2190 enum anv_semaphore_type {
2191 ANV_SEMAPHORE_TYPE_NONE = 0,
2192 ANV_SEMAPHORE_TYPE_DUMMY,
2193 ANV_SEMAPHORE_TYPE_BO,
2194 ANV_SEMAPHORE_TYPE_SYNC_FILE,
2195 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
2196 };
2197
2198 struct anv_semaphore_impl {
2199 enum anv_semaphore_type type;
2200
2201 union {
2202 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2203 * This BO will be added to the object list on any execbuf2 calls for
2204 * which this semaphore is used as a wait or signal fence. When used as
2205 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2206 */
2207 struct anv_bo *bo;
2208
2209 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2210 * If the semaphore is in the unsignaled state due to either just being
2211 * created or because it has been used for a wait, fd will be -1.
2212 */
2213 int fd;
2214
2215 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2216 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2217 * import so we don't need to bother with a userspace cache.
2218 */
2219 uint32_t syncobj;
2220 };
2221 };
2222
2223 struct anv_semaphore {
2224 /* Permanent semaphore state. Every semaphore has some form of permanent
2225 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2226 * (for cross-process semaphores0 or it could just be a dummy for use
2227 * internally.
2228 */
2229 struct anv_semaphore_impl permanent;
2230
2231 /* Temporary semaphore state. A semaphore *may* have temporary state.
2232 * That state is added to the semaphore by an import operation and is reset
2233 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2234 * semaphore with temporary state cannot be signaled because the semaphore
2235 * must already be signaled before the temporary state can be exported from
2236 * the semaphore in the other process and imported here.
2237 */
2238 struct anv_semaphore_impl temporary;
2239 };
2240
2241 void anv_semaphore_reset_temporary(struct anv_device *device,
2242 struct anv_semaphore *semaphore);
2243
2244 struct anv_shader_module {
2245 unsigned char sha1[20];
2246 uint32_t size;
2247 char data[0];
2248 };
2249
2250 static inline gl_shader_stage
2251 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2252 {
2253 assert(__builtin_popcount(vk_stage) == 1);
2254 return ffs(vk_stage) - 1;
2255 }
2256
2257 static inline VkShaderStageFlagBits
2258 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2259 {
2260 return (1 << mesa_stage);
2261 }
2262
2263 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2264
2265 #define anv_foreach_stage(stage, stage_bits) \
2266 for (gl_shader_stage stage, \
2267 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2268 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2269 __tmp &= ~(1 << (stage)))
2270
2271 struct anv_pipeline_bind_map {
2272 uint32_t surface_count;
2273 uint32_t sampler_count;
2274 uint32_t image_count;
2275
2276 struct anv_pipeline_binding * surface_to_descriptor;
2277 struct anv_pipeline_binding * sampler_to_descriptor;
2278 };
2279
2280 struct anv_shader_bin_key {
2281 uint32_t size;
2282 uint8_t data[0];
2283 };
2284
2285 struct anv_shader_bin {
2286 uint32_t ref_cnt;
2287
2288 const struct anv_shader_bin_key *key;
2289
2290 struct anv_state kernel;
2291 uint32_t kernel_size;
2292
2293 const struct brw_stage_prog_data *prog_data;
2294 uint32_t prog_data_size;
2295
2296 struct anv_pipeline_bind_map bind_map;
2297 };
2298
2299 struct anv_shader_bin *
2300 anv_shader_bin_create(struct anv_device *device,
2301 const void *key, uint32_t key_size,
2302 const void *kernel, uint32_t kernel_size,
2303 const struct brw_stage_prog_data *prog_data,
2304 uint32_t prog_data_size, const void *prog_data_param,
2305 const struct anv_pipeline_bind_map *bind_map);
2306
2307 void
2308 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2309
2310 static inline void
2311 anv_shader_bin_ref(struct anv_shader_bin *shader)
2312 {
2313 assert(shader && shader->ref_cnt >= 1);
2314 p_atomic_inc(&shader->ref_cnt);
2315 }
2316
2317 static inline void
2318 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2319 {
2320 assert(shader && shader->ref_cnt >= 1);
2321 if (p_atomic_dec_zero(&shader->ref_cnt))
2322 anv_shader_bin_destroy(device, shader);
2323 }
2324
2325 struct anv_pipeline {
2326 struct anv_device * device;
2327 struct anv_batch batch;
2328 uint32_t batch_data[512];
2329 struct anv_reloc_list batch_relocs;
2330 uint32_t dynamic_state_mask;
2331 struct anv_dynamic_state dynamic_state;
2332
2333 struct anv_subpass * subpass;
2334
2335 bool needs_data_cache;
2336
2337 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2338
2339 struct {
2340 const struct gen_l3_config * l3_config;
2341 uint32_t total_size;
2342 } urb;
2343
2344 VkShaderStageFlags active_stages;
2345 struct anv_state blend_state;
2346
2347 uint32_t vb_used;
2348 uint32_t binding_stride[MAX_VBS];
2349 bool instancing_enable[MAX_VBS];
2350 bool primitive_restart;
2351 uint32_t topology;
2352
2353 uint32_t cs_right_mask;
2354
2355 bool writes_depth;
2356 bool depth_test_enable;
2357 bool writes_stencil;
2358 bool stencil_test_enable;
2359 bool depth_clamp_enable;
2360 bool sample_shading_enable;
2361 bool kill_pixel;
2362
2363 struct {
2364 uint32_t sf[7];
2365 uint32_t depth_stencil_state[3];
2366 } gen7;
2367
2368 struct {
2369 uint32_t sf[4];
2370 uint32_t raster[5];
2371 uint32_t wm_depth_stencil[3];
2372 } gen8;
2373
2374 struct {
2375 uint32_t wm_depth_stencil[4];
2376 } gen9;
2377
2378 uint32_t interface_descriptor_data[8];
2379 };
2380
2381 static inline bool
2382 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2383 gl_shader_stage stage)
2384 {
2385 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2386 }
2387
2388 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2389 static inline const struct brw_##prefix##_prog_data * \
2390 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2391 { \
2392 if (anv_pipeline_has_stage(pipeline, stage)) { \
2393 return (const struct brw_##prefix##_prog_data *) \
2394 pipeline->shaders[stage]->prog_data; \
2395 } else { \
2396 return NULL; \
2397 } \
2398 }
2399
2400 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2401 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2402 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2403 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2404 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2405 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2406
2407 static inline const struct brw_vue_prog_data *
2408 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2409 {
2410 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2411 return &get_gs_prog_data(pipeline)->base;
2412 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2413 return &get_tes_prog_data(pipeline)->base;
2414 else
2415 return &get_vs_prog_data(pipeline)->base;
2416 }
2417
2418 VkResult
2419 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2420 struct anv_pipeline_cache *cache,
2421 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2422 const VkAllocationCallbacks *alloc);
2423
2424 VkResult
2425 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2426 struct anv_pipeline_cache *cache,
2427 const VkComputePipelineCreateInfo *info,
2428 struct anv_shader_module *module,
2429 const char *entrypoint,
2430 const VkSpecializationInfo *spec_info);
2431
2432 struct anv_format_plane {
2433 enum isl_format isl_format:16;
2434 struct isl_swizzle swizzle;
2435
2436 /* Whether this plane contains chroma channels */
2437 bool has_chroma;
2438
2439 /* For downscaling of YUV planes */
2440 uint8_t denominator_scales[2];
2441
2442 /* How to map sampled ycbcr planes to a single 4 component element. */
2443 struct isl_swizzle ycbcr_swizzle;
2444 };
2445
2446
2447 struct anv_format {
2448 struct anv_format_plane planes[3];
2449 uint8_t n_planes;
2450 bool can_ycbcr;
2451 };
2452
2453 static inline uint32_t
2454 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2455 VkImageAspectFlags aspect_mask)
2456 {
2457 switch (aspect_mask) {
2458 case VK_IMAGE_ASPECT_COLOR_BIT:
2459 case VK_IMAGE_ASPECT_DEPTH_BIT:
2460 case VK_IMAGE_ASPECT_PLANE_0_BIT:
2461 return 0;
2462 case VK_IMAGE_ASPECT_STENCIL_BIT:
2463 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2464 return 0;
2465 /* Fall-through */
2466 case VK_IMAGE_ASPECT_PLANE_1_BIT:
2467 return 1;
2468 case VK_IMAGE_ASPECT_PLANE_2_BIT:
2469 return 2;
2470 default:
2471 /* Purposefully assert with depth/stencil aspects. */
2472 unreachable("invalid image aspect");
2473 }
2474 }
2475
2476 static inline uint32_t
2477 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2478 {
2479 uint32_t planes = 0;
2480
2481 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2482 VK_IMAGE_ASPECT_DEPTH_BIT |
2483 VK_IMAGE_ASPECT_STENCIL_BIT |
2484 VK_IMAGE_ASPECT_PLANE_0_BIT))
2485 planes++;
2486 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT)
2487 planes++;
2488 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT)
2489 planes++;
2490
2491 if ((aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) != 0 &&
2492 (aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) != 0)
2493 planes++;
2494
2495 return planes;
2496 }
2497
2498 static inline VkImageAspectFlags
2499 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2500 uint32_t plane)
2501 {
2502 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2503 if (_mesa_bitcount(image_aspects) > 1)
2504 return VK_IMAGE_ASPECT_PLANE_0_BIT << plane;
2505 return VK_IMAGE_ASPECT_COLOR_BIT;
2506 }
2507 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2508 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2509 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2510 return VK_IMAGE_ASPECT_STENCIL_BIT;
2511 }
2512
2513 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2514 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2515
2516 const struct anv_format *
2517 anv_get_format(VkFormat format);
2518
2519 static inline uint32_t
2520 anv_get_format_planes(VkFormat vk_format)
2521 {
2522 const struct anv_format *format = anv_get_format(vk_format);
2523
2524 return format != NULL ? format->n_planes : 0;
2525 }
2526
2527 struct anv_format_plane
2528 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2529 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2530
2531 static inline enum isl_format
2532 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2533 VkImageAspectFlags aspect, VkImageTiling tiling)
2534 {
2535 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2536 }
2537
2538 static inline struct isl_swizzle
2539 anv_swizzle_for_render(struct isl_swizzle swizzle)
2540 {
2541 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2542 * RGB as RGBA for texturing
2543 */
2544 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2545 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2546
2547 /* But it doesn't matter what we render to that channel */
2548 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2549
2550 return swizzle;
2551 }
2552
2553 void
2554 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2555
2556 /**
2557 * Subsurface of an anv_image.
2558 */
2559 struct anv_surface {
2560 /** Valid only if isl_surf::size > 0. */
2561 struct isl_surf isl;
2562
2563 /**
2564 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2565 */
2566 uint32_t offset;
2567 };
2568
2569 struct anv_image {
2570 VkImageType type;
2571 /* The original VkFormat provided by the client. This may not match any
2572 * of the actual surface formats.
2573 */
2574 VkFormat vk_format;
2575 const struct anv_format *format;
2576
2577 VkImageAspectFlags aspects;
2578 VkExtent3D extent;
2579 uint32_t levels;
2580 uint32_t array_size;
2581 uint32_t samples; /**< VkImageCreateInfo::samples */
2582 uint32_t n_planes;
2583 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2584 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2585
2586 /** True if this is needs to be bound to an appropriately tiled BO.
2587 *
2588 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2589 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2590 * we require a dedicated allocation so that we can know to allocate a
2591 * tiled buffer.
2592 */
2593 bool needs_set_tiling;
2594
2595 /**
2596 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2597 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2598 */
2599 uint64_t drm_format_mod;
2600
2601 VkDeviceSize size;
2602 uint32_t alignment;
2603
2604 /* Whether the image is made of several underlying buffer objects rather a
2605 * single one with different offsets.
2606 */
2607 bool disjoint;
2608
2609 /**
2610 * Image subsurfaces
2611 *
2612 * For each foo, anv_image::planes[x].surface is valid if and only if
2613 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2614 * to figure the number associated with a given aspect.
2615 *
2616 * The hardware requires that the depth buffer and stencil buffer be
2617 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2618 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2619 * allocate the depth and stencil buffers as separate surfaces in the same
2620 * bo.
2621 *
2622 * Memory layout :
2623 *
2624 * -----------------------
2625 * | surface0 | /|\
2626 * ----------------------- |
2627 * | shadow surface0 | |
2628 * ----------------------- | Plane 0
2629 * | aux surface0 | |
2630 * ----------------------- |
2631 * | fast clear colors0 | \|/
2632 * -----------------------
2633 * | surface1 | /|\
2634 * ----------------------- |
2635 * | shadow surface1 | |
2636 * ----------------------- | Plane 1
2637 * | aux surface1 | |
2638 * ----------------------- |
2639 * | fast clear colors1 | \|/
2640 * -----------------------
2641 * | ... |
2642 * | |
2643 * -----------------------
2644 */
2645 struct {
2646 /**
2647 * Offset of the entire plane (whenever the image is disjoint this is
2648 * set to 0).
2649 */
2650 uint32_t offset;
2651
2652 VkDeviceSize size;
2653 uint32_t alignment;
2654
2655 struct anv_surface surface;
2656
2657 /**
2658 * A surface which shadows the main surface and may have different
2659 * tiling. This is used for sampling using a tiling that isn't supported
2660 * for other operations.
2661 */
2662 struct anv_surface shadow_surface;
2663
2664 /**
2665 * For color images, this is the aux usage for this image when not used
2666 * as a color attachment.
2667 *
2668 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2669 * image has a HiZ buffer.
2670 */
2671 enum isl_aux_usage aux_usage;
2672
2673 struct anv_surface aux_surface;
2674
2675 /**
2676 * Offset of the fast clear state (used to compute the
2677 * fast_clear_state_offset of the following planes).
2678 */
2679 uint32_t fast_clear_state_offset;
2680
2681 /**
2682 * BO associated with this plane, set when bound.
2683 */
2684 struct anv_address address;
2685
2686 /**
2687 * When destroying the image, also free the bo.
2688 * */
2689 bool bo_is_owned;
2690 } planes[3];
2691 };
2692
2693 /* The ordering of this enum is important */
2694 enum anv_fast_clear_type {
2695 /** Image does not have/support any fast-clear blocks */
2696 ANV_FAST_CLEAR_NONE = 0,
2697 /** Image has/supports fast-clear but only to the default value */
2698 ANV_FAST_CLEAR_DEFAULT_VALUE = 1,
2699 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2700 ANV_FAST_CLEAR_ANY = 2,
2701 };
2702
2703 /* Returns the number of auxiliary buffer levels attached to an image. */
2704 static inline uint8_t
2705 anv_image_aux_levels(const struct anv_image * const image,
2706 VkImageAspectFlagBits aspect)
2707 {
2708 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2709 return image->planes[plane].aux_surface.isl.size > 0 ?
2710 image->planes[plane].aux_surface.isl.levels : 0;
2711 }
2712
2713 /* Returns the number of auxiliary buffer layers attached to an image. */
2714 static inline uint32_t
2715 anv_image_aux_layers(const struct anv_image * const image,
2716 VkImageAspectFlagBits aspect,
2717 const uint8_t miplevel)
2718 {
2719 assert(image);
2720
2721 /* The miplevel must exist in the main buffer. */
2722 assert(miplevel < image->levels);
2723
2724 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2725 /* There are no layers with auxiliary data because the miplevel has no
2726 * auxiliary data.
2727 */
2728 return 0;
2729 } else {
2730 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2731 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2732 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2733 }
2734 }
2735
2736 static inline struct anv_address
2737 anv_image_get_clear_color_addr(const struct anv_device *device,
2738 const struct anv_image *image,
2739 VkImageAspectFlagBits aspect)
2740 {
2741 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
2742
2743 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2744 return anv_address_add(image->planes[plane].address,
2745 image->planes[plane].fast_clear_state_offset);
2746 }
2747
2748 static inline struct anv_address
2749 anv_image_get_fast_clear_type_addr(const struct anv_device *device,
2750 const struct anv_image *image,
2751 VkImageAspectFlagBits aspect)
2752 {
2753 struct anv_address addr =
2754 anv_image_get_clear_color_addr(device, image, aspect);
2755
2756 const unsigned clear_color_state_size = device->info.gen >= 10 ?
2757 device->isl_dev.ss.clear_color_state_size :
2758 device->isl_dev.ss.clear_value_size;
2759 addr.offset += clear_color_state_size;
2760 return addr;
2761 }
2762
2763 static inline struct anv_address
2764 anv_image_get_compression_state_addr(const struct anv_device *device,
2765 const struct anv_image *image,
2766 VkImageAspectFlagBits aspect,
2767 uint32_t level, uint32_t array_layer)
2768 {
2769 assert(level < anv_image_aux_levels(image, aspect));
2770 assert(array_layer < anv_image_aux_layers(image, aspect, level));
2771 UNUSED uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2772 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E);
2773
2774 struct anv_address addr =
2775 anv_image_get_fast_clear_type_addr(device, image, aspect);
2776 addr.offset += 4; /* Go past the fast clear type */
2777
2778 if (image->type == VK_IMAGE_TYPE_3D) {
2779 for (uint32_t l = 0; l < level; l++)
2780 addr.offset += anv_minify(image->extent.depth, l) * 4;
2781 } else {
2782 addr.offset += level * image->array_size * 4;
2783 }
2784 addr.offset += array_layer * 4;
2785
2786 return addr;
2787 }
2788
2789 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2790 static inline bool
2791 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2792 const struct anv_image *image)
2793 {
2794 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2795 return false;
2796
2797 if (devinfo->gen < 8)
2798 return false;
2799
2800 return image->samples == 1;
2801 }
2802
2803 void
2804 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
2805 const struct anv_image *image,
2806 VkImageAspectFlagBits aspect,
2807 enum isl_aux_usage aux_usage,
2808 uint32_t level,
2809 uint32_t base_layer,
2810 uint32_t layer_count);
2811
2812 void
2813 anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
2814 const struct anv_image *image,
2815 VkImageAspectFlagBits aspect,
2816 enum isl_aux_usage aux_usage,
2817 enum isl_format format, struct isl_swizzle swizzle,
2818 uint32_t level, uint32_t base_layer, uint32_t layer_count,
2819 VkRect2D area, union isl_color_value clear_color);
2820 void
2821 anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
2822 const struct anv_image *image,
2823 VkImageAspectFlags aspects,
2824 enum isl_aux_usage depth_aux_usage,
2825 uint32_t level,
2826 uint32_t base_layer, uint32_t layer_count,
2827 VkRect2D area,
2828 float depth_value, uint8_t stencil_value);
2829 void
2830 anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
2831 const struct anv_image *image,
2832 VkImageAspectFlagBits aspect, uint32_t level,
2833 uint32_t base_layer, uint32_t layer_count,
2834 enum isl_aux_op hiz_op);
2835 void
2836 anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
2837 const struct anv_image *image,
2838 VkImageAspectFlags aspects,
2839 uint32_t level,
2840 uint32_t base_layer, uint32_t layer_count,
2841 VkRect2D area, uint8_t stencil_value);
2842 void
2843 anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
2844 const struct anv_image *image,
2845 VkImageAspectFlagBits aspect,
2846 uint32_t base_layer, uint32_t layer_count,
2847 enum isl_aux_op mcs_op, union isl_color_value *clear_value,
2848 bool predicate);
2849 void
2850 anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
2851 const struct anv_image *image,
2852 VkImageAspectFlagBits aspect, uint32_t level,
2853 uint32_t base_layer, uint32_t layer_count,
2854 enum isl_aux_op ccs_op, union isl_color_value *clear_value,
2855 bool predicate);
2856
2857 void
2858 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2859 const struct anv_image *image,
2860 uint32_t base_level, uint32_t level_count,
2861 uint32_t base_layer, uint32_t layer_count);
2862
2863 enum isl_aux_usage
2864 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2865 const struct anv_image *image,
2866 const VkImageAspectFlagBits aspect,
2867 const VkImageLayout layout);
2868
2869 enum anv_fast_clear_type
2870 anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
2871 const struct anv_image * const image,
2872 const VkImageAspectFlagBits aspect,
2873 const VkImageLayout layout);
2874
2875 /* This is defined as a macro so that it works for both
2876 * VkImageSubresourceRange and VkImageSubresourceLayers
2877 */
2878 #define anv_get_layerCount(_image, _range) \
2879 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2880 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2881
2882 static inline uint32_t
2883 anv_get_levelCount(const struct anv_image *image,
2884 const VkImageSubresourceRange *range)
2885 {
2886 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2887 image->levels - range->baseMipLevel : range->levelCount;
2888 }
2889
2890 static inline VkImageAspectFlags
2891 anv_image_expand_aspects(const struct anv_image *image,
2892 VkImageAspectFlags aspects)
2893 {
2894 /* If the underlying image has color plane aspects and
2895 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2896 * the underlying image. */
2897 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
2898 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2899 return image->aspects;
2900
2901 return aspects;
2902 }
2903
2904 static inline bool
2905 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2906 VkImageAspectFlags aspects2)
2907 {
2908 if (aspects1 == aspects2)
2909 return true;
2910
2911 /* Only 1 color aspects are compatibles. */
2912 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2913 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2914 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2915 return true;
2916
2917 return false;
2918 }
2919
2920 struct anv_image_view {
2921 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2922
2923 VkImageAspectFlags aspect_mask;
2924 VkFormat vk_format;
2925 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2926
2927 unsigned n_planes;
2928 struct {
2929 uint32_t image_plane;
2930
2931 struct isl_view isl;
2932
2933 /**
2934 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2935 * image layout of SHADER_READ_ONLY_OPTIMAL or
2936 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2937 */
2938 struct anv_surface_state optimal_sampler_surface_state;
2939
2940 /**
2941 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2942 * image layout of GENERAL.
2943 */
2944 struct anv_surface_state general_sampler_surface_state;
2945
2946 /**
2947 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2948 * states for write-only and readable, using the real format for
2949 * write-only and the lowered format for readable.
2950 */
2951 struct anv_surface_state storage_surface_state;
2952 struct anv_surface_state writeonly_storage_surface_state;
2953
2954 struct brw_image_param storage_image_param;
2955 } planes[3];
2956 };
2957
2958 enum anv_image_view_state_flags {
2959 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2960 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2961 };
2962
2963 void anv_image_fill_surface_state(struct anv_device *device,
2964 const struct anv_image *image,
2965 VkImageAspectFlagBits aspect,
2966 const struct isl_view *view,
2967 isl_surf_usage_flags_t view_usage,
2968 enum isl_aux_usage aux_usage,
2969 const union isl_color_value *clear_color,
2970 enum anv_image_view_state_flags flags,
2971 struct anv_surface_state *state_inout,
2972 struct brw_image_param *image_param_out);
2973
2974 struct anv_image_create_info {
2975 const VkImageCreateInfo *vk_info;
2976
2977 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2978 isl_tiling_flags_t isl_tiling_flags;
2979
2980 /** These flags will be added to any derived from VkImageCreateInfo. */
2981 isl_surf_usage_flags_t isl_extra_usage_flags;
2982
2983 uint32_t stride;
2984 };
2985
2986 VkResult anv_image_create(VkDevice _device,
2987 const struct anv_image_create_info *info,
2988 const VkAllocationCallbacks* alloc,
2989 VkImage *pImage);
2990
2991 #ifdef ANDROID
2992 VkResult anv_image_from_gralloc(VkDevice device_h,
2993 const VkImageCreateInfo *base_info,
2994 const VkNativeBufferANDROID *gralloc_info,
2995 const VkAllocationCallbacks *alloc,
2996 VkImage *pImage);
2997 #endif
2998
2999 const struct anv_surface *
3000 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
3001 VkImageAspectFlags aspect_mask);
3002
3003 enum isl_format
3004 anv_isl_format_for_descriptor_type(VkDescriptorType type);
3005
3006 static inline struct VkExtent3D
3007 anv_sanitize_image_extent(const VkImageType imageType,
3008 const struct VkExtent3D imageExtent)
3009 {
3010 switch (imageType) {
3011 case VK_IMAGE_TYPE_1D:
3012 return (VkExtent3D) { imageExtent.width, 1, 1 };
3013 case VK_IMAGE_TYPE_2D:
3014 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
3015 case VK_IMAGE_TYPE_3D:
3016 return imageExtent;
3017 default:
3018 unreachable("invalid image type");
3019 }
3020 }
3021
3022 static inline struct VkOffset3D
3023 anv_sanitize_image_offset(const VkImageType imageType,
3024 const struct VkOffset3D imageOffset)
3025 {
3026 switch (imageType) {
3027 case VK_IMAGE_TYPE_1D:
3028 return (VkOffset3D) { imageOffset.x, 0, 0 };
3029 case VK_IMAGE_TYPE_2D:
3030 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
3031 case VK_IMAGE_TYPE_3D:
3032 return imageOffset;
3033 default:
3034 unreachable("invalid image type");
3035 }
3036 }
3037
3038
3039 void anv_fill_buffer_surface_state(struct anv_device *device,
3040 struct anv_state state,
3041 enum isl_format format,
3042 struct anv_address address,
3043 uint32_t range, uint32_t stride);
3044
3045 static inline void
3046 anv_clear_color_from_att_state(union isl_color_value *clear_color,
3047 const struct anv_attachment_state *att_state,
3048 const struct anv_image_view *iview)
3049 {
3050 const struct isl_format_layout *view_fmtl =
3051 isl_format_get_layout(iview->planes[0].isl.format);
3052
3053 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3054 if (view_fmtl->channels.c.bits) \
3055 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3056
3057 COPY_CLEAR_COLOR_CHANNEL(r, 0);
3058 COPY_CLEAR_COLOR_CHANNEL(g, 1);
3059 COPY_CLEAR_COLOR_CHANNEL(b, 2);
3060 COPY_CLEAR_COLOR_CHANNEL(a, 3);
3061
3062 #undef COPY_CLEAR_COLOR_CHANNEL
3063 }
3064
3065
3066 struct anv_ycbcr_conversion {
3067 const struct anv_format * format;
3068 VkSamplerYcbcrModelConversion ycbcr_model;
3069 VkSamplerYcbcrRange ycbcr_range;
3070 VkComponentSwizzle mapping[4];
3071 VkChromaLocation chroma_offsets[2];
3072 VkFilter chroma_filter;
3073 bool chroma_reconstruction;
3074 };
3075
3076 struct anv_sampler {
3077 uint32_t state[3][4];
3078 uint32_t n_planes;
3079 struct anv_ycbcr_conversion *conversion;
3080 };
3081
3082 struct anv_framebuffer {
3083 uint32_t width;
3084 uint32_t height;
3085 uint32_t layers;
3086
3087 uint32_t attachment_count;
3088 struct anv_image_view * attachments[0];
3089 };
3090
3091 struct anv_subpass_attachment {
3092 VkImageUsageFlagBits usage;
3093 uint32_t attachment;
3094 VkImageLayout layout;
3095 };
3096
3097 struct anv_subpass {
3098 uint32_t attachment_count;
3099
3100 /**
3101 * A pointer to all attachment references used in this subpass.
3102 * Only valid if ::attachment_count > 0.
3103 */
3104 struct anv_subpass_attachment * attachments;
3105 uint32_t input_count;
3106 struct anv_subpass_attachment * input_attachments;
3107 uint32_t color_count;
3108 struct anv_subpass_attachment * color_attachments;
3109 struct anv_subpass_attachment * resolve_attachments;
3110
3111 struct anv_subpass_attachment depth_stencil_attachment;
3112
3113 uint32_t view_mask;
3114
3115 /** Subpass has a depth/stencil self-dependency */
3116 bool has_ds_self_dep;
3117
3118 /** Subpass has at least one resolve attachment */
3119 bool has_resolve;
3120 };
3121
3122 static inline unsigned
3123 anv_subpass_view_count(const struct anv_subpass *subpass)
3124 {
3125 return MAX2(1, _mesa_bitcount(subpass->view_mask));
3126 }
3127
3128 struct anv_render_pass_attachment {
3129 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3130 * its members individually.
3131 */
3132 VkFormat format;
3133 uint32_t samples;
3134 VkImageUsageFlags usage;
3135 VkAttachmentLoadOp load_op;
3136 VkAttachmentStoreOp store_op;
3137 VkAttachmentLoadOp stencil_load_op;
3138 VkImageLayout initial_layout;
3139 VkImageLayout final_layout;
3140 VkImageLayout first_subpass_layout;
3141
3142 /* The subpass id in which the attachment will be used last. */
3143 uint32_t last_subpass_idx;
3144 };
3145
3146 struct anv_render_pass {
3147 uint32_t attachment_count;
3148 uint32_t subpass_count;
3149 /* An array of subpass_count+1 flushes, one per subpass boundary */
3150 enum anv_pipe_bits * subpass_flushes;
3151 struct anv_render_pass_attachment * attachments;
3152 struct anv_subpass subpasses[0];
3153 };
3154
3155 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3156
3157 struct anv_query_pool {
3158 VkQueryType type;
3159 VkQueryPipelineStatisticFlags pipeline_statistics;
3160 /** Stride between slots, in bytes */
3161 uint32_t stride;
3162 /** Number of slots in this query pool */
3163 uint32_t slots;
3164 struct anv_bo bo;
3165 };
3166
3167 int anv_get_entrypoint_index(const char *name);
3168
3169 bool
3170 anv_entrypoint_is_enabled(int index, uint32_t core_version,
3171 const struct anv_instance_extension_table *instance,
3172 const struct anv_device_extension_table *device);
3173
3174 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
3175 const char *name);
3176
3177 void anv_dump_image_to_ppm(struct anv_device *device,
3178 struct anv_image *image, unsigned miplevel,
3179 unsigned array_layer, VkImageAspectFlagBits aspect,
3180 const char *filename);
3181
3182 enum anv_dump_action {
3183 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
3184 };
3185
3186 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
3187 void anv_dump_finish(void);
3188
3189 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
3190 struct anv_framebuffer *fb);
3191
3192 static inline uint32_t
3193 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
3194 {
3195 /* This function must be called from within a subpass. */
3196 assert(cmd_state->pass && cmd_state->subpass);
3197
3198 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
3199
3200 /* The id of this subpass shouldn't exceed the number of subpasses in this
3201 * render pass minus 1.
3202 */
3203 assert(subpass_id < cmd_state->pass->subpass_count);
3204 return subpass_id;
3205 }
3206
3207 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3208 \
3209 static inline struct __anv_type * \
3210 __anv_type ## _from_handle(__VkType _handle) \
3211 { \
3212 return (struct __anv_type *) _handle; \
3213 } \
3214 \
3215 static inline __VkType \
3216 __anv_type ## _to_handle(struct __anv_type *_obj) \
3217 { \
3218 return (__VkType) _obj; \
3219 }
3220
3221 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3222 \
3223 static inline struct __anv_type * \
3224 __anv_type ## _from_handle(__VkType _handle) \
3225 { \
3226 return (struct __anv_type *)(uintptr_t) _handle; \
3227 } \
3228 \
3229 static inline __VkType \
3230 __anv_type ## _to_handle(struct __anv_type *_obj) \
3231 { \
3232 return (__VkType)(uintptr_t) _obj; \
3233 }
3234
3235 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3236 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3237
3238 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
3239 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
3240 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
3241 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
3242 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
3243
3244 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
3245 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
3246 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
3247 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
3248 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
3249 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
3250 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
3251 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
3252 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
3253 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
3254 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
3255 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
3256 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
3257 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
3258 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
3259 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
3260 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
3261 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
3262 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
3263 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
3264 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
3265 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback, VkDebugReportCallbackEXT)
3266 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversion)
3267
3268 /* Gen-specific function declarations */
3269 #ifdef genX
3270 # include "anv_genX.h"
3271 #else
3272 # define genX(x) gen7_##x
3273 # include "anv_genX.h"
3274 # undef genX
3275 # define genX(x) gen75_##x
3276 # include "anv_genX.h"
3277 # undef genX
3278 # define genX(x) gen8_##x
3279 # include "anv_genX.h"
3280 # undef genX
3281 # define genX(x) gen9_##x
3282 # include "anv_genX.h"
3283 # undef genX
3284 # define genX(x) gen10_##x
3285 # include "anv_genX.h"
3286 # undef genX
3287 # define genX(x) gen11_##x
3288 # include "anv_genX.h"
3289 # undef genX
3290 #endif
3291
3292 #endif /* ANV_PRIVATE_H */