2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_clflush.h"
45 #include "common/gen_gem.h"
46 #include "dev/gen_device_info.h"
47 #include "blorp/blorp.h"
48 #include "compiler/brw_compiler.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/u_atomic.h"
52 #include "util/u_vector.h"
55 #include "vk_debug_report.h"
57 /* Pre-declarations needed for WSI entrypoints */
60 typedef struct xcb_connection_t xcb_connection_t
;
61 typedef uint32_t xcb_visualid_t
;
62 typedef uint32_t xcb_window_t
;
65 struct anv_buffer_view
;
66 struct anv_image_view
;
71 #include <vulkan/vulkan.h>
72 #include <vulkan/vulkan_intel.h>
73 #include <vulkan/vk_icd.h>
74 #include <vulkan/vk_android_native_buffer.h>
76 #include "anv_entrypoints.h"
77 #include "anv_extensions.h"
80 #include "common/gen_debug.h"
81 #include "common/intel_log.h"
82 #include "wsi_common.h"
84 /* anv Virtual Memory Layout
85 * =========================
87 * When the anv driver is determining the virtual graphics addresses of memory
88 * objects itself using the softpin mechanism, the following memory ranges
91 * Three special considerations to notice:
93 * (1) the dynamic state pool is located within the same 4 GiB as the low
94 * heap. This is to work around a VF cache issue described in a comment in
95 * anv_physical_device_init_heaps.
97 * (2) the binding table pool is located at lower addresses than the surface
98 * state pool, within a 4 GiB range. This allows surface state base addresses
99 * to cover both binding tables (16 bit offsets) and surface states (32 bit
102 * (3) the last 4 GiB of the address space is withheld from the high
103 * heap. Various hardware units will read past the end of an object for
104 * various reasons. This healthy margin prevents reads from wrapping around
107 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
108 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
109 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
110 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
111 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
112 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
113 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
114 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
115 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
116 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
117 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
118 #define HIGH_HEAP_MAX_ADDRESS 0xfffeffffffffULL
120 #define LOW_HEAP_SIZE \
121 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
122 #define HIGH_HEAP_SIZE \
123 (HIGH_HEAP_MAX_ADDRESS - HIGH_HEAP_MIN_ADDRESS + 1)
124 #define DYNAMIC_STATE_POOL_SIZE \
125 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
126 #define BINDING_TABLE_POOL_SIZE \
127 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
128 #define SURFACE_STATE_POOL_SIZE \
129 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
130 #define INSTRUCTION_STATE_POOL_SIZE \
131 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
133 /* Allowing different clear colors requires us to perform a depth resolve at
134 * the end of certain render passes. This is because while slow clears store
135 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
136 * See the PRMs for examples describing when additional resolves would be
137 * necessary. To enable fast clears without requiring extra resolves, we set
138 * the clear value to a globally-defined one. We could allow different values
139 * if the user doesn't expect coherent data during or after a render passes
140 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
141 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
142 * 1.0f seems to be the only value used. The only application that doesn't set
143 * this value does so through the usage of an seemingly uninitialized clear
146 #define ANV_HZ_FC_VAL 1.0f
151 #define MAX_VIEWPORTS 16
152 #define MAX_SCISSORS 16
153 #define MAX_PUSH_CONSTANTS_SIZE 128
154 #define MAX_DYNAMIC_BUFFERS 16
156 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
158 /* The kernel relocation API has a limitation of a 32-bit delta value
159 * applied to the address before it is written which, in spite of it being
160 * unsigned, is treated as signed . Because of the way that this maps to
161 * the Vulkan API, we cannot handle an offset into a buffer that does not
162 * fit into a signed 32 bits. The only mechanism we have for dealing with
163 * this at the moment is to limit all VkDeviceMemory objects to a maximum
164 * of 2GB each. The Vulkan spec allows us to do this:
166 * "Some platforms may have a limit on the maximum size of a single
167 * allocation. For example, certain systems may fail to create
168 * allocations with a size greater than or equal to 4GB. Such a limit is
169 * implementation-dependent, and if such a failure occurs then the error
170 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
172 * We don't use vk_error here because it's not an error so much as an
173 * indication to the application that the allocation is too large.
175 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
177 #define ANV_SVGS_VB_INDEX MAX_VBS
178 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
180 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
182 static inline uint32_t
183 align_down_npot_u32(uint32_t v
, uint32_t a
)
188 static inline uint32_t
189 align_u32(uint32_t v
, uint32_t a
)
191 assert(a
!= 0 && a
== (a
& -a
));
192 return (v
+ a
- 1) & ~(a
- 1);
195 static inline uint64_t
196 align_u64(uint64_t v
, uint64_t a
)
198 assert(a
!= 0 && a
== (a
& -a
));
199 return (v
+ a
- 1) & ~(a
- 1);
202 static inline int32_t
203 align_i32(int32_t v
, int32_t a
)
205 assert(a
!= 0 && a
== (a
& -a
));
206 return (v
+ a
- 1) & ~(a
- 1);
209 /** Alignment must be a power of 2. */
211 anv_is_aligned(uintmax_t n
, uintmax_t a
)
213 assert(a
== (a
& -a
));
214 return (n
& (a
- 1)) == 0;
217 static inline uint32_t
218 anv_minify(uint32_t n
, uint32_t levels
)
220 if (unlikely(n
== 0))
223 return MAX2(n
>> levels
, 1);
227 anv_clamp_f(float f
, float min
, float max
)
240 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
242 if (*inout_mask
& clear_mask
) {
243 *inout_mask
&= ~clear_mask
;
250 static inline union isl_color_value
251 vk_to_isl_color(VkClearColorValue color
)
253 return (union isl_color_value
) {
263 #define for_each_bit(b, dword) \
264 for (uint32_t __dword = (dword); \
265 (b) = __builtin_ffs(__dword) - 1, __dword; \
266 __dword &= ~(1 << (b)))
268 #define typed_memcpy(dest, src, count) ({ \
269 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
270 memcpy((dest), (src), (count) * sizeof(*(src))); \
273 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
274 * to be added here in order to utilize mapping in debug/error/perf macros.
276 #define REPORT_OBJECT_TYPE(o) \
277 __builtin_choose_expr ( \
278 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
279 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
280 __builtin_choose_expr ( \
281 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
282 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
283 __builtin_choose_expr ( \
284 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
285 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
286 __builtin_choose_expr ( \
287 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
288 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
289 __builtin_choose_expr ( \
290 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
291 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
292 __builtin_choose_expr ( \
293 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
294 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
295 __builtin_choose_expr ( \
296 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
297 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
298 __builtin_choose_expr ( \
299 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
300 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
301 __builtin_choose_expr ( \
302 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
303 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
304 __builtin_choose_expr ( \
305 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
306 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
307 __builtin_choose_expr ( \
308 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
309 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
310 __builtin_choose_expr ( \
311 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
312 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
313 __builtin_choose_expr ( \
314 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
315 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
316 __builtin_choose_expr ( \
317 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
318 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
319 __builtin_choose_expr ( \
320 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
321 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
322 __builtin_choose_expr ( \
323 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
324 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
325 __builtin_choose_expr ( \
326 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
327 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
328 __builtin_choose_expr ( \
329 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
330 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
331 __builtin_choose_expr ( \
332 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
333 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
334 __builtin_choose_expr ( \
335 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
336 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
337 __builtin_choose_expr ( \
338 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
339 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
340 __builtin_choose_expr ( \
341 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
342 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
343 __builtin_choose_expr ( \
344 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
345 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
346 __builtin_choose_expr ( \
347 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
348 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
349 __builtin_choose_expr ( \
350 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
351 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
352 __builtin_choose_expr ( \
353 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
354 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
355 __builtin_choose_expr ( \
356 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
357 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
358 __builtin_choose_expr ( \
359 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
360 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
361 __builtin_choose_expr ( \
362 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
363 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
364 __builtin_choose_expr ( \
365 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
366 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
367 __builtin_choose_expr ( \
368 __builtin_types_compatible_p (__typeof (o), void*), \
369 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
370 /* The void expression results in a compile-time error \
371 when assigning the result to something. */ \
372 (void)0)))))))))))))))))))))))))))))))
374 /* Whenever we generate an error, pass it through this function. Useful for
375 * debugging, where we can break on it. Only call at error site, not when
376 * propagating errors. Might be useful to plug in a stack trace here.
379 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
380 VkDebugReportObjectTypeEXT type
, VkResult error
,
381 const char *file
, int line
, const char *format
, ...);
384 #define vk_error(error) __vk_errorf(NULL, NULL,\
385 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
386 error, __FILE__, __LINE__, NULL)
387 #define vk_errorf(instance, obj, error, format, ...)\
388 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
389 __FILE__, __LINE__, format, ## __VA_ARGS__)
391 #define vk_error(error) error
392 #define vk_errorf(instance, obj, error, format, ...) error
396 * Warn on ignored extension structs.
398 * The Vulkan spec requires us to ignore unsupported or unknown structs in
399 * a pNext chain. In debug mode, emitting warnings for ignored structs may
400 * help us discover structs that we should not have ignored.
403 * From the Vulkan 1.0.38 spec:
405 * Any component of the implementation (the loader, any enabled layers,
406 * and drivers) must skip over, without processing (other than reading the
407 * sType and pNext members) any chained structures with sType values not
408 * defined by extensions supported by that component.
410 #define anv_debug_ignored_stype(sType) \
411 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
413 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
414 VkDebugReportObjectTypeEXT type
, const char *file
,
415 int line
, const char *format
, ...)
416 anv_printflike(6, 7);
417 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
418 void anv_loge_v(const char *format
, va_list va
);
421 * Print a FINISHME message, including its source location.
423 #define anv_finishme(format, ...) \
425 static bool reported = false; \
427 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
434 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
436 #define anv_perf_warn(instance, obj, format, ...) \
438 static bool reported = false; \
439 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
440 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
441 format, ##__VA_ARGS__); \
446 /* A non-fatal assert. Useful for debugging. */
448 #define anv_assert(x) ({ \
449 if (unlikely(!(x))) \
450 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
453 #define anv_assert(x)
456 /* A multi-pointer allocator
458 * When copying data structures from the user (such as a render pass), it's
459 * common to need to allocate data for a bunch of different things. Instead
460 * of doing several allocations and having to handle all of the error checking
461 * that entails, it can be easier to do a single allocation. This struct
462 * helps facilitate that. The intended usage looks like this:
465 * anv_multialloc_add(&ma, &main_ptr, 1);
466 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
467 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
469 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
470 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
472 struct anv_multialloc
{
480 #define ANV_MULTIALLOC_INIT \
481 ((struct anv_multialloc) { 0, })
483 #define ANV_MULTIALLOC(_name) \
484 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
486 __attribute__((always_inline
))
488 _anv_multialloc_add(struct anv_multialloc
*ma
,
489 void **ptr
, size_t size
, size_t align
)
491 size_t offset
= align_u64(ma
->size
, align
);
492 ma
->size
= offset
+ size
;
493 ma
->align
= MAX2(ma
->align
, align
);
495 /* Store the offset in the pointer. */
496 *ptr
= (void *)(uintptr_t)offset
;
498 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
499 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
502 #define anv_multialloc_add_size(_ma, _ptr, _size) \
503 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
505 #define anv_multialloc_add(_ma, _ptr, _count) \
506 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
508 __attribute__((always_inline
))
510 anv_multialloc_alloc(struct anv_multialloc
*ma
,
511 const VkAllocationCallbacks
*alloc
,
512 VkSystemAllocationScope scope
)
514 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
518 /* Fill out each of the pointers with their final value.
520 * for (uint32_t i = 0; i < ma->ptr_count; i++)
521 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
523 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
524 * constant, GCC is incapable of figuring this out and unrolling the loop
525 * so we have to give it a little help.
527 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
528 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
529 if ((_i) < ma->ptr_count) \
530 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
531 _ANV_MULTIALLOC_UPDATE_POINTER(0);
532 _ANV_MULTIALLOC_UPDATE_POINTER(1);
533 _ANV_MULTIALLOC_UPDATE_POINTER(2);
534 _ANV_MULTIALLOC_UPDATE_POINTER(3);
535 _ANV_MULTIALLOC_UPDATE_POINTER(4);
536 _ANV_MULTIALLOC_UPDATE_POINTER(5);
537 _ANV_MULTIALLOC_UPDATE_POINTER(6);
538 _ANV_MULTIALLOC_UPDATE_POINTER(7);
539 #undef _ANV_MULTIALLOC_UPDATE_POINTER
544 __attribute__((always_inline
))
546 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
547 const VkAllocationCallbacks
*parent_alloc
,
548 const VkAllocationCallbacks
*alloc
,
549 VkSystemAllocationScope scope
)
551 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
557 /* Index into the current validation list. This is used by the
558 * validation list building alrogithm to track which buffers are already
559 * in the validation list so that we can ensure uniqueness.
563 /* Last known offset. This value is provided by the kernel when we
564 * execbuf and is used as the presumed offset for the next bunch of
572 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
577 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
579 bo
->gem_handle
= gem_handle
;
587 /* Represents a lock-free linked list of "free" things. This is used by
588 * both the block pool and the state pools. Unfortunately, in order to
589 * solve the ABA problem, we can't use a single uint32_t head.
591 union anv_free_list
{
595 /* A simple count that is incremented every time the head changes. */
601 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
603 struct anv_block_state
{
613 struct anv_block_pool
{
614 struct anv_device
*device
;
620 /* The offset from the start of the bo to the "center" of the block
621 * pool. Pointers to allocated blocks are given by
622 * bo.map + center_bo_offset + offsets.
624 uint32_t center_bo_offset
;
626 /* Current memory map of the block pool. This pointer may or may not
627 * point to the actual beginning of the block pool memory. If
628 * anv_block_pool_alloc_back has ever been called, then this pointer
629 * will point to the "center" position of the buffer and all offsets
630 * (negative or positive) given out by the block pool alloc functions
631 * will be valid relative to this pointer.
633 * In particular, map == bo.map + center_offset
639 * Array of mmaps and gem handles owned by the block pool, reclaimed when
640 * the block pool is destroyed.
642 struct u_vector mmap_cleanups
;
644 struct anv_block_state state
;
646 struct anv_block_state back_state
;
649 /* Block pools are backed by a fixed-size 1GB memfd */
650 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
652 /* The center of the block pool is also the middle of the memfd. This may
653 * change in the future if we decide differently for some reason.
655 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
657 static inline uint32_t
658 anv_block_pool_size(struct anv_block_pool
*pool
)
660 return pool
->state
.end
+ pool
->back_state
.end
;
669 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
671 struct anv_fixed_size_state_pool
{
672 union anv_free_list free_list
;
673 struct anv_block_state block
;
676 #define ANV_MIN_STATE_SIZE_LOG2 6
677 #define ANV_MAX_STATE_SIZE_LOG2 20
679 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
681 struct anv_state_pool
{
682 struct anv_block_pool block_pool
;
684 /* The size of blocks which will be allocated from the block pool */
687 /** Free list for "back" allocations */
688 union anv_free_list back_alloc_free_list
;
690 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
693 struct anv_state_stream_block
;
695 struct anv_state_stream
{
696 struct anv_state_pool
*state_pool
;
698 /* The size of blocks to allocate from the state pool */
701 /* Current block we're allocating from */
702 struct anv_state block
;
704 /* Offset into the current block at which to allocate the next state */
707 /* List of all blocks allocated from this pool */
708 struct anv_state_stream_block
*block_list
;
711 /* The block_pool functions exported for testing only. The block pool should
712 * only be used via a state pool (see below).
714 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
715 struct anv_device
*device
,
716 uint32_t initial_size
,
718 void anv_block_pool_finish(struct anv_block_pool
*pool
);
719 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
720 uint32_t block_size
);
721 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
722 uint32_t block_size
);
724 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
725 struct anv_device
*device
,
728 void anv_state_pool_finish(struct anv_state_pool
*pool
);
729 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
730 uint32_t state_size
, uint32_t alignment
);
731 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
732 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
733 void anv_state_stream_init(struct anv_state_stream
*stream
,
734 struct anv_state_pool
*state_pool
,
735 uint32_t block_size
);
736 void anv_state_stream_finish(struct anv_state_stream
*stream
);
737 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
738 uint32_t size
, uint32_t alignment
);
741 * Implements a pool of re-usable BOs. The interface is identical to that
742 * of block_pool except that each block is its own BO.
745 struct anv_device
*device
;
752 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
754 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
755 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
757 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
759 struct anv_scratch_bo
{
764 struct anv_scratch_pool
{
765 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
766 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
769 void anv_scratch_pool_init(struct anv_device
*device
,
770 struct anv_scratch_pool
*pool
);
771 void anv_scratch_pool_finish(struct anv_device
*device
,
772 struct anv_scratch_pool
*pool
);
773 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
774 struct anv_scratch_pool
*pool
,
775 gl_shader_stage stage
,
776 unsigned per_thread_scratch
);
778 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
779 struct anv_bo_cache
{
780 struct hash_table
*bo_map
;
781 pthread_mutex_t mutex
;
784 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
785 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
786 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
787 struct anv_bo_cache
*cache
,
788 uint64_t size
, struct anv_bo
**bo
);
789 VkResult
anv_bo_cache_import(struct anv_device
*device
,
790 struct anv_bo_cache
*cache
,
791 int fd
, struct anv_bo
**bo
);
792 VkResult
anv_bo_cache_export(struct anv_device
*device
,
793 struct anv_bo_cache
*cache
,
794 struct anv_bo
*bo_in
, int *fd_out
);
795 void anv_bo_cache_release(struct anv_device
*device
,
796 struct anv_bo_cache
*cache
,
799 struct anv_memory_type
{
800 /* Standard bits passed on to the client */
801 VkMemoryPropertyFlags propertyFlags
;
804 /* Driver-internal book-keeping */
805 VkBufferUsageFlags valid_buffer_usage
;
808 struct anv_memory_heap
{
809 /* Standard bits passed on to the client */
811 VkMemoryHeapFlags flags
;
813 /* Driver-internal book-keeping */
814 bool supports_48bit_addresses
;
817 struct anv_physical_device
{
818 VK_LOADER_DATA _loader_data
;
820 struct anv_instance
* instance
;
825 struct gen_device_info info
;
826 /** Amount of "GPU memory" we want to advertise
828 * Clearly, this value is bogus since Intel is a UMA architecture. On
829 * gen7 platforms, we are limited by GTT size unless we want to implement
830 * fine-grained tracking and GTT splitting. On Broadwell and above we are
831 * practically unlimited. However, we will never report more than 3/4 of
832 * the total system ram to try and avoid running out of RAM.
834 bool supports_48bit_addresses
;
835 struct brw_compiler
* compiler
;
836 struct isl_device isl_dev
;
837 int cmd_parser_version
;
839 bool has_exec_capture
;
842 bool has_syncobj_wait
;
843 bool has_context_priority
;
846 struct anv_device_extension_table supported_extensions
;
849 uint32_t subslice_total
;
853 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
855 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
858 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
859 uint8_t driver_uuid
[VK_UUID_SIZE
];
860 uint8_t device_uuid
[VK_UUID_SIZE
];
862 struct wsi_device wsi_device
;
866 struct anv_instance
{
867 VK_LOADER_DATA _loader_data
;
869 VkAllocationCallbacks alloc
;
872 struct anv_instance_extension_table enabled_extensions
;
873 struct anv_dispatch_table dispatch
;
875 int physicalDeviceCount
;
876 struct anv_physical_device physicalDevice
;
878 struct vk_debug_report_instance debug_report_callbacks
;
881 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
882 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
884 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
885 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
889 VK_LOADER_DATA _loader_data
;
891 struct anv_device
* device
;
893 VkDeviceQueueCreateFlags flags
;
896 struct anv_pipeline_cache
{
897 struct anv_device
* device
;
898 pthread_mutex_t mutex
;
900 struct hash_table
* cache
;
903 struct anv_pipeline_bind_map
;
905 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
906 struct anv_device
*device
,
908 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
910 struct anv_shader_bin
*
911 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
912 const void *key
, uint32_t key_size
);
913 struct anv_shader_bin
*
914 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
915 const void *key_data
, uint32_t key_size
,
916 const void *kernel_data
, uint32_t kernel_size
,
917 const struct brw_stage_prog_data
*prog_data
,
918 uint32_t prog_data_size
,
919 const struct anv_pipeline_bind_map
*bind_map
);
922 VK_LOADER_DATA _loader_data
;
924 VkAllocationCallbacks alloc
;
926 struct anv_instance
* instance
;
929 struct gen_device_info info
;
930 struct isl_device isl_dev
;
933 bool can_chain_batches
;
934 bool robust_buffer_access
;
935 struct anv_device_extension_table enabled_extensions
;
936 struct anv_dispatch_table dispatch
;
938 pthread_mutex_t vma_mutex
;
939 struct util_vma_heap vma_lo
;
940 struct util_vma_heap vma_hi
;
941 uint64_t vma_lo_available
;
942 uint64_t vma_hi_available
;
944 struct anv_bo_pool batch_bo_pool
;
946 struct anv_bo_cache bo_cache
;
948 struct anv_state_pool dynamic_state_pool
;
949 struct anv_state_pool instruction_state_pool
;
950 struct anv_state_pool surface_state_pool
;
952 struct anv_bo workaround_bo
;
953 struct anv_bo trivial_batch_bo
;
954 struct anv_bo hiz_clear_bo
;
956 struct anv_pipeline_cache blorp_shader_cache
;
957 struct blorp_context blorp
;
959 struct anv_state border_colors
;
961 struct anv_queue queue
;
963 struct anv_scratch_pool scratch_pool
;
965 uint32_t default_mocs
;
967 pthread_mutex_t mutex
;
968 pthread_cond_t queue_submit
;
973 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
975 if (device
->info
.has_llc
)
978 gen_flush_range(state
.map
, state
.alloc_size
);
981 void anv_device_init_blorp(struct anv_device
*device
);
982 void anv_device_finish_blorp(struct anv_device
*device
);
984 VkResult
anv_device_execbuf(struct anv_device
*device
,
985 struct drm_i915_gem_execbuffer2
*execbuf
,
986 struct anv_bo
**execbuf_bos
);
987 VkResult
anv_device_query_status(struct anv_device
*device
);
988 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
989 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
992 void* anv_gem_mmap(struct anv_device
*device
,
993 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
994 void anv_gem_munmap(void *p
, uint64_t size
);
995 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
996 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
997 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
998 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
999 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1000 int anv_gem_execbuffer(struct anv_device
*device
,
1001 struct drm_i915_gem_execbuffer2
*execbuf
);
1002 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1003 uint32_t stride
, uint32_t tiling
);
1004 int anv_gem_create_context(struct anv_device
*device
);
1005 bool anv_gem_has_context_priority(int fd
);
1006 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1007 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1009 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1011 int anv_gem_get_param(int fd
, uint32_t param
);
1012 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1013 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1014 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1015 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1016 uint32_t *active
, uint32_t *pending
);
1017 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1018 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1019 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1020 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1021 uint32_t read_domains
, uint32_t write_domain
);
1022 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1023 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1024 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1025 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1026 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1027 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1029 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1030 uint32_t handle
, int fd
);
1031 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1032 bool anv_gem_supports_syncobj_wait(int fd
);
1033 int anv_gem_syncobj_wait(struct anv_device
*device
,
1034 uint32_t *handles
, uint32_t num_handles
,
1035 int64_t abs_timeout_ns
, bool wait_all
);
1037 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1038 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1040 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1042 struct anv_reloc_list
{
1043 uint32_t num_relocs
;
1044 uint32_t array_length
;
1045 struct drm_i915_gem_relocation_entry
* relocs
;
1046 struct anv_bo
** reloc_bos
;
1049 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1050 const VkAllocationCallbacks
*alloc
);
1051 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1052 const VkAllocationCallbacks
*alloc
);
1054 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1055 const VkAllocationCallbacks
*alloc
,
1056 uint32_t offset
, struct anv_bo
*target_bo
,
1059 struct anv_batch_bo
{
1060 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1061 struct list_head link
;
1065 /* Bytes actually consumed in this batch BO */
1068 struct anv_reloc_list relocs
;
1072 const VkAllocationCallbacks
* alloc
;
1078 struct anv_reloc_list
* relocs
;
1080 /* This callback is called (with the associated user data) in the event
1081 * that the batch runs out of space.
1083 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1087 * Current error status of the command buffer. Used to track inconsistent
1088 * or incomplete command buffer states that are the consequence of run-time
1089 * errors such as out of memory scenarios. We want to track this in the
1090 * batch because the command buffer object is not visible to some parts
1096 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1097 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1098 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1099 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1100 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1101 struct anv_batch
*batch
);
1103 static inline VkResult
1104 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1106 assert(error
!= VK_SUCCESS
);
1107 if (batch
->status
== VK_SUCCESS
)
1108 batch
->status
= error
;
1109 return batch
->status
;
1113 anv_batch_has_error(struct anv_batch
*batch
)
1115 return batch
->status
!= VK_SUCCESS
;
1118 struct anv_address
{
1123 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1126 anv_address_is_null(struct anv_address addr
)
1128 return addr
.bo
== NULL
&& addr
.offset
== 0;
1131 static inline uint64_t
1132 anv_address_physical(struct anv_address addr
)
1134 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1135 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1137 return gen_canonical_address(addr
.offset
);
1140 static inline struct anv_address
1141 anv_address_add(struct anv_address addr
, uint64_t offset
)
1143 addr
.offset
+= offset
;
1148 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1150 unsigned reloc_size
= 0;
1151 if (device
->info
.gen
>= 8) {
1152 reloc_size
= sizeof(uint64_t);
1153 *(uint64_t *)p
= gen_canonical_address(v
);
1155 reloc_size
= sizeof(uint32_t);
1159 if (flush
&& !device
->info
.has_llc
)
1160 gen_flush_range(p
, reloc_size
);
1163 static inline uint64_t
1164 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1165 const struct anv_address address
, uint32_t delta
)
1167 if (address
.bo
== NULL
) {
1168 return address
.offset
+ delta
;
1170 assert(batch
->start
<= location
&& location
< batch
->end
);
1172 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1176 #define __gen_address_type struct anv_address
1177 #define __gen_user_data struct anv_batch
1178 #define __gen_combine_address _anv_combine_address
1180 /* Wrapper macros needed to work around preprocessor argument issues. In
1181 * particular, arguments don't get pre-evaluated if they are concatenated.
1182 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1183 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1184 * We can work around this easily enough with these helpers.
1186 #define __anv_cmd_length(cmd) cmd ## _length
1187 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1188 #define __anv_cmd_header(cmd) cmd ## _header
1189 #define __anv_cmd_pack(cmd) cmd ## _pack
1190 #define __anv_reg_num(reg) reg ## _num
1192 #define anv_pack_struct(dst, struc, ...) do { \
1193 struct struc __template = { \
1196 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1197 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1200 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1201 void *__dst = anv_batch_emit_dwords(batch, n); \
1203 struct cmd __template = { \
1204 __anv_cmd_header(cmd), \
1205 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1208 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1213 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1217 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1218 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1221 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1222 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1223 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1226 #define anv_batch_emit(batch, cmd, name) \
1227 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1228 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1229 __builtin_expect(_dst != NULL, 1); \
1230 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1231 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1235 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1236 .GraphicsDataTypeGFDT = 0, \
1237 .LLCCacheabilityControlLLCCC = 0, \
1238 .L3CacheabilityControlL3CC = 1, \
1241 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1242 .LLCeLLCCacheabilityControlLLCCC = 0, \
1243 .L3CacheabilityControlL3CC = 1, \
1246 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1247 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1248 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1249 .AgeforQUADLRU = 0 \
1252 /* Skylake: MOCS is now an index into an array of 62 different caching
1253 * configurations programmed by the kernel.
1256 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1257 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1258 .IndextoMOCSTables = 2 \
1261 #define GEN9_MOCS_PTE { \
1262 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1263 .IndextoMOCSTables = 1 \
1266 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1267 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1268 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1269 .IndextoMOCSTables = 2 \
1272 #define GEN10_MOCS_PTE { \
1273 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1274 .IndextoMOCSTables = 1 \
1277 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1278 #define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1279 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1280 .IndextoMOCSTables = 2 \
1283 #define GEN11_MOCS_PTE { \
1284 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1285 .IndextoMOCSTables = 1 \
1288 struct anv_device_memory
{
1290 struct anv_memory_type
* type
;
1291 VkDeviceSize map_size
;
1296 * Header for Vertex URB Entry (VUE)
1298 struct anv_vue_header
{
1300 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1301 uint32_t ViewportIndex
;
1305 struct anv_descriptor_set_binding_layout
{
1307 /* The type of the descriptors in this binding */
1308 VkDescriptorType type
;
1311 /* Number of array elements in this binding */
1312 uint16_t array_size
;
1314 /* Index into the flattend descriptor set */
1315 uint16_t descriptor_index
;
1317 /* Index into the dynamic state array for a dynamic buffer */
1318 int16_t dynamic_offset_index
;
1320 /* Index into the descriptor set buffer views */
1321 int16_t buffer_index
;
1324 /* Index into the binding table for the associated surface */
1325 int16_t surface_index
;
1327 /* Index into the sampler table for the associated sampler */
1328 int16_t sampler_index
;
1330 /* Index into the image table for the associated image */
1331 int16_t image_index
;
1332 } stage
[MESA_SHADER_STAGES
];
1334 /* Immutable samplers (or NULL if no immutable samplers) */
1335 struct anv_sampler
**immutable_samplers
;
1338 struct anv_descriptor_set_layout
{
1339 /* Descriptor set layouts can be destroyed at almost any time */
1342 /* Number of bindings in this descriptor set */
1343 uint16_t binding_count
;
1345 /* Total size of the descriptor set with room for all array entries */
1348 /* Shader stages affected by this descriptor set */
1349 uint16_t shader_stages
;
1351 /* Number of buffers in this descriptor set */
1352 uint16_t buffer_count
;
1354 /* Number of dynamic offsets used by this descriptor set */
1355 uint16_t dynamic_offset_count
;
1357 /* Bindings in this descriptor set */
1358 struct anv_descriptor_set_binding_layout binding
[0];
1362 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1364 assert(layout
&& layout
->ref_cnt
>= 1);
1365 p_atomic_inc(&layout
->ref_cnt
);
1369 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1370 struct anv_descriptor_set_layout
*layout
)
1372 assert(layout
&& layout
->ref_cnt
>= 1);
1373 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1374 vk_free(&device
->alloc
, layout
);
1377 struct anv_descriptor
{
1378 VkDescriptorType type
;
1382 VkImageLayout layout
;
1383 struct anv_image_view
*image_view
;
1384 struct anv_sampler
*sampler
;
1388 struct anv_buffer
*buffer
;
1393 struct anv_buffer_view
*buffer_view
;
1397 struct anv_descriptor_set
{
1398 struct anv_descriptor_set_layout
*layout
;
1400 uint32_t buffer_count
;
1401 struct anv_buffer_view
*buffer_views
;
1402 struct anv_descriptor descriptors
[0];
1405 struct anv_buffer_view
{
1406 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1407 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1409 struct anv_address address
;
1411 struct anv_state surface_state
;
1412 struct anv_state storage_surface_state
;
1413 struct anv_state writeonly_storage_surface_state
;
1415 struct brw_image_param storage_image_param
;
1418 struct anv_push_descriptor_set
{
1419 struct anv_descriptor_set set
;
1421 /* Put this field right behind anv_descriptor_set so it fills up the
1422 * descriptors[0] field. */
1423 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1424 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1427 struct anv_descriptor_pool
{
1432 struct anv_state_stream surface_state_stream
;
1433 void *surface_state_free_list
;
1438 enum anv_descriptor_template_entry_type
{
1439 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1440 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1441 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1444 struct anv_descriptor_template_entry
{
1445 /* The type of descriptor in this entry */
1446 VkDescriptorType type
;
1448 /* Binding in the descriptor set */
1451 /* Offset at which to write into the descriptor set binding */
1452 uint32_t array_element
;
1454 /* Number of elements to write into the descriptor set binding */
1455 uint32_t array_count
;
1457 /* Offset into the user provided data */
1460 /* Stride between elements into the user provided data */
1464 struct anv_descriptor_update_template
{
1465 VkPipelineBindPoint bind_point
;
1467 /* The descriptor set this template corresponds to. This value is only
1468 * valid if the template was created with the templateType
1469 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1473 /* Number of entries in this template */
1474 uint32_t entry_count
;
1476 /* Entries of the template */
1477 struct anv_descriptor_template_entry entries
[0];
1481 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout
*binding
);
1484 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1487 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1488 const struct gen_device_info
* const devinfo
,
1489 const VkDescriptorImageInfo
* const info
,
1490 VkDescriptorType type
,
1495 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1496 VkDescriptorType type
,
1497 struct anv_buffer_view
*buffer_view
,
1502 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1503 struct anv_device
*device
,
1504 struct anv_state_stream
*alloc_stream
,
1505 VkDescriptorType type
,
1506 struct anv_buffer
*buffer
,
1509 VkDeviceSize offset
,
1510 VkDeviceSize range
);
1513 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1514 struct anv_device
*device
,
1515 struct anv_state_stream
*alloc_stream
,
1516 const struct anv_descriptor_update_template
*template,
1520 anv_descriptor_set_create(struct anv_device
*device
,
1521 struct anv_descriptor_pool
*pool
,
1522 struct anv_descriptor_set_layout
*layout
,
1523 struct anv_descriptor_set
**out_set
);
1526 anv_descriptor_set_destroy(struct anv_device
*device
,
1527 struct anv_descriptor_pool
*pool
,
1528 struct anv_descriptor_set
*set
);
1530 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1532 struct anv_pipeline_binding
{
1533 /* The descriptor set this surface corresponds to. The special value of
1534 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1535 * to a color attachment and not a regular descriptor.
1539 /* Binding in the descriptor set */
1542 /* Index in the binding */
1545 /* Plane in the binding index */
1548 /* Input attachment index (relative to the subpass) */
1549 uint8_t input_attachment_index
;
1551 /* For a storage image, whether it is write-only */
1555 struct anv_pipeline_layout
{
1557 struct anv_descriptor_set_layout
*layout
;
1558 uint32_t dynamic_offset_start
;
1564 bool has_dynamic_offsets
;
1565 } stage
[MESA_SHADER_STAGES
];
1567 unsigned char sha1
[20];
1571 struct anv_device
* device
;
1574 VkBufferUsageFlags usage
;
1576 /* Set when bound */
1577 struct anv_address address
;
1580 static inline uint64_t
1581 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1583 assert(offset
<= buffer
->size
);
1584 if (range
== VK_WHOLE_SIZE
) {
1585 return buffer
->size
- offset
;
1587 assert(range
<= buffer
->size
);
1592 enum anv_cmd_dirty_bits
{
1593 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1594 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1595 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1596 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1597 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1598 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1599 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1600 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1601 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1602 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1603 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1604 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1605 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1607 typedef uint32_t anv_cmd_dirty_mask_t
;
1609 enum anv_pipe_bits
{
1610 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1611 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1612 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1613 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1614 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1615 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1616 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1617 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1618 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1619 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1620 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1622 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1623 * a flush has happened but not a CS stall. The next time we do any sort
1624 * of invalidation we need to insert a CS stall at that time. Otherwise,
1625 * we would have to CS stall on every flush which could be bad.
1627 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1630 #define ANV_PIPE_FLUSH_BITS ( \
1631 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1632 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1633 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1635 #define ANV_PIPE_STALL_BITS ( \
1636 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1637 ANV_PIPE_DEPTH_STALL_BIT | \
1638 ANV_PIPE_CS_STALL_BIT)
1640 #define ANV_PIPE_INVALIDATE_BITS ( \
1641 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1642 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1643 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1644 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1645 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1646 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1648 static inline enum anv_pipe_bits
1649 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1651 enum anv_pipe_bits pipe_bits
= 0;
1654 for_each_bit(b
, flags
) {
1655 switch ((VkAccessFlagBits
)(1 << b
)) {
1656 case VK_ACCESS_SHADER_WRITE_BIT
:
1657 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1659 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1660 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1662 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1663 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1665 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1666 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1667 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1670 break; /* Nothing to do */
1677 static inline enum anv_pipe_bits
1678 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1680 enum anv_pipe_bits pipe_bits
= 0;
1683 for_each_bit(b
, flags
) {
1684 switch ((VkAccessFlagBits
)(1 << b
)) {
1685 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1686 case VK_ACCESS_INDEX_READ_BIT
:
1687 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1688 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1690 case VK_ACCESS_UNIFORM_READ_BIT
:
1691 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1692 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1694 case VK_ACCESS_SHADER_READ_BIT
:
1695 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1696 case VK_ACCESS_TRANSFER_READ_BIT
:
1697 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1700 break; /* Nothing to do */
1707 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1708 VK_IMAGE_ASPECT_COLOR_BIT | \
1709 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1710 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1711 VK_IMAGE_ASPECT_PLANE_2_BIT)
1712 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1713 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1714 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1715 VK_IMAGE_ASPECT_PLANE_2_BIT)
1717 struct anv_vertex_binding
{
1718 struct anv_buffer
* buffer
;
1719 VkDeviceSize offset
;
1722 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1723 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1725 struct anv_push_constants
{
1726 /* Current allocated size of this push constants data structure.
1727 * Because a decent chunk of it may not be used (images on SKL, for
1728 * instance), we won't actually allocate the entire structure up-front.
1732 /* Push constant data provided by the client through vkPushConstants */
1733 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1735 /* Used for vkCmdDispatchBase */
1736 uint32_t base_work_group_id
[3];
1738 /* Image data for image_load_store on pre-SKL */
1739 struct brw_image_param images
[MAX_IMAGES
];
1742 struct anv_dynamic_state
{
1745 VkViewport viewports
[MAX_VIEWPORTS
];
1750 VkRect2D scissors
[MAX_SCISSORS
];
1761 float blend_constants
[4];
1771 } stencil_compare_mask
;
1776 } stencil_write_mask
;
1781 } stencil_reference
;
1784 extern const struct anv_dynamic_state default_dynamic_state
;
1786 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1787 const struct anv_dynamic_state
*src
,
1788 uint32_t copy_mask
);
1790 struct anv_surface_state
{
1791 struct anv_state state
;
1792 /** Address of the surface referred to by this state
1794 * This address is relative to the start of the BO.
1796 struct anv_address address
;
1797 /* Address of the aux surface, if any
1799 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
1801 * With the exception of gen8, the bottom 12 bits of this address' offset
1802 * include extra aux information.
1804 struct anv_address aux_address
;
1805 /* Address of the clear color, if any
1807 * This address is relative to the start of the BO.
1809 struct anv_address clear_address
;
1813 * Attachment state when recording a renderpass instance.
1815 * The clear value is valid only if there exists a pending clear.
1817 struct anv_attachment_state
{
1818 enum isl_aux_usage aux_usage
;
1819 enum isl_aux_usage input_aux_usage
;
1820 struct anv_surface_state color
;
1821 struct anv_surface_state input
;
1823 VkImageLayout current_layout
;
1824 VkImageAspectFlags pending_clear_aspects
;
1825 VkImageAspectFlags pending_load_aspects
;
1827 VkClearValue clear_value
;
1828 bool clear_color_is_zero_one
;
1829 bool clear_color_is_zero
;
1831 /* When multiview is active, attachments with a renderpass clear
1832 * operation have their respective layers cleared on the first
1833 * subpass that uses them, and only in that subpass. We keep track
1834 * of this using a bitfield to indicate which layers of an attachment
1835 * have not been cleared yet when multiview is active.
1837 uint32_t pending_clear_views
;
1840 /** State tracking for particular pipeline bind point
1842 * This struct is the base struct for anv_cmd_graphics_state and
1843 * anv_cmd_compute_state. These are used to track state which is bound to a
1844 * particular type of pipeline. Generic state that applies per-stage such as
1845 * binding table offsets and push constants is tracked generically with a
1846 * per-stage array in anv_cmd_state.
1848 struct anv_cmd_pipeline_state
{
1849 struct anv_pipeline
*pipeline
;
1850 struct anv_pipeline_layout
*layout
;
1852 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
1853 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
1855 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
1858 /** State tracking for graphics pipeline
1860 * This has anv_cmd_pipeline_state as a base struct to track things which get
1861 * bound to a graphics pipeline. Along with general pipeline bind point state
1862 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1863 * state which is graphics-specific.
1865 struct anv_cmd_graphics_state
{
1866 struct anv_cmd_pipeline_state base
;
1868 anv_cmd_dirty_mask_t dirty
;
1871 struct anv_dynamic_state dynamic
;
1874 struct anv_buffer
*index_buffer
;
1875 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1876 uint32_t index_offset
;
1880 /** State tracking for compute pipeline
1882 * This has anv_cmd_pipeline_state as a base struct to track things which get
1883 * bound to a compute pipeline. Along with general pipeline bind point state
1884 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1885 * state which is compute-specific.
1887 struct anv_cmd_compute_state
{
1888 struct anv_cmd_pipeline_state base
;
1890 bool pipeline_dirty
;
1892 struct anv_address num_workgroups
;
1895 /** State required while building cmd buffer */
1896 struct anv_cmd_state
{
1897 /* PIPELINE_SELECT.PipelineSelection */
1898 uint32_t current_pipeline
;
1899 const struct gen_l3_config
* current_l3_config
;
1901 struct anv_cmd_graphics_state gfx
;
1902 struct anv_cmd_compute_state compute
;
1904 enum anv_pipe_bits pending_pipe_bits
;
1905 VkShaderStageFlags descriptors_dirty
;
1906 VkShaderStageFlags push_constants_dirty
;
1908 struct anv_framebuffer
* framebuffer
;
1909 struct anv_render_pass
* pass
;
1910 struct anv_subpass
* subpass
;
1911 VkRect2D render_area
;
1912 uint32_t restart_index
;
1913 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1914 VkShaderStageFlags push_constant_stages
;
1915 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1916 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1917 struct anv_state samplers
[MESA_SHADER_STAGES
];
1920 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1921 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1922 * and before invoking the secondary in ExecuteCommands.
1924 bool pma_fix_enabled
;
1927 * Whether or not we know for certain that HiZ is enabled for the current
1928 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1929 * enabled or not, this will be false.
1934 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1935 * valid only when recording a render pass instance.
1937 struct anv_attachment_state
* attachments
;
1940 * Surface states for color render targets. These are stored in a single
1941 * flat array. For depth-stencil attachments, the surface state is simply
1944 struct anv_state render_pass_states
;
1947 * A null surface state of the right size to match the framebuffer. This
1948 * is one of the states in render_pass_states.
1950 struct anv_state null_surface_state
;
1953 struct anv_cmd_pool
{
1954 VkAllocationCallbacks alloc
;
1955 struct list_head cmd_buffers
;
1958 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1960 enum anv_cmd_buffer_exec_mode
{
1961 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1962 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1963 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1964 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1965 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1968 struct anv_cmd_buffer
{
1969 VK_LOADER_DATA _loader_data
;
1971 struct anv_device
* device
;
1973 struct anv_cmd_pool
* pool
;
1974 struct list_head pool_link
;
1976 struct anv_batch batch
;
1978 /* Fields required for the actual chain of anv_batch_bo's.
1980 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1982 struct list_head batch_bos
;
1983 enum anv_cmd_buffer_exec_mode exec_mode
;
1985 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1986 * referenced by this command buffer
1988 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1990 struct u_vector seen_bbos
;
1992 /* A vector of int32_t's for every block of binding tables.
1994 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1996 struct u_vector bt_block_states
;
1999 struct anv_reloc_list surface_relocs
;
2000 /** Last seen surface state block pool center bo offset */
2001 uint32_t last_ss_pool_center
;
2003 /* Serial for tracking buffer completion */
2006 /* Stream objects for storing temporary data */
2007 struct anv_state_stream surface_state_stream
;
2008 struct anv_state_stream dynamic_state_stream
;
2010 VkCommandBufferUsageFlags usage_flags
;
2011 VkCommandBufferLevel level
;
2013 struct anv_cmd_state state
;
2016 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2017 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2018 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2019 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2020 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2021 struct anv_cmd_buffer
*secondary
);
2022 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2023 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2024 struct anv_cmd_buffer
*cmd_buffer
,
2025 const VkSemaphore
*in_semaphores
,
2026 uint32_t num_in_semaphores
,
2027 const VkSemaphore
*out_semaphores
,
2028 uint32_t num_out_semaphores
,
2031 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2034 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
2035 gl_shader_stage stage
, uint32_t size
);
2036 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
2037 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
2038 (offsetof(struct anv_push_constants, field) + \
2039 sizeof(cmd_buffer->state.push_constants[0]->field)))
2041 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2042 const void *data
, uint32_t size
, uint32_t alignment
);
2043 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2044 uint32_t *a
, uint32_t *b
,
2045 uint32_t dwords
, uint32_t alignment
);
2048 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2050 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2051 uint32_t entries
, uint32_t *state_offset
);
2053 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2055 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2056 uint32_t size
, uint32_t alignment
);
2059 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2061 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2062 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2063 bool depth_clamp_enable
);
2064 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2066 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2067 struct anv_render_pass
*pass
,
2068 struct anv_framebuffer
*framebuffer
,
2069 const VkClearValue
*clear_values
);
2071 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2074 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2075 gl_shader_stage stage
);
2077 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2079 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
2081 const struct anv_image_view
*
2082 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2085 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2086 uint32_t num_entries
,
2087 uint32_t *state_offset
,
2088 struct anv_state
*bt_state
);
2090 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2092 enum anv_fence_type
{
2093 ANV_FENCE_TYPE_NONE
= 0,
2095 ANV_FENCE_TYPE_SYNCOBJ
,
2098 enum anv_bo_fence_state
{
2099 /** Indicates that this is a new (or newly reset fence) */
2100 ANV_BO_FENCE_STATE_RESET
,
2102 /** Indicates that this fence has been submitted to the GPU but is still
2103 * (as far as we know) in use by the GPU.
2105 ANV_BO_FENCE_STATE_SUBMITTED
,
2107 ANV_BO_FENCE_STATE_SIGNALED
,
2110 struct anv_fence_impl
{
2111 enum anv_fence_type type
;
2114 /** Fence implementation for BO fences
2116 * These fences use a BO and a set of CPU-tracked state flags. The BO
2117 * is added to the object list of the last execbuf call in a QueueSubmit
2118 * and is marked EXEC_WRITE. The state flags track when the BO has been
2119 * submitted to the kernel. We need to do this because Vulkan lets you
2120 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2121 * will say it's idle in this case.
2125 enum anv_bo_fence_state state
;
2128 /** DRM syncobj handle for syncobj-based fences */
2134 /* Permanent fence state. Every fence has some form of permanent state
2135 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2136 * cross-process fences) or it could just be a dummy for use internally.
2138 struct anv_fence_impl permanent
;
2140 /* Temporary fence state. A fence *may* have temporary state. That state
2141 * is added to the fence by an import operation and is reset back to
2142 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2143 * state cannot be signaled because the fence must already be signaled
2144 * before the temporary state can be exported from the fence in the other
2145 * process and imported here.
2147 struct anv_fence_impl temporary
;
2152 struct anv_state state
;
2155 enum anv_semaphore_type
{
2156 ANV_SEMAPHORE_TYPE_NONE
= 0,
2157 ANV_SEMAPHORE_TYPE_DUMMY
,
2158 ANV_SEMAPHORE_TYPE_BO
,
2159 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2160 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2163 struct anv_semaphore_impl
{
2164 enum anv_semaphore_type type
;
2167 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2168 * This BO will be added to the object list on any execbuf2 calls for
2169 * which this semaphore is used as a wait or signal fence. When used as
2170 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2174 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2175 * If the semaphore is in the unsignaled state due to either just being
2176 * created or because it has been used for a wait, fd will be -1.
2180 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2181 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2182 * import so we don't need to bother with a userspace cache.
2188 struct anv_semaphore
{
2189 /* Permanent semaphore state. Every semaphore has some form of permanent
2190 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2191 * (for cross-process semaphores0 or it could just be a dummy for use
2194 struct anv_semaphore_impl permanent
;
2196 /* Temporary semaphore state. A semaphore *may* have temporary state.
2197 * That state is added to the semaphore by an import operation and is reset
2198 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2199 * semaphore with temporary state cannot be signaled because the semaphore
2200 * must already be signaled before the temporary state can be exported from
2201 * the semaphore in the other process and imported here.
2203 struct anv_semaphore_impl temporary
;
2206 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2207 struct anv_semaphore
*semaphore
);
2209 struct anv_shader_module
{
2210 unsigned char sha1
[20];
2215 static inline gl_shader_stage
2216 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2218 assert(__builtin_popcount(vk_stage
) == 1);
2219 return ffs(vk_stage
) - 1;
2222 static inline VkShaderStageFlagBits
2223 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2225 return (1 << mesa_stage
);
2228 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2230 #define anv_foreach_stage(stage, stage_bits) \
2231 for (gl_shader_stage stage, \
2232 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2233 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2234 __tmp &= ~(1 << (stage)))
2236 struct anv_pipeline_bind_map
{
2237 uint32_t surface_count
;
2238 uint32_t sampler_count
;
2239 uint32_t image_count
;
2241 struct anv_pipeline_binding
* surface_to_descriptor
;
2242 struct anv_pipeline_binding
* sampler_to_descriptor
;
2245 struct anv_shader_bin_key
{
2250 struct anv_shader_bin
{
2253 const struct anv_shader_bin_key
*key
;
2255 struct anv_state kernel
;
2256 uint32_t kernel_size
;
2258 const struct brw_stage_prog_data
*prog_data
;
2259 uint32_t prog_data_size
;
2261 struct anv_pipeline_bind_map bind_map
;
2264 struct anv_shader_bin
*
2265 anv_shader_bin_create(struct anv_device
*device
,
2266 const void *key
, uint32_t key_size
,
2267 const void *kernel
, uint32_t kernel_size
,
2268 const struct brw_stage_prog_data
*prog_data
,
2269 uint32_t prog_data_size
, const void *prog_data_param
,
2270 const struct anv_pipeline_bind_map
*bind_map
);
2273 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2276 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2278 assert(shader
&& shader
->ref_cnt
>= 1);
2279 p_atomic_inc(&shader
->ref_cnt
);
2283 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2285 assert(shader
&& shader
->ref_cnt
>= 1);
2286 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2287 anv_shader_bin_destroy(device
, shader
);
2290 struct anv_pipeline
{
2291 struct anv_device
* device
;
2292 struct anv_batch batch
;
2293 uint32_t batch_data
[512];
2294 struct anv_reloc_list batch_relocs
;
2295 uint32_t dynamic_state_mask
;
2296 struct anv_dynamic_state dynamic_state
;
2298 struct anv_subpass
* subpass
;
2300 bool needs_data_cache
;
2302 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2305 const struct gen_l3_config
* l3_config
;
2306 uint32_t total_size
;
2309 VkShaderStageFlags active_stages
;
2310 struct anv_state blend_state
;
2313 uint32_t binding_stride
[MAX_VBS
];
2314 bool instancing_enable
[MAX_VBS
];
2315 bool primitive_restart
;
2318 uint32_t cs_right_mask
;
2321 bool depth_test_enable
;
2322 bool writes_stencil
;
2323 bool stencil_test_enable
;
2324 bool depth_clamp_enable
;
2325 bool sample_shading_enable
;
2330 uint32_t depth_stencil_state
[3];
2336 uint32_t wm_depth_stencil
[3];
2340 uint32_t wm_depth_stencil
[4];
2343 uint32_t interface_descriptor_data
[8];
2347 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2348 gl_shader_stage stage
)
2350 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2353 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2354 static inline const struct brw_##prefix##_prog_data * \
2355 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2357 if (anv_pipeline_has_stage(pipeline, stage)) { \
2358 return (const struct brw_##prefix##_prog_data *) \
2359 pipeline->shaders[stage]->prog_data; \
2365 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2366 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2367 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2368 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2369 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2370 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2372 static inline const struct brw_vue_prog_data
*
2373 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2375 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2376 return &get_gs_prog_data(pipeline
)->base
;
2377 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2378 return &get_tes_prog_data(pipeline
)->base
;
2380 return &get_vs_prog_data(pipeline
)->base
;
2384 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2385 struct anv_pipeline_cache
*cache
,
2386 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2387 const VkAllocationCallbacks
*alloc
);
2390 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2391 struct anv_pipeline_cache
*cache
,
2392 const VkComputePipelineCreateInfo
*info
,
2393 struct anv_shader_module
*module
,
2394 const char *entrypoint
,
2395 const VkSpecializationInfo
*spec_info
);
2397 struct anv_format_plane
{
2398 enum isl_format isl_format
:16;
2399 struct isl_swizzle swizzle
;
2401 /* Whether this plane contains chroma channels */
2404 /* For downscaling of YUV planes */
2405 uint8_t denominator_scales
[2];
2407 /* How to map sampled ycbcr planes to a single 4 component element. */
2408 struct isl_swizzle ycbcr_swizzle
;
2413 struct anv_format_plane planes
[3];
2418 static inline uint32_t
2419 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2420 VkImageAspectFlags aspect_mask
)
2422 switch (aspect_mask
) {
2423 case VK_IMAGE_ASPECT_COLOR_BIT
:
2424 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2425 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2427 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2428 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2431 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2433 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2436 /* Purposefully assert with depth/stencil aspects. */
2437 unreachable("invalid image aspect");
2441 static inline uint32_t
2442 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask
)
2444 uint32_t planes
= 0;
2446 if (aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
|
2447 VK_IMAGE_ASPECT_DEPTH_BIT
|
2448 VK_IMAGE_ASPECT_STENCIL_BIT
|
2449 VK_IMAGE_ASPECT_PLANE_0_BIT
))
2451 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_1_BIT
)
2453 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_2_BIT
)
2456 if ((aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) != 0 &&
2457 (aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) != 0)
2463 static inline VkImageAspectFlags
2464 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
2467 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2468 if (_mesa_bitcount(image_aspects
) > 1)
2469 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
2470 return VK_IMAGE_ASPECT_COLOR_BIT
;
2472 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
2473 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
2474 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
2475 return VK_IMAGE_ASPECT_STENCIL_BIT
;
2478 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2479 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2481 const struct anv_format
*
2482 anv_get_format(VkFormat format
);
2484 static inline uint32_t
2485 anv_get_format_planes(VkFormat vk_format
)
2487 const struct anv_format
*format
= anv_get_format(vk_format
);
2489 return format
!= NULL
? format
->n_planes
: 0;
2492 struct anv_format_plane
2493 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2494 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
2496 static inline enum isl_format
2497 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2498 VkImageAspectFlags aspect
, VkImageTiling tiling
)
2500 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
2503 static inline struct isl_swizzle
2504 anv_swizzle_for_render(struct isl_swizzle swizzle
)
2506 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2507 * RGB as RGBA for texturing
2509 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
2510 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
2512 /* But it doesn't matter what we render to that channel */
2513 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
2519 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
2522 * Subsurface of an anv_image.
2524 struct anv_surface
{
2525 /** Valid only if isl_surf::size > 0. */
2526 struct isl_surf isl
;
2529 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2536 /* The original VkFormat provided by the client. This may not match any
2537 * of the actual surface formats.
2540 const struct anv_format
*format
;
2542 VkImageAspectFlags aspects
;
2545 uint32_t array_size
;
2546 uint32_t samples
; /**< VkImageCreateInfo::samples */
2548 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2549 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2551 /** True if this is needs to be bound to an appropriately tiled BO.
2553 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2554 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2555 * we require a dedicated allocation so that we can know to allocate a
2558 bool needs_set_tiling
;
2561 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2562 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2564 uint64_t drm_format_mod
;
2569 /* Whether the image is made of several underlying buffer objects rather a
2570 * single one with different offsets.
2577 * For each foo, anv_image::planes[x].surface is valid if and only if
2578 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2579 * to figure the number associated with a given aspect.
2581 * The hardware requires that the depth buffer and stencil buffer be
2582 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2583 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2584 * allocate the depth and stencil buffers as separate surfaces in the same
2589 * -----------------------
2591 * ----------------------- |
2592 * | shadow surface0 | |
2593 * ----------------------- | Plane 0
2594 * | aux surface0 | |
2595 * ----------------------- |
2596 * | fast clear colors0 | \|/
2597 * -----------------------
2599 * ----------------------- |
2600 * | shadow surface1 | |
2601 * ----------------------- | Plane 1
2602 * | aux surface1 | |
2603 * ----------------------- |
2604 * | fast clear colors1 | \|/
2605 * -----------------------
2608 * -----------------------
2612 * Offset of the entire plane (whenever the image is disjoint this is
2620 struct anv_surface surface
;
2623 * A surface which shadows the main surface and may have different
2624 * tiling. This is used for sampling using a tiling that isn't supported
2625 * for other operations.
2627 struct anv_surface shadow_surface
;
2630 * For color images, this is the aux usage for this image when not used
2631 * as a color attachment.
2633 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2634 * image has a HiZ buffer.
2636 enum isl_aux_usage aux_usage
;
2638 struct anv_surface aux_surface
;
2641 * Offset of the fast clear state (used to compute the
2642 * fast_clear_state_offset of the following planes).
2644 uint32_t fast_clear_state_offset
;
2647 * BO associated with this plane, set when bound.
2649 struct anv_address address
;
2652 * When destroying the image, also free the bo.
2658 /* The ordering of this enum is important */
2659 enum anv_fast_clear_type
{
2660 /** Image does not have/support any fast-clear blocks */
2661 ANV_FAST_CLEAR_NONE
= 0,
2662 /** Image has/supports fast-clear but only to the default value */
2663 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
2664 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2665 ANV_FAST_CLEAR_ANY
= 2,
2668 /* Returns the number of auxiliary buffer levels attached to an image. */
2669 static inline uint8_t
2670 anv_image_aux_levels(const struct anv_image
* const image
,
2671 VkImageAspectFlagBits aspect
)
2673 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2674 return image
->planes
[plane
].aux_surface
.isl
.size
> 0 ?
2675 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
2678 /* Returns the number of auxiliary buffer layers attached to an image. */
2679 static inline uint32_t
2680 anv_image_aux_layers(const struct anv_image
* const image
,
2681 VkImageAspectFlagBits aspect
,
2682 const uint8_t miplevel
)
2686 /* The miplevel must exist in the main buffer. */
2687 assert(miplevel
< image
->levels
);
2689 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
2690 /* There are no layers with auxiliary data because the miplevel has no
2695 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2696 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
2697 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
2701 static inline struct anv_address
2702 anv_image_get_clear_color_addr(const struct anv_device
*device
,
2703 const struct anv_image
*image
,
2704 VkImageAspectFlagBits aspect
)
2706 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
2708 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2709 return anv_address_add(image
->planes
[plane
].address
,
2710 image
->planes
[plane
].fast_clear_state_offset
);
2713 static inline struct anv_address
2714 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
2715 const struct anv_image
*image
,
2716 VkImageAspectFlagBits aspect
)
2718 struct anv_address addr
=
2719 anv_image_get_clear_color_addr(device
, image
, aspect
);
2721 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
2722 device
->isl_dev
.ss
.clear_color_state_size
:
2723 device
->isl_dev
.ss
.clear_value_size
;
2724 addr
.offset
+= clear_color_state_size
;
2728 static inline struct anv_address
2729 anv_image_get_compression_state_addr(const struct anv_device
*device
,
2730 const struct anv_image
*image
,
2731 VkImageAspectFlagBits aspect
,
2732 uint32_t level
, uint32_t array_layer
)
2734 assert(level
< anv_image_aux_levels(image
, aspect
));
2735 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
2736 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2737 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
2739 struct anv_address addr
=
2740 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
2741 addr
.offset
+= 4; /* Go past the fast clear type */
2743 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2744 for (uint32_t l
= 0; l
< level
; l
++)
2745 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
2747 addr
.offset
+= level
* image
->array_size
* 4;
2749 addr
.offset
+= array_layer
* 4;
2754 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2756 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
2757 const struct anv_image
*image
)
2759 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
2762 if (devinfo
->gen
< 8)
2765 return image
->samples
== 1;
2769 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
2770 const struct anv_image
*image
,
2771 VkImageAspectFlagBits aspect
,
2772 enum isl_aux_usage aux_usage
,
2774 uint32_t base_layer
,
2775 uint32_t layer_count
);
2778 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
2779 const struct anv_image
*image
,
2780 VkImageAspectFlagBits aspect
,
2781 enum isl_aux_usage aux_usage
,
2782 enum isl_format format
, struct isl_swizzle swizzle
,
2783 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
2784 VkRect2D area
, union isl_color_value clear_color
);
2786 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
2787 const struct anv_image
*image
,
2788 VkImageAspectFlags aspects
,
2789 enum isl_aux_usage depth_aux_usage
,
2791 uint32_t base_layer
, uint32_t layer_count
,
2793 float depth_value
, uint8_t stencil_value
);
2795 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
2796 const struct anv_image
*image
,
2797 VkImageAspectFlagBits aspect
, uint32_t level
,
2798 uint32_t base_layer
, uint32_t layer_count
,
2799 enum isl_aux_op hiz_op
);
2801 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
2802 const struct anv_image
*image
,
2803 VkImageAspectFlags aspects
,
2805 uint32_t base_layer
, uint32_t layer_count
,
2806 VkRect2D area
, uint8_t stencil_value
);
2808 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
2809 const struct anv_image
*image
,
2810 VkImageAspectFlagBits aspect
,
2811 uint32_t base_layer
, uint32_t layer_count
,
2812 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
2815 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
2816 const struct anv_image
*image
,
2817 VkImageAspectFlagBits aspect
, uint32_t level
,
2818 uint32_t base_layer
, uint32_t layer_count
,
2819 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
2823 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
2824 const struct anv_image
*image
,
2825 uint32_t base_level
, uint32_t level_count
,
2826 uint32_t base_layer
, uint32_t layer_count
);
2829 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
2830 const struct anv_image
*image
,
2831 const VkImageAspectFlagBits aspect
,
2832 const VkImageLayout layout
);
2834 enum anv_fast_clear_type
2835 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
2836 const struct anv_image
* const image
,
2837 const VkImageAspectFlagBits aspect
,
2838 const VkImageLayout layout
);
2840 /* This is defined as a macro so that it works for both
2841 * VkImageSubresourceRange and VkImageSubresourceLayers
2843 #define anv_get_layerCount(_image, _range) \
2844 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2845 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2847 static inline uint32_t
2848 anv_get_levelCount(const struct anv_image
*image
,
2849 const VkImageSubresourceRange
*range
)
2851 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
2852 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
2855 static inline VkImageAspectFlags
2856 anv_image_expand_aspects(const struct anv_image
*image
,
2857 VkImageAspectFlags aspects
)
2859 /* If the underlying image has color plane aspects and
2860 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2861 * the underlying image. */
2862 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
2863 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
2864 return image
->aspects
;
2870 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
2871 VkImageAspectFlags aspects2
)
2873 if (aspects1
== aspects2
)
2876 /* Only 1 color aspects are compatibles. */
2877 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
2878 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
2879 _mesa_bitcount(aspects1
) == _mesa_bitcount(aspects2
))
2885 struct anv_image_view
{
2886 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
2888 VkImageAspectFlags aspect_mask
;
2890 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2894 uint32_t image_plane
;
2896 struct isl_view isl
;
2899 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2900 * image layout of SHADER_READ_ONLY_OPTIMAL or
2901 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2903 struct anv_surface_state optimal_sampler_surface_state
;
2906 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2907 * image layout of GENERAL.
2909 struct anv_surface_state general_sampler_surface_state
;
2912 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2913 * states for write-only and readable, using the real format for
2914 * write-only and the lowered format for readable.
2916 struct anv_surface_state storage_surface_state
;
2917 struct anv_surface_state writeonly_storage_surface_state
;
2919 struct brw_image_param storage_image_param
;
2923 enum anv_image_view_state_flags
{
2924 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
2925 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
2928 void anv_image_fill_surface_state(struct anv_device
*device
,
2929 const struct anv_image
*image
,
2930 VkImageAspectFlagBits aspect
,
2931 const struct isl_view
*view
,
2932 isl_surf_usage_flags_t view_usage
,
2933 enum isl_aux_usage aux_usage
,
2934 const union isl_color_value
*clear_color
,
2935 enum anv_image_view_state_flags flags
,
2936 struct anv_surface_state
*state_inout
,
2937 struct brw_image_param
*image_param_out
);
2939 struct anv_image_create_info
{
2940 const VkImageCreateInfo
*vk_info
;
2942 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2943 isl_tiling_flags_t isl_tiling_flags
;
2945 /** These flags will be added to any derived from VkImageCreateInfo. */
2946 isl_surf_usage_flags_t isl_extra_usage_flags
;
2951 VkResult
anv_image_create(VkDevice _device
,
2952 const struct anv_image_create_info
*info
,
2953 const VkAllocationCallbacks
* alloc
,
2957 VkResult
anv_image_from_gralloc(VkDevice device_h
,
2958 const VkImageCreateInfo
*base_info
,
2959 const VkNativeBufferANDROID
*gralloc_info
,
2960 const VkAllocationCallbacks
*alloc
,
2964 const struct anv_surface
*
2965 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
2966 VkImageAspectFlags aspect_mask
);
2969 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
2971 static inline struct VkExtent3D
2972 anv_sanitize_image_extent(const VkImageType imageType
,
2973 const struct VkExtent3D imageExtent
)
2975 switch (imageType
) {
2976 case VK_IMAGE_TYPE_1D
:
2977 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2978 case VK_IMAGE_TYPE_2D
:
2979 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2980 case VK_IMAGE_TYPE_3D
:
2983 unreachable("invalid image type");
2987 static inline struct VkOffset3D
2988 anv_sanitize_image_offset(const VkImageType imageType
,
2989 const struct VkOffset3D imageOffset
)
2991 switch (imageType
) {
2992 case VK_IMAGE_TYPE_1D
:
2993 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2994 case VK_IMAGE_TYPE_2D
:
2995 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2996 case VK_IMAGE_TYPE_3D
:
2999 unreachable("invalid image type");
3004 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3005 struct anv_state state
,
3006 enum isl_format format
,
3007 struct anv_address address
,
3008 uint32_t range
, uint32_t stride
);
3011 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3012 const struct anv_attachment_state
*att_state
,
3013 const struct anv_image_view
*iview
)
3015 const struct isl_format_layout
*view_fmtl
=
3016 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3018 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3019 if (view_fmtl->channels.c.bits) \
3020 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3022 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3023 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3024 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3025 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3027 #undef COPY_CLEAR_COLOR_CHANNEL
3031 struct anv_ycbcr_conversion
{
3032 const struct anv_format
* format
;
3033 VkSamplerYcbcrModelConversion ycbcr_model
;
3034 VkSamplerYcbcrRange ycbcr_range
;
3035 VkComponentSwizzle mapping
[4];
3036 VkChromaLocation chroma_offsets
[2];
3037 VkFilter chroma_filter
;
3038 bool chroma_reconstruction
;
3041 struct anv_sampler
{
3042 uint32_t state
[3][4];
3044 struct anv_ycbcr_conversion
*conversion
;
3047 struct anv_framebuffer
{
3052 uint32_t attachment_count
;
3053 struct anv_image_view
* attachments
[0];
3056 struct anv_subpass_attachment
{
3057 VkImageUsageFlagBits usage
;
3058 uint32_t attachment
;
3059 VkImageLayout layout
;
3062 struct anv_subpass
{
3063 uint32_t attachment_count
;
3066 * A pointer to all attachment references used in this subpass.
3067 * Only valid if ::attachment_count > 0.
3069 struct anv_subpass_attachment
* attachments
;
3070 uint32_t input_count
;
3071 struct anv_subpass_attachment
* input_attachments
;
3072 uint32_t color_count
;
3073 struct anv_subpass_attachment
* color_attachments
;
3074 struct anv_subpass_attachment
* resolve_attachments
;
3076 struct anv_subpass_attachment depth_stencil_attachment
;
3080 /** Subpass has a depth/stencil self-dependency */
3081 bool has_ds_self_dep
;
3083 /** Subpass has at least one resolve attachment */
3087 static inline unsigned
3088 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3090 return MAX2(1, _mesa_bitcount(subpass
->view_mask
));
3093 struct anv_render_pass_attachment
{
3094 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3095 * its members individually.
3099 VkImageUsageFlags usage
;
3100 VkAttachmentLoadOp load_op
;
3101 VkAttachmentStoreOp store_op
;
3102 VkAttachmentLoadOp stencil_load_op
;
3103 VkImageLayout initial_layout
;
3104 VkImageLayout final_layout
;
3105 VkImageLayout first_subpass_layout
;
3107 /* The subpass id in which the attachment will be used last. */
3108 uint32_t last_subpass_idx
;
3111 struct anv_render_pass
{
3112 uint32_t attachment_count
;
3113 uint32_t subpass_count
;
3114 /* An array of subpass_count+1 flushes, one per subpass boundary */
3115 enum anv_pipe_bits
* subpass_flushes
;
3116 struct anv_render_pass_attachment
* attachments
;
3117 struct anv_subpass subpasses
[0];
3120 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3122 struct anv_query_pool
{
3124 VkQueryPipelineStatisticFlags pipeline_statistics
;
3125 /** Stride between slots, in bytes */
3127 /** Number of slots in this query pool */
3132 int anv_get_entrypoint_index(const char *name
);
3135 anv_entrypoint_is_enabled(int index
, uint32_t core_version
,
3136 const struct anv_instance_extension_table
*instance
,
3137 const struct anv_device_extension_table
*device
);
3139 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3142 void anv_dump_image_to_ppm(struct anv_device
*device
,
3143 struct anv_image
*image
, unsigned miplevel
,
3144 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3145 const char *filename
);
3147 enum anv_dump_action
{
3148 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3151 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3152 void anv_dump_finish(void);
3154 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
3155 struct anv_framebuffer
*fb
);
3157 static inline uint32_t
3158 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3160 /* This function must be called from within a subpass. */
3161 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3163 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3165 /* The id of this subpass shouldn't exceed the number of subpasses in this
3166 * render pass minus 1.
3168 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3172 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3174 static inline struct __anv_type * \
3175 __anv_type ## _from_handle(__VkType _handle) \
3177 return (struct __anv_type *) _handle; \
3180 static inline __VkType \
3181 __anv_type ## _to_handle(struct __anv_type *_obj) \
3183 return (__VkType) _obj; \
3186 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3188 static inline struct __anv_type * \
3189 __anv_type ## _from_handle(__VkType _handle) \
3191 return (struct __anv_type *)(uintptr_t) _handle; \
3194 static inline __VkType \
3195 __anv_type ## _to_handle(struct __anv_type *_obj) \
3197 return (__VkType)(uintptr_t) _obj; \
3200 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3201 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3203 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3204 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3205 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3206 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3207 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3209 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3210 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3211 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3212 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3213 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3214 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3215 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
3216 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3217 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3218 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3219 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3220 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3221 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3222 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3223 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3224 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3225 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3226 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3227 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3228 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3229 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3230 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3231 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3233 /* Gen-specific function declarations */
3235 # include "anv_genX.h"
3237 # define genX(x) gen7_##x
3238 # include "anv_genX.h"
3240 # define genX(x) gen75_##x
3241 # include "anv_genX.h"
3243 # define genX(x) gen8_##x
3244 # include "anv_genX.h"
3246 # define genX(x) gen9_##x
3247 # include "anv_genX.h"
3249 # define genX(x) gen10_##x
3250 # include "anv_genX.h"
3252 # define genX(x) gen11_##x
3253 # include "anv_genX.h"
3257 #endif /* ANV_PRIVATE_H */