2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "compiler/brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_atomic.h"
50 #include "util/u_vector.h"
53 /* Pre-declarations needed for WSI entrypoints */
56 typedef struct xcb_connection_t xcb_connection_t
;
57 typedef uint32_t xcb_visualid_t
;
58 typedef uint32_t xcb_window_t
;
61 struct anv_buffer_view
;
62 struct anv_image_view
;
66 #include <vulkan/vulkan.h>
67 #include <vulkan/vulkan_intel.h>
68 #include <vulkan/vk_icd.h>
70 #include "anv_entrypoints.h"
73 #include "common/gen_debug.h"
74 #include "wsi_common.h"
76 /* Allowing different clear colors requires us to perform a depth resolve at
77 * the end of certain render passes. This is because while slow clears store
78 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
79 * See the PRMs for examples describing when additional resolves would be
80 * necessary. To enable fast clears without requiring extra resolves, we set
81 * the clear value to a globally-defined one. We could allow different values
82 * if the user doesn't expect coherent data during or after a render passes
83 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
84 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
85 * 1.0f seems to be the only value used. The only application that doesn't set
86 * this value does so through the usage of an seemingly uninitialized clear
89 #define ANV_HZ_FC_VAL 1.0f
94 #define MAX_VIEWPORTS 16
95 #define MAX_SCISSORS 16
96 #define MAX_PUSH_CONSTANTS_SIZE 128
97 #define MAX_DYNAMIC_BUFFERS 16
99 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
101 #define ANV_SVGS_VB_INDEX MAX_VBS
102 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
104 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
106 static inline uint32_t
107 align_down_npot_u32(uint32_t v
, uint32_t a
)
112 static inline uint32_t
113 align_u32(uint32_t v
, uint32_t a
)
115 assert(a
!= 0 && a
== (a
& -a
));
116 return (v
+ a
- 1) & ~(a
- 1);
119 static inline uint64_t
120 align_u64(uint64_t v
, uint64_t a
)
122 assert(a
!= 0 && a
== (a
& -a
));
123 return (v
+ a
- 1) & ~(a
- 1);
126 static inline int32_t
127 align_i32(int32_t v
, int32_t a
)
129 assert(a
!= 0 && a
== (a
& -a
));
130 return (v
+ a
- 1) & ~(a
- 1);
133 /** Alignment must be a power of 2. */
135 anv_is_aligned(uintmax_t n
, uintmax_t a
)
137 assert(a
== (a
& -a
));
138 return (n
& (a
- 1)) == 0;
141 static inline uint32_t
142 anv_minify(uint32_t n
, uint32_t levels
)
144 if (unlikely(n
== 0))
147 return MAX2(n
>> levels
, 1);
151 anv_clamp_f(float f
, float min
, float max
)
164 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
166 if (*inout_mask
& clear_mask
) {
167 *inout_mask
&= ~clear_mask
;
174 static inline union isl_color_value
175 vk_to_isl_color(VkClearColorValue color
)
177 return (union isl_color_value
) {
187 #define for_each_bit(b, dword) \
188 for (uint32_t __dword = (dword); \
189 (b) = __builtin_ffs(__dword) - 1, __dword; \
190 __dword &= ~(1 << (b)))
192 #define typed_memcpy(dest, src, count) ({ \
193 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
194 memcpy((dest), (src), (count) * sizeof(*(src))); \
197 /* Whenever we generate an error, pass it through this function. Useful for
198 * debugging, where we can break on it. Only call at error site, not when
199 * propagating errors. Might be useful to plug in a stack trace here.
202 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
205 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
206 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
207 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
209 #define vk_error(error) error
210 #define vk_errorf(error, format, ...) error
211 #define anv_debug(format, ...)
215 * Warn on ignored extension structs.
217 * The Vulkan spec requires us to ignore unsupported or unknown structs in
218 * a pNext chain. In debug mode, emitting warnings for ignored structs may
219 * help us discover structs that we should not have ignored.
222 * From the Vulkan 1.0.38 spec:
224 * Any component of the implementation (the loader, any enabled layers,
225 * and drivers) must skip over, without processing (other than reading the
226 * sType and pNext members) any chained structures with sType values not
227 * defined by extensions supported by that component.
229 #define anv_debug_ignored_stype(sType) \
230 anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType))
232 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
233 anv_printflike(3, 4);
234 void __anv_perf_warn(const char *file
, int line
, const char *format
, ...)
235 anv_printflike(3, 4);
236 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
237 void anv_loge_v(const char *format
, va_list va
);
240 * Print a FINISHME message, including its source location.
242 #define anv_finishme(format, ...) \
244 static bool reported = false; \
246 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
252 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
254 #define anv_perf_warn(format, ...) \
256 static bool reported = false; \
257 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
258 __anv_perf_warn(__FILE__, __LINE__, format, ##__VA_ARGS__); \
263 /* A non-fatal assert. Useful for debugging. */
265 #define anv_assert(x) ({ \
266 if (unlikely(!(x))) \
267 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
270 #define anv_assert(x)
273 /* A multi-pointer allocator
275 * When copying data structures from the user (such as a render pass), it's
276 * common to need to allocate data for a bunch of different things. Instead
277 * of doing several allocations and having to handle all of the error checking
278 * that entails, it can be easier to do a single allocation. This struct
279 * helps facilitate that. The intended usage looks like this:
282 * anv_multialloc_add(&ma, &main_ptr, 1);
283 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
284 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
286 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
287 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
289 struct anv_multialloc
{
297 #define ANV_MULTIALLOC_INIT \
298 ((struct anv_multialloc) { 0, })
300 #define ANV_MULTIALLOC(_name) \
301 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
303 __attribute__((always_inline
))
305 _anv_multialloc_add(struct anv_multialloc
*ma
,
306 void **ptr
, size_t size
, size_t align
)
308 size_t offset
= align_u64(ma
->size
, align
);
309 ma
->size
= offset
+ size
;
310 ma
->align
= MAX2(ma
->align
, align
);
312 /* Store the offset in the pointer. */
313 *ptr
= (void *)(uintptr_t)offset
;
315 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
316 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
319 #define anv_multialloc_add(_ma, _ptr, _count) \
320 _anv_multialloc_add((_ma), (void **)(_ptr), \
321 (_count) * sizeof(**(_ptr)), __alignof__(**(_ptr)))
323 __attribute__((always_inline
))
325 anv_multialloc_alloc(struct anv_multialloc
*ma
,
326 const VkAllocationCallbacks
*alloc
,
327 VkSystemAllocationScope scope
)
329 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
333 /* Fill out each of the pointers with their final value.
335 * for (uint32_t i = 0; i < ma->ptr_count; i++)
336 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
338 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
339 * constant, GCC is incapable of figuring this out and unrolling the loop
340 * so we have to give it a little help.
342 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
343 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
344 if ((_i) < ma->ptr_count) \
345 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
346 _ANV_MULTIALLOC_UPDATE_POINTER(0);
347 _ANV_MULTIALLOC_UPDATE_POINTER(1);
348 _ANV_MULTIALLOC_UPDATE_POINTER(2);
349 _ANV_MULTIALLOC_UPDATE_POINTER(3);
350 _ANV_MULTIALLOC_UPDATE_POINTER(4);
351 _ANV_MULTIALLOC_UPDATE_POINTER(5);
352 _ANV_MULTIALLOC_UPDATE_POINTER(6);
353 _ANV_MULTIALLOC_UPDATE_POINTER(7);
354 #undef _ANV_MULTIALLOC_UPDATE_POINTER
359 __attribute__((always_inline
))
361 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
362 const VkAllocationCallbacks
*parent_alloc
,
363 const VkAllocationCallbacks
*alloc
,
364 VkSystemAllocationScope scope
)
366 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
370 * A dynamically growable, circular buffer. Elements are added at head and
371 * removed from tail. head and tail are free-running uint32_t indices and we
372 * only compute the modulo with size when accessing the array. This way,
373 * number of bytes in the queue is always head - tail, even in case of
380 /* Index into the current validation list. This is used by the
381 * validation list building alrogithm to track which buffers are already
382 * in the validation list so that we can ensure uniqueness.
386 /* Last known offset. This value is provided by the kernel when we
387 * execbuf and is used as the presumed offset for the next bunch of
395 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
400 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
402 bo
->gem_handle
= gem_handle
;
410 /* Represents a lock-free linked list of "free" things. This is used by
411 * both the block pool and the state pools. Unfortunately, in order to
412 * solve the ABA problem, we can't use a single uint32_t head.
414 union anv_free_list
{
418 /* A simple count that is incremented every time the head changes. */
424 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
426 struct anv_block_state
{
436 struct anv_block_pool
{
437 struct anv_device
*device
;
441 /* The offset from the start of the bo to the "center" of the block
442 * pool. Pointers to allocated blocks are given by
443 * bo.map + center_bo_offset + offsets.
445 uint32_t center_bo_offset
;
447 /* Current memory map of the block pool. This pointer may or may not
448 * point to the actual beginning of the block pool memory. If
449 * anv_block_pool_alloc_back has ever been called, then this pointer
450 * will point to the "center" position of the buffer and all offsets
451 * (negative or positive) given out by the block pool alloc functions
452 * will be valid relative to this pointer.
454 * In particular, map == bo.map + center_offset
460 * Array of mmaps and gem handles owned by the block pool, reclaimed when
461 * the block pool is destroyed.
463 struct u_vector mmap_cleanups
;
465 struct anv_block_state state
;
467 struct anv_block_state back_state
;
470 /* Block pools are backed by a fixed-size 1GB memfd */
471 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
473 /* The center of the block pool is also the middle of the memfd. This may
474 * change in the future if we decide differently for some reason.
476 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
478 static inline uint32_t
479 anv_block_pool_size(struct anv_block_pool
*pool
)
481 return pool
->state
.end
+ pool
->back_state
.end
;
490 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
492 struct anv_fixed_size_state_pool
{
493 union anv_free_list free_list
;
494 struct anv_block_state block
;
497 #define ANV_MIN_STATE_SIZE_LOG2 6
498 #define ANV_MAX_STATE_SIZE_LOG2 20
500 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
502 struct anv_state_pool
{
503 struct anv_block_pool block_pool
;
505 /* The size of blocks which will be allocated from the block pool */
508 /** Free list for "back" allocations */
509 union anv_free_list back_alloc_free_list
;
511 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
514 struct anv_state_stream_block
;
516 struct anv_state_stream
{
517 struct anv_state_pool
*state_pool
;
519 /* The size of blocks to allocate from the state pool */
522 /* Current block we're allocating from */
523 struct anv_state block
;
525 /* Offset into the current block at which to allocate the next state */
528 /* List of all blocks allocated from this pool */
529 struct anv_state_stream_block
*block_list
;
532 #define CACHELINE_SIZE 64
533 #define CACHELINE_MASK 63
536 anv_clflush_range(void *start
, size_t size
)
538 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
539 void *end
= start
+ size
;
542 __builtin_ia32_clflush(p
);
548 anv_flush_range(void *start
, size_t size
)
550 __builtin_ia32_mfence();
551 anv_clflush_range(start
, size
);
555 anv_invalidate_range(void *start
, size_t size
)
557 anv_clflush_range(start
, size
);
558 __builtin_ia32_mfence();
561 /* The block_pool functions exported for testing only. The block pool should
562 * only be used via a state pool (see below).
564 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
565 struct anv_device
*device
,
566 uint32_t initial_size
);
567 void anv_block_pool_finish(struct anv_block_pool
*pool
);
568 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
569 uint32_t block_size
);
570 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
571 uint32_t block_size
);
573 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
574 struct anv_device
*device
,
575 uint32_t block_size
);
576 void anv_state_pool_finish(struct anv_state_pool
*pool
);
577 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
578 uint32_t state_size
, uint32_t alignment
);
579 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
580 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
581 void anv_state_stream_init(struct anv_state_stream
*stream
,
582 struct anv_state_pool
*state_pool
,
583 uint32_t block_size
);
584 void anv_state_stream_finish(struct anv_state_stream
*stream
);
585 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
586 uint32_t size
, uint32_t alignment
);
589 * Implements a pool of re-usable BOs. The interface is identical to that
590 * of block_pool except that each block is its own BO.
593 struct anv_device
*device
;
598 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
599 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
600 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
602 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
604 struct anv_scratch_bo
{
609 struct anv_scratch_pool
{
610 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
611 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
614 void anv_scratch_pool_init(struct anv_device
*device
,
615 struct anv_scratch_pool
*pool
);
616 void anv_scratch_pool_finish(struct anv_device
*device
,
617 struct anv_scratch_pool
*pool
);
618 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
619 struct anv_scratch_pool
*pool
,
620 gl_shader_stage stage
,
621 unsigned per_thread_scratch
);
623 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
624 struct anv_bo_cache
{
625 struct hash_table
*bo_map
;
626 pthread_mutex_t mutex
;
629 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
630 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
631 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
632 struct anv_bo_cache
*cache
,
633 uint64_t size
, struct anv_bo
**bo
);
634 VkResult
anv_bo_cache_import(struct anv_device
*device
,
635 struct anv_bo_cache
*cache
,
636 int fd
, uint64_t size
, struct anv_bo
**bo
);
637 VkResult
anv_bo_cache_export(struct anv_device
*device
,
638 struct anv_bo_cache
*cache
,
639 struct anv_bo
*bo_in
, int *fd_out
);
640 void anv_bo_cache_release(struct anv_device
*device
,
641 struct anv_bo_cache
*cache
,
644 struct anv_memory_type
{
645 /* Standard bits passed on to the client */
646 VkMemoryPropertyFlags propertyFlags
;
649 /* Driver-internal book-keeping */
650 VkBufferUsageFlags valid_buffer_usage
;
653 struct anv_memory_heap
{
654 /* Standard bits passed on to the client */
656 VkMemoryHeapFlags flags
;
658 /* Driver-internal book-keeping */
659 bool supports_48bit_addresses
;
662 struct anv_physical_device
{
663 VK_LOADER_DATA _loader_data
;
665 struct anv_instance
* instance
;
669 struct gen_device_info info
;
670 /** Amount of "GPU memory" we want to advertise
672 * Clearly, this value is bogus since Intel is a UMA architecture. On
673 * gen7 platforms, we are limited by GTT size unless we want to implement
674 * fine-grained tracking and GTT splitting. On Broadwell and above we are
675 * practically unlimited. However, we will never report more than 3/4 of
676 * the total system ram to try and avoid running out of RAM.
678 bool supports_48bit_addresses
;
679 struct brw_compiler
* compiler
;
680 struct isl_device isl_dev
;
681 int cmd_parser_version
;
685 uint32_t subslice_total
;
689 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
691 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
694 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
695 uint8_t driver_uuid
[VK_UUID_SIZE
];
696 uint8_t device_uuid
[VK_UUID_SIZE
];
698 struct wsi_device wsi_device
;
702 struct anv_instance
{
703 VK_LOADER_DATA _loader_data
;
705 VkAllocationCallbacks alloc
;
708 int physicalDeviceCount
;
709 struct anv_physical_device physicalDevice
;
712 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
713 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
716 VK_LOADER_DATA _loader_data
;
718 struct anv_device
* device
;
720 struct anv_state_pool
* pool
;
723 struct anv_pipeline_cache
{
724 struct anv_device
* device
;
725 pthread_mutex_t mutex
;
727 struct hash_table
* cache
;
730 struct anv_pipeline_bind_map
;
732 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
733 struct anv_device
*device
,
735 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
737 struct anv_shader_bin
*
738 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
739 const void *key
, uint32_t key_size
);
740 struct anv_shader_bin
*
741 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
742 const void *key_data
, uint32_t key_size
,
743 const void *kernel_data
, uint32_t kernel_size
,
744 const struct brw_stage_prog_data
*prog_data
,
745 uint32_t prog_data_size
,
746 const struct anv_pipeline_bind_map
*bind_map
);
749 VK_LOADER_DATA _loader_data
;
751 VkAllocationCallbacks alloc
;
753 struct anv_instance
* instance
;
755 struct gen_device_info info
;
756 struct isl_device isl_dev
;
759 bool can_chain_batches
;
760 bool robust_buffer_access
;
762 struct anv_bo_pool batch_bo_pool
;
764 struct anv_bo_cache bo_cache
;
766 struct anv_state_pool dynamic_state_pool
;
767 struct anv_state_pool instruction_state_pool
;
768 struct anv_state_pool surface_state_pool
;
770 struct anv_bo workaround_bo
;
772 struct anv_pipeline_cache blorp_shader_cache
;
773 struct blorp_context blorp
;
775 struct anv_state border_colors
;
777 struct anv_queue queue
;
779 struct anv_scratch_pool scratch_pool
;
781 uint32_t default_mocs
;
783 pthread_mutex_t mutex
;
784 pthread_cond_t queue_submit
;
789 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
791 if (device
->info
.has_llc
)
794 anv_flush_range(state
.map
, state
.alloc_size
);
797 void anv_device_init_blorp(struct anv_device
*device
);
798 void anv_device_finish_blorp(struct anv_device
*device
);
800 VkResult
anv_device_execbuf(struct anv_device
*device
,
801 struct drm_i915_gem_execbuffer2
*execbuf
,
802 struct anv_bo
**execbuf_bos
);
803 VkResult
anv_device_query_status(struct anv_device
*device
);
804 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
805 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
808 void* anv_gem_mmap(struct anv_device
*device
,
809 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
810 void anv_gem_munmap(void *p
, uint64_t size
);
811 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
812 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
813 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
814 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
815 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
816 int anv_gem_execbuffer(struct anv_device
*device
,
817 struct drm_i915_gem_execbuffer2
*execbuf
);
818 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
819 uint32_t stride
, uint32_t tiling
);
820 int anv_gem_create_context(struct anv_device
*device
);
821 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
822 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
824 int anv_gem_get_param(int fd
, uint32_t param
);
825 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
826 int anv_gem_get_aperture(int fd
, uint64_t *size
);
827 bool anv_gem_supports_48b_addresses(int fd
);
828 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
829 uint32_t *active
, uint32_t *pending
);
830 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
831 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
832 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
833 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
834 uint32_t read_domains
, uint32_t write_domain
);
836 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
838 struct anv_reloc_list
{
840 uint32_t array_length
;
841 struct drm_i915_gem_relocation_entry
* relocs
;
842 struct anv_bo
** reloc_bos
;
845 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
846 const VkAllocationCallbacks
*alloc
);
847 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
848 const VkAllocationCallbacks
*alloc
);
850 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
851 const VkAllocationCallbacks
*alloc
,
852 uint32_t offset
, struct anv_bo
*target_bo
,
855 struct anv_batch_bo
{
856 /* Link in the anv_cmd_buffer.owned_batch_bos list */
857 struct list_head link
;
861 /* Bytes actually consumed in this batch BO */
864 struct anv_reloc_list relocs
;
868 const VkAllocationCallbacks
* alloc
;
874 struct anv_reloc_list
* relocs
;
876 /* This callback is called (with the associated user data) in the event
877 * that the batch runs out of space.
879 VkResult (*extend_cb
)(struct anv_batch
*, void *);
883 * Current error status of the command buffer. Used to track inconsistent
884 * or incomplete command buffer states that are the consequence of run-time
885 * errors such as out of memory scenarios. We want to track this in the
886 * batch because the command buffer object is not visible to some parts
892 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
893 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
894 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
895 void *location
, struct anv_bo
*bo
, uint32_t offset
);
896 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
897 struct anv_batch
*batch
);
899 static inline VkResult
900 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
902 assert(error
!= VK_SUCCESS
);
903 if (batch
->status
== VK_SUCCESS
)
904 batch
->status
= error
;
905 return batch
->status
;
909 anv_batch_has_error(struct anv_batch
*batch
)
911 return batch
->status
!= VK_SUCCESS
;
919 static inline uint64_t
920 _anv_combine_address(struct anv_batch
*batch
, void *location
,
921 const struct anv_address address
, uint32_t delta
)
923 if (address
.bo
== NULL
) {
924 return address
.offset
+ delta
;
926 assert(batch
->start
<= location
&& location
< batch
->end
);
928 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
932 #define __gen_address_type struct anv_address
933 #define __gen_user_data struct anv_batch
934 #define __gen_combine_address _anv_combine_address
936 /* Wrapper macros needed to work around preprocessor argument issues. In
937 * particular, arguments don't get pre-evaluated if they are concatenated.
938 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
939 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
940 * We can work around this easily enough with these helpers.
942 #define __anv_cmd_length(cmd) cmd ## _length
943 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
944 #define __anv_cmd_header(cmd) cmd ## _header
945 #define __anv_cmd_pack(cmd) cmd ## _pack
946 #define __anv_reg_num(reg) reg ## _num
948 #define anv_pack_struct(dst, struc, ...) do { \
949 struct struc __template = { \
952 __anv_cmd_pack(struc)(NULL, dst, &__template); \
953 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
956 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
957 void *__dst = anv_batch_emit_dwords(batch, n); \
959 struct cmd __template = { \
960 __anv_cmd_header(cmd), \
961 .DWordLength = n - __anv_cmd_length_bias(cmd), \
964 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
969 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
973 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
974 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
977 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
978 dw[i] = (dwords0)[i] | (dwords1)[i]; \
979 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
982 #define anv_batch_emit(batch, cmd, name) \
983 for (struct cmd name = { __anv_cmd_header(cmd) }, \
984 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
985 __builtin_expect(_dst != NULL, 1); \
986 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
987 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
991 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
992 .GraphicsDataTypeGFDT = 0, \
993 .LLCCacheabilityControlLLCCC = 0, \
994 .L3CacheabilityControlL3CC = 1, \
997 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
998 .LLCeLLCCacheabilityControlLLCCC = 0, \
999 .L3CacheabilityControlL3CC = 1, \
1002 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1003 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1004 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1005 .AgeforQUADLRU = 0 \
1008 /* Skylake: MOCS is now an index into an array of 62 different caching
1009 * configurations programmed by the kernel.
1012 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1013 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1014 .IndextoMOCSTables = 2 \
1017 #define GEN9_MOCS_PTE { \
1018 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1019 .IndextoMOCSTables = 1 \
1022 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1023 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1024 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1025 .IndextoMOCSTables = 2 \
1028 #define GEN10_MOCS_PTE { \
1029 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1030 .IndextoMOCSTables = 1 \
1033 struct anv_device_memory
{
1035 struct anv_memory_type
* type
;
1036 VkDeviceSize map_size
;
1041 * Header for Vertex URB Entry (VUE)
1043 struct anv_vue_header
{
1045 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1046 uint32_t ViewportIndex
;
1050 struct anv_descriptor_set_binding_layout
{
1052 /* The type of the descriptors in this binding */
1053 VkDescriptorType type
;
1056 /* Number of array elements in this binding */
1057 uint16_t array_size
;
1059 /* Index into the flattend descriptor set */
1060 uint16_t descriptor_index
;
1062 /* Index into the dynamic state array for a dynamic buffer */
1063 int16_t dynamic_offset_index
;
1065 /* Index into the descriptor set buffer views */
1066 int16_t buffer_index
;
1069 /* Index into the binding table for the associated surface */
1070 int16_t surface_index
;
1072 /* Index into the sampler table for the associated sampler */
1073 int16_t sampler_index
;
1075 /* Index into the image table for the associated image */
1076 int16_t image_index
;
1077 } stage
[MESA_SHADER_STAGES
];
1079 /* Immutable samplers (or NULL if no immutable samplers) */
1080 struct anv_sampler
**immutable_samplers
;
1083 struct anv_descriptor_set_layout
{
1084 /* Number of bindings in this descriptor set */
1085 uint16_t binding_count
;
1087 /* Total size of the descriptor set with room for all array entries */
1090 /* Shader stages affected by this descriptor set */
1091 uint16_t shader_stages
;
1093 /* Number of buffers in this descriptor set */
1094 uint16_t buffer_count
;
1096 /* Number of dynamic offsets used by this descriptor set */
1097 uint16_t dynamic_offset_count
;
1099 /* Bindings in this descriptor set */
1100 struct anv_descriptor_set_binding_layout binding
[0];
1103 struct anv_descriptor
{
1104 VkDescriptorType type
;
1108 struct anv_image_view
*image_view
;
1109 struct anv_sampler
*sampler
;
1111 /* Used to determine whether or not we need the surface state to have
1112 * the auxiliary buffer enabled.
1114 enum isl_aux_usage aux_usage
;
1118 struct anv_buffer
*buffer
;
1123 struct anv_buffer_view
*buffer_view
;
1127 struct anv_descriptor_set
{
1128 const struct anv_descriptor_set_layout
*layout
;
1130 uint32_t buffer_count
;
1131 struct anv_buffer_view
*buffer_views
;
1132 struct anv_descriptor descriptors
[0];
1135 struct anv_buffer_view
{
1136 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1138 uint32_t offset
; /**< Offset into bo. */
1139 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1141 struct anv_state surface_state
;
1142 struct anv_state storage_surface_state
;
1143 struct anv_state writeonly_storage_surface_state
;
1145 struct brw_image_param storage_image_param
;
1148 struct anv_push_descriptor_set
{
1149 struct anv_descriptor_set set
;
1151 /* Put this field right behind anv_descriptor_set so it fills up the
1152 * descriptors[0] field. */
1153 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1155 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1158 struct anv_descriptor_pool
{
1163 struct anv_state_stream surface_state_stream
;
1164 void *surface_state_free_list
;
1169 enum anv_descriptor_template_entry_type
{
1170 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1171 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1172 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1175 struct anv_descriptor_template_entry
{
1176 /* The type of descriptor in this entry */
1177 VkDescriptorType type
;
1179 /* Binding in the descriptor set */
1182 /* Offset at which to write into the descriptor set binding */
1183 uint32_t array_element
;
1185 /* Number of elements to write into the descriptor set binding */
1186 uint32_t array_count
;
1188 /* Offset into the user provided data */
1191 /* Stride between elements into the user provided data */
1195 struct anv_descriptor_update_template
{
1196 /* The descriptor set this template corresponds to. This value is only
1197 * valid if the template was created with the templateType
1198 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1202 /* Number of entries in this template */
1203 uint32_t entry_count
;
1205 /* Entries of the template */
1206 struct anv_descriptor_template_entry entries
[0];
1210 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1213 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1214 const struct gen_device_info
* const devinfo
,
1215 const VkDescriptorImageInfo
* const info
,
1216 VkDescriptorType type
,
1221 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1222 VkDescriptorType type
,
1223 struct anv_buffer_view
*buffer_view
,
1228 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1229 struct anv_device
*device
,
1230 struct anv_state_stream
*alloc_stream
,
1231 VkDescriptorType type
,
1232 struct anv_buffer
*buffer
,
1235 VkDeviceSize offset
,
1236 VkDeviceSize range
);
1239 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1240 struct anv_device
*device
,
1241 struct anv_state_stream
*alloc_stream
,
1242 const struct anv_descriptor_update_template
*template,
1246 anv_descriptor_set_create(struct anv_device
*device
,
1247 struct anv_descriptor_pool
*pool
,
1248 const struct anv_descriptor_set_layout
*layout
,
1249 struct anv_descriptor_set
**out_set
);
1252 anv_descriptor_set_destroy(struct anv_device
*device
,
1253 struct anv_descriptor_pool
*pool
,
1254 struct anv_descriptor_set
*set
);
1256 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1258 struct anv_pipeline_binding
{
1259 /* The descriptor set this surface corresponds to. The special value of
1260 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1261 * to a color attachment and not a regular descriptor.
1265 /* Binding in the descriptor set */
1268 /* Index in the binding */
1271 /* Input attachment index (relative to the subpass) */
1272 uint8_t input_attachment_index
;
1274 /* For a storage image, whether it is write-only */
1278 struct anv_pipeline_layout
{
1280 struct anv_descriptor_set_layout
*layout
;
1281 uint32_t dynamic_offset_start
;
1287 bool has_dynamic_offsets
;
1288 } stage
[MESA_SHADER_STAGES
];
1290 unsigned char sha1
[20];
1294 struct anv_device
* device
;
1297 VkBufferUsageFlags usage
;
1299 /* Set when bound */
1301 VkDeviceSize offset
;
1304 static inline uint64_t
1305 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1307 assert(offset
<= buffer
->size
);
1308 if (range
== VK_WHOLE_SIZE
) {
1309 return buffer
->size
- offset
;
1311 assert(range
<= buffer
->size
);
1316 enum anv_cmd_dirty_bits
{
1317 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1318 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1319 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1320 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1321 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1322 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1323 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1324 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1325 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1326 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1327 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1328 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1329 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1331 typedef uint32_t anv_cmd_dirty_mask_t
;
1333 enum anv_pipe_bits
{
1334 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1335 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1336 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1337 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1338 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1339 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1340 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1341 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1342 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1343 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1344 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1346 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1347 * a flush has happened but not a CS stall. The next time we do any sort
1348 * of invalidation we need to insert a CS stall at that time. Otherwise,
1349 * we would have to CS stall on every flush which could be bad.
1351 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1354 #define ANV_PIPE_FLUSH_BITS ( \
1355 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1356 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1357 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1359 #define ANV_PIPE_STALL_BITS ( \
1360 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1361 ANV_PIPE_DEPTH_STALL_BIT | \
1362 ANV_PIPE_CS_STALL_BIT)
1364 #define ANV_PIPE_INVALIDATE_BITS ( \
1365 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1366 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1367 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1368 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1369 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1370 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1372 static inline enum anv_pipe_bits
1373 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1375 enum anv_pipe_bits pipe_bits
= 0;
1378 for_each_bit(b
, flags
) {
1379 switch ((VkAccessFlagBits
)(1 << b
)) {
1380 case VK_ACCESS_SHADER_WRITE_BIT
:
1381 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1383 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1384 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1386 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1387 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1389 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1390 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1391 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1394 break; /* Nothing to do */
1401 static inline enum anv_pipe_bits
1402 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1404 enum anv_pipe_bits pipe_bits
= 0;
1407 for_each_bit(b
, flags
) {
1408 switch ((VkAccessFlagBits
)(1 << b
)) {
1409 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1410 case VK_ACCESS_INDEX_READ_BIT
:
1411 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1412 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1414 case VK_ACCESS_UNIFORM_READ_BIT
:
1415 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1416 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1418 case VK_ACCESS_SHADER_READ_BIT
:
1419 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1420 case VK_ACCESS_TRANSFER_READ_BIT
:
1421 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1424 break; /* Nothing to do */
1431 struct anv_vertex_binding
{
1432 struct anv_buffer
* buffer
;
1433 VkDeviceSize offset
;
1436 struct anv_push_constants
{
1437 /* Current allocated size of this push constants data structure.
1438 * Because a decent chunk of it may not be used (images on SKL, for
1439 * instance), we won't actually allocate the entire structure up-front.
1443 /* Push constant data provided by the client through vkPushConstants */
1444 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1446 /* Our hardware only provides zero-based vertex and instance id so, in
1447 * order to satisfy the vulkan requirements, we may have to push one or
1448 * both of these into the shader.
1450 uint32_t base_vertex
;
1451 uint32_t base_instance
;
1453 /* Image data for image_load_store on pre-SKL */
1454 struct brw_image_param images
[MAX_IMAGES
];
1457 struct anv_dynamic_state
{
1460 VkViewport viewports
[MAX_VIEWPORTS
];
1465 VkRect2D scissors
[MAX_SCISSORS
];
1476 float blend_constants
[4];
1486 } stencil_compare_mask
;
1491 } stencil_write_mask
;
1496 } stencil_reference
;
1499 extern const struct anv_dynamic_state default_dynamic_state
;
1501 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1502 const struct anv_dynamic_state
*src
,
1503 uint32_t copy_mask
);
1506 * Attachment state when recording a renderpass instance.
1508 * The clear value is valid only if there exists a pending clear.
1510 struct anv_attachment_state
{
1511 enum isl_aux_usage aux_usage
;
1512 enum isl_aux_usage input_aux_usage
;
1513 struct anv_state color_rt_state
;
1514 struct anv_state input_att_state
;
1516 VkImageLayout current_layout
;
1517 VkImageAspectFlags pending_clear_aspects
;
1519 VkClearValue clear_value
;
1520 bool clear_color_is_zero_one
;
1523 /** State required while building cmd buffer */
1524 struct anv_cmd_state
{
1525 /* PIPELINE_SELECT.PipelineSelection */
1526 uint32_t current_pipeline
;
1527 const struct gen_l3_config
* current_l3_config
;
1529 anv_cmd_dirty_mask_t dirty
;
1530 anv_cmd_dirty_mask_t compute_dirty
;
1531 enum anv_pipe_bits pending_pipe_bits
;
1532 uint32_t num_workgroups_offset
;
1533 struct anv_bo
*num_workgroups_bo
;
1534 VkShaderStageFlags descriptors_dirty
;
1535 VkShaderStageFlags push_constants_dirty
;
1536 uint32_t scratch_size
;
1537 struct anv_pipeline
* pipeline
;
1538 struct anv_pipeline
* compute_pipeline
;
1539 struct anv_framebuffer
* framebuffer
;
1540 struct anv_render_pass
* pass
;
1541 struct anv_subpass
* subpass
;
1542 VkRect2D render_area
;
1543 uint32_t restart_index
;
1544 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1545 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1546 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
1547 VkShaderStageFlags push_constant_stages
;
1548 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1549 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1550 struct anv_state samplers
[MESA_SHADER_STAGES
];
1551 struct anv_dynamic_state dynamic
;
1554 struct anv_push_descriptor_set push_descriptor
;
1557 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1558 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1559 * and before invoking the secondary in ExecuteCommands.
1561 bool pma_fix_enabled
;
1564 * Whether or not we know for certain that HiZ is enabled for the current
1565 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1566 * enabled or not, this will be false.
1571 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1572 * valid only when recording a render pass instance.
1574 struct anv_attachment_state
* attachments
;
1577 * Surface states for color render targets. These are stored in a single
1578 * flat array. For depth-stencil attachments, the surface state is simply
1581 struct anv_state render_pass_states
;
1584 * A null surface state of the right size to match the framebuffer. This
1585 * is one of the states in render_pass_states.
1587 struct anv_state null_surface_state
;
1590 struct anv_buffer
* index_buffer
;
1591 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1592 uint32_t index_offset
;
1596 struct anv_cmd_pool
{
1597 VkAllocationCallbacks alloc
;
1598 struct list_head cmd_buffers
;
1601 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1603 enum anv_cmd_buffer_exec_mode
{
1604 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1605 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1606 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1607 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1608 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1611 struct anv_cmd_buffer
{
1612 VK_LOADER_DATA _loader_data
;
1614 struct anv_device
* device
;
1616 struct anv_cmd_pool
* pool
;
1617 struct list_head pool_link
;
1619 struct anv_batch batch
;
1621 /* Fields required for the actual chain of anv_batch_bo's.
1623 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1625 struct list_head batch_bos
;
1626 enum anv_cmd_buffer_exec_mode exec_mode
;
1628 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1629 * referenced by this command buffer
1631 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1633 struct u_vector seen_bbos
;
1635 /* A vector of int32_t's for every block of binding tables.
1637 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1639 struct u_vector bt_block_states
;
1642 struct anv_reloc_list surface_relocs
;
1643 /** Last seen surface state block pool center bo offset */
1644 uint32_t last_ss_pool_center
;
1646 /* Serial for tracking buffer completion */
1649 /* Stream objects for storing temporary data */
1650 struct anv_state_stream surface_state_stream
;
1651 struct anv_state_stream dynamic_state_stream
;
1653 VkCommandBufferUsageFlags usage_flags
;
1654 VkCommandBufferLevel level
;
1656 struct anv_cmd_state state
;
1659 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1660 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1661 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1662 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1663 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1664 struct anv_cmd_buffer
*secondary
);
1665 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1666 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1667 struct anv_cmd_buffer
*cmd_buffer
,
1668 const VkSemaphore
*in_semaphores
,
1669 uint32_t num_in_semaphores
,
1670 const VkSemaphore
*out_semaphores
,
1671 uint32_t num_out_semaphores
);
1673 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1676 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1677 gl_shader_stage stage
, uint32_t size
);
1678 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1679 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1680 (offsetof(struct anv_push_constants, field) + \
1681 sizeof(cmd_buffer->state.push_constants[0]->field)))
1683 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1684 const void *data
, uint32_t size
, uint32_t alignment
);
1685 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1686 uint32_t *a
, uint32_t *b
,
1687 uint32_t dwords
, uint32_t alignment
);
1690 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1692 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1693 uint32_t entries
, uint32_t *state_offset
);
1695 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1697 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1698 uint32_t size
, uint32_t alignment
);
1701 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1703 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1704 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1705 bool depth_clamp_enable
);
1706 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1708 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1709 struct anv_render_pass
*pass
,
1710 struct anv_framebuffer
*framebuffer
,
1711 const VkClearValue
*clear_values
);
1713 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1716 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1717 gl_shader_stage stage
);
1719 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1721 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1722 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1724 const struct anv_image_view
*
1725 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1728 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1729 uint32_t num_entries
,
1730 uint32_t *state_offset
,
1731 struct anv_state
*bt_state
);
1733 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1735 enum anv_fence_state
{
1736 /** Indicates that this is a new (or newly reset fence) */
1737 ANV_FENCE_STATE_RESET
,
1739 /** Indicates that this fence has been submitted to the GPU but is still
1740 * (as far as we know) in use by the GPU.
1742 ANV_FENCE_STATE_SUBMITTED
,
1744 ANV_FENCE_STATE_SIGNALED
,
1749 struct drm_i915_gem_execbuffer2 execbuf
;
1750 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1751 enum anv_fence_state state
;
1756 struct anv_state state
;
1759 enum anv_semaphore_type
{
1760 ANV_SEMAPHORE_TYPE_NONE
= 0,
1761 ANV_SEMAPHORE_TYPE_DUMMY
,
1762 ANV_SEMAPHORE_TYPE_BO
,
1765 struct anv_semaphore_impl
{
1766 enum anv_semaphore_type type
;
1768 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1769 * This BO will be added to the object list on any execbuf2 calls for
1770 * which this semaphore is used as a wait or signal fence. When used as
1771 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1776 struct anv_semaphore
{
1777 /* Permanent semaphore state. Every semaphore has some form of permanent
1778 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1779 * (for cross-process semaphores0 or it could just be a dummy for use
1782 struct anv_semaphore_impl permanent
;
1784 /* Temporary semaphore state. A semaphore *may* have temporary state.
1785 * That state is added to the semaphore by an import operation and is reset
1786 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1787 * semaphore with temporary state cannot be signaled because the semaphore
1788 * must already be signaled before the temporary state can be exported from
1789 * the semaphore in the other process and imported here.
1791 struct anv_semaphore_impl temporary
;
1794 struct anv_shader_module
{
1795 unsigned char sha1
[20];
1800 static inline gl_shader_stage
1801 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1803 assert(__builtin_popcount(vk_stage
) == 1);
1804 return ffs(vk_stage
) - 1;
1807 static inline VkShaderStageFlagBits
1808 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1810 return (1 << mesa_stage
);
1813 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1815 #define anv_foreach_stage(stage, stage_bits) \
1816 for (gl_shader_stage stage, \
1817 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1818 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1819 __tmp &= ~(1 << (stage)))
1821 struct anv_pipeline_bind_map
{
1822 uint32_t surface_count
;
1823 uint32_t sampler_count
;
1824 uint32_t image_count
;
1826 struct anv_pipeline_binding
* surface_to_descriptor
;
1827 struct anv_pipeline_binding
* sampler_to_descriptor
;
1830 struct anv_shader_bin_key
{
1835 struct anv_shader_bin
{
1838 const struct anv_shader_bin_key
*key
;
1840 struct anv_state kernel
;
1841 uint32_t kernel_size
;
1843 const struct brw_stage_prog_data
*prog_data
;
1844 uint32_t prog_data_size
;
1846 struct anv_pipeline_bind_map bind_map
;
1848 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1851 struct anv_shader_bin
*
1852 anv_shader_bin_create(struct anv_device
*device
,
1853 const void *key
, uint32_t key_size
,
1854 const void *kernel
, uint32_t kernel_size
,
1855 const struct brw_stage_prog_data
*prog_data
,
1856 uint32_t prog_data_size
, const void *prog_data_param
,
1857 const struct anv_pipeline_bind_map
*bind_map
);
1860 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1863 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1865 assert(shader
&& shader
->ref_cnt
>= 1);
1866 p_atomic_inc(&shader
->ref_cnt
);
1870 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1872 assert(shader
&& shader
->ref_cnt
>= 1);
1873 if (p_atomic_dec_zero(&shader
->ref_cnt
))
1874 anv_shader_bin_destroy(device
, shader
);
1877 struct anv_pipeline
{
1878 struct anv_device
* device
;
1879 struct anv_batch batch
;
1880 uint32_t batch_data
[512];
1881 struct anv_reloc_list batch_relocs
;
1882 uint32_t dynamic_state_mask
;
1883 struct anv_dynamic_state dynamic_state
;
1885 struct anv_subpass
* subpass
;
1886 struct anv_pipeline_layout
* layout
;
1888 bool needs_data_cache
;
1890 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1893 const struct gen_l3_config
* l3_config
;
1894 uint32_t total_size
;
1897 VkShaderStageFlags active_stages
;
1898 struct anv_state blend_state
;
1901 uint32_t binding_stride
[MAX_VBS
];
1902 bool instancing_enable
[MAX_VBS
];
1903 bool primitive_restart
;
1906 uint32_t cs_right_mask
;
1909 bool depth_test_enable
;
1910 bool writes_stencil
;
1911 bool stencil_test_enable
;
1912 bool depth_clamp_enable
;
1913 bool sample_shading_enable
;
1918 uint32_t depth_stencil_state
[3];
1924 uint32_t wm_depth_stencil
[3];
1928 uint32_t wm_depth_stencil
[4];
1931 uint32_t interface_descriptor_data
[8];
1935 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1936 gl_shader_stage stage
)
1938 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1941 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1942 static inline const struct brw_##prefix##_prog_data * \
1943 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1945 if (anv_pipeline_has_stage(pipeline, stage)) { \
1946 return (const struct brw_##prefix##_prog_data *) \
1947 pipeline->shaders[stage]->prog_data; \
1953 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1954 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
1955 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
1956 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1957 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1958 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1960 static inline const struct brw_vue_prog_data
*
1961 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
1963 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1964 return &get_gs_prog_data(pipeline
)->base
;
1965 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1966 return &get_tes_prog_data(pipeline
)->base
;
1968 return &get_vs_prog_data(pipeline
)->base
;
1972 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1973 struct anv_pipeline_cache
*cache
,
1974 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1975 const VkAllocationCallbacks
*alloc
);
1978 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1979 struct anv_pipeline_cache
*cache
,
1980 const VkComputePipelineCreateInfo
*info
,
1981 struct anv_shader_module
*module
,
1982 const char *entrypoint
,
1983 const VkSpecializationInfo
*spec_info
);
1986 enum isl_format isl_format
:16;
1987 struct isl_swizzle swizzle
;
1991 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1992 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1994 static inline enum isl_format
1995 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1996 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1998 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
2001 static inline struct isl_swizzle
2002 anv_swizzle_for_render(struct isl_swizzle swizzle
)
2004 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2005 * RGB as RGBA for texturing
2007 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
2008 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
2010 /* But it doesn't matter what we render to that channel */
2011 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
2017 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
2020 * Subsurface of an anv_image.
2022 struct anv_surface
{
2023 /** Valid only if isl_surf::size > 0. */
2024 struct isl_surf isl
;
2027 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2034 /* The original VkFormat provided by the client. This may not match any
2035 * of the actual surface formats.
2038 VkImageAspectFlags aspects
;
2041 uint32_t array_size
;
2042 uint32_t samples
; /**< VkImageCreateInfo::samples */
2043 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2044 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2049 /* Set when bound */
2051 VkDeviceSize offset
;
2056 * For each foo, anv_image::foo_surface is valid if and only if
2057 * anv_image::aspects has a foo aspect.
2059 * The hardware requires that the depth buffer and stencil buffer be
2060 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2061 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2062 * allocate the depth and stencil buffers as separate surfaces in the same
2066 struct anv_surface color_surface
;
2069 struct anv_surface depth_surface
;
2070 struct anv_surface stencil_surface
;
2075 * For color images, this is the aux usage for this image when not used as a
2078 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
2081 enum isl_aux_usage aux_usage
;
2083 struct anv_surface aux_surface
;
2086 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2088 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
2089 const VkImageAspectFlags aspect_mask
,
2090 const uint32_t samples
)
2092 /* Validate the inputs. */
2093 assert(devinfo
&& aspect_mask
&& samples
);
2094 return devinfo
->gen
>= 8 && (aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2099 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
2100 const struct anv_image
*image
,
2101 enum blorp_hiz_op op
);
2104 anv_image_ccs_clear(struct anv_cmd_buffer
*cmd_buffer
,
2105 const struct anv_image
*image
,
2106 const struct isl_view
*view
,
2107 const VkImageSubresourceRange
*subresourceRange
);
2110 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
2111 const struct anv_image
*image
,
2112 const VkImageAspectFlags aspects
,
2113 const VkImageLayout layout
);
2115 /* This is defined as a macro so that it works for both
2116 * VkImageSubresourceRange and VkImageSubresourceLayers
2118 #define anv_get_layerCount(_image, _range) \
2119 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2120 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2122 static inline uint32_t
2123 anv_get_levelCount(const struct anv_image
*image
,
2124 const VkImageSubresourceRange
*range
)
2126 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
2127 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
2131 struct anv_image_view
{
2132 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
2134 uint32_t offset
; /**< Offset into bo. */
2136 struct isl_view isl
;
2138 VkImageAspectFlags aspect_mask
;
2140 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2142 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
2143 struct anv_state sampler_surface_state
;
2146 * RENDER_SURFACE_STATE when using image as a sampler surface with the
2147 * auxiliary buffer disabled.
2149 struct anv_state no_aux_sampler_surface_state
;
2152 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
2153 * for write-only and readable, using the real format for write-only and the
2154 * lowered format for readable.
2156 struct anv_state storage_surface_state
;
2157 struct anv_state writeonly_storage_surface_state
;
2159 struct brw_image_param storage_image_param
;
2162 struct anv_image_create_info
{
2163 const VkImageCreateInfo
*vk_info
;
2165 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2166 isl_tiling_flags_t isl_tiling_flags
;
2171 VkResult
anv_image_create(VkDevice _device
,
2172 const struct anv_image_create_info
*info
,
2173 const VkAllocationCallbacks
* alloc
,
2176 const struct anv_surface
*
2177 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
2178 VkImageAspectFlags aspect_mask
);
2181 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
2183 static inline struct VkExtent3D
2184 anv_sanitize_image_extent(const VkImageType imageType
,
2185 const struct VkExtent3D imageExtent
)
2187 switch (imageType
) {
2188 case VK_IMAGE_TYPE_1D
:
2189 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2190 case VK_IMAGE_TYPE_2D
:
2191 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2192 case VK_IMAGE_TYPE_3D
:
2195 unreachable("invalid image type");
2199 static inline struct VkOffset3D
2200 anv_sanitize_image_offset(const VkImageType imageType
,
2201 const struct VkOffset3D imageOffset
)
2203 switch (imageType
) {
2204 case VK_IMAGE_TYPE_1D
:
2205 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2206 case VK_IMAGE_TYPE_2D
:
2207 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2208 case VK_IMAGE_TYPE_3D
:
2211 unreachable("invalid image type");
2216 void anv_fill_buffer_surface_state(struct anv_device
*device
,
2217 struct anv_state state
,
2218 enum isl_format format
,
2219 uint32_t offset
, uint32_t range
,
2222 void anv_image_view_fill_image_param(struct anv_device
*device
,
2223 struct anv_image_view
*view
,
2224 struct brw_image_param
*param
);
2225 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
2226 struct anv_buffer_view
*view
,
2227 struct brw_image_param
*param
);
2229 struct anv_sampler
{
2233 struct anv_framebuffer
{
2238 uint32_t attachment_count
;
2239 struct anv_image_view
* attachments
[0];
2242 struct anv_subpass
{
2243 uint32_t attachment_count
;
2246 * A pointer to all attachment references used in this subpass.
2247 * Only valid if ::attachment_count > 0.
2249 VkAttachmentReference
* attachments
;
2250 uint32_t input_count
;
2251 VkAttachmentReference
* input_attachments
;
2252 uint32_t color_count
;
2253 VkAttachmentReference
* color_attachments
;
2254 VkAttachmentReference
* resolve_attachments
;
2256 VkAttachmentReference depth_stencil_attachment
;
2260 /** Subpass has a depth/stencil self-dependency */
2261 bool has_ds_self_dep
;
2263 /** Subpass has at least one resolve attachment */
2267 static inline unsigned
2268 anv_subpass_view_count(const struct anv_subpass
*subpass
)
2270 return MAX2(1, _mesa_bitcount(subpass
->view_mask
));
2273 enum anv_subpass_usage
{
2274 ANV_SUBPASS_USAGE_DRAW
= (1 << 0),
2275 ANV_SUBPASS_USAGE_INPUT
= (1 << 1),
2276 ANV_SUBPASS_USAGE_RESOLVE_SRC
= (1 << 2),
2277 ANV_SUBPASS_USAGE_RESOLVE_DST
= (1 << 3),
2280 struct anv_render_pass_attachment
{
2281 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2282 * its members individually.
2286 VkImageUsageFlags usage
;
2287 VkAttachmentLoadOp load_op
;
2288 VkAttachmentStoreOp store_op
;
2289 VkAttachmentLoadOp stencil_load_op
;
2290 VkImageLayout initial_layout
;
2291 VkImageLayout final_layout
;
2293 /* An array, indexed by subpass id, of how the attachment will be used. */
2294 enum anv_subpass_usage
* subpass_usage
;
2296 /* The subpass id in which the attachment will be used last. */
2297 uint32_t last_subpass_idx
;
2300 struct anv_render_pass
{
2301 uint32_t attachment_count
;
2302 uint32_t subpass_count
;
2303 /* An array of subpass_count+1 flushes, one per subpass boundary */
2304 enum anv_pipe_bits
* subpass_flushes
;
2305 struct anv_render_pass_attachment
* attachments
;
2306 struct anv_subpass subpasses
[0];
2309 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2311 struct anv_query_pool
{
2313 VkQueryPipelineStatisticFlags pipeline_statistics
;
2314 /** Stride between slots, in bytes */
2316 /** Number of slots in this query pool */
2321 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
2324 void anv_dump_image_to_ppm(struct anv_device
*device
,
2325 struct anv_image
*image
, unsigned miplevel
,
2326 unsigned array_layer
, VkImageAspectFlagBits aspect
,
2327 const char *filename
);
2329 enum anv_dump_action
{
2330 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
2333 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
2334 void anv_dump_finish(void);
2336 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
2337 struct anv_framebuffer
*fb
);
2339 static inline uint32_t
2340 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
2342 /* This function must be called from within a subpass. */
2343 assert(cmd_state
->pass
&& cmd_state
->subpass
);
2345 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
2347 /* The id of this subpass shouldn't exceed the number of subpasses in this
2348 * render pass minus 1.
2350 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
2354 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2356 static inline struct __anv_type * \
2357 __anv_type ## _from_handle(__VkType _handle) \
2359 return (struct __anv_type *) _handle; \
2362 static inline __VkType \
2363 __anv_type ## _to_handle(struct __anv_type *_obj) \
2365 return (__VkType) _obj; \
2368 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2370 static inline struct __anv_type * \
2371 __anv_type ## _from_handle(__VkType _handle) \
2373 return (struct __anv_type *)(uintptr_t) _handle; \
2376 static inline __VkType \
2377 __anv_type ## _to_handle(struct __anv_type *_obj) \
2379 return (__VkType)(uintptr_t) _obj; \
2382 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2383 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2385 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
2386 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
2387 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
2388 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
2389 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
2391 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
2392 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
2393 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
2394 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
2395 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
2396 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
2397 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
2398 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
2399 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
2400 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
2401 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
2402 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
2403 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
2404 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
2405 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
2406 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
2407 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
2408 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
2409 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
2410 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
2411 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
2413 /* Gen-specific function declarations */
2415 # include "anv_genX.h"
2417 # define genX(x) gen7_##x
2418 # include "anv_genX.h"
2420 # define genX(x) gen75_##x
2421 # include "anv_genX.h"
2423 # define genX(x) gen8_##x
2424 # include "anv_genX.h"
2426 # define genX(x) gen9_##x
2427 # include "anv_genX.h"
2429 # define genX(x) gen10_##x
2430 # include "anv_genX.h"
2434 #endif /* ANV_PRIVATE_H */