2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
52 /* Pre-declarations needed for WSI entrypoints */
55 typedef struct xcb_connection_t xcb_connection_t
;
56 typedef uint32_t xcb_visualid_t
;
57 typedef uint32_t xcb_window_t
;
61 #include <vulkan/vulkan.h>
62 #include <vulkan/vulkan_intel.h>
63 #include <vulkan/vk_icd.h>
65 #include "anv_entrypoints.h"
66 #include "brw_context.h"
69 #include "wsi_common.h"
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
83 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
85 #define anv_noreturn __attribute__((__noreturn__))
86 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
88 static inline uint32_t
89 align_down_npot_u32(uint32_t v
, uint32_t a
)
94 static inline uint32_t
95 align_u32(uint32_t v
, uint32_t a
)
97 assert(a
!= 0 && a
== (a
& -a
));
98 return (v
+ a
- 1) & ~(a
- 1);
101 static inline uint64_t
102 align_u64(uint64_t v
, uint64_t a
)
104 assert(a
!= 0 && a
== (a
& -a
));
105 return (v
+ a
- 1) & ~(a
- 1);
108 static inline int32_t
109 align_i32(int32_t v
, int32_t a
)
111 assert(a
!= 0 && a
== (a
& -a
));
112 return (v
+ a
- 1) & ~(a
- 1);
115 /** Alignment must be a power of 2. */
117 anv_is_aligned(uintmax_t n
, uintmax_t a
)
119 assert(a
== (a
& -a
));
120 return (n
& (a
- 1)) == 0;
123 static inline uint32_t
124 anv_minify(uint32_t n
, uint32_t levels
)
126 if (unlikely(n
== 0))
129 return MAX2(n
>> levels
, 1);
133 anv_clamp_f(float f
, float min
, float max
)
146 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
148 if (*inout_mask
& clear_mask
) {
149 *inout_mask
&= ~clear_mask
;
156 #define for_each_bit(b, dword) \
157 for (uint32_t __dword = (dword); \
158 (b) = __builtin_ffs(__dword) - 1, __dword; \
159 __dword &= ~(1 << (b)))
161 #define typed_memcpy(dest, src, count) ({ \
162 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
163 memcpy((dest), (src), (count) * sizeof(*(src))); \
166 /* Define no kernel as 1, since that's an illegal offset for a kernel */
170 VkStructureType sType
;
174 /* Whenever we generate an error, pass it through this function. Useful for
175 * debugging, where we can break on it. Only call at error site, not when
176 * propagating errors. Might be useful to plug in a stack trace here.
179 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
182 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
183 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
185 #define vk_error(error) error
186 #define vk_errorf(error, format, ...) error
189 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
190 anv_printflike(3, 4);
191 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
192 void anv_loge_v(const char *format
, va_list va
);
195 * Print a FINISHME message, including its source location.
197 #define anv_finishme(format, ...) ({ \
198 static bool reported = false; \
200 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
205 /* A non-fatal assert. Useful for debugging. */
207 #define anv_assert(x) ({ \
208 if (unlikely(!(x))) \
209 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
212 #define anv_assert(x)
216 * If a block of code is annotated with anv_validate, then the block runs only
220 #define anv_validate if (1)
222 #define anv_validate if (0)
225 void anv_abortf(const char *format
, ...) anv_noreturn
anv_printflike(1, 2);
226 void anv_abortfv(const char *format
, va_list va
) anv_noreturn
;
228 #define stub_return(v) \
230 anv_finishme("stub %s", __func__); \
236 anv_finishme("stub %s", __func__); \
241 * A dynamically growable, circular buffer. Elements are added at head and
242 * removed from tail. head and tail are free-running uint32_t indices and we
243 * only compute the modulo with size when accessing the array. This way,
244 * number of bytes in the queue is always head - tail, even in case of
251 /* Index into the current validation list. This is used by the
252 * validation list building alrogithm to track which buffers are already
253 * in the validation list so that we can ensure uniqueness.
257 /* Last known offset. This value is provided by the kernel when we
258 * execbuf and is used as the presumed offset for the next bunch of
266 /* We need to set the WRITE flag on winsys bos so GEM will know we're
267 * writing to them and synchronize uses on other rings (eg if the display
268 * server uses the blitter ring).
274 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
276 bo
->gem_handle
= gem_handle
;
281 bo
->is_winsys_bo
= false;
284 /* Represents a lock-free linked list of "free" things. This is used by
285 * both the block pool and the state pools. Unfortunately, in order to
286 * solve the ABA problem, we can't use a single uint32_t head.
288 union anv_free_list
{
292 /* A simple count that is incremented every time the head changes. */
298 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
300 struct anv_block_state
{
310 struct anv_block_pool
{
311 struct anv_device
*device
;
315 /* The offset from the start of the bo to the "center" of the block
316 * pool. Pointers to allocated blocks are given by
317 * bo.map + center_bo_offset + offsets.
319 uint32_t center_bo_offset
;
321 /* Current memory map of the block pool. This pointer may or may not
322 * point to the actual beginning of the block pool memory. If
323 * anv_block_pool_alloc_back has ever been called, then this pointer
324 * will point to the "center" position of the buffer and all offsets
325 * (negative or positive) given out by the block pool alloc functions
326 * will be valid relative to this pointer.
328 * In particular, map == bo.map + center_offset
334 * Array of mmaps and gem handles owned by the block pool, reclaimed when
335 * the block pool is destroyed.
337 struct u_vector mmap_cleanups
;
341 union anv_free_list free_list
;
342 struct anv_block_state state
;
344 union anv_free_list back_free_list
;
345 struct anv_block_state back_state
;
348 /* Block pools are backed by a fixed-size 2GB memfd */
349 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
351 /* The center of the block pool is also the middle of the memfd. This may
352 * change in the future if we decide differently for some reason.
354 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
356 static inline uint32_t
357 anv_block_pool_size(struct anv_block_pool
*pool
)
359 return pool
->state
.end
+ pool
->back_state
.end
;
368 struct anv_fixed_size_state_pool
{
370 union anv_free_list free_list
;
371 struct anv_block_state block
;
374 #define ANV_MIN_STATE_SIZE_LOG2 6
375 #define ANV_MAX_STATE_SIZE_LOG2 17
377 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
379 struct anv_state_pool
{
380 struct anv_block_pool
*block_pool
;
381 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
384 struct anv_state_stream_block
;
386 struct anv_state_stream
{
387 struct anv_block_pool
*block_pool
;
389 /* The current working block */
390 struct anv_state_stream_block
*block
;
392 /* Offset at which the current block starts */
394 /* Offset at which to allocate the next state */
396 /* Offset at which the current block ends */
400 #define CACHELINE_SIZE 64
401 #define CACHELINE_MASK 63
404 anv_clflush_range(void *start
, size_t size
)
406 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
407 void *end
= start
+ size
;
409 __builtin_ia32_mfence();
411 __builtin_ia32_clflush(p
);
417 anv_state_clflush(struct anv_state state
)
419 anv_clflush_range(state
.map
, state
.alloc_size
);
422 void anv_block_pool_init(struct anv_block_pool
*pool
,
423 struct anv_device
*device
, uint32_t block_size
);
424 void anv_block_pool_finish(struct anv_block_pool
*pool
);
425 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
);
426 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
);
427 void anv_block_pool_free(struct anv_block_pool
*pool
, int32_t offset
);
428 void anv_state_pool_init(struct anv_state_pool
*pool
,
429 struct anv_block_pool
*block_pool
);
430 void anv_state_pool_finish(struct anv_state_pool
*pool
);
431 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
432 size_t state_size
, size_t alignment
);
433 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
434 void anv_state_stream_init(struct anv_state_stream
*stream
,
435 struct anv_block_pool
*block_pool
);
436 void anv_state_stream_finish(struct anv_state_stream
*stream
);
437 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
438 uint32_t size
, uint32_t alignment
);
441 * Implements a pool of re-usable BOs. The interface is identical to that
442 * of block_pool except that each block is its own BO.
445 struct anv_device
*device
;
450 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
451 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
452 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
454 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
456 struct anv_scratch_bo
{
461 struct anv_scratch_pool
{
462 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
463 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
466 void anv_scratch_pool_init(struct anv_device
*device
,
467 struct anv_scratch_pool
*pool
);
468 void anv_scratch_pool_finish(struct anv_device
*device
,
469 struct anv_scratch_pool
*pool
);
470 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
471 struct anv_scratch_pool
*pool
,
472 gl_shader_stage stage
,
473 unsigned per_thread_scratch
);
475 extern struct anv_dispatch_table dtable
;
477 #define VK_ICD_WSI_PLATFORM_MAX 5
479 struct anv_physical_device
{
480 VK_LOADER_DATA _loader_data
;
482 struct anv_instance
* instance
;
486 struct gen_device_info info
;
487 uint64_t aperture_size
;
488 struct brw_compiler
* compiler
;
489 struct isl_device isl_dev
;
490 int cmd_parser_version
;
493 uint32_t subslice_total
;
495 struct wsi_device wsi_device
;
498 struct anv_instance
{
499 VK_LOADER_DATA _loader_data
;
501 VkAllocationCallbacks alloc
;
504 int physicalDeviceCount
;
505 struct anv_physical_device physicalDevice
;
508 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
509 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
512 VK_LOADER_DATA _loader_data
;
514 struct anv_device
* device
;
516 struct anv_state_pool
* pool
;
519 struct anv_pipeline_cache
{
520 struct anv_device
* device
;
521 pthread_mutex_t mutex
;
523 struct hash_table
* cache
;
526 struct anv_pipeline_bind_map
;
528 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
529 struct anv_device
*device
,
531 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
533 struct anv_shader_bin
*
534 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
535 const void *key
, uint32_t key_size
);
536 struct anv_shader_bin
*
537 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
538 const void *key_data
, uint32_t key_size
,
539 const void *kernel_data
, uint32_t kernel_size
,
540 const struct brw_stage_prog_data
*prog_data
,
541 uint32_t prog_data_size
,
542 const struct anv_pipeline_bind_map
*bind_map
);
545 VK_LOADER_DATA _loader_data
;
547 VkAllocationCallbacks alloc
;
549 struct anv_instance
* instance
;
551 struct gen_device_info info
;
552 struct isl_device isl_dev
;
555 bool can_chain_batches
;
556 bool robust_buffer_access
;
558 struct anv_bo_pool batch_bo_pool
;
560 struct anv_block_pool dynamic_state_block_pool
;
561 struct anv_state_pool dynamic_state_pool
;
563 struct anv_block_pool instruction_block_pool
;
564 struct anv_state_pool instruction_state_pool
;
566 struct anv_block_pool surface_state_block_pool
;
567 struct anv_state_pool surface_state_pool
;
569 struct anv_bo workaround_bo
;
571 struct anv_pipeline_cache blorp_shader_cache
;
572 struct blorp_context blorp
;
574 struct anv_state border_colors
;
576 struct anv_queue queue
;
578 struct anv_scratch_pool scratch_pool
;
580 uint32_t default_mocs
;
582 pthread_mutex_t mutex
;
583 pthread_cond_t queue_submit
;
586 void anv_device_get_cache_uuid(void *uuid
);
588 void anv_device_init_blorp(struct anv_device
*device
);
589 void anv_device_finish_blorp(struct anv_device
*device
);
591 VkResult
anv_device_execbuf(struct anv_device
*device
,
592 struct drm_i915_gem_execbuffer2
*execbuf
,
593 struct anv_bo
**execbuf_bos
);
595 void* anv_gem_mmap(struct anv_device
*device
,
596 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
597 void anv_gem_munmap(void *p
, uint64_t size
);
598 uint32_t anv_gem_create(struct anv_device
*device
, size_t size
);
599 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
600 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
601 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
602 int anv_gem_execbuffer(struct anv_device
*device
,
603 struct drm_i915_gem_execbuffer2
*execbuf
);
604 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
605 uint32_t stride
, uint32_t tiling
);
606 int anv_gem_create_context(struct anv_device
*device
);
607 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
608 int anv_gem_get_param(int fd
, uint32_t param
);
609 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
610 int anv_gem_get_aperture(int fd
, uint64_t *size
);
611 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
612 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
613 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
614 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
615 uint32_t read_domains
, uint32_t write_domain
);
617 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
619 struct anv_reloc_list
{
622 struct drm_i915_gem_relocation_entry
* relocs
;
623 struct anv_bo
** reloc_bos
;
626 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
627 const VkAllocationCallbacks
*alloc
);
628 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
629 const VkAllocationCallbacks
*alloc
);
631 uint64_t anv_reloc_list_add(struct anv_reloc_list
*list
,
632 const VkAllocationCallbacks
*alloc
,
633 uint32_t offset
, struct anv_bo
*target_bo
,
636 struct anv_batch_bo
{
637 /* Link in the anv_cmd_buffer.owned_batch_bos list */
638 struct list_head link
;
642 /* Bytes actually consumed in this batch BO */
645 struct anv_reloc_list relocs
;
649 const VkAllocationCallbacks
* alloc
;
655 struct anv_reloc_list
* relocs
;
657 /* This callback is called (with the associated user data) in the event
658 * that the batch runs out of space.
660 VkResult (*extend_cb
)(struct anv_batch
*, void *);
664 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
665 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
666 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
667 void *location
, struct anv_bo
*bo
, uint32_t offset
);
668 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
669 struct anv_batch
*batch
);
676 static inline uint64_t
677 _anv_combine_address(struct anv_batch
*batch
, void *location
,
678 const struct anv_address address
, uint32_t delta
)
680 if (address
.bo
== NULL
) {
681 return address
.offset
+ delta
;
683 assert(batch
->start
<= location
&& location
< batch
->end
);
685 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
689 #define __gen_address_type struct anv_address
690 #define __gen_user_data struct anv_batch
691 #define __gen_combine_address _anv_combine_address
693 /* Wrapper macros needed to work around preprocessor argument issues. In
694 * particular, arguments don't get pre-evaluated if they are concatenated.
695 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
696 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
697 * We can work around this easily enough with these helpers.
699 #define __anv_cmd_length(cmd) cmd ## _length
700 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
701 #define __anv_cmd_header(cmd) cmd ## _header
702 #define __anv_cmd_pack(cmd) cmd ## _pack
703 #define __anv_reg_num(reg) reg ## _num
705 #define anv_pack_struct(dst, struc, ...) do { \
706 struct struc __template = { \
709 __anv_cmd_pack(struc)(NULL, dst, &__template); \
710 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
713 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
714 void *__dst = anv_batch_emit_dwords(batch, n); \
715 struct cmd __template = { \
716 __anv_cmd_header(cmd), \
717 .DWordLength = n - __anv_cmd_length_bias(cmd), \
720 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
724 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
728 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
729 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
730 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
731 dw[i] = (dwords0)[i] | (dwords1)[i]; \
732 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
735 #define anv_batch_emit(batch, cmd, name) \
736 for (struct cmd name = { __anv_cmd_header(cmd) }, \
737 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
738 __builtin_expect(_dst != NULL, 1); \
739 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
740 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
744 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
745 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
746 struct anv_state __state = \
747 anv_state_pool_alloc((pool), __size, align); \
748 struct cmd __template = { \
751 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
752 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
753 if (!(pool)->block_pool->device->info.has_llc) \
754 anv_state_clflush(__state); \
758 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
759 .GraphicsDataTypeGFDT = 0, \
760 .LLCCacheabilityControlLLCCC = 0, \
761 .L3CacheabilityControlL3CC = 1, \
764 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
765 .LLCeLLCCacheabilityControlLLCCC = 0, \
766 .L3CacheabilityControlL3CC = 1, \
769 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
770 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
771 .TargetCache = L3DefertoPATforLLCeLLCselection, \
775 /* Skylake: MOCS is now an index into an array of 62 different caching
776 * configurations programmed by the kernel.
779 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
780 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
781 .IndextoMOCSTables = 2 \
784 #define GEN9_MOCS_PTE { \
785 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
786 .IndextoMOCSTables = 1 \
789 struct anv_device_memory
{
792 VkDeviceSize map_size
;
797 * Header for Vertex URB Entry (VUE)
799 struct anv_vue_header
{
801 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
802 uint32_t ViewportIndex
;
806 struct anv_descriptor_set_binding_layout
{
808 /* The type of the descriptors in this binding */
809 VkDescriptorType type
;
812 /* Number of array elements in this binding */
815 /* Index into the flattend descriptor set */
816 uint16_t descriptor_index
;
818 /* Index into the dynamic state array for a dynamic buffer */
819 int16_t dynamic_offset_index
;
821 /* Index into the descriptor set buffer views */
822 int16_t buffer_index
;
825 /* Index into the binding table for the associated surface */
826 int16_t surface_index
;
828 /* Index into the sampler table for the associated sampler */
829 int16_t sampler_index
;
831 /* Index into the image table for the associated image */
833 } stage
[MESA_SHADER_STAGES
];
835 /* Immutable samplers (or NULL if no immutable samplers) */
836 struct anv_sampler
**immutable_samplers
;
839 struct anv_descriptor_set_layout
{
840 /* Number of bindings in this descriptor set */
841 uint16_t binding_count
;
843 /* Total size of the descriptor set with room for all array entries */
846 /* Shader stages affected by this descriptor set */
847 uint16_t shader_stages
;
849 /* Number of buffers in this descriptor set */
850 uint16_t buffer_count
;
852 /* Number of dynamic offsets used by this descriptor set */
853 uint16_t dynamic_offset_count
;
855 /* Bindings in this descriptor set */
856 struct anv_descriptor_set_binding_layout binding
[0];
859 struct anv_descriptor
{
860 VkDescriptorType type
;
864 struct anv_image_view
*image_view
;
865 struct anv_sampler
*sampler
;
868 struct anv_buffer_view
*buffer_view
;
872 struct anv_descriptor_set
{
873 const struct anv_descriptor_set_layout
*layout
;
875 uint32_t buffer_count
;
876 struct anv_buffer_view
*buffer_views
;
877 struct anv_descriptor descriptors
[0];
880 struct anv_descriptor_pool
{
885 struct anv_state_stream surface_state_stream
;
886 void *surface_state_free_list
;
892 anv_descriptor_set_create(struct anv_device
*device
,
893 struct anv_descriptor_pool
*pool
,
894 const struct anv_descriptor_set_layout
*layout
,
895 struct anv_descriptor_set
**out_set
);
898 anv_descriptor_set_destroy(struct anv_device
*device
,
899 struct anv_descriptor_pool
*pool
,
900 struct anv_descriptor_set
*set
);
902 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
904 struct anv_pipeline_binding
{
905 /* The descriptor set this surface corresponds to. The special value of
906 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
907 * to a color attachment and not a regular descriptor.
911 /* Binding in the descriptor set */
914 /* Index in the binding */
918 struct anv_pipeline_layout
{
920 struct anv_descriptor_set_layout
*layout
;
921 uint32_t dynamic_offset_start
;
927 bool has_dynamic_offsets
;
928 } stage
[MESA_SHADER_STAGES
];
930 unsigned char sha1
[20];
934 struct anv_device
* device
;
937 VkBufferUsageFlags usage
;
944 enum anv_cmd_dirty_bits
{
945 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
946 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
947 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
948 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
949 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
950 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
951 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
952 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
953 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
954 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
955 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
956 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
957 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
959 typedef uint32_t anv_cmd_dirty_mask_t
;
962 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
963 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
964 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
965 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
966 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
967 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
968 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
969 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
970 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
971 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
972 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
974 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
975 * a flush has happened but not a CS stall. The next time we do any sort
976 * of invalidation we need to insert a CS stall at that time. Otherwise,
977 * we would have to CS stall on every flush which could be bad.
979 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
982 #define ANV_PIPE_FLUSH_BITS ( \
983 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
984 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
985 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
987 #define ANV_PIPE_STALL_BITS ( \
988 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
989 ANV_PIPE_DEPTH_STALL_BIT | \
990 ANV_PIPE_CS_STALL_BIT)
992 #define ANV_PIPE_INVALIDATE_BITS ( \
993 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
994 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
995 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
996 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
997 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
998 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1000 struct anv_vertex_binding
{
1001 struct anv_buffer
* buffer
;
1002 VkDeviceSize offset
;
1005 struct anv_push_constants
{
1006 /* Current allocated size of this push constants data structure.
1007 * Because a decent chunk of it may not be used (images on SKL, for
1008 * instance), we won't actually allocate the entire structure up-front.
1012 /* Push constant data provided by the client through vkPushConstants */
1013 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1015 /* Our hardware only provides zero-based vertex and instance id so, in
1016 * order to satisfy the vulkan requirements, we may have to push one or
1017 * both of these into the shader.
1019 uint32_t base_vertex
;
1020 uint32_t base_instance
;
1022 /* Offsets and ranges for dynamically bound buffers */
1026 } dynamic
[MAX_DYNAMIC_BUFFERS
];
1028 /* Image data for image_load_store on pre-SKL */
1029 struct brw_image_param images
[MAX_IMAGES
];
1032 struct anv_dynamic_state
{
1035 VkViewport viewports
[MAX_VIEWPORTS
];
1040 VkRect2D scissors
[MAX_SCISSORS
];
1051 float blend_constants
[4];
1061 } stencil_compare_mask
;
1066 } stencil_write_mask
;
1071 } stencil_reference
;
1074 extern const struct anv_dynamic_state default_dynamic_state
;
1076 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1077 const struct anv_dynamic_state
*src
,
1078 uint32_t copy_mask
);
1081 * Attachment state when recording a renderpass instance.
1083 * The clear value is valid only if there exists a pending clear.
1085 struct anv_attachment_state
{
1086 enum isl_aux_usage aux_usage
;
1087 struct anv_state color_rt_state
;
1089 VkImageAspectFlags pending_clear_aspects
;
1090 VkClearValue clear_value
;
1093 /** State required while building cmd buffer */
1094 struct anv_cmd_state
{
1095 /* PIPELINE_SELECT.PipelineSelection */
1096 uint32_t current_pipeline
;
1097 const struct gen_l3_config
* current_l3_config
;
1099 anv_cmd_dirty_mask_t dirty
;
1100 anv_cmd_dirty_mask_t compute_dirty
;
1101 enum anv_pipe_bits pending_pipe_bits
;
1102 uint32_t num_workgroups_offset
;
1103 struct anv_bo
*num_workgroups_bo
;
1104 VkShaderStageFlags descriptors_dirty
;
1105 VkShaderStageFlags push_constants_dirty
;
1106 uint32_t scratch_size
;
1107 struct anv_pipeline
* pipeline
;
1108 struct anv_pipeline
* compute_pipeline
;
1109 struct anv_framebuffer
* framebuffer
;
1110 struct anv_render_pass
* pass
;
1111 struct anv_subpass
* subpass
;
1112 VkRect2D render_area
;
1113 uint32_t restart_index
;
1114 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1115 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1116 VkShaderStageFlags push_constant_stages
;
1117 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1118 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1119 struct anv_state samplers
[MESA_SHADER_STAGES
];
1120 struct anv_dynamic_state dynamic
;
1124 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1125 * valid only when recording a render pass instance.
1127 struct anv_attachment_state
* attachments
;
1130 * Surface states for color render targets. These are stored in a single
1131 * flat array. For depth-stencil attachments, the surface state is simply
1134 struct anv_state render_pass_states
;
1137 * A null surface state of the right size to match the framebuffer. This
1138 * is one of the states in render_pass_states.
1140 struct anv_state null_surface_state
;
1143 struct anv_buffer
* index_buffer
;
1144 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1145 uint32_t index_offset
;
1149 struct anv_cmd_pool
{
1150 VkAllocationCallbacks alloc
;
1151 struct list_head cmd_buffers
;
1154 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1156 enum anv_cmd_buffer_exec_mode
{
1157 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1158 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1159 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1160 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1161 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1164 struct anv_cmd_buffer
{
1165 VK_LOADER_DATA _loader_data
;
1167 struct anv_device
* device
;
1169 struct anv_cmd_pool
* pool
;
1170 struct list_head pool_link
;
1172 struct anv_batch batch
;
1174 /* Fields required for the actual chain of anv_batch_bo's.
1176 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1178 struct list_head batch_bos
;
1179 enum anv_cmd_buffer_exec_mode exec_mode
;
1181 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1182 * referenced by this command buffer
1184 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1186 struct u_vector seen_bbos
;
1188 /* A vector of int32_t's for every block of binding tables.
1190 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1192 struct u_vector bt_blocks
;
1195 struct anv_reloc_list surface_relocs
;
1196 /** Last seen surface state block pool center bo offset */
1197 uint32_t last_ss_pool_center
;
1199 /* Serial for tracking buffer completion */
1202 /* Stream objects for storing temporary data */
1203 struct anv_state_stream surface_state_stream
;
1204 struct anv_state_stream dynamic_state_stream
;
1206 VkCommandBufferUsageFlags usage_flags
;
1207 VkCommandBufferLevel level
;
1209 struct anv_cmd_state state
;
1212 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1213 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1214 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1215 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1216 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1217 struct anv_cmd_buffer
*secondary
);
1218 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1219 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1220 struct anv_cmd_buffer
*cmd_buffer
);
1222 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1225 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1226 gl_shader_stage stage
, uint32_t size
);
1227 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1228 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1229 (offsetof(struct anv_push_constants, field) + \
1230 sizeof(cmd_buffer->state.push_constants[0]->field)))
1232 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1233 const void *data
, uint32_t size
, uint32_t alignment
);
1234 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1235 uint32_t *a
, uint32_t *b
,
1236 uint32_t dwords
, uint32_t alignment
);
1239 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1241 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1242 uint32_t entries
, uint32_t *state_offset
);
1244 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1246 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1247 uint32_t size
, uint32_t alignment
);
1250 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1252 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1253 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1254 bool depth_clamp_enable
);
1255 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1257 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1258 struct anv_render_pass
*pass
,
1259 struct anv_framebuffer
*framebuffer
,
1260 const VkClearValue
*clear_values
);
1262 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1265 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1266 gl_shader_stage stage
);
1268 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1270 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1271 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1273 const struct anv_image_view
*
1274 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1277 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1278 uint32_t num_entries
,
1279 uint32_t *state_offset
);
1281 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1283 enum anv_fence_state
{
1284 /** Indicates that this is a new (or newly reset fence) */
1285 ANV_FENCE_STATE_RESET
,
1287 /** Indicates that this fence has been submitted to the GPU but is still
1288 * (as far as we know) in use by the GPU.
1290 ANV_FENCE_STATE_SUBMITTED
,
1292 ANV_FENCE_STATE_SIGNALED
,
1297 struct drm_i915_gem_execbuffer2 execbuf
;
1298 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1299 enum anv_fence_state state
;
1304 struct anv_state state
;
1307 struct anv_shader_module
{
1308 unsigned char sha1
[20];
1313 void anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
1314 struct anv_shader_module
*module
,
1315 const char *entrypoint
,
1316 const struct anv_pipeline_layout
*pipeline_layout
,
1317 const VkSpecializationInfo
*spec_info
);
1319 static inline gl_shader_stage
1320 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1322 assert(__builtin_popcount(vk_stage
) == 1);
1323 return ffs(vk_stage
) - 1;
1326 static inline VkShaderStageFlagBits
1327 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1329 return (1 << mesa_stage
);
1332 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1334 #define anv_foreach_stage(stage, stage_bits) \
1335 for (gl_shader_stage stage, \
1336 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1337 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1338 __tmp &= ~(1 << (stage)))
1340 struct anv_pipeline_bind_map
{
1341 uint32_t surface_count
;
1342 uint32_t sampler_count
;
1343 uint32_t image_count
;
1345 struct anv_pipeline_binding
* surface_to_descriptor
;
1346 struct anv_pipeline_binding
* sampler_to_descriptor
;
1349 struct anv_shader_bin_key
{
1354 struct anv_shader_bin
{
1357 const struct anv_shader_bin_key
*key
;
1359 struct anv_state kernel
;
1360 uint32_t kernel_size
;
1362 const struct brw_stage_prog_data
*prog_data
;
1363 uint32_t prog_data_size
;
1365 struct anv_pipeline_bind_map bind_map
;
1367 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1370 struct anv_shader_bin
*
1371 anv_shader_bin_create(struct anv_device
*device
,
1372 const void *key
, uint32_t key_size
,
1373 const void *kernel
, uint32_t kernel_size
,
1374 const struct brw_stage_prog_data
*prog_data
,
1375 uint32_t prog_data_size
, const void *prog_data_param
,
1376 const struct anv_pipeline_bind_map
*bind_map
);
1379 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1382 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1384 assert(shader
->ref_cnt
>= 1);
1385 __sync_fetch_and_add(&shader
->ref_cnt
, 1);
1389 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1391 assert(shader
->ref_cnt
>= 1);
1392 if (__sync_fetch_and_add(&shader
->ref_cnt
, -1) == 1)
1393 anv_shader_bin_destroy(device
, shader
);
1396 struct anv_pipeline
{
1397 struct anv_device
* device
;
1398 struct anv_batch batch
;
1399 uint32_t batch_data
[512];
1400 struct anv_reloc_list batch_relocs
;
1401 uint32_t dynamic_state_mask
;
1402 struct anv_dynamic_state dynamic_state
;
1404 struct anv_pipeline_layout
* layout
;
1406 bool needs_data_cache
;
1408 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1411 const struct gen_l3_config
* l3_config
;
1412 uint32_t total_size
;
1415 VkShaderStageFlags active_stages
;
1416 struct anv_state blend_state
;
1419 uint32_t binding_stride
[MAX_VBS
];
1420 bool instancing_enable
[MAX_VBS
];
1421 bool primitive_restart
;
1424 uint32_t cs_right_mask
;
1426 bool depth_clamp_enable
;
1430 uint32_t depth_stencil_state
[3];
1436 uint32_t wm_depth_stencil
[3];
1440 uint32_t wm_depth_stencil
[4];
1443 uint32_t interface_descriptor_data
[8];
1447 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1448 gl_shader_stage stage
)
1450 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1453 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1454 static inline const struct brw_##prefix##_prog_data * \
1455 get_##prefix##_prog_data(struct anv_pipeline *pipeline) \
1457 if (anv_pipeline_has_stage(pipeline, stage)) { \
1458 return (const struct brw_##prefix##_prog_data *) \
1459 pipeline->shaders[stage]->prog_data; \
1465 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1466 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1467 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1468 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1471 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1472 struct anv_pipeline_cache
*cache
,
1473 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1474 const VkAllocationCallbacks
*alloc
);
1477 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1478 struct anv_pipeline_cache
*cache
,
1479 const VkComputePipelineCreateInfo
*info
,
1480 struct anv_shader_module
*module
,
1481 const char *entrypoint
,
1482 const VkSpecializationInfo
*spec_info
);
1485 enum isl_format isl_format
:16;
1486 struct isl_swizzle swizzle
;
1490 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1491 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1493 static inline enum isl_format
1494 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1495 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1497 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1501 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
1504 * Subsurface of an anv_image.
1506 struct anv_surface
{
1507 /** Valid only if isl_surf::size > 0. */
1508 struct isl_surf isl
;
1511 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1518 /* The original VkFormat provided by the client. This may not match any
1519 * of the actual surface formats.
1522 VkImageAspectFlags aspects
;
1525 uint32_t array_size
;
1526 uint32_t samples
; /**< VkImageCreateInfo::samples */
1527 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1528 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1533 /* Set when bound */
1535 VkDeviceSize offset
;
1540 * For each foo, anv_image::foo_surface is valid if and only if
1541 * anv_image::aspects has a foo aspect.
1543 * The hardware requires that the depth buffer and stencil buffer be
1544 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1545 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1546 * allocate the depth and stencil buffers as separate surfaces in the same
1550 struct anv_surface color_surface
;
1553 struct anv_surface depth_surface
;
1554 struct anv_surface stencil_surface
;
1558 struct anv_surface aux_surface
;
1561 static inline uint32_t
1562 anv_get_layerCount(const struct anv_image
*image
,
1563 const VkImageSubresourceRange
*range
)
1565 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1566 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1569 static inline uint32_t
1570 anv_get_levelCount(const struct anv_image
*image
,
1571 const VkImageSubresourceRange
*range
)
1573 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1574 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1578 struct anv_image_view
{
1579 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
1581 uint32_t offset
; /**< Offset into bo. */
1583 struct isl_view isl
;
1585 VkImageAspectFlags aspect_mask
;
1587 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1589 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1590 struct anv_state sampler_surface_state
;
1592 /** RENDER_SURFACE_STATE when using image as a storage image. */
1593 struct anv_state storage_surface_state
;
1595 struct brw_image_param storage_image_param
;
1598 struct anv_image_create_info
{
1599 const VkImageCreateInfo
*vk_info
;
1601 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1602 isl_tiling_flags_t isl_tiling_flags
;
1607 VkResult
anv_image_create(VkDevice _device
,
1608 const struct anv_image_create_info
*info
,
1609 const VkAllocationCallbacks
* alloc
,
1612 const struct anv_surface
*
1613 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1614 VkImageAspectFlags aspect_mask
);
1617 anv_image_has_hiz(const struct anv_image
*image
)
1619 /* We must check the aspect because anv_image::aux_surface may be used for
1620 * any type of auxiliary surface, not just HiZ.
1622 return (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1623 image
->aux_surface
.isl
.size
> 0;
1626 struct anv_buffer_view
{
1627 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1629 uint32_t offset
; /**< Offset into bo. */
1630 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1632 struct anv_state surface_state
;
1633 struct anv_state storage_surface_state
;
1635 struct brw_image_param storage_image_param
;
1639 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
1641 static inline struct VkExtent3D
1642 anv_sanitize_image_extent(const VkImageType imageType
,
1643 const struct VkExtent3D imageExtent
)
1645 switch (imageType
) {
1646 case VK_IMAGE_TYPE_1D
:
1647 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1648 case VK_IMAGE_TYPE_2D
:
1649 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1650 case VK_IMAGE_TYPE_3D
:
1653 unreachable("invalid image type");
1657 static inline struct VkOffset3D
1658 anv_sanitize_image_offset(const VkImageType imageType
,
1659 const struct VkOffset3D imageOffset
)
1661 switch (imageType
) {
1662 case VK_IMAGE_TYPE_1D
:
1663 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1664 case VK_IMAGE_TYPE_2D
:
1665 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1666 case VK_IMAGE_TYPE_3D
:
1669 unreachable("invalid image type");
1674 void anv_fill_buffer_surface_state(struct anv_device
*device
,
1675 struct anv_state state
,
1676 enum isl_format format
,
1677 uint32_t offset
, uint32_t range
,
1680 void anv_image_view_fill_image_param(struct anv_device
*device
,
1681 struct anv_image_view
*view
,
1682 struct brw_image_param
*param
);
1683 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
1684 struct anv_buffer_view
*view
,
1685 struct brw_image_param
*param
);
1687 struct anv_sampler
{
1691 struct anv_framebuffer
{
1696 uint32_t attachment_count
;
1697 struct anv_image_view
* attachments
[0];
1700 struct anv_subpass
{
1701 uint32_t input_count
;
1702 uint32_t * input_attachments
;
1703 uint32_t color_count
;
1704 uint32_t * color_attachments
;
1705 uint32_t * resolve_attachments
;
1706 uint32_t depth_stencil_attachment
;
1708 /** Subpass has at least one resolve attachment */
1712 enum anv_subpass_usage
{
1713 ANV_SUBPASS_USAGE_DRAW
= (1 << 0),
1714 ANV_SUBPASS_USAGE_INPUT
= (1 << 1),
1715 ANV_SUBPASS_USAGE_RESOLVE_SRC
= (1 << 2),
1716 ANV_SUBPASS_USAGE_RESOLVE_DST
= (1 << 3),
1719 struct anv_render_pass_attachment
{
1722 VkAttachmentLoadOp load_op
;
1723 VkAttachmentStoreOp store_op
;
1724 VkAttachmentLoadOp stencil_load_op
;
1726 /* An array, indexed by subpass id, of how the attachment will be used. */
1727 enum anv_subpass_usage
* subpass_usage
;
1730 struct anv_render_pass
{
1731 uint32_t attachment_count
;
1732 uint32_t subpass_count
;
1733 uint32_t * subpass_attachments
;
1734 enum anv_subpass_usage
* subpass_usages
;
1735 struct anv_render_pass_attachment
* attachments
;
1736 struct anv_subpass subpasses
[0];
1739 struct anv_query_pool_slot
{
1745 struct anv_query_pool
{
1751 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
1754 void anv_dump_image_to_ppm(struct anv_device
*device
,
1755 struct anv_image
*image
, unsigned miplevel
,
1756 unsigned array_layer
, VkImageAspectFlagBits aspect
,
1757 const char *filename
);
1759 enum anv_dump_action
{
1760 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
1763 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
1764 void anv_dump_finish(void);
1766 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
1767 struct anv_framebuffer
*fb
);
1769 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1771 static inline struct __anv_type * \
1772 __anv_type ## _from_handle(__VkType _handle) \
1774 return (struct __anv_type *) _handle; \
1777 static inline __VkType \
1778 __anv_type ## _to_handle(struct __anv_type *_obj) \
1780 return (__VkType) _obj; \
1783 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1785 static inline struct __anv_type * \
1786 __anv_type ## _from_handle(__VkType _handle) \
1788 return (struct __anv_type *)(uintptr_t) _handle; \
1791 static inline __VkType \
1792 __anv_type ## _to_handle(struct __anv_type *_obj) \
1794 return (__VkType)(uintptr_t) _obj; \
1797 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1798 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1800 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
1801 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
1802 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
1803 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
1804 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
1806 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
1807 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
1808 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
1809 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
1810 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
1811 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
1812 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
1813 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
1814 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
1815 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
1816 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
1817 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
1818 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
1819 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
1820 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
1821 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
1822 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
1823 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
1824 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
1826 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1828 static inline const __VkType * \
1829 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1831 return (const __VkType *) __anv_obj; \
1834 #define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1835 const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name)
1837 ANV_DEFINE_STRUCT_CASTS(anv_common
, VkMemoryBarrier
)
1838 ANV_DEFINE_STRUCT_CASTS(anv_common
, VkBufferMemoryBarrier
)
1839 ANV_DEFINE_STRUCT_CASTS(anv_common
, VkImageMemoryBarrier
)
1841 /* Gen-specific function declarations */
1843 # include "anv_genX.h"
1845 # define genX(x) gen7_##x
1846 # include "anv_genX.h"
1848 # define genX(x) gen75_##x
1849 # include "anv_genX.h"
1851 # define genX(x) gen8_##x
1852 # include "anv_genX.h"
1854 # define genX(x) gen9_##x
1855 # include "anv_genX.h"
1863 #endif /* ANV_PRIVATE_H */