2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
46 #include "common/gen_clflush.h"
47 #include "common/gen_gem.h"
48 #include "dev/gen_device_info.h"
49 #include "blorp/blorp.h"
50 #include "compiler/brw_compiler.h"
51 #include "util/macros.h"
52 #include "util/hash_table.h"
53 #include "util/list.h"
55 #include "util/u_atomic.h"
56 #include "util/u_vector.h"
59 #include "vk_debug_report.h"
61 /* Pre-declarations needed for WSI entrypoints */
64 typedef struct xcb_connection_t xcb_connection_t
;
65 typedef uint32_t xcb_visualid_t
;
66 typedef uint32_t xcb_window_t
;
69 struct anv_buffer_view
;
70 struct anv_image_view
;
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
80 #include "anv_entrypoints.h"
81 #include "anv_extensions.h"
84 #include "common/gen_debug.h"
85 #include "common/intel_log.h"
86 #include "wsi_common.h"
88 /* anv Virtual Memory Layout
89 * =========================
91 * When the anv driver is determining the virtual graphics addresses of memory
92 * objects itself using the softpin mechanism, the following memory ranges
95 * Three special considerations to notice:
97 * (1) the dynamic state pool is located within the same 4 GiB as the low
98 * heap. This is to work around a VF cache issue described in a comment in
99 * anv_physical_device_init_heaps.
101 * (2) the binding table pool is located at lower addresses than the surface
102 * state pool, within a 4 GiB range. This allows surface state base addresses
103 * to cover both binding tables (16 bit offsets) and surface states (32 bit
106 * (3) the last 4 GiB of the address space is withheld from the high
107 * heap. Various hardware units will read past the end of an object for
108 * various reasons. This healthy margin prevents reads from wrapping around
111 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
112 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
113 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
114 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
115 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
116 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
117 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
118 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
119 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
120 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
121 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
122 #define HIGH_HEAP_MAX_ADDRESS 0xfffeffffffffULL
124 #define LOW_HEAP_SIZE \
125 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
126 #define HIGH_HEAP_SIZE \
127 (HIGH_HEAP_MAX_ADDRESS - HIGH_HEAP_MIN_ADDRESS + 1)
128 #define DYNAMIC_STATE_POOL_SIZE \
129 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
130 #define BINDING_TABLE_POOL_SIZE \
131 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
132 #define SURFACE_STATE_POOL_SIZE \
133 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
134 #define INSTRUCTION_STATE_POOL_SIZE \
135 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
137 /* Allowing different clear colors requires us to perform a depth resolve at
138 * the end of certain render passes. This is because while slow clears store
139 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
140 * See the PRMs for examples describing when additional resolves would be
141 * necessary. To enable fast clears without requiring extra resolves, we set
142 * the clear value to a globally-defined one. We could allow different values
143 * if the user doesn't expect coherent data during or after a render passes
144 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
145 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
146 * 1.0f seems to be the only value used. The only application that doesn't set
147 * this value does so through the usage of an seemingly uninitialized clear
150 #define ANV_HZ_FC_VAL 1.0f
155 #define MAX_VIEWPORTS 16
156 #define MAX_SCISSORS 16
157 #define MAX_PUSH_CONSTANTS_SIZE 128
158 #define MAX_DYNAMIC_BUFFERS 16
160 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
162 /* The kernel relocation API has a limitation of a 32-bit delta value
163 * applied to the address before it is written which, in spite of it being
164 * unsigned, is treated as signed . Because of the way that this maps to
165 * the Vulkan API, we cannot handle an offset into a buffer that does not
166 * fit into a signed 32 bits. The only mechanism we have for dealing with
167 * this at the moment is to limit all VkDeviceMemory objects to a maximum
168 * of 2GB each. The Vulkan spec allows us to do this:
170 * "Some platforms may have a limit on the maximum size of a single
171 * allocation. For example, certain systems may fail to create
172 * allocations with a size greater than or equal to 4GB. Such a limit is
173 * implementation-dependent, and if such a failure occurs then the error
174 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
176 * We don't use vk_error here because it's not an error so much as an
177 * indication to the application that the allocation is too large.
179 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
181 #define ANV_SVGS_VB_INDEX MAX_VBS
182 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
184 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
186 static inline uint32_t
187 align_down_npot_u32(uint32_t v
, uint32_t a
)
192 static inline uint32_t
193 align_u32(uint32_t v
, uint32_t a
)
195 assert(a
!= 0 && a
== (a
& -a
));
196 return (v
+ a
- 1) & ~(a
- 1);
199 static inline uint64_t
200 align_u64(uint64_t v
, uint64_t a
)
202 assert(a
!= 0 && a
== (a
& -a
));
203 return (v
+ a
- 1) & ~(a
- 1);
206 static inline int32_t
207 align_i32(int32_t v
, int32_t a
)
209 assert(a
!= 0 && a
== (a
& -a
));
210 return (v
+ a
- 1) & ~(a
- 1);
213 /** Alignment must be a power of 2. */
215 anv_is_aligned(uintmax_t n
, uintmax_t a
)
217 assert(a
== (a
& -a
));
218 return (n
& (a
- 1)) == 0;
221 static inline uint32_t
222 anv_minify(uint32_t n
, uint32_t levels
)
224 if (unlikely(n
== 0))
227 return MAX2(n
>> levels
, 1);
231 anv_clamp_f(float f
, float min
, float max
)
244 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
246 if (*inout_mask
& clear_mask
) {
247 *inout_mask
&= ~clear_mask
;
254 static inline union isl_color_value
255 vk_to_isl_color(VkClearColorValue color
)
257 return (union isl_color_value
) {
267 #define for_each_bit(b, dword) \
268 for (uint32_t __dword = (dword); \
269 (b) = __builtin_ffs(__dword) - 1, __dword; \
270 __dword &= ~(1 << (b)))
272 #define typed_memcpy(dest, src, count) ({ \
273 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
274 memcpy((dest), (src), (count) * sizeof(*(src))); \
277 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
278 * to be added here in order to utilize mapping in debug/error/perf macros.
280 #define REPORT_OBJECT_TYPE(o) \
281 __builtin_choose_expr ( \
282 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
283 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
284 __builtin_choose_expr ( \
285 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
286 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
287 __builtin_choose_expr ( \
288 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
289 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
290 __builtin_choose_expr ( \
291 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
292 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
293 __builtin_choose_expr ( \
294 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
295 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
296 __builtin_choose_expr ( \
297 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
298 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
299 __builtin_choose_expr ( \
300 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
301 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
302 __builtin_choose_expr ( \
303 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
304 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
305 __builtin_choose_expr ( \
306 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
307 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
308 __builtin_choose_expr ( \
309 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
310 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
311 __builtin_choose_expr ( \
312 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
313 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
314 __builtin_choose_expr ( \
315 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
316 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
317 __builtin_choose_expr ( \
318 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
319 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
320 __builtin_choose_expr ( \
321 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
322 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
323 __builtin_choose_expr ( \
324 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
325 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
326 __builtin_choose_expr ( \
327 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
328 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
329 __builtin_choose_expr ( \
330 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
331 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
332 __builtin_choose_expr ( \
333 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
334 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
335 __builtin_choose_expr ( \
336 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
337 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
338 __builtin_choose_expr ( \
339 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
340 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), void*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
374 /* The void expression results in a compile-time error \
375 when assigning the result to something. */ \
376 (void)0)))))))))))))))))))))))))))))))
378 /* Whenever we generate an error, pass it through this function. Useful for
379 * debugging, where we can break on it. Only call at error site, not when
380 * propagating errors. Might be useful to plug in a stack trace here.
383 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
384 VkDebugReportObjectTypeEXT type
, VkResult error
,
385 const char *file
, int line
, const char *format
, ...);
388 #define vk_error(error) __vk_errorf(NULL, NULL,\
389 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
390 error, __FILE__, __LINE__, NULL)
391 #define vk_errorf(instance, obj, error, format, ...)\
392 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
393 __FILE__, __LINE__, format, ## __VA_ARGS__)
395 #define vk_error(error) error
396 #define vk_errorf(instance, obj, error, format, ...) error
400 * Warn on ignored extension structs.
402 * The Vulkan spec requires us to ignore unsupported or unknown structs in
403 * a pNext chain. In debug mode, emitting warnings for ignored structs may
404 * help us discover structs that we should not have ignored.
407 * From the Vulkan 1.0.38 spec:
409 * Any component of the implementation (the loader, any enabled layers,
410 * and drivers) must skip over, without processing (other than reading the
411 * sType and pNext members) any chained structures with sType values not
412 * defined by extensions supported by that component.
414 #define anv_debug_ignored_stype(sType) \
415 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
417 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
418 VkDebugReportObjectTypeEXT type
, const char *file
,
419 int line
, const char *format
, ...)
420 anv_printflike(6, 7);
421 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
422 void anv_loge_v(const char *format
, va_list va
);
425 * Print a FINISHME message, including its source location.
427 #define anv_finishme(format, ...) \
429 static bool reported = false; \
431 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
438 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
440 #define anv_perf_warn(instance, obj, format, ...) \
442 static bool reported = false; \
443 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
444 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
445 format, ##__VA_ARGS__); \
450 /* A non-fatal assert. Useful for debugging. */
452 #define anv_assert(x) ({ \
453 if (unlikely(!(x))) \
454 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
457 #define anv_assert(x)
460 /* A multi-pointer allocator
462 * When copying data structures from the user (such as a render pass), it's
463 * common to need to allocate data for a bunch of different things. Instead
464 * of doing several allocations and having to handle all of the error checking
465 * that entails, it can be easier to do a single allocation. This struct
466 * helps facilitate that. The intended usage looks like this:
469 * anv_multialloc_add(&ma, &main_ptr, 1);
470 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
471 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
473 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
474 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
476 struct anv_multialloc
{
484 #define ANV_MULTIALLOC_INIT \
485 ((struct anv_multialloc) { 0, })
487 #define ANV_MULTIALLOC(_name) \
488 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
490 __attribute__((always_inline
))
492 _anv_multialloc_add(struct anv_multialloc
*ma
,
493 void **ptr
, size_t size
, size_t align
)
495 size_t offset
= align_u64(ma
->size
, align
);
496 ma
->size
= offset
+ size
;
497 ma
->align
= MAX2(ma
->align
, align
);
499 /* Store the offset in the pointer. */
500 *ptr
= (void *)(uintptr_t)offset
;
502 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
503 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
506 #define anv_multialloc_add_size(_ma, _ptr, _size) \
507 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
509 #define anv_multialloc_add(_ma, _ptr, _count) \
510 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
512 __attribute__((always_inline
))
514 anv_multialloc_alloc(struct anv_multialloc
*ma
,
515 const VkAllocationCallbacks
*alloc
,
516 VkSystemAllocationScope scope
)
518 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
522 /* Fill out each of the pointers with their final value.
524 * for (uint32_t i = 0; i < ma->ptr_count; i++)
525 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
527 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
528 * constant, GCC is incapable of figuring this out and unrolling the loop
529 * so we have to give it a little help.
531 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
532 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
533 if ((_i) < ma->ptr_count) \
534 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
535 _ANV_MULTIALLOC_UPDATE_POINTER(0);
536 _ANV_MULTIALLOC_UPDATE_POINTER(1);
537 _ANV_MULTIALLOC_UPDATE_POINTER(2);
538 _ANV_MULTIALLOC_UPDATE_POINTER(3);
539 _ANV_MULTIALLOC_UPDATE_POINTER(4);
540 _ANV_MULTIALLOC_UPDATE_POINTER(5);
541 _ANV_MULTIALLOC_UPDATE_POINTER(6);
542 _ANV_MULTIALLOC_UPDATE_POINTER(7);
543 #undef _ANV_MULTIALLOC_UPDATE_POINTER
548 __attribute__((always_inline
))
550 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
551 const VkAllocationCallbacks
*parent_alloc
,
552 const VkAllocationCallbacks
*alloc
,
553 VkSystemAllocationScope scope
)
555 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
561 /* Index into the current validation list. This is used by the
562 * validation list building alrogithm to track which buffers are already
563 * in the validation list so that we can ensure uniqueness.
567 /* Last known offset. This value is provided by the kernel when we
568 * execbuf and is used as the presumed offset for the next bunch of
576 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
581 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
583 bo
->gem_handle
= gem_handle
;
591 /* Represents a lock-free linked list of "free" things. This is used by
592 * both the block pool and the state pools. Unfortunately, in order to
593 * solve the ABA problem, we can't use a single uint32_t head.
595 union anv_free_list
{
599 /* A simple count that is incremented every time the head changes. */
605 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
607 struct anv_block_state
{
617 struct anv_block_pool
{
618 struct anv_device
*device
;
624 /* The address where the start of the pool is pinned. The various bos that
625 * are created as the pool grows will have addresses in the range
626 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
628 uint64_t start_address
;
630 /* The offset from the start of the bo to the "center" of the block
631 * pool. Pointers to allocated blocks are given by
632 * bo.map + center_bo_offset + offsets.
634 uint32_t center_bo_offset
;
636 /* Current memory map of the block pool. This pointer may or may not
637 * point to the actual beginning of the block pool memory. If
638 * anv_block_pool_alloc_back has ever been called, then this pointer
639 * will point to the "center" position of the buffer and all offsets
640 * (negative or positive) given out by the block pool alloc functions
641 * will be valid relative to this pointer.
643 * In particular, map == bo.map + center_offset
649 * Array of mmaps and gem handles owned by the block pool, reclaimed when
650 * the block pool is destroyed.
652 struct u_vector mmap_cleanups
;
654 struct anv_block_state state
;
656 struct anv_block_state back_state
;
659 /* Block pools are backed by a fixed-size 1GB memfd */
660 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
662 /* The center of the block pool is also the middle of the memfd. This may
663 * change in the future if we decide differently for some reason.
665 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
667 static inline uint32_t
668 anv_block_pool_size(struct anv_block_pool
*pool
)
670 return pool
->state
.end
+ pool
->back_state
.end
;
679 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
681 struct anv_fixed_size_state_pool
{
682 union anv_free_list free_list
;
683 struct anv_block_state block
;
686 #define ANV_MIN_STATE_SIZE_LOG2 6
687 #define ANV_MAX_STATE_SIZE_LOG2 20
689 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
691 struct anv_state_pool
{
692 struct anv_block_pool block_pool
;
694 /* The size of blocks which will be allocated from the block pool */
697 /** Free list for "back" allocations */
698 union anv_free_list back_alloc_free_list
;
700 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
703 struct anv_state_stream_block
;
705 struct anv_state_stream
{
706 struct anv_state_pool
*state_pool
;
708 /* The size of blocks to allocate from the state pool */
711 /* Current block we're allocating from */
712 struct anv_state block
;
714 /* Offset into the current block at which to allocate the next state */
717 /* List of all blocks allocated from this pool */
718 struct anv_state_stream_block
*block_list
;
721 /* The block_pool functions exported for testing only. The block pool should
722 * only be used via a state pool (see below).
724 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
725 struct anv_device
*device
,
726 uint64_t start_address
,
727 uint32_t initial_size
,
729 void anv_block_pool_finish(struct anv_block_pool
*pool
);
730 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
731 uint32_t block_size
);
732 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
733 uint32_t block_size
);
735 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
736 struct anv_device
*device
,
737 uint64_t start_address
,
740 void anv_state_pool_finish(struct anv_state_pool
*pool
);
741 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
742 uint32_t state_size
, uint32_t alignment
);
743 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
744 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
745 void anv_state_stream_init(struct anv_state_stream
*stream
,
746 struct anv_state_pool
*state_pool
,
747 uint32_t block_size
);
748 void anv_state_stream_finish(struct anv_state_stream
*stream
);
749 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
750 uint32_t size
, uint32_t alignment
);
753 * Implements a pool of re-usable BOs. The interface is identical to that
754 * of block_pool except that each block is its own BO.
757 struct anv_device
*device
;
764 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
766 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
767 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
769 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
771 struct anv_scratch_bo
{
776 struct anv_scratch_pool
{
777 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
778 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
781 void anv_scratch_pool_init(struct anv_device
*device
,
782 struct anv_scratch_pool
*pool
);
783 void anv_scratch_pool_finish(struct anv_device
*device
,
784 struct anv_scratch_pool
*pool
);
785 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
786 struct anv_scratch_pool
*pool
,
787 gl_shader_stage stage
,
788 unsigned per_thread_scratch
);
790 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
791 struct anv_bo_cache
{
792 struct hash_table
*bo_map
;
793 pthread_mutex_t mutex
;
796 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
797 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
798 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
799 struct anv_bo_cache
*cache
,
800 uint64_t size
, uint64_t bo_flags
,
802 VkResult
anv_bo_cache_import(struct anv_device
*device
,
803 struct anv_bo_cache
*cache
,
804 int fd
, uint64_t bo_flags
,
806 VkResult
anv_bo_cache_export(struct anv_device
*device
,
807 struct anv_bo_cache
*cache
,
808 struct anv_bo
*bo_in
, int *fd_out
);
809 void anv_bo_cache_release(struct anv_device
*device
,
810 struct anv_bo_cache
*cache
,
813 struct anv_memory_type
{
814 /* Standard bits passed on to the client */
815 VkMemoryPropertyFlags propertyFlags
;
818 /* Driver-internal book-keeping */
819 VkBufferUsageFlags valid_buffer_usage
;
822 struct anv_memory_heap
{
823 /* Standard bits passed on to the client */
825 VkMemoryHeapFlags flags
;
827 /* Driver-internal book-keeping */
828 bool supports_48bit_addresses
;
831 struct anv_physical_device
{
832 VK_LOADER_DATA _loader_data
;
834 struct anv_instance
* instance
;
839 struct gen_device_info info
;
840 /** Amount of "GPU memory" we want to advertise
842 * Clearly, this value is bogus since Intel is a UMA architecture. On
843 * gen7 platforms, we are limited by GTT size unless we want to implement
844 * fine-grained tracking and GTT splitting. On Broadwell and above we are
845 * practically unlimited. However, we will never report more than 3/4 of
846 * the total system ram to try and avoid running out of RAM.
848 bool supports_48bit_addresses
;
849 struct brw_compiler
* compiler
;
850 struct isl_device isl_dev
;
851 int cmd_parser_version
;
853 bool has_exec_capture
;
856 bool has_syncobj_wait
;
857 bool has_context_priority
;
859 bool has_context_isolation
;
861 struct anv_device_extension_table supported_extensions
;
864 uint32_t subslice_total
;
868 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
870 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
873 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
874 uint8_t driver_uuid
[VK_UUID_SIZE
];
875 uint8_t device_uuid
[VK_UUID_SIZE
];
877 struct wsi_device wsi_device
;
882 struct anv_instance
{
883 VK_LOADER_DATA _loader_data
;
885 VkAllocationCallbacks alloc
;
888 struct anv_instance_extension_table enabled_extensions
;
889 struct anv_dispatch_table dispatch
;
891 int physicalDeviceCount
;
892 struct anv_physical_device physicalDevice
;
894 struct vk_debug_report_instance debug_report_callbacks
;
897 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
898 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
900 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
901 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
905 VK_LOADER_DATA _loader_data
;
907 struct anv_device
* device
;
909 VkDeviceQueueCreateFlags flags
;
912 struct anv_pipeline_cache
{
913 struct anv_device
* device
;
914 pthread_mutex_t mutex
;
916 struct hash_table
* cache
;
919 struct anv_pipeline_bind_map
;
921 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
922 struct anv_device
*device
,
924 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
926 struct anv_shader_bin
*
927 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
928 const void *key
, uint32_t key_size
);
929 struct anv_shader_bin
*
930 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
931 const void *key_data
, uint32_t key_size
,
932 const void *kernel_data
, uint32_t kernel_size
,
933 const void *constant_data
,
934 uint32_t constant_data_size
,
935 const struct brw_stage_prog_data
*prog_data
,
936 uint32_t prog_data_size
,
937 const struct anv_pipeline_bind_map
*bind_map
);
940 VK_LOADER_DATA _loader_data
;
942 VkAllocationCallbacks alloc
;
944 struct anv_instance
* instance
;
947 struct gen_device_info info
;
948 struct isl_device isl_dev
;
951 bool can_chain_batches
;
952 bool robust_buffer_access
;
953 struct anv_device_extension_table enabled_extensions
;
954 struct anv_dispatch_table dispatch
;
956 pthread_mutex_t vma_mutex
;
957 struct util_vma_heap vma_lo
;
958 struct util_vma_heap vma_hi
;
959 uint64_t vma_lo_available
;
960 uint64_t vma_hi_available
;
962 struct anv_bo_pool batch_bo_pool
;
964 struct anv_bo_cache bo_cache
;
966 struct anv_state_pool dynamic_state_pool
;
967 struct anv_state_pool instruction_state_pool
;
968 struct anv_state_pool binding_table_pool
;
969 struct anv_state_pool surface_state_pool
;
971 struct anv_bo workaround_bo
;
972 struct anv_bo trivial_batch_bo
;
973 struct anv_bo hiz_clear_bo
;
975 struct anv_pipeline_cache blorp_shader_cache
;
976 struct blorp_context blorp
;
978 struct anv_state border_colors
;
980 struct anv_queue queue
;
982 struct anv_scratch_pool scratch_pool
;
984 uint32_t default_mocs
;
986 pthread_mutex_t mutex
;
987 pthread_cond_t queue_submit
;
991 static inline struct anv_state_pool
*
992 anv_binding_table_pool(struct anv_device
*device
)
994 if (device
->instance
->physicalDevice
.use_softpin
)
995 return &device
->binding_table_pool
;
997 return &device
->surface_state_pool
;
1000 static inline struct anv_state
1001 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1002 if (device
->instance
->physicalDevice
.use_softpin
)
1003 return anv_state_pool_alloc(&device
->binding_table_pool
,
1004 device
->binding_table_pool
.block_size
, 0);
1006 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1010 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1011 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1015 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
1017 if (device
->info
.has_llc
)
1020 gen_flush_range(state
.map
, state
.alloc_size
);
1023 void anv_device_init_blorp(struct anv_device
*device
);
1024 void anv_device_finish_blorp(struct anv_device
*device
);
1026 VkResult
anv_device_execbuf(struct anv_device
*device
,
1027 struct drm_i915_gem_execbuffer2
*execbuf
,
1028 struct anv_bo
**execbuf_bos
);
1029 VkResult
anv_device_query_status(struct anv_device
*device
);
1030 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1031 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1034 void* anv_gem_mmap(struct anv_device
*device
,
1035 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1036 void anv_gem_munmap(void *p
, uint64_t size
);
1037 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1038 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1039 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1040 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1041 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1042 int anv_gem_execbuffer(struct anv_device
*device
,
1043 struct drm_i915_gem_execbuffer2
*execbuf
);
1044 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1045 uint32_t stride
, uint32_t tiling
);
1046 int anv_gem_create_context(struct anv_device
*device
);
1047 bool anv_gem_has_context_priority(int fd
);
1048 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1049 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1051 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1053 int anv_gem_get_param(int fd
, uint32_t param
);
1054 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1055 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1056 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1057 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1058 uint32_t *active
, uint32_t *pending
);
1059 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1060 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1061 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1062 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1063 uint32_t read_domains
, uint32_t write_domain
);
1064 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1065 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1066 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1067 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1068 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1069 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1071 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1072 uint32_t handle
, int fd
);
1073 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1074 bool anv_gem_supports_syncobj_wait(int fd
);
1075 int anv_gem_syncobj_wait(struct anv_device
*device
,
1076 uint32_t *handles
, uint32_t num_handles
,
1077 int64_t abs_timeout_ns
, bool wait_all
);
1079 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1080 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1082 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1084 struct anv_reloc_list
{
1085 uint32_t num_relocs
;
1086 uint32_t array_length
;
1087 struct drm_i915_gem_relocation_entry
* relocs
;
1088 struct anv_bo
** reloc_bos
;
1092 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1093 const VkAllocationCallbacks
*alloc
);
1094 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1095 const VkAllocationCallbacks
*alloc
);
1097 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1098 const VkAllocationCallbacks
*alloc
,
1099 uint32_t offset
, struct anv_bo
*target_bo
,
1102 struct anv_batch_bo
{
1103 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1104 struct list_head link
;
1108 /* Bytes actually consumed in this batch BO */
1111 struct anv_reloc_list relocs
;
1115 const VkAllocationCallbacks
* alloc
;
1121 struct anv_reloc_list
* relocs
;
1123 /* This callback is called (with the associated user data) in the event
1124 * that the batch runs out of space.
1126 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1130 * Current error status of the command buffer. Used to track inconsistent
1131 * or incomplete command buffer states that are the consequence of run-time
1132 * errors such as out of memory scenarios. We want to track this in the
1133 * batch because the command buffer object is not visible to some parts
1139 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1140 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1141 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1142 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1143 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1144 struct anv_batch
*batch
);
1146 static inline VkResult
1147 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1149 assert(error
!= VK_SUCCESS
);
1150 if (batch
->status
== VK_SUCCESS
)
1151 batch
->status
= error
;
1152 return batch
->status
;
1156 anv_batch_has_error(struct anv_batch
*batch
)
1158 return batch
->status
!= VK_SUCCESS
;
1161 struct anv_address
{
1166 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1169 anv_address_is_null(struct anv_address addr
)
1171 return addr
.bo
== NULL
&& addr
.offset
== 0;
1174 static inline uint64_t
1175 anv_address_physical(struct anv_address addr
)
1177 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1178 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1180 return gen_canonical_address(addr
.offset
);
1183 static inline struct anv_address
1184 anv_address_add(struct anv_address addr
, uint64_t offset
)
1186 addr
.offset
+= offset
;
1191 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1193 unsigned reloc_size
= 0;
1194 if (device
->info
.gen
>= 8) {
1195 reloc_size
= sizeof(uint64_t);
1196 *(uint64_t *)p
= gen_canonical_address(v
);
1198 reloc_size
= sizeof(uint32_t);
1202 if (flush
&& !device
->info
.has_llc
)
1203 gen_flush_range(p
, reloc_size
);
1206 static inline uint64_t
1207 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1208 const struct anv_address address
, uint32_t delta
)
1210 if (address
.bo
== NULL
) {
1211 return address
.offset
+ delta
;
1213 assert(batch
->start
<= location
&& location
< batch
->end
);
1215 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1219 #define __gen_address_type struct anv_address
1220 #define __gen_user_data struct anv_batch
1221 #define __gen_combine_address _anv_combine_address
1223 /* Wrapper macros needed to work around preprocessor argument issues. In
1224 * particular, arguments don't get pre-evaluated if they are concatenated.
1225 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1226 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1227 * We can work around this easily enough with these helpers.
1229 #define __anv_cmd_length(cmd) cmd ## _length
1230 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1231 #define __anv_cmd_header(cmd) cmd ## _header
1232 #define __anv_cmd_pack(cmd) cmd ## _pack
1233 #define __anv_reg_num(reg) reg ## _num
1235 #define anv_pack_struct(dst, struc, ...) do { \
1236 struct struc __template = { \
1239 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1240 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1243 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1244 void *__dst = anv_batch_emit_dwords(batch, n); \
1246 struct cmd __template = { \
1247 __anv_cmd_header(cmd), \
1248 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1251 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1256 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1260 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1261 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1264 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1265 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1266 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1269 #define anv_batch_emit(batch, cmd, name) \
1270 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1271 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1272 __builtin_expect(_dst != NULL, 1); \
1273 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1274 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1278 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1279 .GraphicsDataTypeGFDT = 0, \
1280 .LLCCacheabilityControlLLCCC = 0, \
1281 .L3CacheabilityControlL3CC = 1, \
1284 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1285 .LLCeLLCCacheabilityControlLLCCC = 0, \
1286 .L3CacheabilityControlL3CC = 1, \
1289 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1290 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1291 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1292 .AgeforQUADLRU = 0 \
1295 /* Skylake: MOCS is now an index into an array of 62 different caching
1296 * configurations programmed by the kernel.
1299 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1300 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1301 .IndextoMOCSTables = 2 \
1304 #define GEN9_MOCS_PTE { \
1305 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1306 .IndextoMOCSTables = 1 \
1309 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1310 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1311 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1312 .IndextoMOCSTables = 2 \
1315 #define GEN10_MOCS_PTE { \
1316 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1317 .IndextoMOCSTables = 1 \
1320 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1321 #define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1322 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1323 .IndextoMOCSTables = 2 \
1326 #define GEN11_MOCS_PTE { \
1327 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1328 .IndextoMOCSTables = 1 \
1331 struct anv_device_memory
{
1333 struct anv_memory_type
* type
;
1334 VkDeviceSize map_size
;
1339 * Header for Vertex URB Entry (VUE)
1341 struct anv_vue_header
{
1343 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1344 uint32_t ViewportIndex
;
1348 struct anv_descriptor_set_binding_layout
{
1350 /* The type of the descriptors in this binding */
1351 VkDescriptorType type
;
1354 /* Number of array elements in this binding */
1355 uint16_t array_size
;
1357 /* Index into the flattend descriptor set */
1358 uint16_t descriptor_index
;
1360 /* Index into the dynamic state array for a dynamic buffer */
1361 int16_t dynamic_offset_index
;
1363 /* Index into the descriptor set buffer views */
1364 int16_t buffer_index
;
1367 /* Index into the binding table for the associated surface */
1368 int16_t surface_index
;
1370 /* Index into the sampler table for the associated sampler */
1371 int16_t sampler_index
;
1373 /* Index into the image table for the associated image */
1374 int16_t image_index
;
1375 } stage
[MESA_SHADER_STAGES
];
1377 /* Immutable samplers (or NULL if no immutable samplers) */
1378 struct anv_sampler
**immutable_samplers
;
1381 struct anv_descriptor_set_layout
{
1382 /* Descriptor set layouts can be destroyed at almost any time */
1385 /* Number of bindings in this descriptor set */
1386 uint16_t binding_count
;
1388 /* Total size of the descriptor set with room for all array entries */
1391 /* Shader stages affected by this descriptor set */
1392 uint16_t shader_stages
;
1394 /* Number of buffers in this descriptor set */
1395 uint16_t buffer_count
;
1397 /* Number of dynamic offsets used by this descriptor set */
1398 uint16_t dynamic_offset_count
;
1400 /* Bindings in this descriptor set */
1401 struct anv_descriptor_set_binding_layout binding
[0];
1405 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1407 assert(layout
&& layout
->ref_cnt
>= 1);
1408 p_atomic_inc(&layout
->ref_cnt
);
1412 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1413 struct anv_descriptor_set_layout
*layout
)
1415 assert(layout
&& layout
->ref_cnt
>= 1);
1416 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1417 vk_free(&device
->alloc
, layout
);
1420 struct anv_descriptor
{
1421 VkDescriptorType type
;
1425 VkImageLayout layout
;
1426 struct anv_image_view
*image_view
;
1427 struct anv_sampler
*sampler
;
1431 struct anv_buffer
*buffer
;
1436 struct anv_buffer_view
*buffer_view
;
1440 struct anv_descriptor_set
{
1441 struct anv_descriptor_set_layout
*layout
;
1443 uint32_t buffer_count
;
1444 struct anv_buffer_view
*buffer_views
;
1445 struct anv_descriptor descriptors
[0];
1448 struct anv_buffer_view
{
1449 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1450 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1452 struct anv_address address
;
1454 struct anv_state surface_state
;
1455 struct anv_state storage_surface_state
;
1456 struct anv_state writeonly_storage_surface_state
;
1458 struct brw_image_param storage_image_param
;
1461 struct anv_push_descriptor_set
{
1462 struct anv_descriptor_set set
;
1464 /* Put this field right behind anv_descriptor_set so it fills up the
1465 * descriptors[0] field. */
1466 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1467 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1470 struct anv_descriptor_pool
{
1475 struct anv_state_stream surface_state_stream
;
1476 void *surface_state_free_list
;
1481 enum anv_descriptor_template_entry_type
{
1482 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1483 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1484 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1487 struct anv_descriptor_template_entry
{
1488 /* The type of descriptor in this entry */
1489 VkDescriptorType type
;
1491 /* Binding in the descriptor set */
1494 /* Offset at which to write into the descriptor set binding */
1495 uint32_t array_element
;
1497 /* Number of elements to write into the descriptor set binding */
1498 uint32_t array_count
;
1500 /* Offset into the user provided data */
1503 /* Stride between elements into the user provided data */
1507 struct anv_descriptor_update_template
{
1508 VkPipelineBindPoint bind_point
;
1510 /* The descriptor set this template corresponds to. This value is only
1511 * valid if the template was created with the templateType
1512 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1516 /* Number of entries in this template */
1517 uint32_t entry_count
;
1519 /* Entries of the template */
1520 struct anv_descriptor_template_entry entries
[0];
1524 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout
*binding
);
1527 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1530 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1531 const struct gen_device_info
* const devinfo
,
1532 const VkDescriptorImageInfo
* const info
,
1533 VkDescriptorType type
,
1538 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1539 VkDescriptorType type
,
1540 struct anv_buffer_view
*buffer_view
,
1545 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1546 struct anv_device
*device
,
1547 struct anv_state_stream
*alloc_stream
,
1548 VkDescriptorType type
,
1549 struct anv_buffer
*buffer
,
1552 VkDeviceSize offset
,
1553 VkDeviceSize range
);
1556 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1557 struct anv_device
*device
,
1558 struct anv_state_stream
*alloc_stream
,
1559 const struct anv_descriptor_update_template
*template,
1563 anv_descriptor_set_create(struct anv_device
*device
,
1564 struct anv_descriptor_pool
*pool
,
1565 struct anv_descriptor_set_layout
*layout
,
1566 struct anv_descriptor_set
**out_set
);
1569 anv_descriptor_set_destroy(struct anv_device
*device
,
1570 struct anv_descriptor_pool
*pool
,
1571 struct anv_descriptor_set
*set
);
1573 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1575 struct anv_pipeline_binding
{
1576 /* The descriptor set this surface corresponds to. The special value of
1577 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1578 * to a color attachment and not a regular descriptor.
1582 /* Binding in the descriptor set */
1585 /* Index in the binding */
1588 /* Plane in the binding index */
1591 /* Input attachment index (relative to the subpass) */
1592 uint8_t input_attachment_index
;
1594 /* For a storage image, whether it is write-only */
1598 struct anv_pipeline_layout
{
1600 struct anv_descriptor_set_layout
*layout
;
1601 uint32_t dynamic_offset_start
;
1607 bool has_dynamic_offsets
;
1608 } stage
[MESA_SHADER_STAGES
];
1610 unsigned char sha1
[20];
1614 struct anv_device
* device
;
1617 VkBufferUsageFlags usage
;
1619 /* Set when bound */
1620 struct anv_address address
;
1623 static inline uint64_t
1624 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1626 assert(offset
<= buffer
->size
);
1627 if (range
== VK_WHOLE_SIZE
) {
1628 return buffer
->size
- offset
;
1630 assert(range
<= buffer
->size
);
1635 enum anv_cmd_dirty_bits
{
1636 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1637 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1638 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1639 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1640 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1641 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1642 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1643 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1644 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1645 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1646 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1647 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1648 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1650 typedef uint32_t anv_cmd_dirty_mask_t
;
1652 enum anv_pipe_bits
{
1653 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1654 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1655 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1656 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1657 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1658 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1659 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1660 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1661 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1662 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1663 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1665 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1666 * a flush has happened but not a CS stall. The next time we do any sort
1667 * of invalidation we need to insert a CS stall at that time. Otherwise,
1668 * we would have to CS stall on every flush which could be bad.
1670 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1673 #define ANV_PIPE_FLUSH_BITS ( \
1674 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1675 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1676 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1678 #define ANV_PIPE_STALL_BITS ( \
1679 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1680 ANV_PIPE_DEPTH_STALL_BIT | \
1681 ANV_PIPE_CS_STALL_BIT)
1683 #define ANV_PIPE_INVALIDATE_BITS ( \
1684 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1685 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1686 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1687 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1688 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1689 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1691 static inline enum anv_pipe_bits
1692 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1694 enum anv_pipe_bits pipe_bits
= 0;
1697 for_each_bit(b
, flags
) {
1698 switch ((VkAccessFlagBits
)(1 << b
)) {
1699 case VK_ACCESS_SHADER_WRITE_BIT
:
1700 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1702 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1703 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1705 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1706 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1708 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1709 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1710 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1713 break; /* Nothing to do */
1720 static inline enum anv_pipe_bits
1721 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1723 enum anv_pipe_bits pipe_bits
= 0;
1726 for_each_bit(b
, flags
) {
1727 switch ((VkAccessFlagBits
)(1 << b
)) {
1728 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1729 case VK_ACCESS_INDEX_READ_BIT
:
1730 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1731 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1733 case VK_ACCESS_UNIFORM_READ_BIT
:
1734 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1735 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1737 case VK_ACCESS_SHADER_READ_BIT
:
1738 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1739 case VK_ACCESS_TRANSFER_READ_BIT
:
1740 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1743 break; /* Nothing to do */
1750 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1751 VK_IMAGE_ASPECT_COLOR_BIT | \
1752 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1753 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1754 VK_IMAGE_ASPECT_PLANE_2_BIT)
1755 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1756 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1757 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1758 VK_IMAGE_ASPECT_PLANE_2_BIT)
1760 struct anv_vertex_binding
{
1761 struct anv_buffer
* buffer
;
1762 VkDeviceSize offset
;
1765 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1766 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1768 struct anv_push_constants
{
1769 /* Current allocated size of this push constants data structure.
1770 * Because a decent chunk of it may not be used (images on SKL, for
1771 * instance), we won't actually allocate the entire structure up-front.
1775 /* Push constant data provided by the client through vkPushConstants */
1776 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1778 /* Used for vkCmdDispatchBase */
1779 uint32_t base_work_group_id
[3];
1781 /* Image data for image_load_store on pre-SKL */
1782 struct brw_image_param images
[MAX_IMAGES
];
1785 struct anv_dynamic_state
{
1788 VkViewport viewports
[MAX_VIEWPORTS
];
1793 VkRect2D scissors
[MAX_SCISSORS
];
1804 float blend_constants
[4];
1814 } stencil_compare_mask
;
1819 } stencil_write_mask
;
1824 } stencil_reference
;
1827 extern const struct anv_dynamic_state default_dynamic_state
;
1829 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1830 const struct anv_dynamic_state
*src
,
1831 uint32_t copy_mask
);
1833 struct anv_surface_state
{
1834 struct anv_state state
;
1835 /** Address of the surface referred to by this state
1837 * This address is relative to the start of the BO.
1839 struct anv_address address
;
1840 /* Address of the aux surface, if any
1842 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
1844 * With the exception of gen8, the bottom 12 bits of this address' offset
1845 * include extra aux information.
1847 struct anv_address aux_address
;
1848 /* Address of the clear color, if any
1850 * This address is relative to the start of the BO.
1852 struct anv_address clear_address
;
1856 * Attachment state when recording a renderpass instance.
1858 * The clear value is valid only if there exists a pending clear.
1860 struct anv_attachment_state
{
1861 enum isl_aux_usage aux_usage
;
1862 enum isl_aux_usage input_aux_usage
;
1863 struct anv_surface_state color
;
1864 struct anv_surface_state input
;
1866 VkImageLayout current_layout
;
1867 VkImageAspectFlags pending_clear_aspects
;
1868 VkImageAspectFlags pending_load_aspects
;
1870 VkClearValue clear_value
;
1871 bool clear_color_is_zero_one
;
1872 bool clear_color_is_zero
;
1874 /* When multiview is active, attachments with a renderpass clear
1875 * operation have their respective layers cleared on the first
1876 * subpass that uses them, and only in that subpass. We keep track
1877 * of this using a bitfield to indicate which layers of an attachment
1878 * have not been cleared yet when multiview is active.
1880 uint32_t pending_clear_views
;
1883 /** State tracking for particular pipeline bind point
1885 * This struct is the base struct for anv_cmd_graphics_state and
1886 * anv_cmd_compute_state. These are used to track state which is bound to a
1887 * particular type of pipeline. Generic state that applies per-stage such as
1888 * binding table offsets and push constants is tracked generically with a
1889 * per-stage array in anv_cmd_state.
1891 struct anv_cmd_pipeline_state
{
1892 struct anv_pipeline
*pipeline
;
1893 struct anv_pipeline_layout
*layout
;
1895 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
1896 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
1898 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
1901 /** State tracking for graphics pipeline
1903 * This has anv_cmd_pipeline_state as a base struct to track things which get
1904 * bound to a graphics pipeline. Along with general pipeline bind point state
1905 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1906 * state which is graphics-specific.
1908 struct anv_cmd_graphics_state
{
1909 struct anv_cmd_pipeline_state base
;
1911 anv_cmd_dirty_mask_t dirty
;
1914 struct anv_dynamic_state dynamic
;
1917 struct anv_buffer
*index_buffer
;
1918 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1919 uint32_t index_offset
;
1923 /** State tracking for compute pipeline
1925 * This has anv_cmd_pipeline_state as a base struct to track things which get
1926 * bound to a compute pipeline. Along with general pipeline bind point state
1927 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1928 * state which is compute-specific.
1930 struct anv_cmd_compute_state
{
1931 struct anv_cmd_pipeline_state base
;
1933 bool pipeline_dirty
;
1935 struct anv_address num_workgroups
;
1938 /** State required while building cmd buffer */
1939 struct anv_cmd_state
{
1940 /* PIPELINE_SELECT.PipelineSelection */
1941 uint32_t current_pipeline
;
1942 const struct gen_l3_config
* current_l3_config
;
1944 struct anv_cmd_graphics_state gfx
;
1945 struct anv_cmd_compute_state compute
;
1947 enum anv_pipe_bits pending_pipe_bits
;
1948 VkShaderStageFlags descriptors_dirty
;
1949 VkShaderStageFlags push_constants_dirty
;
1951 struct anv_framebuffer
* framebuffer
;
1952 struct anv_render_pass
* pass
;
1953 struct anv_subpass
* subpass
;
1954 VkRect2D render_area
;
1955 uint32_t restart_index
;
1956 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1957 VkShaderStageFlags push_constant_stages
;
1958 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1959 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1960 struct anv_state samplers
[MESA_SHADER_STAGES
];
1963 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1964 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1965 * and before invoking the secondary in ExecuteCommands.
1967 bool pma_fix_enabled
;
1970 * Whether or not we know for certain that HiZ is enabled for the current
1971 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1972 * enabled or not, this will be false.
1977 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1978 * valid only when recording a render pass instance.
1980 struct anv_attachment_state
* attachments
;
1983 * Surface states for color render targets. These are stored in a single
1984 * flat array. For depth-stencil attachments, the surface state is simply
1987 struct anv_state render_pass_states
;
1990 * A null surface state of the right size to match the framebuffer. This
1991 * is one of the states in render_pass_states.
1993 struct anv_state null_surface_state
;
1996 struct anv_cmd_pool
{
1997 VkAllocationCallbacks alloc
;
1998 struct list_head cmd_buffers
;
2001 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2003 enum anv_cmd_buffer_exec_mode
{
2004 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2005 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2006 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2007 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2008 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2011 struct anv_cmd_buffer
{
2012 VK_LOADER_DATA _loader_data
;
2014 struct anv_device
* device
;
2016 struct anv_cmd_pool
* pool
;
2017 struct list_head pool_link
;
2019 struct anv_batch batch
;
2021 /* Fields required for the actual chain of anv_batch_bo's.
2023 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2025 struct list_head batch_bos
;
2026 enum anv_cmd_buffer_exec_mode exec_mode
;
2028 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2029 * referenced by this command buffer
2031 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2033 struct u_vector seen_bbos
;
2035 /* A vector of int32_t's for every block of binding tables.
2037 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2039 struct u_vector bt_block_states
;
2042 struct anv_reloc_list surface_relocs
;
2043 /** Last seen surface state block pool center bo offset */
2044 uint32_t last_ss_pool_center
;
2046 /* Serial for tracking buffer completion */
2049 /* Stream objects for storing temporary data */
2050 struct anv_state_stream surface_state_stream
;
2051 struct anv_state_stream dynamic_state_stream
;
2053 VkCommandBufferUsageFlags usage_flags
;
2054 VkCommandBufferLevel level
;
2056 struct anv_cmd_state state
;
2059 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2060 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2061 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2062 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2063 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2064 struct anv_cmd_buffer
*secondary
);
2065 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2066 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2067 struct anv_cmd_buffer
*cmd_buffer
,
2068 const VkSemaphore
*in_semaphores
,
2069 uint32_t num_in_semaphores
,
2070 const VkSemaphore
*out_semaphores
,
2071 uint32_t num_out_semaphores
,
2074 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2077 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
2078 gl_shader_stage stage
, uint32_t size
);
2079 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
2080 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
2081 (offsetof(struct anv_push_constants, field) + \
2082 sizeof(cmd_buffer->state.push_constants[0]->field)))
2084 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2085 const void *data
, uint32_t size
, uint32_t alignment
);
2086 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2087 uint32_t *a
, uint32_t *b
,
2088 uint32_t dwords
, uint32_t alignment
);
2091 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2093 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2094 uint32_t entries
, uint32_t *state_offset
);
2096 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2098 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2099 uint32_t size
, uint32_t alignment
);
2102 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2104 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2105 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2106 bool depth_clamp_enable
);
2107 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2109 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2110 struct anv_render_pass
*pass
,
2111 struct anv_framebuffer
*framebuffer
,
2112 const VkClearValue
*clear_values
);
2114 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2117 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2118 gl_shader_stage stage
);
2120 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2122 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
2124 const struct anv_image_view
*
2125 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2128 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2129 uint32_t num_entries
,
2130 uint32_t *state_offset
,
2131 struct anv_state
*bt_state
);
2133 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2135 enum anv_fence_type
{
2136 ANV_FENCE_TYPE_NONE
= 0,
2138 ANV_FENCE_TYPE_SYNCOBJ
,
2142 enum anv_bo_fence_state
{
2143 /** Indicates that this is a new (or newly reset fence) */
2144 ANV_BO_FENCE_STATE_RESET
,
2146 /** Indicates that this fence has been submitted to the GPU but is still
2147 * (as far as we know) in use by the GPU.
2149 ANV_BO_FENCE_STATE_SUBMITTED
,
2151 ANV_BO_FENCE_STATE_SIGNALED
,
2154 struct anv_fence_impl
{
2155 enum anv_fence_type type
;
2158 /** Fence implementation for BO fences
2160 * These fences use a BO and a set of CPU-tracked state flags. The BO
2161 * is added to the object list of the last execbuf call in a QueueSubmit
2162 * and is marked EXEC_WRITE. The state flags track when the BO has been
2163 * submitted to the kernel. We need to do this because Vulkan lets you
2164 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2165 * will say it's idle in this case.
2169 enum anv_bo_fence_state state
;
2172 /** DRM syncobj handle for syncobj-based fences */
2176 struct wsi_fence
*fence_wsi
;
2181 /* Permanent fence state. Every fence has some form of permanent state
2182 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2183 * cross-process fences) or it could just be a dummy for use internally.
2185 struct anv_fence_impl permanent
;
2187 /* Temporary fence state. A fence *may* have temporary state. That state
2188 * is added to the fence by an import operation and is reset back to
2189 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2190 * state cannot be signaled because the fence must already be signaled
2191 * before the temporary state can be exported from the fence in the other
2192 * process and imported here.
2194 struct anv_fence_impl temporary
;
2199 struct anv_state state
;
2202 enum anv_semaphore_type
{
2203 ANV_SEMAPHORE_TYPE_NONE
= 0,
2204 ANV_SEMAPHORE_TYPE_DUMMY
,
2205 ANV_SEMAPHORE_TYPE_BO
,
2206 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2207 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2210 struct anv_semaphore_impl
{
2211 enum anv_semaphore_type type
;
2214 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2215 * This BO will be added to the object list on any execbuf2 calls for
2216 * which this semaphore is used as a wait or signal fence. When used as
2217 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2221 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2222 * If the semaphore is in the unsignaled state due to either just being
2223 * created or because it has been used for a wait, fd will be -1.
2227 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2228 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2229 * import so we don't need to bother with a userspace cache.
2235 struct anv_semaphore
{
2236 /* Permanent semaphore state. Every semaphore has some form of permanent
2237 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2238 * (for cross-process semaphores0 or it could just be a dummy for use
2241 struct anv_semaphore_impl permanent
;
2243 /* Temporary semaphore state. A semaphore *may* have temporary state.
2244 * That state is added to the semaphore by an import operation and is reset
2245 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2246 * semaphore with temporary state cannot be signaled because the semaphore
2247 * must already be signaled before the temporary state can be exported from
2248 * the semaphore in the other process and imported here.
2250 struct anv_semaphore_impl temporary
;
2253 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2254 struct anv_semaphore
*semaphore
);
2256 struct anv_shader_module
{
2257 unsigned char sha1
[20];
2262 static inline gl_shader_stage
2263 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2265 assert(__builtin_popcount(vk_stage
) == 1);
2266 return ffs(vk_stage
) - 1;
2269 static inline VkShaderStageFlagBits
2270 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2272 return (1 << mesa_stage
);
2275 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2277 #define anv_foreach_stage(stage, stage_bits) \
2278 for (gl_shader_stage stage, \
2279 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2280 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2281 __tmp &= ~(1 << (stage)))
2283 struct anv_pipeline_bind_map
{
2284 uint32_t surface_count
;
2285 uint32_t sampler_count
;
2286 uint32_t image_count
;
2288 struct anv_pipeline_binding
* surface_to_descriptor
;
2289 struct anv_pipeline_binding
* sampler_to_descriptor
;
2292 struct anv_shader_bin_key
{
2297 struct anv_shader_bin
{
2300 const struct anv_shader_bin_key
*key
;
2302 struct anv_state kernel
;
2303 uint32_t kernel_size
;
2305 struct anv_state constant_data
;
2306 uint32_t constant_data_size
;
2308 const struct brw_stage_prog_data
*prog_data
;
2309 uint32_t prog_data_size
;
2311 struct anv_pipeline_bind_map bind_map
;
2314 struct anv_shader_bin
*
2315 anv_shader_bin_create(struct anv_device
*device
,
2316 const void *key
, uint32_t key_size
,
2317 const void *kernel
, uint32_t kernel_size
,
2318 const void *constant_data
, uint32_t constant_data_size
,
2319 const struct brw_stage_prog_data
*prog_data
,
2320 uint32_t prog_data_size
, const void *prog_data_param
,
2321 const struct anv_pipeline_bind_map
*bind_map
);
2324 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2327 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2329 assert(shader
&& shader
->ref_cnt
>= 1);
2330 p_atomic_inc(&shader
->ref_cnt
);
2334 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2336 assert(shader
&& shader
->ref_cnt
>= 1);
2337 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2338 anv_shader_bin_destroy(device
, shader
);
2341 struct anv_pipeline
{
2342 struct anv_device
* device
;
2343 struct anv_batch batch
;
2344 uint32_t batch_data
[512];
2345 struct anv_reloc_list batch_relocs
;
2346 uint32_t dynamic_state_mask
;
2347 struct anv_dynamic_state dynamic_state
;
2349 struct anv_subpass
* subpass
;
2351 bool needs_data_cache
;
2353 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2356 const struct gen_l3_config
* l3_config
;
2357 uint32_t total_size
;
2360 VkShaderStageFlags active_stages
;
2361 struct anv_state blend_state
;
2364 uint32_t binding_stride
[MAX_VBS
];
2365 bool instancing_enable
[MAX_VBS
];
2366 bool primitive_restart
;
2369 uint32_t cs_right_mask
;
2372 bool depth_test_enable
;
2373 bool writes_stencil
;
2374 bool stencil_test_enable
;
2375 bool depth_clamp_enable
;
2376 bool sample_shading_enable
;
2381 uint32_t depth_stencil_state
[3];
2387 uint32_t wm_depth_stencil
[3];
2391 uint32_t wm_depth_stencil
[4];
2394 uint32_t interface_descriptor_data
[8];
2398 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2399 gl_shader_stage stage
)
2401 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2404 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2405 static inline const struct brw_##prefix##_prog_data * \
2406 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2408 if (anv_pipeline_has_stage(pipeline, stage)) { \
2409 return (const struct brw_##prefix##_prog_data *) \
2410 pipeline->shaders[stage]->prog_data; \
2416 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2417 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2418 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2419 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2420 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2421 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2423 static inline const struct brw_vue_prog_data
*
2424 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2426 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2427 return &get_gs_prog_data(pipeline
)->base
;
2428 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2429 return &get_tes_prog_data(pipeline
)->base
;
2431 return &get_vs_prog_data(pipeline
)->base
;
2435 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2436 struct anv_pipeline_cache
*cache
,
2437 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2438 const VkAllocationCallbacks
*alloc
);
2441 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2442 struct anv_pipeline_cache
*cache
,
2443 const VkComputePipelineCreateInfo
*info
,
2444 struct anv_shader_module
*module
,
2445 const char *entrypoint
,
2446 const VkSpecializationInfo
*spec_info
);
2448 struct anv_format_plane
{
2449 enum isl_format isl_format
:16;
2450 struct isl_swizzle swizzle
;
2452 /* Whether this plane contains chroma channels */
2455 /* For downscaling of YUV planes */
2456 uint8_t denominator_scales
[2];
2458 /* How to map sampled ycbcr planes to a single 4 component element. */
2459 struct isl_swizzle ycbcr_swizzle
;
2464 struct anv_format_plane planes
[3];
2469 static inline uint32_t
2470 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2471 VkImageAspectFlags aspect_mask
)
2473 switch (aspect_mask
) {
2474 case VK_IMAGE_ASPECT_COLOR_BIT
:
2475 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2476 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2478 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2479 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2482 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2484 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2487 /* Purposefully assert with depth/stencil aspects. */
2488 unreachable("invalid image aspect");
2492 static inline uint32_t
2493 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask
)
2495 uint32_t planes
= 0;
2497 if (aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
|
2498 VK_IMAGE_ASPECT_DEPTH_BIT
|
2499 VK_IMAGE_ASPECT_STENCIL_BIT
|
2500 VK_IMAGE_ASPECT_PLANE_0_BIT
))
2502 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_1_BIT
)
2504 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_2_BIT
)
2507 if ((aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) != 0 &&
2508 (aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) != 0)
2514 static inline VkImageAspectFlags
2515 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
2518 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2519 if (_mesa_bitcount(image_aspects
) > 1)
2520 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
2521 return VK_IMAGE_ASPECT_COLOR_BIT
;
2523 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
2524 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
2525 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
2526 return VK_IMAGE_ASPECT_STENCIL_BIT
;
2529 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2530 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2532 const struct anv_format
*
2533 anv_get_format(VkFormat format
);
2535 static inline uint32_t
2536 anv_get_format_planes(VkFormat vk_format
)
2538 const struct anv_format
*format
= anv_get_format(vk_format
);
2540 return format
!= NULL
? format
->n_planes
: 0;
2543 struct anv_format_plane
2544 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2545 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
2547 static inline enum isl_format
2548 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2549 VkImageAspectFlags aspect
, VkImageTiling tiling
)
2551 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
2554 static inline struct isl_swizzle
2555 anv_swizzle_for_render(struct isl_swizzle swizzle
)
2557 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2558 * RGB as RGBA for texturing
2560 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
2561 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
2563 /* But it doesn't matter what we render to that channel */
2564 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
2570 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
2573 * Subsurface of an anv_image.
2575 struct anv_surface
{
2576 /** Valid only if isl_surf::size > 0. */
2577 struct isl_surf isl
;
2580 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2587 /* The original VkFormat provided by the client. This may not match any
2588 * of the actual surface formats.
2591 const struct anv_format
*format
;
2593 VkImageAspectFlags aspects
;
2596 uint32_t array_size
;
2597 uint32_t samples
; /**< VkImageCreateInfo::samples */
2599 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2600 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2602 /** True if this is needs to be bound to an appropriately tiled BO.
2604 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2605 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2606 * we require a dedicated allocation so that we can know to allocate a
2609 bool needs_set_tiling
;
2612 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2613 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2615 uint64_t drm_format_mod
;
2620 /* Whether the image is made of several underlying buffer objects rather a
2621 * single one with different offsets.
2628 * For each foo, anv_image::planes[x].surface is valid if and only if
2629 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2630 * to figure the number associated with a given aspect.
2632 * The hardware requires that the depth buffer and stencil buffer be
2633 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2634 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2635 * allocate the depth and stencil buffers as separate surfaces in the same
2640 * -----------------------
2642 * ----------------------- |
2643 * | shadow surface0 | |
2644 * ----------------------- | Plane 0
2645 * | aux surface0 | |
2646 * ----------------------- |
2647 * | fast clear colors0 | \|/
2648 * -----------------------
2650 * ----------------------- |
2651 * | shadow surface1 | |
2652 * ----------------------- | Plane 1
2653 * | aux surface1 | |
2654 * ----------------------- |
2655 * | fast clear colors1 | \|/
2656 * -----------------------
2659 * -----------------------
2663 * Offset of the entire plane (whenever the image is disjoint this is
2671 struct anv_surface surface
;
2674 * A surface which shadows the main surface and may have different
2675 * tiling. This is used for sampling using a tiling that isn't supported
2676 * for other operations.
2678 struct anv_surface shadow_surface
;
2681 * For color images, this is the aux usage for this image when not used
2682 * as a color attachment.
2684 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2685 * image has a HiZ buffer.
2687 enum isl_aux_usage aux_usage
;
2689 struct anv_surface aux_surface
;
2692 * Offset of the fast clear state (used to compute the
2693 * fast_clear_state_offset of the following planes).
2695 uint32_t fast_clear_state_offset
;
2698 * BO associated with this plane, set when bound.
2700 struct anv_address address
;
2703 * When destroying the image, also free the bo.
2709 /* The ordering of this enum is important */
2710 enum anv_fast_clear_type
{
2711 /** Image does not have/support any fast-clear blocks */
2712 ANV_FAST_CLEAR_NONE
= 0,
2713 /** Image has/supports fast-clear but only to the default value */
2714 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
2715 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2716 ANV_FAST_CLEAR_ANY
= 2,
2719 /* Returns the number of auxiliary buffer levels attached to an image. */
2720 static inline uint8_t
2721 anv_image_aux_levels(const struct anv_image
* const image
,
2722 VkImageAspectFlagBits aspect
)
2724 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2725 return image
->planes
[plane
].aux_surface
.isl
.size
> 0 ?
2726 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
2729 /* Returns the number of auxiliary buffer layers attached to an image. */
2730 static inline uint32_t
2731 anv_image_aux_layers(const struct anv_image
* const image
,
2732 VkImageAspectFlagBits aspect
,
2733 const uint8_t miplevel
)
2737 /* The miplevel must exist in the main buffer. */
2738 assert(miplevel
< image
->levels
);
2740 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
2741 /* There are no layers with auxiliary data because the miplevel has no
2746 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2747 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
2748 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
2752 static inline struct anv_address
2753 anv_image_get_clear_color_addr(const struct anv_device
*device
,
2754 const struct anv_image
*image
,
2755 VkImageAspectFlagBits aspect
)
2757 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
2759 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2760 return anv_address_add(image
->planes
[plane
].address
,
2761 image
->planes
[plane
].fast_clear_state_offset
);
2764 static inline struct anv_address
2765 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
2766 const struct anv_image
*image
,
2767 VkImageAspectFlagBits aspect
)
2769 struct anv_address addr
=
2770 anv_image_get_clear_color_addr(device
, image
, aspect
);
2772 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
2773 device
->isl_dev
.ss
.clear_color_state_size
:
2774 device
->isl_dev
.ss
.clear_value_size
;
2775 addr
.offset
+= clear_color_state_size
;
2779 static inline struct anv_address
2780 anv_image_get_compression_state_addr(const struct anv_device
*device
,
2781 const struct anv_image
*image
,
2782 VkImageAspectFlagBits aspect
,
2783 uint32_t level
, uint32_t array_layer
)
2785 assert(level
< anv_image_aux_levels(image
, aspect
));
2786 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
2787 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2788 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
2790 struct anv_address addr
=
2791 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
2792 addr
.offset
+= 4; /* Go past the fast clear type */
2794 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2795 for (uint32_t l
= 0; l
< level
; l
++)
2796 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
2798 addr
.offset
+= level
* image
->array_size
* 4;
2800 addr
.offset
+= array_layer
* 4;
2805 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2807 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
2808 const struct anv_image
*image
)
2810 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
2813 if (devinfo
->gen
< 8)
2816 return image
->samples
== 1;
2820 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
2821 const struct anv_image
*image
,
2822 VkImageAspectFlagBits aspect
,
2823 enum isl_aux_usage aux_usage
,
2825 uint32_t base_layer
,
2826 uint32_t layer_count
);
2829 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
2830 const struct anv_image
*image
,
2831 VkImageAspectFlagBits aspect
,
2832 enum isl_aux_usage aux_usage
,
2833 enum isl_format format
, struct isl_swizzle swizzle
,
2834 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
2835 VkRect2D area
, union isl_color_value clear_color
);
2837 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
2838 const struct anv_image
*image
,
2839 VkImageAspectFlags aspects
,
2840 enum isl_aux_usage depth_aux_usage
,
2842 uint32_t base_layer
, uint32_t layer_count
,
2844 float depth_value
, uint8_t stencil_value
);
2846 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
2847 const struct anv_image
*image
,
2848 VkImageAspectFlagBits aspect
, uint32_t level
,
2849 uint32_t base_layer
, uint32_t layer_count
,
2850 enum isl_aux_op hiz_op
);
2852 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
2853 const struct anv_image
*image
,
2854 VkImageAspectFlags aspects
,
2856 uint32_t base_layer
, uint32_t layer_count
,
2857 VkRect2D area
, uint8_t stencil_value
);
2859 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
2860 const struct anv_image
*image
,
2861 VkImageAspectFlagBits aspect
,
2862 uint32_t base_layer
, uint32_t layer_count
,
2863 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
2866 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
2867 const struct anv_image
*image
,
2868 VkImageAspectFlagBits aspect
, uint32_t level
,
2869 uint32_t base_layer
, uint32_t layer_count
,
2870 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
2874 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
2875 const struct anv_image
*image
,
2876 uint32_t base_level
, uint32_t level_count
,
2877 uint32_t base_layer
, uint32_t layer_count
);
2880 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
2881 const struct anv_image
*image
,
2882 const VkImageAspectFlagBits aspect
,
2883 const VkImageLayout layout
);
2885 enum anv_fast_clear_type
2886 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
2887 const struct anv_image
* const image
,
2888 const VkImageAspectFlagBits aspect
,
2889 const VkImageLayout layout
);
2891 /* This is defined as a macro so that it works for both
2892 * VkImageSubresourceRange and VkImageSubresourceLayers
2894 #define anv_get_layerCount(_image, _range) \
2895 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2896 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2898 static inline uint32_t
2899 anv_get_levelCount(const struct anv_image
*image
,
2900 const VkImageSubresourceRange
*range
)
2902 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
2903 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
2906 static inline VkImageAspectFlags
2907 anv_image_expand_aspects(const struct anv_image
*image
,
2908 VkImageAspectFlags aspects
)
2910 /* If the underlying image has color plane aspects and
2911 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2912 * the underlying image. */
2913 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
2914 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
2915 return image
->aspects
;
2921 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
2922 VkImageAspectFlags aspects2
)
2924 if (aspects1
== aspects2
)
2927 /* Only 1 color aspects are compatibles. */
2928 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
2929 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
2930 _mesa_bitcount(aspects1
) == _mesa_bitcount(aspects2
))
2936 struct anv_image_view
{
2937 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
2939 VkImageAspectFlags aspect_mask
;
2941 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2945 uint32_t image_plane
;
2947 struct isl_view isl
;
2950 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2951 * image layout of SHADER_READ_ONLY_OPTIMAL or
2952 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2954 struct anv_surface_state optimal_sampler_surface_state
;
2957 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2958 * image layout of GENERAL.
2960 struct anv_surface_state general_sampler_surface_state
;
2963 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2964 * states for write-only and readable, using the real format for
2965 * write-only and the lowered format for readable.
2967 struct anv_surface_state storage_surface_state
;
2968 struct anv_surface_state writeonly_storage_surface_state
;
2970 struct brw_image_param storage_image_param
;
2974 enum anv_image_view_state_flags
{
2975 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
2976 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
2979 void anv_image_fill_surface_state(struct anv_device
*device
,
2980 const struct anv_image
*image
,
2981 VkImageAspectFlagBits aspect
,
2982 const struct isl_view
*view
,
2983 isl_surf_usage_flags_t view_usage
,
2984 enum isl_aux_usage aux_usage
,
2985 const union isl_color_value
*clear_color
,
2986 enum anv_image_view_state_flags flags
,
2987 struct anv_surface_state
*state_inout
,
2988 struct brw_image_param
*image_param_out
);
2990 struct anv_image_create_info
{
2991 const VkImageCreateInfo
*vk_info
;
2993 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2994 isl_tiling_flags_t isl_tiling_flags
;
2996 /** These flags will be added to any derived from VkImageCreateInfo. */
2997 isl_surf_usage_flags_t isl_extra_usage_flags
;
3002 VkResult
anv_image_create(VkDevice _device
,
3003 const struct anv_image_create_info
*info
,
3004 const VkAllocationCallbacks
* alloc
,
3008 VkResult
anv_image_from_gralloc(VkDevice device_h
,
3009 const VkImageCreateInfo
*base_info
,
3010 const VkNativeBufferANDROID
*gralloc_info
,
3011 const VkAllocationCallbacks
*alloc
,
3015 const struct anv_surface
*
3016 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3017 VkImageAspectFlags aspect_mask
);
3020 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3022 static inline struct VkExtent3D
3023 anv_sanitize_image_extent(const VkImageType imageType
,
3024 const struct VkExtent3D imageExtent
)
3026 switch (imageType
) {
3027 case VK_IMAGE_TYPE_1D
:
3028 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3029 case VK_IMAGE_TYPE_2D
:
3030 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3031 case VK_IMAGE_TYPE_3D
:
3034 unreachable("invalid image type");
3038 static inline struct VkOffset3D
3039 anv_sanitize_image_offset(const VkImageType imageType
,
3040 const struct VkOffset3D imageOffset
)
3042 switch (imageType
) {
3043 case VK_IMAGE_TYPE_1D
:
3044 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3045 case VK_IMAGE_TYPE_2D
:
3046 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3047 case VK_IMAGE_TYPE_3D
:
3050 unreachable("invalid image type");
3055 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3056 struct anv_state state
,
3057 enum isl_format format
,
3058 struct anv_address address
,
3059 uint32_t range
, uint32_t stride
);
3062 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3063 const struct anv_attachment_state
*att_state
,
3064 const struct anv_image_view
*iview
)
3066 const struct isl_format_layout
*view_fmtl
=
3067 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3069 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3070 if (view_fmtl->channels.c.bits) \
3071 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3073 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3074 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3075 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3076 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3078 #undef COPY_CLEAR_COLOR_CHANNEL
3082 struct anv_ycbcr_conversion
{
3083 const struct anv_format
* format
;
3084 VkSamplerYcbcrModelConversion ycbcr_model
;
3085 VkSamplerYcbcrRange ycbcr_range
;
3086 VkComponentSwizzle mapping
[4];
3087 VkChromaLocation chroma_offsets
[2];
3088 VkFilter chroma_filter
;
3089 bool chroma_reconstruction
;
3092 struct anv_sampler
{
3093 uint32_t state
[3][4];
3095 struct anv_ycbcr_conversion
*conversion
;
3098 struct anv_framebuffer
{
3103 uint32_t attachment_count
;
3104 struct anv_image_view
* attachments
[0];
3107 struct anv_subpass_attachment
{
3108 VkImageUsageFlagBits usage
;
3109 uint32_t attachment
;
3110 VkImageLayout layout
;
3113 struct anv_subpass
{
3114 uint32_t attachment_count
;
3117 * A pointer to all attachment references used in this subpass.
3118 * Only valid if ::attachment_count > 0.
3120 struct anv_subpass_attachment
* attachments
;
3121 uint32_t input_count
;
3122 struct anv_subpass_attachment
* input_attachments
;
3123 uint32_t color_count
;
3124 struct anv_subpass_attachment
* color_attachments
;
3125 struct anv_subpass_attachment
* resolve_attachments
;
3127 struct anv_subpass_attachment depth_stencil_attachment
;
3131 /** Subpass has a depth/stencil self-dependency */
3132 bool has_ds_self_dep
;
3134 /** Subpass has at least one resolve attachment */
3138 static inline unsigned
3139 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3141 return MAX2(1, _mesa_bitcount(subpass
->view_mask
));
3144 struct anv_render_pass_attachment
{
3145 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3146 * its members individually.
3150 VkImageUsageFlags usage
;
3151 VkAttachmentLoadOp load_op
;
3152 VkAttachmentStoreOp store_op
;
3153 VkAttachmentLoadOp stencil_load_op
;
3154 VkImageLayout initial_layout
;
3155 VkImageLayout final_layout
;
3156 VkImageLayout first_subpass_layout
;
3158 /* The subpass id in which the attachment will be used last. */
3159 uint32_t last_subpass_idx
;
3162 struct anv_render_pass
{
3163 uint32_t attachment_count
;
3164 uint32_t subpass_count
;
3165 /* An array of subpass_count+1 flushes, one per subpass boundary */
3166 enum anv_pipe_bits
* subpass_flushes
;
3167 struct anv_render_pass_attachment
* attachments
;
3168 struct anv_subpass subpasses
[0];
3171 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3173 struct anv_query_pool
{
3175 VkQueryPipelineStatisticFlags pipeline_statistics
;
3176 /** Stride between slots, in bytes */
3178 /** Number of slots in this query pool */
3183 int anv_get_entrypoint_index(const char *name
);
3186 anv_entrypoint_is_enabled(int index
, uint32_t core_version
,
3187 const struct anv_instance_extension_table
*instance
,
3188 const struct anv_device_extension_table
*device
);
3190 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3193 void anv_dump_image_to_ppm(struct anv_device
*device
,
3194 struct anv_image
*image
, unsigned miplevel
,
3195 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3196 const char *filename
);
3198 enum anv_dump_action
{
3199 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3202 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3203 void anv_dump_finish(void);
3205 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
3206 struct anv_framebuffer
*fb
);
3208 static inline uint32_t
3209 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3211 /* This function must be called from within a subpass. */
3212 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3214 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3216 /* The id of this subpass shouldn't exceed the number of subpasses in this
3217 * render pass minus 1.
3219 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3223 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3225 static inline struct __anv_type * \
3226 __anv_type ## _from_handle(__VkType _handle) \
3228 return (struct __anv_type *) _handle; \
3231 static inline __VkType \
3232 __anv_type ## _to_handle(struct __anv_type *_obj) \
3234 return (__VkType) _obj; \
3237 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3239 static inline struct __anv_type * \
3240 __anv_type ## _from_handle(__VkType _handle) \
3242 return (struct __anv_type *)(uintptr_t) _handle; \
3245 static inline __VkType \
3246 __anv_type ## _to_handle(struct __anv_type *_obj) \
3248 return (__VkType)(uintptr_t) _obj; \
3251 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3252 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3254 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3255 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3256 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3257 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3258 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3260 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3261 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3262 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3263 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3264 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3265 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3266 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
3267 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3268 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3269 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3270 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3271 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3272 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3273 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3274 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3275 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3276 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3277 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3278 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3279 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3280 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3281 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3282 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3284 /* Gen-specific function declarations */
3286 # include "anv_genX.h"
3288 # define genX(x) gen7_##x
3289 # include "anv_genX.h"
3291 # define genX(x) gen75_##x
3292 # include "anv_genX.h"
3294 # define genX(x) gen8_##x
3295 # include "anv_genX.h"
3297 # define genX(x) gen9_##x
3298 # include "anv_genX.h"
3300 # define genX(x) gen10_##x
3301 # include "anv_genX.h"
3303 # define genX(x) gen11_##x
3304 # include "anv_genX.h"
3308 #endif /* ANV_PRIVATE_H */