anv: Add func anv_image_has_hiz()
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #pragma once
25
26 #include <stdlib.h>
27 #include <stdio.h>
28 #include <stdbool.h>
29 #include <pthread.h>
30 #include <assert.h>
31 #include <stdint.h>
32 #include <i915_drm.h>
33
34 #ifdef HAVE_VALGRIND
35 #include <valgrind.h>
36 #include <memcheck.h>
37 #define VG(x) x
38 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
39 #else
40 #define VG(x)
41 #endif
42
43 #include "common/gen_device_info.h"
44 #include "blorp/blorp.h"
45 #include "brw_compiler.h"
46 #include "util/macros.h"
47 #include "util/list.h"
48
49 /* Pre-declarations needed for WSI entrypoints */
50 struct wl_surface;
51 struct wl_display;
52 typedef struct xcb_connection_t xcb_connection_t;
53 typedef uint32_t xcb_visualid_t;
54 typedef uint32_t xcb_window_t;
55
56 struct gen_l3_config;
57
58 #include <vulkan/vulkan.h>
59 #include <vulkan/vulkan_intel.h>
60 #include <vulkan/vk_icd.h>
61
62 #include "anv_entrypoints.h"
63 #include "brw_context.h"
64 #include "isl/isl.h"
65
66 #ifdef __cplusplus
67 extern "C" {
68 #endif
69
70 #define MAX_VBS 32
71 #define MAX_SETS 8
72 #define MAX_RTS 8
73 #define MAX_VIEWPORTS 16
74 #define MAX_SCISSORS 16
75 #define MAX_PUSH_CONSTANTS_SIZE 128
76 #define MAX_DYNAMIC_BUFFERS 16
77 #define MAX_IMAGES 8
78 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
79
80 #define anv_noreturn __attribute__((__noreturn__))
81 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
82
83 #define MIN(a, b) ((a) < (b) ? (a) : (b))
84 #define MAX(a, b) ((a) > (b) ? (a) : (b))
85
86 static inline uint32_t
87 align_down_npot_u32(uint32_t v, uint32_t a)
88 {
89 return v - (v % a);
90 }
91
92 static inline uint32_t
93 align_u32(uint32_t v, uint32_t a)
94 {
95 assert(a != 0 && a == (a & -a));
96 return (v + a - 1) & ~(a - 1);
97 }
98
99 static inline uint64_t
100 align_u64(uint64_t v, uint64_t a)
101 {
102 assert(a != 0 && a == (a & -a));
103 return (v + a - 1) & ~(a - 1);
104 }
105
106 static inline int32_t
107 align_i32(int32_t v, int32_t a)
108 {
109 assert(a != 0 && a == (a & -a));
110 return (v + a - 1) & ~(a - 1);
111 }
112
113 /** Alignment must be a power of 2. */
114 static inline bool
115 anv_is_aligned(uintmax_t n, uintmax_t a)
116 {
117 assert(a == (a & -a));
118 return (n & (a - 1)) == 0;
119 }
120
121 static inline uint32_t
122 anv_minify(uint32_t n, uint32_t levels)
123 {
124 if (unlikely(n == 0))
125 return 0;
126 else
127 return MAX(n >> levels, 1);
128 }
129
130 static inline float
131 anv_clamp_f(float f, float min, float max)
132 {
133 assert(min < max);
134
135 if (f > max)
136 return max;
137 else if (f < min)
138 return min;
139 else
140 return f;
141 }
142
143 static inline bool
144 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
145 {
146 if (*inout_mask & clear_mask) {
147 *inout_mask &= ~clear_mask;
148 return true;
149 } else {
150 return false;
151 }
152 }
153
154 #define for_each_bit(b, dword) \
155 for (uint32_t __dword = (dword); \
156 (b) = __builtin_ffs(__dword) - 1, __dword; \
157 __dword &= ~(1 << (b)))
158
159 #define typed_memcpy(dest, src, count) ({ \
160 static_assert(sizeof(*src) == sizeof(*dest), ""); \
161 memcpy((dest), (src), (count) * sizeof(*(src))); \
162 })
163
164 #define zero(x) (memset(&(x), 0, sizeof(x)))
165
166 /* Define no kernel as 1, since that's an illegal offset for a kernel */
167 #define NO_KERNEL 1
168
169 struct anv_common {
170 VkStructureType sType;
171 const void* pNext;
172 };
173
174 /* Whenever we generate an error, pass it through this function. Useful for
175 * debugging, where we can break on it. Only call at error site, not when
176 * propagating errors. Might be useful to plug in a stack trace here.
177 */
178
179 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
180
181 #ifdef DEBUG
182 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
183 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
184 #else
185 #define vk_error(error) error
186 #define vk_errorf(error, format, ...) error
187 #endif
188
189 void __anv_finishme(const char *file, int line, const char *format, ...)
190 anv_printflike(3, 4);
191 void anv_loge(const char *format, ...) anv_printflike(1, 2);
192 void anv_loge_v(const char *format, va_list va);
193
194 /**
195 * Print a FINISHME message, including its source location.
196 */
197 #define anv_finishme(format, ...) \
198 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
199
200 /* A non-fatal assert. Useful for debugging. */
201 #ifdef DEBUG
202 #define anv_assert(x) ({ \
203 if (unlikely(!(x))) \
204 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
205 })
206 #else
207 #define anv_assert(x)
208 #endif
209
210 /**
211 * If a block of code is annotated with anv_validate, then the block runs only
212 * in debug builds.
213 */
214 #ifdef DEBUG
215 #define anv_validate if (1)
216 #else
217 #define anv_validate if (0)
218 #endif
219
220 void anv_abortf(const char *format, ...) anv_noreturn anv_printflike(1, 2);
221 void anv_abortfv(const char *format, va_list va) anv_noreturn;
222
223 #define stub_return(v) \
224 do { \
225 anv_finishme("stub %s", __func__); \
226 return (v); \
227 } while (0)
228
229 #define stub() \
230 do { \
231 anv_finishme("stub %s", __func__); \
232 return; \
233 } while (0)
234
235 /**
236 * A dynamically growable, circular buffer. Elements are added at head and
237 * removed from tail. head and tail are free-running uint32_t indices and we
238 * only compute the modulo with size when accessing the array. This way,
239 * number of bytes in the queue is always head - tail, even in case of
240 * wraparound.
241 */
242
243 struct anv_vector {
244 uint32_t head;
245 uint32_t tail;
246 uint32_t element_size;
247 uint32_t size;
248 void *data;
249 };
250
251 int anv_vector_init(struct anv_vector *queue, uint32_t element_size, uint32_t size);
252 void *anv_vector_add(struct anv_vector *queue);
253 void *anv_vector_remove(struct anv_vector *queue);
254
255 static inline int
256 anv_vector_length(struct anv_vector *queue)
257 {
258 return (queue->head - queue->tail) / queue->element_size;
259 }
260
261 static inline void *
262 anv_vector_head(struct anv_vector *vector)
263 {
264 assert(vector->tail < vector->head);
265 return (void *)((char *)vector->data +
266 ((vector->head - vector->element_size) &
267 (vector->size - 1)));
268 }
269
270 static inline void *
271 anv_vector_tail(struct anv_vector *vector)
272 {
273 return (void *)((char *)vector->data + (vector->tail & (vector->size - 1)));
274 }
275
276 static inline void
277 anv_vector_finish(struct anv_vector *queue)
278 {
279 free(queue->data);
280 }
281
282 #define anv_vector_foreach(elem, queue) \
283 static_assert(__builtin_types_compatible_p(__typeof__(queue), struct anv_vector *), ""); \
284 for (uint32_t __anv_vector_offset = (queue)->tail; \
285 elem = (queue)->data + (__anv_vector_offset & ((queue)->size - 1)), __anv_vector_offset < (queue)->head; \
286 __anv_vector_offset += (queue)->element_size)
287
288 struct anv_bo {
289 uint32_t gem_handle;
290
291 /* Index into the current validation list. This is used by the
292 * validation list building alrogithm to track which buffers are already
293 * in the validation list so that we can ensure uniqueness.
294 */
295 uint32_t index;
296
297 /* Last known offset. This value is provided by the kernel when we
298 * execbuf and is used as the presumed offset for the next bunch of
299 * relocations.
300 */
301 uint64_t offset;
302
303 uint64_t size;
304 void *map;
305
306 /* We need to set the WRITE flag on winsys bos so GEM will know we're
307 * writing to them and synchronize uses on other rings (eg if the display
308 * server uses the blitter ring).
309 */
310 bool is_winsys_bo;
311 };
312
313 /* Represents a lock-free linked list of "free" things. This is used by
314 * both the block pool and the state pools. Unfortunately, in order to
315 * solve the ABA problem, we can't use a single uint32_t head.
316 */
317 union anv_free_list {
318 struct {
319 int32_t offset;
320
321 /* A simple count that is incremented every time the head changes. */
322 uint32_t count;
323 };
324 uint64_t u64;
325 };
326
327 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
328
329 struct anv_block_state {
330 union {
331 struct {
332 uint32_t next;
333 uint32_t end;
334 };
335 uint64_t u64;
336 };
337 };
338
339 struct anv_block_pool {
340 struct anv_device *device;
341
342 struct anv_bo bo;
343
344 /* The offset from the start of the bo to the "center" of the block
345 * pool. Pointers to allocated blocks are given by
346 * bo.map + center_bo_offset + offsets.
347 */
348 uint32_t center_bo_offset;
349
350 /* Current memory map of the block pool. This pointer may or may not
351 * point to the actual beginning of the block pool memory. If
352 * anv_block_pool_alloc_back has ever been called, then this pointer
353 * will point to the "center" position of the buffer and all offsets
354 * (negative or positive) given out by the block pool alloc functions
355 * will be valid relative to this pointer.
356 *
357 * In particular, map == bo.map + center_offset
358 */
359 void *map;
360 int fd;
361
362 /**
363 * Array of mmaps and gem handles owned by the block pool, reclaimed when
364 * the block pool is destroyed.
365 */
366 struct anv_vector mmap_cleanups;
367
368 uint32_t block_size;
369
370 union anv_free_list free_list;
371 struct anv_block_state state;
372
373 union anv_free_list back_free_list;
374 struct anv_block_state back_state;
375 };
376
377 /* Block pools are backed by a fixed-size 2GB memfd */
378 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
379
380 /* The center of the block pool is also the middle of the memfd. This may
381 * change in the future if we decide differently for some reason.
382 */
383 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
384
385 static inline uint32_t
386 anv_block_pool_size(struct anv_block_pool *pool)
387 {
388 return pool->state.end + pool->back_state.end;
389 }
390
391 struct anv_state {
392 int32_t offset;
393 uint32_t alloc_size;
394 void *map;
395 };
396
397 struct anv_fixed_size_state_pool {
398 size_t state_size;
399 union anv_free_list free_list;
400 struct anv_block_state block;
401 };
402
403 #define ANV_MIN_STATE_SIZE_LOG2 6
404 #define ANV_MAX_STATE_SIZE_LOG2 17
405
406 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
407
408 struct anv_state_pool {
409 struct anv_block_pool *block_pool;
410 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
411 };
412
413 struct anv_state_stream_block;
414
415 struct anv_state_stream {
416 struct anv_block_pool *block_pool;
417
418 /* The current working block */
419 struct anv_state_stream_block *block;
420
421 /* Offset at which the current block starts */
422 uint32_t start;
423 /* Offset at which to allocate the next state */
424 uint32_t next;
425 /* Offset at which the current block ends */
426 uint32_t end;
427 };
428
429 #define CACHELINE_SIZE 64
430 #define CACHELINE_MASK 63
431
432 static inline void
433 anv_clflush_range(void *start, size_t size)
434 {
435 void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
436 void *end = start + size;
437
438 __builtin_ia32_mfence();
439 while (p < end) {
440 __builtin_ia32_clflush(p);
441 p += CACHELINE_SIZE;
442 }
443 }
444
445 static void inline
446 anv_state_clflush(struct anv_state state)
447 {
448 anv_clflush_range(state.map, state.alloc_size);
449 }
450
451 void anv_block_pool_init(struct anv_block_pool *pool,
452 struct anv_device *device, uint32_t block_size);
453 void anv_block_pool_finish(struct anv_block_pool *pool);
454 int32_t anv_block_pool_alloc(struct anv_block_pool *pool);
455 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool);
456 void anv_block_pool_free(struct anv_block_pool *pool, int32_t offset);
457 void anv_state_pool_init(struct anv_state_pool *pool,
458 struct anv_block_pool *block_pool);
459 void anv_state_pool_finish(struct anv_state_pool *pool);
460 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
461 size_t state_size, size_t alignment);
462 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
463 void anv_state_stream_init(struct anv_state_stream *stream,
464 struct anv_block_pool *block_pool);
465 void anv_state_stream_finish(struct anv_state_stream *stream);
466 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
467 uint32_t size, uint32_t alignment);
468
469 /**
470 * Implements a pool of re-usable BOs. The interface is identical to that
471 * of block_pool except that each block is its own BO.
472 */
473 struct anv_bo_pool {
474 struct anv_device *device;
475
476 void *free_list[16];
477 };
478
479 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
480 void anv_bo_pool_finish(struct anv_bo_pool *pool);
481 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
482 uint32_t size);
483 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
484
485 struct anv_scratch_pool {
486 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
487 struct anv_bo bos[16][MESA_SHADER_STAGES];
488 };
489
490 void anv_scratch_pool_init(struct anv_device *device,
491 struct anv_scratch_pool *pool);
492 void anv_scratch_pool_finish(struct anv_device *device,
493 struct anv_scratch_pool *pool);
494 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
495 struct anv_scratch_pool *pool,
496 gl_shader_stage stage,
497 unsigned per_thread_scratch);
498
499 void *anv_resolve_entrypoint(uint32_t index);
500
501 extern struct anv_dispatch_table dtable;
502
503 #define ANV_CALL(func) ({ \
504 if (dtable.func == NULL) { \
505 size_t idx = offsetof(struct anv_dispatch_table, func) / sizeof(void *); \
506 dtable.entrypoints[idx] = anv_resolve_entrypoint(idx); \
507 } \
508 dtable.func; \
509 })
510
511 static inline void *
512 anv_alloc(const VkAllocationCallbacks *alloc,
513 size_t size, size_t align,
514 VkSystemAllocationScope scope)
515 {
516 return alloc->pfnAllocation(alloc->pUserData, size, align, scope);
517 }
518
519 static inline void *
520 anv_realloc(const VkAllocationCallbacks *alloc,
521 void *ptr, size_t size, size_t align,
522 VkSystemAllocationScope scope)
523 {
524 return alloc->pfnReallocation(alloc->pUserData, ptr, size, align, scope);
525 }
526
527 static inline void
528 anv_free(const VkAllocationCallbacks *alloc, void *data)
529 {
530 alloc->pfnFree(alloc->pUserData, data);
531 }
532
533 static inline void *
534 anv_alloc2(const VkAllocationCallbacks *parent_alloc,
535 const VkAllocationCallbacks *alloc,
536 size_t size, size_t align,
537 VkSystemAllocationScope scope)
538 {
539 if (alloc)
540 return anv_alloc(alloc, size, align, scope);
541 else
542 return anv_alloc(parent_alloc, size, align, scope);
543 }
544
545 static inline void
546 anv_free2(const VkAllocationCallbacks *parent_alloc,
547 const VkAllocationCallbacks *alloc,
548 void *data)
549 {
550 if (alloc)
551 anv_free(alloc, data);
552 else
553 anv_free(parent_alloc, data);
554 }
555
556 struct anv_wsi_interaface;
557
558 #define VK_ICD_WSI_PLATFORM_MAX 5
559
560 struct anv_physical_device {
561 VK_LOADER_DATA _loader_data;
562
563 struct anv_instance * instance;
564 uint32_t chipset_id;
565 char path[20];
566 const char * name;
567 struct gen_device_info info;
568 uint64_t aperture_size;
569 struct brw_compiler * compiler;
570 struct isl_device isl_dev;
571 int cmd_parser_version;
572
573 uint32_t eu_total;
574 uint32_t subslice_total;
575
576 struct anv_wsi_interface * wsi[VK_ICD_WSI_PLATFORM_MAX];
577 };
578
579 struct anv_instance {
580 VK_LOADER_DATA _loader_data;
581
582 VkAllocationCallbacks alloc;
583
584 uint32_t apiVersion;
585 int physicalDeviceCount;
586 struct anv_physical_device physicalDevice;
587 };
588
589 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
590 void anv_finish_wsi(struct anv_physical_device *physical_device);
591
592 struct anv_meta_state {
593 VkAllocationCallbacks alloc;
594
595 /**
596 * Use array element `i` for images with `2^i` samples.
597 */
598 struct {
599 /**
600 * Pipeline N is used to clear color attachment N of the current
601 * subpass.
602 *
603 * HACK: We use one pipeline per color attachment to work around the
604 * compiler's inability to dynamically set the render target index of
605 * the render target write message.
606 */
607 struct anv_pipeline *color_pipelines[MAX_RTS];
608
609 struct anv_pipeline *depth_only_pipeline;
610 struct anv_pipeline *stencil_only_pipeline;
611 struct anv_pipeline *depthstencil_pipeline;
612 } clear[1 + MAX_SAMPLES_LOG2];
613
614 struct {
615 VkRenderPass render_pass;
616
617 /** Pipeline that blits from a 1D image. */
618 VkPipeline pipeline_1d_src;
619
620 /** Pipeline that blits from a 2D image. */
621 VkPipeline pipeline_2d_src;
622
623 /** Pipeline that blits from a 3D image. */
624 VkPipeline pipeline_3d_src;
625
626 VkPipelineLayout pipeline_layout;
627 VkDescriptorSetLayout ds_layout;
628 } blit;
629
630 struct {
631 VkRenderPass render_pass;
632
633 VkPipelineLayout img_p_layout;
634 VkDescriptorSetLayout img_ds_layout;
635 VkPipelineLayout buf_p_layout;
636 VkDescriptorSetLayout buf_ds_layout;
637
638 /* Pipelines indexed by source and destination type. See the
639 * blit2d_src_type and blit2d_dst_type enums in anv_meta_blit2d.c to
640 * see what these mean.
641 */
642 VkPipeline pipelines[2][3];
643 } blit2d;
644
645 struct {
646 /** Pipeline [i] resolves an image with 2^(i+1) samples. */
647 VkPipeline pipelines[MAX_SAMPLES_LOG2];
648
649 VkRenderPass pass;
650 VkPipelineLayout pipeline_layout;
651 VkDescriptorSetLayout ds_layout;
652 } resolve;
653 };
654
655 struct anv_queue {
656 VK_LOADER_DATA _loader_data;
657
658 struct anv_device * device;
659
660 struct anv_state_pool * pool;
661 };
662
663 struct anv_pipeline_cache {
664 struct anv_device * device;
665 pthread_mutex_t mutex;
666
667 struct hash_table * cache;
668 };
669
670 struct anv_pipeline_bind_map;
671
672 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
673 struct anv_device *device,
674 bool cache_enabled);
675 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
676
677 struct anv_shader_bin *
678 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
679 const void *key, uint32_t key_size);
680 struct anv_shader_bin *
681 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
682 const void *key_data, uint32_t key_size,
683 const void *kernel_data, uint32_t kernel_size,
684 const void *prog_data, uint32_t prog_data_size,
685 const struct anv_pipeline_bind_map *bind_map);
686
687 struct anv_device {
688 VK_LOADER_DATA _loader_data;
689
690 VkAllocationCallbacks alloc;
691
692 struct anv_instance * instance;
693 uint32_t chipset_id;
694 struct gen_device_info info;
695 struct isl_device isl_dev;
696 int context_id;
697 int fd;
698 bool can_chain_batches;
699 bool robust_buffer_access;
700
701 struct anv_bo_pool batch_bo_pool;
702
703 struct anv_block_pool dynamic_state_block_pool;
704 struct anv_state_pool dynamic_state_pool;
705
706 struct anv_block_pool instruction_block_pool;
707 struct anv_state_pool instruction_state_pool;
708
709 struct anv_block_pool surface_state_block_pool;
710 struct anv_state_pool surface_state_pool;
711
712 struct anv_bo workaround_bo;
713
714 struct anv_meta_state meta_state;
715
716 struct anv_pipeline_cache blorp_shader_cache;
717 struct blorp_context blorp;
718
719 struct anv_state border_colors;
720
721 struct anv_queue queue;
722
723 struct anv_scratch_pool scratch_pool;
724
725 uint32_t default_mocs;
726
727 pthread_mutex_t mutex;
728 };
729
730 void anv_device_get_cache_uuid(void *uuid);
731
732 void anv_device_init_blorp(struct anv_device *device);
733 void anv_device_finish_blorp(struct anv_device *device);
734
735 void* anv_gem_mmap(struct anv_device *device,
736 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
737 void anv_gem_munmap(void *p, uint64_t size);
738 uint32_t anv_gem_create(struct anv_device *device, size_t size);
739 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
740 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
741 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
742 int anv_gem_execbuffer(struct anv_device *device,
743 struct drm_i915_gem_execbuffer2 *execbuf);
744 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
745 uint32_t stride, uint32_t tiling);
746 int anv_gem_create_context(struct anv_device *device);
747 int anv_gem_destroy_context(struct anv_device *device, int context);
748 int anv_gem_get_param(int fd, uint32_t param);
749 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
750 int anv_gem_get_aperture(int fd, uint64_t *size);
751 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
752 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
753 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
754 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
755 uint32_t read_domains, uint32_t write_domain);
756
757 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
758
759 struct anv_reloc_list {
760 size_t num_relocs;
761 size_t array_length;
762 struct drm_i915_gem_relocation_entry * relocs;
763 struct anv_bo ** reloc_bos;
764 };
765
766 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
767 const VkAllocationCallbacks *alloc);
768 void anv_reloc_list_finish(struct anv_reloc_list *list,
769 const VkAllocationCallbacks *alloc);
770
771 uint64_t anv_reloc_list_add(struct anv_reloc_list *list,
772 const VkAllocationCallbacks *alloc,
773 uint32_t offset, struct anv_bo *target_bo,
774 uint32_t delta);
775
776 struct anv_batch_bo {
777 /* Link in the anv_cmd_buffer.owned_batch_bos list */
778 struct list_head link;
779
780 struct anv_bo bo;
781
782 /* Bytes actually consumed in this batch BO */
783 size_t length;
784
785 /* Last seen surface state block pool bo offset */
786 uint32_t last_ss_pool_bo_offset;
787
788 struct anv_reloc_list relocs;
789 };
790
791 struct anv_batch {
792 const VkAllocationCallbacks * alloc;
793
794 void * start;
795 void * end;
796 void * next;
797
798 struct anv_reloc_list * relocs;
799
800 /* This callback is called (with the associated user data) in the event
801 * that the batch runs out of space.
802 */
803 VkResult (*extend_cb)(struct anv_batch *, void *);
804 void * user_data;
805 };
806
807 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
808 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
809 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
810 void *location, struct anv_bo *bo, uint32_t offset);
811 VkResult anv_device_submit_simple_batch(struct anv_device *device,
812 struct anv_batch *batch);
813
814 struct anv_address {
815 struct anv_bo *bo;
816 uint32_t offset;
817 };
818
819 static inline uint64_t
820 _anv_combine_address(struct anv_batch *batch, void *location,
821 const struct anv_address address, uint32_t delta)
822 {
823 if (address.bo == NULL) {
824 return address.offset + delta;
825 } else {
826 assert(batch->start <= location && location < batch->end);
827
828 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
829 }
830 }
831
832 #define __gen_address_type struct anv_address
833 #define __gen_user_data struct anv_batch
834 #define __gen_combine_address _anv_combine_address
835
836 /* Wrapper macros needed to work around preprocessor argument issues. In
837 * particular, arguments don't get pre-evaluated if they are concatenated.
838 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
839 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
840 * We can work around this easily enough with these helpers.
841 */
842 #define __anv_cmd_length(cmd) cmd ## _length
843 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
844 #define __anv_cmd_header(cmd) cmd ## _header
845 #define __anv_cmd_pack(cmd) cmd ## _pack
846 #define __anv_reg_num(reg) reg ## _num
847
848 #define anv_pack_struct(dst, struc, ...) do { \
849 struct struc __template = { \
850 __VA_ARGS__ \
851 }; \
852 __anv_cmd_pack(struc)(NULL, dst, &__template); \
853 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
854 } while (0)
855
856 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
857 void *__dst = anv_batch_emit_dwords(batch, n); \
858 struct cmd __template = { \
859 __anv_cmd_header(cmd), \
860 .DWordLength = n - __anv_cmd_length_bias(cmd), \
861 __VA_ARGS__ \
862 }; \
863 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
864 __dst; \
865 })
866
867 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
868 do { \
869 uint32_t *dw; \
870 \
871 static_assert(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1), "mismatch merge"); \
872 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
873 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
874 dw[i] = (dwords0)[i] | (dwords1)[i]; \
875 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
876 } while (0)
877
878 #define anv_batch_emit(batch, cmd, name) \
879 for (struct cmd name = { __anv_cmd_header(cmd) }, \
880 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
881 __builtin_expect(_dst != NULL, 1); \
882 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
883 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
884 _dst = NULL; \
885 }))
886
887 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
888 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
889 struct anv_state __state = \
890 anv_state_pool_alloc((pool), __size, align); \
891 struct cmd __template = { \
892 __VA_ARGS__ \
893 }; \
894 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
895 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
896 if (!(pool)->block_pool->device->info.has_llc) \
897 anv_state_clflush(__state); \
898 __state; \
899 })
900
901 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
902 .GraphicsDataTypeGFDT = 0, \
903 .LLCCacheabilityControlLLCCC = 0, \
904 .L3CacheabilityControlL3CC = 1, \
905 }
906
907 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
908 .LLCeLLCCacheabilityControlLLCCC = 0, \
909 .L3CacheabilityControlL3CC = 1, \
910 }
911
912 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
913 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
914 .TargetCache = L3DefertoPATforLLCeLLCselection, \
915 .AgeforQUADLRU = 0 \
916 }
917
918 /* Skylake: MOCS is now an index into an array of 62 different caching
919 * configurations programmed by the kernel.
920 */
921
922 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
923 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
924 .IndextoMOCSTables = 2 \
925 }
926
927 #define GEN9_MOCS_PTE { \
928 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
929 .IndextoMOCSTables = 1 \
930 }
931
932 struct anv_device_memory {
933 struct anv_bo bo;
934 uint32_t type_index;
935 VkDeviceSize map_size;
936 void * map;
937 };
938
939 /**
940 * Header for Vertex URB Entry (VUE)
941 */
942 struct anv_vue_header {
943 uint32_t Reserved;
944 uint32_t RTAIndex; /* RenderTargetArrayIndex */
945 uint32_t ViewportIndex;
946 float PointWidth;
947 };
948
949 struct anv_descriptor_set_binding_layout {
950 #ifndef NDEBUG
951 /* The type of the descriptors in this binding */
952 VkDescriptorType type;
953 #endif
954
955 /* Number of array elements in this binding */
956 uint16_t array_size;
957
958 /* Index into the flattend descriptor set */
959 uint16_t descriptor_index;
960
961 /* Index into the dynamic state array for a dynamic buffer */
962 int16_t dynamic_offset_index;
963
964 /* Index into the descriptor set buffer views */
965 int16_t buffer_index;
966
967 struct {
968 /* Index into the binding table for the associated surface */
969 int16_t surface_index;
970
971 /* Index into the sampler table for the associated sampler */
972 int16_t sampler_index;
973
974 /* Index into the image table for the associated image */
975 int16_t image_index;
976 } stage[MESA_SHADER_STAGES];
977
978 /* Immutable samplers (or NULL if no immutable samplers) */
979 struct anv_sampler **immutable_samplers;
980 };
981
982 struct anv_descriptor_set_layout {
983 /* Number of bindings in this descriptor set */
984 uint16_t binding_count;
985
986 /* Total size of the descriptor set with room for all array entries */
987 uint16_t size;
988
989 /* Shader stages affected by this descriptor set */
990 uint16_t shader_stages;
991
992 /* Number of buffers in this descriptor set */
993 uint16_t buffer_count;
994
995 /* Number of dynamic offsets used by this descriptor set */
996 uint16_t dynamic_offset_count;
997
998 /* Bindings in this descriptor set */
999 struct anv_descriptor_set_binding_layout binding[0];
1000 };
1001
1002 struct anv_descriptor {
1003 VkDescriptorType type;
1004
1005 union {
1006 struct {
1007 struct anv_image_view *image_view;
1008 struct anv_sampler *sampler;
1009 };
1010
1011 struct anv_buffer_view *buffer_view;
1012 };
1013 };
1014
1015 struct anv_descriptor_set {
1016 const struct anv_descriptor_set_layout *layout;
1017 uint32_t size;
1018 uint32_t buffer_count;
1019 struct anv_buffer_view *buffer_views;
1020 struct anv_descriptor descriptors[0];
1021 };
1022
1023 struct anv_descriptor_pool {
1024 uint32_t size;
1025 uint32_t next;
1026 uint32_t free_list;
1027
1028 struct anv_state_stream surface_state_stream;
1029 void *surface_state_free_list;
1030
1031 char data[0];
1032 };
1033
1034 VkResult
1035 anv_descriptor_set_create(struct anv_device *device,
1036 struct anv_descriptor_pool *pool,
1037 const struct anv_descriptor_set_layout *layout,
1038 struct anv_descriptor_set **out_set);
1039
1040 void
1041 anv_descriptor_set_destroy(struct anv_device *device,
1042 struct anv_descriptor_pool *pool,
1043 struct anv_descriptor_set *set);
1044
1045 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1046
1047 struct anv_pipeline_binding {
1048 /* The descriptor set this surface corresponds to. The special value of
1049 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1050 * to a color attachment and not a regular descriptor.
1051 */
1052 uint8_t set;
1053
1054 /* Binding in the descriptor set */
1055 uint8_t binding;
1056
1057 /* Index in the binding */
1058 uint8_t index;
1059 };
1060
1061 struct anv_pipeline_layout {
1062 struct {
1063 struct anv_descriptor_set_layout *layout;
1064 uint32_t dynamic_offset_start;
1065 } set[MAX_SETS];
1066
1067 uint32_t num_sets;
1068
1069 struct {
1070 bool has_dynamic_offsets;
1071 } stage[MESA_SHADER_STAGES];
1072
1073 unsigned char sha1[20];
1074 };
1075
1076 struct anv_buffer {
1077 struct anv_device * device;
1078 VkDeviceSize size;
1079
1080 VkBufferUsageFlags usage;
1081
1082 /* Set when bound */
1083 struct anv_bo * bo;
1084 VkDeviceSize offset;
1085 };
1086
1087 enum anv_cmd_dirty_bits {
1088 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1089 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1090 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1091 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1092 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1093 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1094 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1095 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1096 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1097 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1098 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1099 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1100 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1101 };
1102 typedef uint32_t anv_cmd_dirty_mask_t;
1103
1104 enum anv_pipe_bits {
1105 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1106 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1107 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1108 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1109 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1110 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1111 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1112 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1113 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1114 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1115 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1116
1117 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1118 * a flush has happened but not a CS stall. The next time we do any sort
1119 * of invalidation we need to insert a CS stall at that time. Otherwise,
1120 * we would have to CS stall on every flush which could be bad.
1121 */
1122 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1123 };
1124
1125 #define ANV_PIPE_FLUSH_BITS ( \
1126 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1127 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1128 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1129
1130 #define ANV_PIPE_STALL_BITS ( \
1131 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1132 ANV_PIPE_DEPTH_STALL_BIT | \
1133 ANV_PIPE_CS_STALL_BIT)
1134
1135 #define ANV_PIPE_INVALIDATE_BITS ( \
1136 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1137 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1138 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1139 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1140 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1141 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1142
1143 struct anv_vertex_binding {
1144 struct anv_buffer * buffer;
1145 VkDeviceSize offset;
1146 };
1147
1148 struct anv_push_constants {
1149 /* Current allocated size of this push constants data structure.
1150 * Because a decent chunk of it may not be used (images on SKL, for
1151 * instance), we won't actually allocate the entire structure up-front.
1152 */
1153 uint32_t size;
1154
1155 /* Push constant data provided by the client through vkPushConstants */
1156 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1157
1158 /* Our hardware only provides zero-based vertex and instance id so, in
1159 * order to satisfy the vulkan requirements, we may have to push one or
1160 * both of these into the shader.
1161 */
1162 uint32_t base_vertex;
1163 uint32_t base_instance;
1164
1165 /* Offsets and ranges for dynamically bound buffers */
1166 struct {
1167 uint32_t offset;
1168 uint32_t range;
1169 } dynamic[MAX_DYNAMIC_BUFFERS];
1170
1171 /* Image data for image_load_store on pre-SKL */
1172 struct brw_image_param images[MAX_IMAGES];
1173 };
1174
1175 struct anv_dynamic_state {
1176 struct {
1177 uint32_t count;
1178 VkViewport viewports[MAX_VIEWPORTS];
1179 } viewport;
1180
1181 struct {
1182 uint32_t count;
1183 VkRect2D scissors[MAX_SCISSORS];
1184 } scissor;
1185
1186 float line_width;
1187
1188 struct {
1189 float bias;
1190 float clamp;
1191 float slope;
1192 } depth_bias;
1193
1194 float blend_constants[4];
1195
1196 struct {
1197 float min;
1198 float max;
1199 } depth_bounds;
1200
1201 struct {
1202 uint32_t front;
1203 uint32_t back;
1204 } stencil_compare_mask;
1205
1206 struct {
1207 uint32_t front;
1208 uint32_t back;
1209 } stencil_write_mask;
1210
1211 struct {
1212 uint32_t front;
1213 uint32_t back;
1214 } stencil_reference;
1215 };
1216
1217 extern const struct anv_dynamic_state default_dynamic_state;
1218
1219 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1220 const struct anv_dynamic_state *src,
1221 uint32_t copy_mask);
1222
1223 /**
1224 * Attachment state when recording a renderpass instance.
1225 *
1226 * The clear value is valid only if there exists a pending clear.
1227 */
1228 struct anv_attachment_state {
1229 VkImageAspectFlags pending_clear_aspects;
1230 VkClearValue clear_value;
1231 };
1232
1233 /** State required while building cmd buffer */
1234 struct anv_cmd_state {
1235 /* PIPELINE_SELECT.PipelineSelection */
1236 uint32_t current_pipeline;
1237 const struct gen_l3_config * current_l3_config;
1238 uint32_t vb_dirty;
1239 anv_cmd_dirty_mask_t dirty;
1240 anv_cmd_dirty_mask_t compute_dirty;
1241 enum anv_pipe_bits pending_pipe_bits;
1242 uint32_t num_workgroups_offset;
1243 struct anv_bo *num_workgroups_bo;
1244 VkShaderStageFlags descriptors_dirty;
1245 VkShaderStageFlags push_constants_dirty;
1246 uint32_t scratch_size;
1247 struct anv_pipeline * pipeline;
1248 struct anv_pipeline * compute_pipeline;
1249 struct anv_framebuffer * framebuffer;
1250 struct anv_render_pass * pass;
1251 struct anv_subpass * subpass;
1252 VkRect2D render_area;
1253 uint32_t restart_index;
1254 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1255 struct anv_descriptor_set * descriptors[MAX_SETS];
1256 VkShaderStageFlags push_constant_stages;
1257 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1258 struct anv_state binding_tables[MESA_SHADER_STAGES];
1259 struct anv_state samplers[MESA_SHADER_STAGES];
1260 struct anv_dynamic_state dynamic;
1261 bool need_query_wa;
1262
1263 /**
1264 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1265 * valid only when recording a render pass instance.
1266 */
1267 struct anv_attachment_state * attachments;
1268
1269 struct {
1270 struct anv_buffer * index_buffer;
1271 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1272 uint32_t index_offset;
1273 } gen7;
1274 };
1275
1276 struct anv_cmd_pool {
1277 VkAllocationCallbacks alloc;
1278 struct list_head cmd_buffers;
1279 };
1280
1281 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1282
1283 enum anv_cmd_buffer_exec_mode {
1284 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1285 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1286 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1287 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1288 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1289 };
1290
1291 struct anv_cmd_buffer {
1292 VK_LOADER_DATA _loader_data;
1293
1294 struct anv_device * device;
1295
1296 struct anv_cmd_pool * pool;
1297 struct list_head pool_link;
1298
1299 struct anv_batch batch;
1300
1301 /* Fields required for the actual chain of anv_batch_bo's.
1302 *
1303 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1304 */
1305 struct list_head batch_bos;
1306 enum anv_cmd_buffer_exec_mode exec_mode;
1307
1308 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1309 * referenced by this command buffer
1310 *
1311 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1312 */
1313 struct anv_vector seen_bbos;
1314
1315 /* A vector of int32_t's for every block of binding tables.
1316 *
1317 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1318 */
1319 struct anv_vector bt_blocks;
1320 uint32_t bt_next;
1321 struct anv_reloc_list surface_relocs;
1322
1323 /* Information needed for execbuf
1324 *
1325 * These fields are generated by anv_cmd_buffer_prepare_execbuf().
1326 */
1327 struct {
1328 struct drm_i915_gem_execbuffer2 execbuf;
1329
1330 struct drm_i915_gem_exec_object2 * objects;
1331 uint32_t bo_count;
1332 struct anv_bo ** bos;
1333
1334 /* Allocated length of the 'objects' and 'bos' arrays */
1335 uint32_t array_length;
1336
1337 bool need_reloc;
1338 } execbuf2;
1339
1340 /* Serial for tracking buffer completion */
1341 uint32_t serial;
1342
1343 /* Stream objects for storing temporary data */
1344 struct anv_state_stream surface_state_stream;
1345 struct anv_state_stream dynamic_state_stream;
1346
1347 VkCommandBufferUsageFlags usage_flags;
1348 VkCommandBufferLevel level;
1349
1350 struct anv_cmd_state state;
1351 };
1352
1353 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1354 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1355 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1356 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1357 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1358 struct anv_cmd_buffer *secondary);
1359 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1360
1361 VkResult anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
1362 unsigned stage, struct anv_state *bt_state);
1363 VkResult anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
1364 unsigned stage, struct anv_state *state);
1365 uint32_t anv_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer);
1366
1367 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1368 const void *data, uint32_t size, uint32_t alignment);
1369 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1370 uint32_t *a, uint32_t *b,
1371 uint32_t dwords, uint32_t alignment);
1372
1373 struct anv_address
1374 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1375 struct anv_state
1376 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1377 uint32_t entries, uint32_t *state_offset);
1378 struct anv_state
1379 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1380 struct anv_state
1381 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1382 uint32_t size, uint32_t alignment);
1383
1384 VkResult
1385 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1386
1387 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1388 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1389 bool depth_clamp_enable);
1390 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1391
1392 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1393
1394 void anv_cmd_state_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1395 const VkRenderPassBeginInfo *info);
1396
1397 struct anv_state
1398 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1399 gl_shader_stage stage);
1400 struct anv_state
1401 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1402
1403 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1404 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1405
1406 const struct anv_image_view *
1407 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1408
1409 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1410
1411 struct anv_fence {
1412 struct anv_bo bo;
1413 struct drm_i915_gem_execbuffer2 execbuf;
1414 struct drm_i915_gem_exec_object2 exec2_objects[1];
1415 bool ready;
1416 };
1417
1418 struct anv_event {
1419 uint64_t semaphore;
1420 struct anv_state state;
1421 };
1422
1423 struct nir_shader;
1424
1425 struct anv_shader_module {
1426 struct nir_shader * nir;
1427
1428 unsigned char sha1[20];
1429 uint32_t size;
1430 char data[0];
1431 };
1432
1433 void anv_hash_shader(unsigned char *hash, const void *key, size_t key_size,
1434 struct anv_shader_module *module,
1435 const char *entrypoint,
1436 const struct anv_pipeline_layout *pipeline_layout,
1437 const VkSpecializationInfo *spec_info);
1438
1439 static inline gl_shader_stage
1440 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1441 {
1442 assert(__builtin_popcount(vk_stage) == 1);
1443 return ffs(vk_stage) - 1;
1444 }
1445
1446 static inline VkShaderStageFlagBits
1447 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1448 {
1449 return (1 << mesa_stage);
1450 }
1451
1452 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1453
1454 #define anv_foreach_stage(stage, stage_bits) \
1455 for (gl_shader_stage stage, \
1456 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1457 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1458 __tmp &= ~(1 << (stage)))
1459
1460 struct anv_pipeline_bind_map {
1461 uint32_t surface_count;
1462 uint32_t sampler_count;
1463 uint32_t image_count;
1464
1465 struct anv_pipeline_binding * surface_to_descriptor;
1466 struct anv_pipeline_binding * sampler_to_descriptor;
1467 };
1468
1469 struct anv_shader_bin {
1470 uint32_t ref_cnt;
1471
1472 struct anv_state kernel;
1473 uint32_t kernel_size;
1474
1475 struct anv_pipeline_bind_map bind_map;
1476
1477 uint32_t prog_data_size;
1478
1479 /* Prog data follows, then the key, both aligned to 8-bytes */
1480 };
1481
1482 struct anv_shader_bin *
1483 anv_shader_bin_create(struct anv_device *device,
1484 const void *key, uint32_t key_size,
1485 const void *kernel, uint32_t kernel_size,
1486 const void *prog_data, uint32_t prog_data_size,
1487 const struct anv_pipeline_bind_map *bind_map);
1488
1489 void
1490 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
1491
1492 static inline void
1493 anv_shader_bin_ref(struct anv_shader_bin *shader)
1494 {
1495 assert(shader->ref_cnt >= 1);
1496 __sync_fetch_and_add(&shader->ref_cnt, 1);
1497 }
1498
1499 static inline void
1500 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
1501 {
1502 assert(shader->ref_cnt >= 1);
1503 if (__sync_fetch_and_add(&shader->ref_cnt, -1) == 1)
1504 anv_shader_bin_destroy(device, shader);
1505 }
1506
1507 static inline const struct brw_stage_prog_data *
1508 anv_shader_bin_get_prog_data(const struct anv_shader_bin *shader)
1509 {
1510 const void *data = shader;
1511 data += align_u32(sizeof(struct anv_shader_bin), 8);
1512 return data;
1513 }
1514
1515 struct anv_pipeline {
1516 struct anv_device * device;
1517 struct anv_batch batch;
1518 uint32_t batch_data[512];
1519 struct anv_reloc_list batch_relocs;
1520 uint32_t dynamic_state_mask;
1521 struct anv_dynamic_state dynamic_state;
1522
1523 struct anv_pipeline_layout * layout;
1524
1525 bool use_repclear;
1526 bool needs_data_cache;
1527
1528 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
1529
1530 struct {
1531 const struct gen_l3_config * l3_config;
1532 uint32_t total_size;
1533 } urb;
1534
1535 VkShaderStageFlags active_stages;
1536 struct anv_state blend_state;
1537 uint32_t vs_simd8;
1538 uint32_t vs_vec4;
1539 uint32_t ps_ksp0;
1540 uint32_t gs_kernel;
1541 uint32_t cs_simd;
1542
1543 uint32_t vb_used;
1544 uint32_t binding_stride[MAX_VBS];
1545 bool instancing_enable[MAX_VBS];
1546 bool primitive_restart;
1547 uint32_t topology;
1548
1549 uint32_t cs_right_mask;
1550
1551 bool depth_clamp_enable;
1552
1553 struct {
1554 uint32_t sf[7];
1555 uint32_t depth_stencil_state[3];
1556 } gen7;
1557
1558 struct {
1559 uint32_t sf[4];
1560 uint32_t raster[5];
1561 uint32_t wm_depth_stencil[3];
1562 } gen8;
1563
1564 struct {
1565 uint32_t wm_depth_stencil[4];
1566 } gen9;
1567 };
1568
1569 static inline bool
1570 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
1571 gl_shader_stage stage)
1572 {
1573 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
1574 }
1575
1576 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1577 static inline const struct brw_##prefix##_prog_data * \
1578 get_##prefix##_prog_data(struct anv_pipeline *pipeline) \
1579 { \
1580 if (anv_pipeline_has_stage(pipeline, stage)) { \
1581 return (const struct brw_##prefix##_prog_data *) \
1582 anv_shader_bin_get_prog_data(pipeline->shaders[stage]); \
1583 } else { \
1584 return NULL; \
1585 } \
1586 }
1587
1588 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
1589 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
1590 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
1591 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
1592
1593 struct anv_graphics_pipeline_create_info {
1594 /**
1595 * If non-negative, overrides the color attachment count of the pipeline's
1596 * subpass.
1597 */
1598 int8_t color_attachment_count;
1599
1600 bool use_repclear;
1601 bool disable_vs;
1602 bool use_rectlist;
1603 };
1604
1605 VkResult
1606 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
1607 struct anv_pipeline_cache *cache,
1608 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1609 const struct anv_graphics_pipeline_create_info *extra,
1610 const VkAllocationCallbacks *alloc);
1611
1612 VkResult
1613 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1614 struct anv_pipeline_cache *cache,
1615 const VkComputePipelineCreateInfo *info,
1616 struct anv_shader_module *module,
1617 const char *entrypoint,
1618 const VkSpecializationInfo *spec_info);
1619
1620 VkResult
1621 anv_graphics_pipeline_create(VkDevice device,
1622 VkPipelineCache cache,
1623 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1624 const struct anv_graphics_pipeline_create_info *extra,
1625 const VkAllocationCallbacks *alloc,
1626 VkPipeline *pPipeline);
1627
1628 struct anv_format {
1629 enum isl_format isl_format:16;
1630 struct isl_swizzle swizzle;
1631 };
1632
1633 struct anv_format
1634 anv_get_format(const struct gen_device_info *devinfo, VkFormat format,
1635 VkImageAspectFlags aspect, VkImageTiling tiling);
1636
1637 static inline enum isl_format
1638 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
1639 VkImageAspectFlags aspect, VkImageTiling tiling)
1640 {
1641 return anv_get_format(devinfo, vk_format, aspect, tiling).isl_format;
1642 }
1643
1644 void
1645 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
1646
1647 /**
1648 * Subsurface of an anv_image.
1649 */
1650 struct anv_surface {
1651 /** Valid only if isl_surf::size > 0. */
1652 struct isl_surf isl;
1653
1654 /**
1655 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1656 */
1657 uint32_t offset;
1658 };
1659
1660 struct anv_image {
1661 VkImageType type;
1662 /* The original VkFormat provided by the client. This may not match any
1663 * of the actual surface formats.
1664 */
1665 VkFormat vk_format;
1666 VkImageAspectFlags aspects;
1667 VkExtent3D extent;
1668 uint32_t levels;
1669 uint32_t array_size;
1670 uint32_t samples; /**< VkImageCreateInfo::samples */
1671 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1672 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1673
1674 VkDeviceSize size;
1675 uint32_t alignment;
1676
1677 /* Set when bound */
1678 struct anv_bo *bo;
1679 VkDeviceSize offset;
1680
1681 /**
1682 * Image subsurfaces
1683 *
1684 * For each foo, anv_image::foo_surface is valid if and only if
1685 * anv_image::aspects has a foo aspect.
1686 *
1687 * The hardware requires that the depth buffer and stencil buffer be
1688 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1689 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1690 * allocate the depth and stencil buffers as separate surfaces in the same
1691 * bo.
1692 */
1693 union {
1694 struct anv_surface color_surface;
1695
1696 struct {
1697 struct anv_surface depth_surface;
1698 struct anv_surface hiz_surface;
1699 struct anv_surface stencil_surface;
1700 };
1701 };
1702 };
1703
1704 static inline uint32_t
1705 anv_get_layerCount(const struct anv_image *image,
1706 const VkImageSubresourceRange *range)
1707 {
1708 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1709 image->array_size - range->baseArrayLayer : range->layerCount;
1710 }
1711
1712 static inline uint32_t
1713 anv_get_levelCount(const struct anv_image *image,
1714 const VkImageSubresourceRange *range)
1715 {
1716 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1717 image->levels - range->baseMipLevel : range->levelCount;
1718 }
1719
1720
1721 struct anv_image_view {
1722 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
1723 struct anv_bo *bo;
1724 uint32_t offset; /**< Offset into bo. */
1725
1726 VkImageAspectFlags aspect_mask;
1727 VkFormat vk_format;
1728 uint32_t base_layer;
1729 uint32_t base_mip;
1730 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1731
1732 /** RENDER_SURFACE_STATE when using image as a color render target. */
1733 struct anv_state color_rt_surface_state;
1734
1735 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1736 struct anv_state sampler_surface_state;
1737
1738 /** RENDER_SURFACE_STATE when using image as a storage image. */
1739 struct anv_state storage_surface_state;
1740
1741 struct brw_image_param storage_image_param;
1742 };
1743
1744 struct anv_image_create_info {
1745 const VkImageCreateInfo *vk_info;
1746
1747 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1748 isl_tiling_flags_t isl_tiling_flags;
1749
1750 uint32_t stride;
1751 };
1752
1753 VkResult anv_image_create(VkDevice _device,
1754 const struct anv_image_create_info *info,
1755 const VkAllocationCallbacks* alloc,
1756 VkImage *pImage);
1757
1758 const struct anv_surface *
1759 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
1760 VkImageAspectFlags aspect_mask);
1761
1762 static inline bool
1763 anv_image_has_hiz(const struct anv_image *image)
1764 {
1765 /* We must check the aspect because anv_image::hiz_surface belongs to
1766 * a union.
1767 */
1768 return (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1769 image->hiz_surface.isl.size > 0;
1770 }
1771
1772 void anv_image_view_init(struct anv_image_view *view,
1773 struct anv_device *device,
1774 const VkImageViewCreateInfo* pCreateInfo,
1775 struct anv_cmd_buffer *cmd_buffer,
1776 VkImageUsageFlags usage_mask);
1777
1778 struct anv_buffer_view {
1779 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1780 struct anv_bo *bo;
1781 uint32_t offset; /**< Offset into bo. */
1782 uint64_t range; /**< VkBufferViewCreateInfo::range */
1783
1784 struct anv_state surface_state;
1785 struct anv_state storage_surface_state;
1786
1787 struct brw_image_param storage_image_param;
1788 };
1789
1790 void anv_buffer_view_init(struct anv_buffer_view *view,
1791 struct anv_device *device,
1792 const VkBufferViewCreateInfo* pCreateInfo,
1793 struct anv_cmd_buffer *cmd_buffer);
1794
1795 enum isl_format
1796 anv_isl_format_for_descriptor_type(VkDescriptorType type);
1797
1798 static inline struct VkExtent3D
1799 anv_sanitize_image_extent(const VkImageType imageType,
1800 const struct VkExtent3D imageExtent)
1801 {
1802 switch (imageType) {
1803 case VK_IMAGE_TYPE_1D:
1804 return (VkExtent3D) { imageExtent.width, 1, 1 };
1805 case VK_IMAGE_TYPE_2D:
1806 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1807 case VK_IMAGE_TYPE_3D:
1808 return imageExtent;
1809 default:
1810 unreachable("invalid image type");
1811 }
1812 }
1813
1814 static inline struct VkOffset3D
1815 anv_sanitize_image_offset(const VkImageType imageType,
1816 const struct VkOffset3D imageOffset)
1817 {
1818 switch (imageType) {
1819 case VK_IMAGE_TYPE_1D:
1820 return (VkOffset3D) { imageOffset.x, 0, 0 };
1821 case VK_IMAGE_TYPE_2D:
1822 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1823 case VK_IMAGE_TYPE_3D:
1824 return imageOffset;
1825 default:
1826 unreachable("invalid image type");
1827 }
1828 }
1829
1830
1831 void anv_fill_buffer_surface_state(struct anv_device *device,
1832 struct anv_state state,
1833 enum isl_format format,
1834 uint32_t offset, uint32_t range,
1835 uint32_t stride);
1836
1837 void anv_image_view_fill_image_param(struct anv_device *device,
1838 struct anv_image_view *view,
1839 struct brw_image_param *param);
1840 void anv_buffer_view_fill_image_param(struct anv_device *device,
1841 struct anv_buffer_view *view,
1842 struct brw_image_param *param);
1843
1844 struct anv_sampler {
1845 uint32_t state[4];
1846 };
1847
1848 struct anv_framebuffer {
1849 uint32_t width;
1850 uint32_t height;
1851 uint32_t layers;
1852
1853 uint32_t attachment_count;
1854 struct anv_image_view * attachments[0];
1855 };
1856
1857 struct anv_subpass {
1858 uint32_t input_count;
1859 uint32_t * input_attachments;
1860 uint32_t color_count;
1861 uint32_t * color_attachments;
1862 uint32_t * resolve_attachments;
1863 uint32_t depth_stencil_attachment;
1864
1865 /** Subpass has at least one resolve attachment */
1866 bool has_resolve;
1867 };
1868
1869 struct anv_render_pass_attachment {
1870 VkFormat format;
1871 uint32_t samples;
1872 VkAttachmentLoadOp load_op;
1873 VkAttachmentStoreOp store_op;
1874 VkAttachmentLoadOp stencil_load_op;
1875 };
1876
1877 struct anv_render_pass {
1878 uint32_t attachment_count;
1879 uint32_t subpass_count;
1880 uint32_t * subpass_attachments;
1881 struct anv_render_pass_attachment * attachments;
1882 struct anv_subpass subpasses[0];
1883 };
1884
1885 extern struct anv_render_pass anv_meta_dummy_renderpass;
1886
1887 struct anv_query_pool_slot {
1888 uint64_t begin;
1889 uint64_t end;
1890 uint64_t available;
1891 };
1892
1893 struct anv_query_pool {
1894 VkQueryType type;
1895 uint32_t slots;
1896 struct anv_bo bo;
1897 };
1898
1899 VkResult anv_device_init_meta(struct anv_device *device);
1900 void anv_device_finish_meta(struct anv_device *device);
1901
1902 void *anv_lookup_entrypoint(const char *name);
1903
1904 void anv_dump_image_to_ppm(struct anv_device *device,
1905 struct anv_image *image, unsigned miplevel,
1906 unsigned array_layer, VkImageAspectFlagBits aspect,
1907 const char *filename);
1908
1909 enum anv_dump_action {
1910 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
1911 };
1912
1913 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
1914 void anv_dump_finish(void);
1915
1916 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
1917 struct anv_framebuffer *fb);
1918
1919 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1920 \
1921 static inline struct __anv_type * \
1922 __anv_type ## _from_handle(__VkType _handle) \
1923 { \
1924 return (struct __anv_type *) _handle; \
1925 } \
1926 \
1927 static inline __VkType \
1928 __anv_type ## _to_handle(struct __anv_type *_obj) \
1929 { \
1930 return (__VkType) _obj; \
1931 }
1932
1933 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1934 \
1935 static inline struct __anv_type * \
1936 __anv_type ## _from_handle(__VkType _handle) \
1937 { \
1938 return (struct __anv_type *)(uintptr_t) _handle; \
1939 } \
1940 \
1941 static inline __VkType \
1942 __anv_type ## _to_handle(struct __anv_type *_obj) \
1943 { \
1944 return (__VkType)(uintptr_t) _obj; \
1945 }
1946
1947 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1948 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1949
1950 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
1951 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
1952 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
1953 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
1954 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
1955
1956 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
1957 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
1958 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
1959 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
1960 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
1961 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
1962 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
1963 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
1964 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
1965 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
1966 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
1967 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
1968 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
1969 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
1970 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
1971 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
1972 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
1973 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
1974 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
1975
1976 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1977 \
1978 static inline const __VkType * \
1979 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1980 { \
1981 return (const __VkType *) __anv_obj; \
1982 }
1983
1984 #define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1985 const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name)
1986
1987 ANV_DEFINE_STRUCT_CASTS(anv_common, VkMemoryBarrier)
1988 ANV_DEFINE_STRUCT_CASTS(anv_common, VkBufferMemoryBarrier)
1989 ANV_DEFINE_STRUCT_CASTS(anv_common, VkImageMemoryBarrier)
1990
1991 /* Gen-specific function declarations */
1992 #ifdef genX
1993 # include "anv_genX.h"
1994 #else
1995 # define genX(x) gen7_##x
1996 # include "anv_genX.h"
1997 # undef genX
1998 # define genX(x) gen75_##x
1999 # include "anv_genX.h"
2000 # undef genX
2001 # define genX(x) gen8_##x
2002 # include "anv_genX.h"
2003 # undef genX
2004 # define genX(x) gen9_##x
2005 # include "anv_genX.h"
2006 # undef genX
2007 #endif
2008
2009 #ifdef __cplusplus
2010 }
2011 #endif