2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/bitset.h"
53 #include "util/macros.h"
54 #include "util/hash_table.h"
55 #include "util/list.h"
56 #include "util/sparse_array.h"
57 #include "util/u_atomic.h"
58 #include "util/u_vector.h"
59 #include "util/u_math.h"
61 #include "util/xmlconfig.h"
63 #include "vk_debug_report.h"
65 /* Pre-declarations needed for WSI entrypoints */
68 typedef struct xcb_connection_t xcb_connection_t
;
69 typedef uint32_t xcb_visualid_t
;
70 typedef uint32_t xcb_window_t
;
74 struct anv_buffer_view
;
75 struct anv_image_view
;
78 struct gen_aux_map_context
;
80 struct gen_perf_config
;
82 #include <vulkan/vulkan.h>
83 #include <vulkan/vulkan_intel.h>
84 #include <vulkan/vk_icd.h>
86 #include "anv_android.h"
87 #include "anv_entrypoints.h"
88 #include "anv_extensions.h"
91 #include "dev/gen_debug.h"
92 #include "common/intel_log.h"
93 #include "wsi_common.h"
95 #define NSEC_PER_SEC 1000000000ull
97 /* anv Virtual Memory Layout
98 * =========================
100 * When the anv driver is determining the virtual graphics addresses of memory
101 * objects itself using the softpin mechanism, the following memory ranges
104 * Three special considerations to notice:
106 * (1) the dynamic state pool is located within the same 4 GiB as the low
107 * heap. This is to work around a VF cache issue described in a comment in
108 * anv_physical_device_init_heaps.
110 * (2) the binding table pool is located at lower addresses than the surface
111 * state pool, within a 4 GiB range. This allows surface state base addresses
112 * to cover both binding tables (16 bit offsets) and surface states (32 bit
115 * (3) the last 4 GiB of the address space is withheld from the high
116 * heap. Various hardware units will read past the end of an object for
117 * various reasons. This healthy margin prevents reads from wrapping around
120 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
121 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
122 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
123 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
124 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
125 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
126 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
127 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
128 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
129 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
130 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
131 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
132 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
134 #define LOW_HEAP_SIZE \
135 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
136 #define DYNAMIC_STATE_POOL_SIZE \
137 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
138 #define BINDING_TABLE_POOL_SIZE \
139 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
140 #define SURFACE_STATE_POOL_SIZE \
141 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
142 #define INSTRUCTION_STATE_POOL_SIZE \
143 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
144 #define CLIENT_VISIBLE_HEAP_SIZE \
145 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
147 /* Allowing different clear colors requires us to perform a depth resolve at
148 * the end of certain render passes. This is because while slow clears store
149 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
150 * See the PRMs for examples describing when additional resolves would be
151 * necessary. To enable fast clears without requiring extra resolves, we set
152 * the clear value to a globally-defined one. We could allow different values
153 * if the user doesn't expect coherent data during or after a render passes
154 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
155 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
156 * 1.0f seems to be the only value used. The only application that doesn't set
157 * this value does so through the usage of an seemingly uninitialized clear
160 #define ANV_HZ_FC_VAL 1.0f
163 #define MAX_XFB_BUFFERS 4
164 #define MAX_XFB_STREAMS 4
167 #define MAX_VIEWPORTS 16
168 #define MAX_SCISSORS 16
169 #define MAX_PUSH_CONSTANTS_SIZE 128
170 #define MAX_DYNAMIC_BUFFERS 16
171 #define MAX_IMAGES 64
172 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
173 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
174 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
176 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
178 * "The surface state model is used when a Binding Table Index (specified
179 * in the message descriptor) of less than 240 is specified. In this model,
180 * the Binding Table Index is used to index into the binding table, and the
181 * binding table entry contains a pointer to the SURFACE_STATE."
183 * Binding table values above 240 are used for various things in the hardware
184 * such as stateless, stateless with incoherent cache, SLM, and bindless.
186 #define MAX_BINDING_TABLE_SIZE 240
188 /* The kernel relocation API has a limitation of a 32-bit delta value
189 * applied to the address before it is written which, in spite of it being
190 * unsigned, is treated as signed . Because of the way that this maps to
191 * the Vulkan API, we cannot handle an offset into a buffer that does not
192 * fit into a signed 32 bits. The only mechanism we have for dealing with
193 * this at the moment is to limit all VkDeviceMemory objects to a maximum
194 * of 2GB each. The Vulkan spec allows us to do this:
196 * "Some platforms may have a limit on the maximum size of a single
197 * allocation. For example, certain systems may fail to create
198 * allocations with a size greater than or equal to 4GB. Such a limit is
199 * implementation-dependent, and if such a failure occurs then the error
200 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
202 * We don't use vk_error here because it's not an error so much as an
203 * indication to the application that the allocation is too large.
205 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
207 #define ANV_SVGS_VB_INDEX MAX_VBS
208 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
210 /* We reserve this MI ALU register for the purpose of handling predication.
211 * Other code which uses the MI ALU should leave it alone.
213 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
215 /* For gen12 we set the streamout buffers using 4 separate commands
216 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
217 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
218 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
219 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
220 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
221 * 3DSTATE_SO_BUFFER_INDEX_0.
223 #define SO_BUFFER_INDEX_0_CMD 0x60
224 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
226 static inline uint32_t
227 align_down_npot_u32(uint32_t v
, uint32_t a
)
232 static inline uint32_t
233 align_u32(uint32_t v
, uint32_t a
)
235 assert(a
!= 0 && a
== (a
& -a
));
236 return (v
+ a
- 1) & ~(a
- 1);
239 static inline uint64_t
240 align_u64(uint64_t v
, uint64_t a
)
242 assert(a
!= 0 && a
== (a
& -a
));
243 return (v
+ a
- 1) & ~(a
- 1);
246 static inline int32_t
247 align_i32(int32_t v
, int32_t a
)
249 assert(a
!= 0 && a
== (a
& -a
));
250 return (v
+ a
- 1) & ~(a
- 1);
253 /** Alignment must be a power of 2. */
255 anv_is_aligned(uintmax_t n
, uintmax_t a
)
257 assert(a
== (a
& -a
));
258 return (n
& (a
- 1)) == 0;
261 static inline uint32_t
262 anv_minify(uint32_t n
, uint32_t levels
)
264 if (unlikely(n
== 0))
267 return MAX2(n
>> levels
, 1);
271 anv_clamp_f(float f
, float min
, float max
)
284 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
286 if (*inout_mask
& clear_mask
) {
287 *inout_mask
&= ~clear_mask
;
294 static inline union isl_color_value
295 vk_to_isl_color(VkClearColorValue color
)
297 return (union isl_color_value
) {
307 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
309 uintptr_t mask
= (1ull << bits
) - 1;
311 return (void *) (ptr
& ~mask
);
314 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
316 uintptr_t value
= (uintptr_t) ptr
;
317 uintptr_t mask
= (1ull << bits
) - 1;
318 return value
| (mask
& flags
);
321 #define for_each_bit(b, dword) \
322 for (uint32_t __dword = (dword); \
323 (b) = __builtin_ffs(__dword) - 1, __dword; \
324 __dword &= ~(1 << (b)))
326 #define typed_memcpy(dest, src, count) ({ \
327 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
328 memcpy((dest), (src), (count) * sizeof(*(src))); \
331 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
332 * to be added here in order to utilize mapping in debug/error/perf macros.
334 #define REPORT_OBJECT_TYPE(o) \
335 __builtin_choose_expr ( \
336 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
337 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
338 __builtin_choose_expr ( \
339 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
340 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
407 __builtin_choose_expr ( \
408 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
409 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
410 __builtin_choose_expr ( \
411 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
412 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
413 __builtin_choose_expr ( \
414 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
415 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
416 __builtin_choose_expr ( \
417 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
418 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
419 __builtin_choose_expr ( \
420 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
421 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
422 __builtin_choose_expr ( \
423 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
424 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
425 __builtin_choose_expr ( \
426 __builtin_types_compatible_p (__typeof (o), void*), \
427 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
428 /* The void expression results in a compile-time error \
429 when assigning the result to something. */ \
430 (void)0)))))))))))))))))))))))))))))))
432 /* Whenever we generate an error, pass it through this function. Useful for
433 * debugging, where we can break on it. Only call at error site, not when
434 * propagating errors. Might be useful to plug in a stack trace here.
437 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
438 VkDebugReportObjectTypeEXT type
, VkResult error
,
439 const char *file
, int line
, const char *format
,
442 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
443 VkDebugReportObjectTypeEXT type
, VkResult error
,
444 const char *file
, int line
, const char *format
, ...)
445 anv_printflike(7, 8);
448 #define vk_error(error) __vk_errorf(NULL, NULL,\
449 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
450 error, __FILE__, __LINE__, NULL)
451 #define vk_errorfi(instance, obj, error, format, ...)\
452 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
453 __FILE__, __LINE__, format, ## __VA_ARGS__)
454 #define vk_errorf(device, obj, error, format, ...)\
455 vk_errorfi(anv_device_instance_or_null(device),\
456 obj, error, format, ## __VA_ARGS__)
458 #define vk_error(error) error
459 #define vk_errorfi(instance, obj, error, format, ...) error
460 #define vk_errorf(device, obj, error, format, ...) error
464 * Warn on ignored extension structs.
466 * The Vulkan spec requires us to ignore unsupported or unknown structs in
467 * a pNext chain. In debug mode, emitting warnings for ignored structs may
468 * help us discover structs that we should not have ignored.
471 * From the Vulkan 1.0.38 spec:
473 * Any component of the implementation (the loader, any enabled layers,
474 * and drivers) must skip over, without processing (other than reading the
475 * sType and pNext members) any chained structures with sType values not
476 * defined by extensions supported by that component.
478 #define anv_debug_ignored_stype(sType) \
479 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
481 void __anv_perf_warn(struct anv_device
*device
, const void *object
,
482 VkDebugReportObjectTypeEXT type
, const char *file
,
483 int line
, const char *format
, ...)
484 anv_printflike(6, 7);
485 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
486 void anv_loge_v(const char *format
, va_list va
);
489 * Print a FINISHME message, including its source location.
491 #define anv_finishme(format, ...) \
493 static bool reported = false; \
495 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
502 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
504 #define anv_perf_warn(instance, obj, format, ...) \
506 static bool reported = false; \
507 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
508 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
509 format, ##__VA_ARGS__); \
514 /* A non-fatal assert. Useful for debugging. */
516 #define anv_assert(x) ({ \
517 if (unlikely(!(x))) \
518 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
521 #define anv_assert(x)
524 /* A multi-pointer allocator
526 * When copying data structures from the user (such as a render pass), it's
527 * common to need to allocate data for a bunch of different things. Instead
528 * of doing several allocations and having to handle all of the error checking
529 * that entails, it can be easier to do a single allocation. This struct
530 * helps facilitate that. The intended usage looks like this:
533 * anv_multialloc_add(&ma, &main_ptr, 1);
534 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
535 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
537 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
538 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
540 struct anv_multialloc
{
548 #define ANV_MULTIALLOC_INIT \
549 ((struct anv_multialloc) { 0, })
551 #define ANV_MULTIALLOC(_name) \
552 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
554 __attribute__((always_inline
))
556 _anv_multialloc_add(struct anv_multialloc
*ma
,
557 void **ptr
, size_t size
, size_t align
)
559 size_t offset
= align_u64(ma
->size
, align
);
560 ma
->size
= offset
+ size
;
561 ma
->align
= MAX2(ma
->align
, align
);
563 /* Store the offset in the pointer. */
564 *ptr
= (void *)(uintptr_t)offset
;
566 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
567 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
570 #define anv_multialloc_add_size(_ma, _ptr, _size) \
571 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
573 #define anv_multialloc_add(_ma, _ptr, _count) \
574 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
576 __attribute__((always_inline
))
578 anv_multialloc_alloc(struct anv_multialloc
*ma
,
579 const VkAllocationCallbacks
*alloc
,
580 VkSystemAllocationScope scope
)
582 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
586 /* Fill out each of the pointers with their final value.
588 * for (uint32_t i = 0; i < ma->ptr_count; i++)
589 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
591 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
592 * constant, GCC is incapable of figuring this out and unrolling the loop
593 * so we have to give it a little help.
595 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
596 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
597 if ((_i) < ma->ptr_count) \
598 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
599 _ANV_MULTIALLOC_UPDATE_POINTER(0);
600 _ANV_MULTIALLOC_UPDATE_POINTER(1);
601 _ANV_MULTIALLOC_UPDATE_POINTER(2);
602 _ANV_MULTIALLOC_UPDATE_POINTER(3);
603 _ANV_MULTIALLOC_UPDATE_POINTER(4);
604 _ANV_MULTIALLOC_UPDATE_POINTER(5);
605 _ANV_MULTIALLOC_UPDATE_POINTER(6);
606 _ANV_MULTIALLOC_UPDATE_POINTER(7);
607 #undef _ANV_MULTIALLOC_UPDATE_POINTER
612 __attribute__((always_inline
))
614 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
615 const VkAllocationCallbacks
*parent_alloc
,
616 const VkAllocationCallbacks
*alloc
,
617 VkSystemAllocationScope scope
)
619 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
627 /* Index into the current validation list. This is used by the
628 * validation list building alrogithm to track which buffers are already
629 * in the validation list so that we can ensure uniqueness.
633 /* Index for use with util_sparse_array_free_list */
636 /* Last known offset. This value is provided by the kernel when we
637 * execbuf and is used as the presumed offset for the next bunch of
644 /* Map for internally mapped BOs.
646 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
650 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
653 /** True if this BO may be shared with other processes */
656 /** True if this BO is a wrapper
658 * When set to true, none of the fields in this BO are meaningful except
659 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
660 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
661 * is set in the physical device.
665 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
666 bool has_fixed_address
:1;
668 /** True if this BO wraps a host pointer */
669 bool from_host_ptr
:1;
671 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
672 bool has_client_visible_address
:1;
675 static inline struct anv_bo
*
676 anv_bo_ref(struct anv_bo
*bo
)
678 p_atomic_inc(&bo
->refcount
);
682 static inline struct anv_bo
*
683 anv_bo_unwrap(struct anv_bo
*bo
)
685 while (bo
->is_wrapper
)
690 /* Represents a lock-free linked list of "free" things. This is used by
691 * both the block pool and the state pools. Unfortunately, in order to
692 * solve the ABA problem, we can't use a single uint32_t head.
694 union anv_free_list
{
698 /* A simple count that is incremented every time the head changes. */
701 /* Make sure it's aligned to 64 bits. This will make atomic operations
702 * faster on 32 bit platforms.
704 uint64_t u64
__attribute__ ((aligned (8)));
707 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
709 struct anv_block_state
{
715 /* Make sure it's aligned to 64 bits. This will make atomic operations
716 * faster on 32 bit platforms.
718 uint64_t u64
__attribute__ ((aligned (8)));
722 #define anv_block_pool_foreach_bo(bo, pool) \
723 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
724 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
727 #define ANV_MAX_BLOCK_POOL_BOS 20
729 struct anv_block_pool
{
730 struct anv_device
*device
;
733 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
734 * around the actual BO so that we grow the pool after the wrapper BO has
735 * been put in a relocation list. This is only used in the non-softpin
738 struct anv_bo wrapper_bo
;
740 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
746 /* The address where the start of the pool is pinned. The various bos that
747 * are created as the pool grows will have addresses in the range
748 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
750 uint64_t start_address
;
752 /* The offset from the start of the bo to the "center" of the block
753 * pool. Pointers to allocated blocks are given by
754 * bo.map + center_bo_offset + offsets.
756 uint32_t center_bo_offset
;
758 /* Current memory map of the block pool. This pointer may or may not
759 * point to the actual beginning of the block pool memory. If
760 * anv_block_pool_alloc_back has ever been called, then this pointer
761 * will point to the "center" position of the buffer and all offsets
762 * (negative or positive) given out by the block pool alloc functions
763 * will be valid relative to this pointer.
765 * In particular, map == bo.map + center_offset
767 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
768 * since it will handle the softpin case as well, where this points to NULL.
774 * Array of mmaps and gem handles owned by the block pool, reclaimed when
775 * the block pool is destroyed.
777 struct u_vector mmap_cleanups
;
779 struct anv_block_state state
;
781 struct anv_block_state back_state
;
784 /* Block pools are backed by a fixed-size 1GB memfd */
785 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
787 /* The center of the block pool is also the middle of the memfd. This may
788 * change in the future if we decide differently for some reason.
790 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
792 static inline uint32_t
793 anv_block_pool_size(struct anv_block_pool
*pool
)
795 return pool
->state
.end
+ pool
->back_state
.end
;
805 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
807 struct anv_fixed_size_state_pool
{
808 union anv_free_list free_list
;
809 struct anv_block_state block
;
812 #define ANV_MIN_STATE_SIZE_LOG2 6
813 #define ANV_MAX_STATE_SIZE_LOG2 21
815 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
817 struct anv_free_entry
{
819 struct anv_state state
;
822 struct anv_state_table
{
823 struct anv_device
*device
;
825 struct anv_free_entry
*map
;
827 struct anv_block_state state
;
828 struct u_vector cleanups
;
831 struct anv_state_pool
{
832 struct anv_block_pool block_pool
;
834 struct anv_state_table table
;
836 /* The size of blocks which will be allocated from the block pool */
839 /** Free list for "back" allocations */
840 union anv_free_list back_alloc_free_list
;
842 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
845 struct anv_state_stream_block
;
847 struct anv_state_stream
{
848 struct anv_state_pool
*state_pool
;
850 /* The size of blocks to allocate from the state pool */
853 /* Current block we're allocating from */
854 struct anv_state block
;
856 /* Offset into the current block at which to allocate the next state */
859 /* List of all blocks allocated from this pool */
860 struct anv_state_stream_block
*block_list
;
863 /* The block_pool functions exported for testing only. The block pool should
864 * only be used via a state pool (see below).
866 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
867 struct anv_device
*device
,
868 uint64_t start_address
,
869 uint32_t initial_size
);
870 void anv_block_pool_finish(struct anv_block_pool
*pool
);
871 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
872 uint32_t block_size
, uint32_t *padding
);
873 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
874 uint32_t block_size
);
875 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
877 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
878 struct anv_device
*device
,
879 uint64_t start_address
,
880 uint32_t block_size
);
881 void anv_state_pool_finish(struct anv_state_pool
*pool
);
882 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
883 uint32_t state_size
, uint32_t alignment
);
884 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
885 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
886 void anv_state_stream_init(struct anv_state_stream
*stream
,
887 struct anv_state_pool
*state_pool
,
888 uint32_t block_size
);
889 void anv_state_stream_finish(struct anv_state_stream
*stream
);
890 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
891 uint32_t size
, uint32_t alignment
);
893 VkResult
anv_state_table_init(struct anv_state_table
*table
,
894 struct anv_device
*device
,
895 uint32_t initial_entries
);
896 void anv_state_table_finish(struct anv_state_table
*table
);
897 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
899 void anv_free_list_push(union anv_free_list
*list
,
900 struct anv_state_table
*table
,
901 uint32_t idx
, uint32_t count
);
902 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
903 struct anv_state_table
*table
);
906 static inline struct anv_state
*
907 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
909 return &table
->map
[idx
].state
;
912 * Implements a pool of re-usable BOs. The interface is identical to that
913 * of block_pool except that each block is its own BO.
916 struct anv_device
*device
;
918 struct util_sparse_array_free_list free_list
[16];
921 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
922 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
923 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
924 struct anv_bo
**bo_out
);
925 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
927 struct anv_scratch_pool
{
928 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
929 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
932 void anv_scratch_pool_init(struct anv_device
*device
,
933 struct anv_scratch_pool
*pool
);
934 void anv_scratch_pool_finish(struct anv_device
*device
,
935 struct anv_scratch_pool
*pool
);
936 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
937 struct anv_scratch_pool
*pool
,
938 gl_shader_stage stage
,
939 unsigned per_thread_scratch
);
941 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
942 struct anv_bo_cache
{
943 struct util_sparse_array bo_map
;
944 pthread_mutex_t mutex
;
947 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
948 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
950 struct anv_memory_type
{
951 /* Standard bits passed on to the client */
952 VkMemoryPropertyFlags propertyFlags
;
956 struct anv_memory_heap
{
957 /* Standard bits passed on to the client */
959 VkMemoryHeapFlags flags
;
961 /* Driver-internal book-keeping */
965 struct anv_physical_device
{
966 VK_LOADER_DATA _loader_data
;
968 struct anv_instance
* instance
;
978 struct gen_device_info info
;
979 /** Amount of "GPU memory" we want to advertise
981 * Clearly, this value is bogus since Intel is a UMA architecture. On
982 * gen7 platforms, we are limited by GTT size unless we want to implement
983 * fine-grained tracking and GTT splitting. On Broadwell and above we are
984 * practically unlimited. However, we will never report more than 3/4 of
985 * the total system ram to try and avoid running out of RAM.
987 bool supports_48bit_addresses
;
988 struct brw_compiler
* compiler
;
989 struct isl_device isl_dev
;
990 struct gen_perf_config
* perf
;
991 int cmd_parser_version
;
994 bool has_exec_capture
;
997 bool has_syncobj_wait
;
998 bool has_context_priority
;
999 bool has_context_isolation
;
1000 bool has_mem_available
;
1004 bool always_use_bindless
;
1006 /** True if we can access buffers using A64 messages */
1007 bool has_a64_buffer_access
;
1008 /** True if we can use bindless access for images */
1009 bool has_bindless_images
;
1010 /** True if we can use bindless access for samplers */
1011 bool has_bindless_samplers
;
1013 bool always_flush_cache
;
1015 struct anv_device_extension_table supported_extensions
;
1018 uint32_t subslice_total
;
1021 uint32_t type_count
;
1022 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1023 uint32_t heap_count
;
1024 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1027 uint8_t driver_build_sha1
[20];
1028 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1029 uint8_t driver_uuid
[VK_UUID_SIZE
];
1030 uint8_t device_uuid
[VK_UUID_SIZE
];
1032 struct disk_cache
* disk_cache
;
1034 struct wsi_device wsi_device
;
1039 struct anv_app_info
{
1040 const char* app_name
;
1041 uint32_t app_version
;
1042 const char* engine_name
;
1043 uint32_t engine_version
;
1044 uint32_t api_version
;
1047 struct anv_instance
{
1048 VK_LOADER_DATA _loader_data
;
1050 VkAllocationCallbacks alloc
;
1052 struct anv_app_info app_info
;
1054 struct anv_instance_extension_table enabled_extensions
;
1055 struct anv_instance_dispatch_table dispatch
;
1056 struct anv_physical_device_dispatch_table physical_device_dispatch
;
1057 struct anv_device_dispatch_table device_dispatch
;
1059 int physicalDeviceCount
;
1060 struct anv_physical_device physicalDevice
;
1062 bool pipeline_cache_enabled
;
1064 struct vk_debug_report_instance debug_report_callbacks
;
1066 struct driOptionCache dri_options
;
1067 struct driOptionCache available_dri_options
;
1070 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1071 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1073 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1074 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1077 struct anv_queue_submit
{
1078 struct anv_cmd_buffer
* cmd_buffer
;
1080 uint32_t fence_count
;
1081 uint32_t fence_array_length
;
1082 struct drm_i915_gem_exec_fence
* fences
;
1084 uint32_t temporary_semaphore_count
;
1085 uint32_t temporary_semaphore_array_length
;
1086 struct anv_semaphore_impl
* temporary_semaphores
;
1088 /* Semaphores to be signaled with a SYNC_FD. */
1089 struct anv_semaphore
** sync_fd_semaphores
;
1090 uint32_t sync_fd_semaphore_count
;
1091 uint32_t sync_fd_semaphore_array_length
;
1093 /* Allocated only with non shareable timelines. */
1094 struct anv_timeline
** wait_timelines
;
1095 uint32_t wait_timeline_count
;
1096 uint32_t wait_timeline_array_length
;
1097 uint64_t * wait_timeline_values
;
1099 struct anv_timeline
** signal_timelines
;
1100 uint32_t signal_timeline_count
;
1101 uint32_t signal_timeline_array_length
;
1102 uint64_t * signal_timeline_values
;
1105 bool need_out_fence
;
1108 uint32_t fence_bo_count
;
1109 uint32_t fence_bo_array_length
;
1110 /* An array of struct anv_bo pointers with lower bit used as a flag to
1111 * signal we will wait on that BO (see anv_(un)pack_ptr).
1113 uintptr_t * fence_bos
;
1115 const VkAllocationCallbacks
* alloc
;
1116 VkSystemAllocationScope alloc_scope
;
1118 struct anv_bo
* simple_bo
;
1119 uint32_t simple_bo_size
;
1121 struct list_head link
;
1125 VK_LOADER_DATA _loader_data
;
1127 struct anv_device
* device
;
1130 * A list of struct anv_queue_submit to be submitted to i915.
1132 struct list_head queued_submits
;
1134 VkDeviceQueueCreateFlags flags
;
1137 struct anv_pipeline_cache
{
1138 struct anv_device
* device
;
1139 pthread_mutex_t mutex
;
1141 struct hash_table
* nir_cache
;
1143 struct hash_table
* cache
;
1146 struct nir_xfb_info
;
1147 struct anv_pipeline_bind_map
;
1149 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1150 struct anv_device
*device
,
1151 bool cache_enabled
);
1152 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1154 struct anv_shader_bin
*
1155 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1156 const void *key
, uint32_t key_size
);
1157 struct anv_shader_bin
*
1158 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1159 const void *key_data
, uint32_t key_size
,
1160 const void *kernel_data
, uint32_t kernel_size
,
1161 const void *constant_data
,
1162 uint32_t constant_data_size
,
1163 const struct brw_stage_prog_data
*prog_data
,
1164 uint32_t prog_data_size
,
1165 const struct brw_compile_stats
*stats
,
1167 const struct nir_xfb_info
*xfb_info
,
1168 const struct anv_pipeline_bind_map
*bind_map
);
1170 struct anv_shader_bin
*
1171 anv_device_search_for_kernel(struct anv_device
*device
,
1172 struct anv_pipeline_cache
*cache
,
1173 const void *key_data
, uint32_t key_size
,
1174 bool *user_cache_bit
);
1176 struct anv_shader_bin
*
1177 anv_device_upload_kernel(struct anv_device
*device
,
1178 struct anv_pipeline_cache
*cache
,
1179 const void *key_data
, uint32_t key_size
,
1180 const void *kernel_data
, uint32_t kernel_size
,
1181 const void *constant_data
,
1182 uint32_t constant_data_size
,
1183 const struct brw_stage_prog_data
*prog_data
,
1184 uint32_t prog_data_size
,
1185 const struct brw_compile_stats
*stats
,
1187 const struct nir_xfb_info
*xfb_info
,
1188 const struct anv_pipeline_bind_map
*bind_map
);
1191 struct nir_shader_compiler_options
;
1194 anv_device_search_for_nir(struct anv_device
*device
,
1195 struct anv_pipeline_cache
*cache
,
1196 const struct nir_shader_compiler_options
*nir_options
,
1197 unsigned char sha1_key
[20],
1201 anv_device_upload_nir(struct anv_device
*device
,
1202 struct anv_pipeline_cache
*cache
,
1203 const struct nir_shader
*nir
,
1204 unsigned char sha1_key
[20]);
1207 VK_LOADER_DATA _loader_data
;
1209 VkAllocationCallbacks alloc
;
1211 struct anv_physical_device
* physical
;
1213 struct gen_device_info info
;
1214 struct isl_device isl_dev
;
1217 bool can_chain_batches
;
1218 bool robust_buffer_access
;
1219 struct anv_device_extension_table enabled_extensions
;
1220 struct anv_device_dispatch_table dispatch
;
1222 pthread_mutex_t vma_mutex
;
1223 struct util_vma_heap vma_lo
;
1224 struct util_vma_heap vma_cva
;
1225 struct util_vma_heap vma_hi
;
1227 /** List of all anv_device_memory objects */
1228 struct list_head memory_objects
;
1230 struct anv_bo_pool batch_bo_pool
;
1232 struct anv_bo_cache bo_cache
;
1234 struct anv_state_pool dynamic_state_pool
;
1235 struct anv_state_pool instruction_state_pool
;
1236 struct anv_state_pool binding_table_pool
;
1237 struct anv_state_pool surface_state_pool
;
1239 struct anv_bo
* workaround_bo
;
1240 struct anv_bo
* trivial_batch_bo
;
1241 struct anv_bo
* hiz_clear_bo
;
1243 struct anv_pipeline_cache default_pipeline_cache
;
1244 struct blorp_context blorp
;
1246 struct anv_state border_colors
;
1248 struct anv_state slice_hash
;
1250 struct anv_queue queue
;
1252 struct anv_scratch_pool scratch_pool
;
1254 pthread_mutex_t mutex
;
1255 pthread_cond_t queue_submit
;
1258 struct gen_batch_decode_ctx decoder_ctx
;
1260 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1261 * the cmd_buffer's list.
1263 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1265 int perf_fd
; /* -1 if no opened */
1266 uint64_t perf_metric
; /* 0 if unset */
1268 struct gen_aux_map_context
*aux_map_ctx
;
1271 static inline struct anv_instance
*
1272 anv_device_instance_or_null(const struct anv_device
*device
)
1274 return device
? device
->physical
->instance
: NULL
;
1277 static inline struct anv_state_pool
*
1278 anv_binding_table_pool(struct anv_device
*device
)
1280 if (device
->physical
->use_softpin
)
1281 return &device
->binding_table_pool
;
1283 return &device
->surface_state_pool
;
1286 static inline struct anv_state
1287 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1288 if (device
->physical
->use_softpin
)
1289 return anv_state_pool_alloc(&device
->binding_table_pool
,
1290 device
->binding_table_pool
.block_size
, 0);
1292 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1296 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1297 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1300 static inline uint32_t
1301 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1303 if (bo
->is_external
)
1304 return device
->isl_dev
.mocs
.external
;
1306 return device
->isl_dev
.mocs
.internal
;
1309 void anv_device_init_blorp(struct anv_device
*device
);
1310 void anv_device_finish_blorp(struct anv_device
*device
);
1312 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1313 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1314 const char *file
, int line
,
1315 const char *msg
, ...)
1316 anv_printflike(4, 5);
1317 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1318 const char *file
, int line
,
1319 const char *msg
, ...)
1320 anv_printflike(4, 5);
1321 #define anv_device_set_lost(dev, ...) \
1322 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1323 #define anv_queue_set_lost(queue, ...) \
1324 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1327 anv_device_is_lost(struct anv_device
*device
)
1329 return unlikely(p_atomic_read(&device
->_lost
));
1332 VkResult
anv_device_query_status(struct anv_device
*device
);
1335 enum anv_bo_alloc_flags
{
1336 /** Specifies that the BO must have a 32-bit address
1338 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1340 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1342 /** Specifies that the BO may be shared externally */
1343 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1345 /** Specifies that the BO should be mapped */
1346 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1348 /** Specifies that the BO should be snooped so we get coherency */
1349 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1351 /** Specifies that the BO should be captured in error states */
1352 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1354 /** Specifies that the BO will have an address assigned by the caller
1356 * Such BOs do not exist in any VMA heap.
1358 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1360 /** Enables implicit synchronization on the BO
1362 * This is the opposite of EXEC_OBJECT_ASYNC.
1364 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1366 /** Enables implicit synchronization on the BO
1368 * This is equivalent to EXEC_OBJECT_WRITE.
1370 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1372 /** Has an address which is visible to the client */
1373 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS
= (1 << 8),
1376 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1377 enum anv_bo_alloc_flags alloc_flags
,
1378 uint64_t explicit_address
,
1379 struct anv_bo
**bo
);
1380 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1381 void *host_ptr
, uint32_t size
,
1382 enum anv_bo_alloc_flags alloc_flags
,
1383 uint64_t client_address
,
1384 struct anv_bo
**bo_out
);
1385 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1386 enum anv_bo_alloc_flags alloc_flags
,
1387 uint64_t client_address
,
1388 struct anv_bo
**bo
);
1389 VkResult
anv_device_export_bo(struct anv_device
*device
,
1390 struct anv_bo
*bo
, int *fd_out
);
1391 void anv_device_release_bo(struct anv_device
*device
,
1394 static inline struct anv_bo
*
1395 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1397 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1400 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1401 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1404 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1405 void anv_queue_finish(struct anv_queue
*queue
);
1407 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1408 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1409 struct anv_batch
*batch
);
1411 uint64_t anv_gettime_ns(void);
1412 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1414 void* anv_gem_mmap(struct anv_device
*device
,
1415 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1416 void anv_gem_munmap(void *p
, uint64_t size
);
1417 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1418 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1419 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1420 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1421 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1422 int anv_gem_execbuffer(struct anv_device
*device
,
1423 struct drm_i915_gem_execbuffer2
*execbuf
);
1424 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1425 uint32_t stride
, uint32_t tiling
);
1426 int anv_gem_create_context(struct anv_device
*device
);
1427 bool anv_gem_has_context_priority(int fd
);
1428 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1429 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1431 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1433 int anv_gem_get_param(int fd
, uint32_t param
);
1434 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1435 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1436 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1437 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1438 uint32_t *active
, uint32_t *pending
);
1439 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1440 int anv_gem_reg_read(struct anv_device
*device
,
1441 uint32_t offset
, uint64_t *result
);
1442 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1443 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1444 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1445 uint32_t read_domains
, uint32_t write_domain
);
1446 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1447 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1448 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1449 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1450 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1451 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1453 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1454 uint32_t handle
, int fd
);
1455 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1456 bool anv_gem_supports_syncobj_wait(int fd
);
1457 int anv_gem_syncobj_wait(struct anv_device
*device
,
1458 uint32_t *handles
, uint32_t num_handles
,
1459 int64_t abs_timeout_ns
, bool wait_all
);
1461 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
,
1462 uint64_t client_address
);
1463 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1465 struct anv_reloc_list
{
1466 uint32_t num_relocs
;
1467 uint32_t array_length
;
1468 struct drm_i915_gem_relocation_entry
* relocs
;
1469 struct anv_bo
** reloc_bos
;
1474 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1475 const VkAllocationCallbacks
*alloc
);
1476 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1477 const VkAllocationCallbacks
*alloc
);
1479 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1480 const VkAllocationCallbacks
*alloc
,
1481 uint32_t offset
, struct anv_bo
*target_bo
,
1482 uint32_t delta
, uint64_t *address_u64_out
);
1484 struct anv_batch_bo
{
1485 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1486 struct list_head link
;
1490 /* Bytes actually consumed in this batch BO */
1493 struct anv_reloc_list relocs
;
1497 const VkAllocationCallbacks
* alloc
;
1503 struct anv_reloc_list
* relocs
;
1505 /* This callback is called (with the associated user data) in the event
1506 * that the batch runs out of space.
1508 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1512 * Current error status of the command buffer. Used to track inconsistent
1513 * or incomplete command buffer states that are the consequence of run-time
1514 * errors such as out of memory scenarios. We want to track this in the
1515 * batch because the command buffer object is not visible to some parts
1521 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1522 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1523 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1524 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1526 static inline VkResult
1527 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1529 assert(error
!= VK_SUCCESS
);
1530 if (batch
->status
== VK_SUCCESS
)
1531 batch
->status
= error
;
1532 return batch
->status
;
1536 anv_batch_has_error(struct anv_batch
*batch
)
1538 return batch
->status
!= VK_SUCCESS
;
1541 struct anv_address
{
1546 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1549 anv_address_is_null(struct anv_address addr
)
1551 return addr
.bo
== NULL
&& addr
.offset
== 0;
1554 static inline uint64_t
1555 anv_address_physical(struct anv_address addr
)
1557 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1558 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1560 return gen_canonical_address(addr
.offset
);
1563 static inline struct anv_address
1564 anv_address_add(struct anv_address addr
, uint64_t offset
)
1566 addr
.offset
+= offset
;
1571 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1573 unsigned reloc_size
= 0;
1574 if (device
->info
.gen
>= 8) {
1575 reloc_size
= sizeof(uint64_t);
1576 *(uint64_t *)p
= gen_canonical_address(v
);
1578 reloc_size
= sizeof(uint32_t);
1582 if (flush
&& !device
->info
.has_llc
)
1583 gen_flush_range(p
, reloc_size
);
1586 static inline uint64_t
1587 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1588 const struct anv_address address
, uint32_t delta
)
1590 if (address
.bo
== NULL
) {
1591 return address
.offset
+ delta
;
1593 assert(batch
->start
<= location
&& location
< batch
->end
);
1595 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1599 #define __gen_address_type struct anv_address
1600 #define __gen_user_data struct anv_batch
1601 #define __gen_combine_address _anv_combine_address
1603 /* Wrapper macros needed to work around preprocessor argument issues. In
1604 * particular, arguments don't get pre-evaluated if they are concatenated.
1605 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1606 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1607 * We can work around this easily enough with these helpers.
1609 #define __anv_cmd_length(cmd) cmd ## _length
1610 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1611 #define __anv_cmd_header(cmd) cmd ## _header
1612 #define __anv_cmd_pack(cmd) cmd ## _pack
1613 #define __anv_reg_num(reg) reg ## _num
1615 #define anv_pack_struct(dst, struc, ...) do { \
1616 struct struc __template = { \
1619 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1620 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1623 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1624 void *__dst = anv_batch_emit_dwords(batch, n); \
1626 struct cmd __template = { \
1627 __anv_cmd_header(cmd), \
1628 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1631 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1636 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1640 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1641 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1644 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1645 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1646 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1649 #define anv_batch_emit(batch, cmd, name) \
1650 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1651 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1652 __builtin_expect(_dst != NULL, 1); \
1653 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1654 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1658 struct anv_device_memory
{
1659 struct list_head link
;
1662 struct anv_memory_type
* type
;
1663 VkDeviceSize map_size
;
1666 /* If set, we are holding reference to AHardwareBuffer
1667 * which we must release when memory is freed.
1669 struct AHardwareBuffer
* ahw
;
1671 /* If set, this memory comes from a host pointer. */
1676 * Header for Vertex URB Entry (VUE)
1678 struct anv_vue_header
{
1680 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1681 uint32_t ViewportIndex
;
1685 /** Struct representing a sampled image descriptor
1687 * This descriptor layout is used for sampled images, bare sampler, and
1688 * combined image/sampler descriptors.
1690 struct anv_sampled_image_descriptor
{
1691 /** Bindless image handle
1693 * This is expected to already be shifted such that the 20-bit
1694 * SURFACE_STATE table index is in the top 20 bits.
1698 /** Bindless sampler handle
1700 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1701 * to the dynamic state base address.
1706 struct anv_texture_swizzle_descriptor
{
1709 * See also nir_intrinsic_channel_select_intel
1713 /** Unused padding to ensure the struct is a multiple of 64 bits */
1717 /** Struct representing a storage image descriptor */
1718 struct anv_storage_image_descriptor
{
1719 /** Bindless image handles
1721 * These are expected to already be shifted such that the 20-bit
1722 * SURFACE_STATE table index is in the top 20 bits.
1724 uint32_t read_write
;
1725 uint32_t write_only
;
1728 /** Struct representing a address/range descriptor
1730 * The fields of this struct correspond directly to the data layout of
1731 * nir_address_format_64bit_bounded_global addresses. The last field is the
1732 * offset in the NIR address so it must be zero so that when you load the
1733 * descriptor you get a pointer to the start of the range.
1735 struct anv_address_range_descriptor
{
1741 enum anv_descriptor_data
{
1742 /** The descriptor contains a BTI reference to a surface state */
1743 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1744 /** The descriptor contains a BTI reference to a sampler state */
1745 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1746 /** The descriptor contains an actual buffer view */
1747 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1748 /** The descriptor contains auxiliary image layout data */
1749 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1750 /** The descriptor contains auxiliary image layout data */
1751 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1752 /** anv_address_range_descriptor with a buffer address and range */
1753 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1754 /** Bindless surface handle */
1755 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1756 /** Storage image handles */
1757 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1758 /** Storage image handles */
1759 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1762 struct anv_descriptor_set_binding_layout
{
1764 /* The type of the descriptors in this binding */
1765 VkDescriptorType type
;
1768 /* Flags provided when this binding was created */
1769 VkDescriptorBindingFlagsEXT flags
;
1771 /* Bitfield representing the type of data this descriptor contains */
1772 enum anv_descriptor_data data
;
1774 /* Maximum number of YCbCr texture/sampler planes */
1775 uint8_t max_plane_count
;
1777 /* Number of array elements in this binding (or size in bytes for inline
1780 uint16_t array_size
;
1782 /* Index into the flattend descriptor set */
1783 uint16_t descriptor_index
;
1785 /* Index into the dynamic state array for a dynamic buffer */
1786 int16_t dynamic_offset_index
;
1788 /* Index into the descriptor set buffer views */
1789 int16_t buffer_view_index
;
1791 /* Offset into the descriptor buffer where this descriptor lives */
1792 uint32_t descriptor_offset
;
1794 /* Immutable samplers (or NULL if no immutable samplers) */
1795 struct anv_sampler
**immutable_samplers
;
1798 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1800 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1801 VkDescriptorType type
);
1803 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1804 const struct anv_descriptor_set_binding_layout
*binding
,
1807 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1808 const struct anv_descriptor_set_binding_layout
*binding
,
1811 struct anv_descriptor_set_layout
{
1812 /* Descriptor set layouts can be destroyed at almost any time */
1815 /* Number of bindings in this descriptor set */
1816 uint16_t binding_count
;
1818 /* Total size of the descriptor set with room for all array entries */
1821 /* Shader stages affected by this descriptor set */
1822 uint16_t shader_stages
;
1824 /* Number of buffer views in this descriptor set */
1825 uint16_t buffer_view_count
;
1827 /* Number of dynamic offsets used by this descriptor set */
1828 uint16_t dynamic_offset_count
;
1830 /* For each shader stage, which offsets apply to that stage */
1831 uint16_t stage_dynamic_offsets
[MESA_SHADER_STAGES
];
1833 /* Size of the descriptor buffer for this descriptor set */
1834 uint32_t descriptor_buffer_size
;
1836 /* Bindings in this descriptor set */
1837 struct anv_descriptor_set_binding_layout binding
[0];
1841 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1843 assert(layout
&& layout
->ref_cnt
>= 1);
1844 p_atomic_inc(&layout
->ref_cnt
);
1848 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1849 struct anv_descriptor_set_layout
*layout
)
1851 assert(layout
&& layout
->ref_cnt
>= 1);
1852 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1853 vk_free(&device
->alloc
, layout
);
1856 struct anv_descriptor
{
1857 VkDescriptorType type
;
1861 VkImageLayout layout
;
1862 struct anv_image_view
*image_view
;
1863 struct anv_sampler
*sampler
;
1867 struct anv_buffer
*buffer
;
1872 struct anv_buffer_view
*buffer_view
;
1876 struct anv_descriptor_set
{
1877 struct anv_descriptor_pool
*pool
;
1878 struct anv_descriptor_set_layout
*layout
;
1881 /* State relative to anv_descriptor_pool::bo */
1882 struct anv_state desc_mem
;
1883 /* Surface state for the descriptor buffer */
1884 struct anv_state desc_surface_state
;
1886 uint32_t buffer_view_count
;
1887 struct anv_buffer_view
*buffer_views
;
1889 /* Link to descriptor pool's desc_sets list . */
1890 struct list_head pool_link
;
1892 struct anv_descriptor descriptors
[0];
1895 struct anv_buffer_view
{
1896 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1897 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1899 struct anv_address address
;
1901 struct anv_state surface_state
;
1902 struct anv_state storage_surface_state
;
1903 struct anv_state writeonly_storage_surface_state
;
1905 struct brw_image_param storage_image_param
;
1908 struct anv_push_descriptor_set
{
1909 struct anv_descriptor_set set
;
1911 /* Put this field right behind anv_descriptor_set so it fills up the
1912 * descriptors[0] field. */
1913 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1915 /** True if the descriptor set buffer has been referenced by a draw or
1918 bool set_used_on_gpu
;
1920 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1923 struct anv_descriptor_pool
{
1929 struct util_vma_heap bo_heap
;
1931 struct anv_state_stream surface_state_stream
;
1932 void *surface_state_free_list
;
1934 struct list_head desc_sets
;
1939 enum anv_descriptor_template_entry_type
{
1940 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1941 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1942 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1945 struct anv_descriptor_template_entry
{
1946 /* The type of descriptor in this entry */
1947 VkDescriptorType type
;
1949 /* Binding in the descriptor set */
1952 /* Offset at which to write into the descriptor set binding */
1953 uint32_t array_element
;
1955 /* Number of elements to write into the descriptor set binding */
1956 uint32_t array_count
;
1958 /* Offset into the user provided data */
1961 /* Stride between elements into the user provided data */
1965 struct anv_descriptor_update_template
{
1966 VkPipelineBindPoint bind_point
;
1968 /* The descriptor set this template corresponds to. This value is only
1969 * valid if the template was created with the templateType
1970 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1974 /* Number of entries in this template */
1975 uint32_t entry_count
;
1977 /* Entries of the template */
1978 struct anv_descriptor_template_entry entries
[0];
1982 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1985 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1986 struct anv_descriptor_set
*set
,
1987 const VkDescriptorImageInfo
* const info
,
1988 VkDescriptorType type
,
1993 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1994 struct anv_descriptor_set
*set
,
1995 VkDescriptorType type
,
1996 struct anv_buffer_view
*buffer_view
,
2001 anv_descriptor_set_write_buffer(struct anv_device
*device
,
2002 struct anv_descriptor_set
*set
,
2003 struct anv_state_stream
*alloc_stream
,
2004 VkDescriptorType type
,
2005 struct anv_buffer
*buffer
,
2008 VkDeviceSize offset
,
2009 VkDeviceSize range
);
2011 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
2012 struct anv_descriptor_set
*set
,
2019 anv_descriptor_set_write_template(struct anv_device
*device
,
2020 struct anv_descriptor_set
*set
,
2021 struct anv_state_stream
*alloc_stream
,
2022 const struct anv_descriptor_update_template
*template,
2026 anv_descriptor_set_create(struct anv_device
*device
,
2027 struct anv_descriptor_pool
*pool
,
2028 struct anv_descriptor_set_layout
*layout
,
2029 struct anv_descriptor_set
**out_set
);
2032 anv_descriptor_set_destroy(struct anv_device
*device
,
2033 struct anv_descriptor_pool
*pool
,
2034 struct anv_descriptor_set
*set
);
2036 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2037 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2038 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2039 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2040 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2041 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2043 struct anv_pipeline_binding
{
2044 /** Index in the descriptor set
2046 * This is a flattened index; the descriptor set layout is already taken
2051 /** The descriptor set this surface corresponds to.
2053 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2054 * binding is not a normal descriptor set but something else.
2059 /** Plane in the binding index for images */
2062 /** Input attachment index (relative to the subpass) */
2063 uint8_t input_attachment_index
;
2065 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2066 uint8_t dynamic_offset_index
;
2069 /** For a storage image, whether it is write-only */
2072 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2073 * assuming POD zero-initialization.
2078 struct anv_push_range
{
2079 /** Index in the descriptor set */
2082 /** Descriptor set index */
2085 /** Dynamic offset index (for dynamic UBOs) */
2086 uint8_t dynamic_offset_index
;
2088 /** Start offset in units of 32B */
2091 /** Range in units of 32B */
2095 struct anv_pipeline_layout
{
2097 struct anv_descriptor_set_layout
*layout
;
2098 uint32_t dynamic_offset_start
;
2103 unsigned char sha1
[20];
2107 struct anv_device
* device
;
2110 VkBufferUsageFlags usage
;
2112 /* Set when bound */
2113 struct anv_address address
;
2116 static inline uint64_t
2117 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2119 assert(offset
<= buffer
->size
);
2120 if (range
== VK_WHOLE_SIZE
) {
2121 return buffer
->size
- offset
;
2123 assert(range
+ offset
>= range
);
2124 assert(range
+ offset
<= buffer
->size
);
2129 enum anv_cmd_dirty_bits
{
2130 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2131 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2132 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2133 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2134 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2135 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2136 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2137 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2138 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2139 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2140 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2141 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2142 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2143 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2145 typedef uint32_t anv_cmd_dirty_mask_t
;
2147 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2148 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2149 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2150 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2151 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2152 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2153 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2154 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2155 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2156 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2157 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2159 static inline enum anv_cmd_dirty_bits
2160 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2163 case VK_DYNAMIC_STATE_VIEWPORT
:
2164 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2165 case VK_DYNAMIC_STATE_SCISSOR
:
2166 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2167 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2168 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2169 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2170 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2171 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2172 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2173 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2174 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2175 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2176 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2177 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2178 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2179 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2180 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2181 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2182 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2184 assert(!"Unsupported dynamic state");
2190 enum anv_pipe_bits
{
2191 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2192 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2193 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2194 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2195 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2196 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2197 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2198 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2199 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2200 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2201 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2202 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2204 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2205 * a flush has happened but not a CS stall. The next time we do any sort
2206 * of invalidation we need to insert a CS stall at that time. Otherwise,
2207 * we would have to CS stall on every flush which could be bad.
2209 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2211 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2212 * target operations related to transfer commands with VkBuffer as
2213 * destination are ongoing. Some operations like copies on the command
2214 * streamer might need to be aware of this to trigger the appropriate stall
2215 * before they can proceed with the copy.
2217 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2220 #define ANV_PIPE_FLUSH_BITS ( \
2221 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2222 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2223 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2224 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2226 #define ANV_PIPE_STALL_BITS ( \
2227 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2228 ANV_PIPE_DEPTH_STALL_BIT | \
2229 ANV_PIPE_CS_STALL_BIT)
2231 #define ANV_PIPE_INVALIDATE_BITS ( \
2232 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2233 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2234 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2235 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2236 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2237 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2239 static inline enum anv_pipe_bits
2240 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2242 enum anv_pipe_bits pipe_bits
= 0;
2245 for_each_bit(b
, flags
) {
2246 switch ((VkAccessFlagBits
)(1 << b
)) {
2247 case VK_ACCESS_SHADER_WRITE_BIT
:
2248 /* We're transitioning a buffer that was previously used as write
2249 * destination through the data port. To make its content available
2250 * to future operations, flush the data cache.
2252 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2254 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2255 /* We're transitioning a buffer that was previously used as render
2256 * target. To make its content available to future operations, flush
2257 * the render target cache.
2259 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2261 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2262 /* We're transitioning a buffer that was previously used as depth
2263 * buffer. To make its content available to future operations, flush
2266 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2268 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2269 /* We're transitioning a buffer that was previously used as a
2270 * transfer write destination. Generic write operations include color
2271 * & depth operations as well as buffer operations like :
2272 * - vkCmdClearColorImage()
2273 * - vkCmdClearDepthStencilImage()
2274 * - vkCmdBlitImage()
2275 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2277 * Most of these operations are implemented using Blorp which writes
2278 * through the render target, so flush that cache to make it visible
2279 * to future operations. And for depth related operations we also
2280 * need to flush the depth cache.
2282 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2283 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2285 case VK_ACCESS_MEMORY_WRITE_BIT
:
2286 /* We're transitioning a buffer for generic write operations. Flush
2289 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2292 break; /* Nothing to do */
2299 static inline enum anv_pipe_bits
2300 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2302 enum anv_pipe_bits pipe_bits
= 0;
2305 for_each_bit(b
, flags
) {
2306 switch ((VkAccessFlagBits
)(1 << b
)) {
2307 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2308 /* Indirect draw commands take a buffer as input that we're going to
2309 * read from the command streamer to load some of the HW registers
2310 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2311 * command streamer stall so that all the cache flushes have
2312 * completed before the command streamer loads from memory.
2314 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2315 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2316 * through a vertex buffer, so invalidate that cache.
2318 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2319 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2320 * UBO from the buffer, so we need to invalidate constant cache.
2322 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2324 case VK_ACCESS_INDEX_READ_BIT
:
2325 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2326 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2327 * commands, so we invalidate the VF cache to make sure there is no
2328 * stale data when we start rendering.
2330 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2332 case VK_ACCESS_UNIFORM_READ_BIT
:
2333 /* We transitioning a buffer to be used as uniform data. Because
2334 * uniform is accessed through the data port & sampler, we need to
2335 * invalidate the texture cache (sampler) & constant cache (data
2336 * port) to avoid stale data.
2338 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2339 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2341 case VK_ACCESS_SHADER_READ_BIT
:
2342 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2343 case VK_ACCESS_TRANSFER_READ_BIT
:
2344 /* Transitioning a buffer to be read through the sampler, so
2345 * invalidate the texture cache, we don't want any stale data.
2347 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2349 case VK_ACCESS_MEMORY_READ_BIT
:
2350 /* Transitioning a buffer for generic read, invalidate all the
2353 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2355 case VK_ACCESS_MEMORY_WRITE_BIT
:
2356 /* Generic write, make sure all previously written things land in
2359 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2361 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2362 /* Transitioning a buffer for conditional rendering. We'll load the
2363 * content of this buffer into HW registers using the command
2364 * streamer, so we need to stall the command streamer to make sure
2365 * any in-flight flush operations have completed.
2367 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2370 break; /* Nothing to do */
2377 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2378 VK_IMAGE_ASPECT_COLOR_BIT | \
2379 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2380 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2381 VK_IMAGE_ASPECT_PLANE_2_BIT)
2382 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2383 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2384 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2385 VK_IMAGE_ASPECT_PLANE_2_BIT)
2387 struct anv_vertex_binding
{
2388 struct anv_buffer
* buffer
;
2389 VkDeviceSize offset
;
2392 struct anv_xfb_binding
{
2393 struct anv_buffer
* buffer
;
2394 VkDeviceSize offset
;
2398 struct anv_push_constants
{
2399 /** Push constant data provided by the client through vkPushConstants */
2400 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2402 /** Dynamic offsets for dynamic UBOs and SSBOs */
2403 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2406 /** Base workgroup ID
2408 * Used for vkCmdDispatchBase.
2410 uint32_t base_work_group_id
[3];
2414 * This is never set by software but is implicitly filled out when
2415 * uploading the push constants for compute shaders.
2417 uint32_t subgroup_id
;
2419 /** Pad out to a multiple of 32 bytes */
2424 struct anv_dynamic_state
{
2427 VkViewport viewports
[MAX_VIEWPORTS
];
2432 VkRect2D scissors
[MAX_SCISSORS
];
2443 float blend_constants
[4];
2453 } stencil_compare_mask
;
2458 } stencil_write_mask
;
2463 } stencil_reference
;
2471 extern const struct anv_dynamic_state default_dynamic_state
;
2473 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2474 const struct anv_dynamic_state
*src
,
2475 uint32_t copy_mask
);
2477 struct anv_surface_state
{
2478 struct anv_state state
;
2479 /** Address of the surface referred to by this state
2481 * This address is relative to the start of the BO.
2483 struct anv_address address
;
2484 /* Address of the aux surface, if any
2486 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2488 * With the exception of gen8, the bottom 12 bits of this address' offset
2489 * include extra aux information.
2491 struct anv_address aux_address
;
2492 /* Address of the clear color, if any
2494 * This address is relative to the start of the BO.
2496 struct anv_address clear_address
;
2500 * Attachment state when recording a renderpass instance.
2502 * The clear value is valid only if there exists a pending clear.
2504 struct anv_attachment_state
{
2505 enum isl_aux_usage aux_usage
;
2506 enum isl_aux_usage input_aux_usage
;
2507 struct anv_surface_state color
;
2508 struct anv_surface_state input
;
2510 VkImageLayout current_layout
;
2511 VkImageLayout current_stencil_layout
;
2512 VkImageAspectFlags pending_clear_aspects
;
2513 VkImageAspectFlags pending_load_aspects
;
2515 VkClearValue clear_value
;
2516 bool clear_color_is_zero_one
;
2517 bool clear_color_is_zero
;
2519 /* When multiview is active, attachments with a renderpass clear
2520 * operation have their respective layers cleared on the first
2521 * subpass that uses them, and only in that subpass. We keep track
2522 * of this using a bitfield to indicate which layers of an attachment
2523 * have not been cleared yet when multiview is active.
2525 uint32_t pending_clear_views
;
2526 struct anv_image_view
* image_view
;
2529 /** State tracking for vertex buffer flushes
2531 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2532 * addresses. If you happen to have two vertex buffers which get placed
2533 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2534 * collisions. In order to solve this problem, we track vertex address ranges
2535 * which are live in the cache and invalidate the cache if one ever exceeds 32
2538 struct anv_vb_cache_range
{
2539 /* Virtual address at which the live vertex buffer cache range starts for
2540 * this vertex buffer index.
2544 /* Virtual address of the byte after where vertex buffer cache range ends.
2545 * This is exclusive such that end - start is the size of the range.
2550 /** State tracking for particular pipeline bind point
2552 * This struct is the base struct for anv_cmd_graphics_state and
2553 * anv_cmd_compute_state. These are used to track state which is bound to a
2554 * particular type of pipeline. Generic state that applies per-stage such as
2555 * binding table offsets and push constants is tracked generically with a
2556 * per-stage array in anv_cmd_state.
2558 struct anv_cmd_pipeline_state
{
2559 struct anv_pipeline
*pipeline
;
2561 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2562 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2565 /** State tracking for graphics pipeline
2567 * This has anv_cmd_pipeline_state as a base struct to track things which get
2568 * bound to a graphics pipeline. Along with general pipeline bind point state
2569 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2570 * state which is graphics-specific.
2572 struct anv_cmd_graphics_state
{
2573 struct anv_cmd_pipeline_state base
;
2575 anv_cmd_dirty_mask_t dirty
;
2578 struct anv_vb_cache_range ib_bound_range
;
2579 struct anv_vb_cache_range ib_dirty_range
;
2580 struct anv_vb_cache_range vb_bound_ranges
[33];
2581 struct anv_vb_cache_range vb_dirty_ranges
[33];
2583 struct anv_dynamic_state dynamic
;
2586 struct anv_buffer
*index_buffer
;
2587 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2588 uint32_t index_offset
;
2592 /** State tracking for compute pipeline
2594 * This has anv_cmd_pipeline_state as a base struct to track things which get
2595 * bound to a compute pipeline. Along with general pipeline bind point state
2596 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2597 * state which is compute-specific.
2599 struct anv_cmd_compute_state
{
2600 struct anv_cmd_pipeline_state base
;
2602 bool pipeline_dirty
;
2604 struct anv_address num_workgroups
;
2607 /** State required while building cmd buffer */
2608 struct anv_cmd_state
{
2609 /* PIPELINE_SELECT.PipelineSelection */
2610 uint32_t current_pipeline
;
2611 const struct gen_l3_config
* current_l3_config
;
2612 uint32_t last_aux_map_state
;
2614 struct anv_cmd_graphics_state gfx
;
2615 struct anv_cmd_compute_state compute
;
2617 enum anv_pipe_bits pending_pipe_bits
;
2618 VkShaderStageFlags descriptors_dirty
;
2619 VkShaderStageFlags push_constants_dirty
;
2621 struct anv_framebuffer
* framebuffer
;
2622 struct anv_render_pass
* pass
;
2623 struct anv_subpass
* subpass
;
2624 VkRect2D render_area
;
2625 uint32_t restart_index
;
2626 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2628 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2629 VkShaderStageFlags push_constant_stages
;
2630 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2631 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2632 struct anv_state samplers
[MESA_SHADER_STAGES
];
2634 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2635 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2636 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2639 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2640 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2641 * and before invoking the secondary in ExecuteCommands.
2643 bool pma_fix_enabled
;
2646 * Whether or not we know for certain that HiZ is enabled for the current
2647 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2648 * enabled or not, this will be false.
2652 bool conditional_render_enabled
;
2655 * Last rendering scale argument provided to
2656 * genX(cmd_buffer_emit_hashing_mode)().
2658 unsigned current_hash_scale
;
2661 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2662 * valid only when recording a render pass instance.
2664 struct anv_attachment_state
* attachments
;
2667 * Surface states for color render targets. These are stored in a single
2668 * flat array. For depth-stencil attachments, the surface state is simply
2671 struct anv_state render_pass_states
;
2674 * A null surface state of the right size to match the framebuffer. This
2675 * is one of the states in render_pass_states.
2677 struct anv_state null_surface_state
;
2680 struct anv_cmd_pool
{
2681 VkAllocationCallbacks alloc
;
2682 struct list_head cmd_buffers
;
2685 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2687 enum anv_cmd_buffer_exec_mode
{
2688 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2689 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2690 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2691 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2692 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2695 struct anv_cmd_buffer
{
2696 VK_LOADER_DATA _loader_data
;
2698 struct anv_device
* device
;
2700 struct anv_cmd_pool
* pool
;
2701 struct list_head pool_link
;
2703 struct anv_batch batch
;
2705 /* Fields required for the actual chain of anv_batch_bo's.
2707 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2709 struct list_head batch_bos
;
2710 enum anv_cmd_buffer_exec_mode exec_mode
;
2712 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2713 * referenced by this command buffer
2715 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2717 struct u_vector seen_bbos
;
2719 /* A vector of int32_t's for every block of binding tables.
2721 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2723 struct u_vector bt_block_states
;
2724 struct anv_state bt_next
;
2726 struct anv_reloc_list surface_relocs
;
2727 /** Last seen surface state block pool center bo offset */
2728 uint32_t last_ss_pool_center
;
2730 /* Serial for tracking buffer completion */
2733 /* Stream objects for storing temporary data */
2734 struct anv_state_stream surface_state_stream
;
2735 struct anv_state_stream dynamic_state_stream
;
2737 VkCommandBufferUsageFlags usage_flags
;
2738 VkCommandBufferLevel level
;
2740 struct anv_cmd_state state
;
2742 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2743 uint64_t intel_perf_marker
;
2746 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2747 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2748 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2749 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2750 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2751 struct anv_cmd_buffer
*secondary
);
2752 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2753 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
2754 struct anv_cmd_buffer
*cmd_buffer
,
2755 const VkSemaphore
*in_semaphores
,
2756 const uint64_t *in_wait_values
,
2757 uint32_t num_in_semaphores
,
2758 const VkSemaphore
*out_semaphores
,
2759 const uint64_t *out_signal_values
,
2760 uint32_t num_out_semaphores
,
2763 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2765 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2766 const void *data
, uint32_t size
, uint32_t alignment
);
2767 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2768 uint32_t *a
, uint32_t *b
,
2769 uint32_t dwords
, uint32_t alignment
);
2772 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2774 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2775 uint32_t entries
, uint32_t *state_offset
);
2777 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2779 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2780 uint32_t size
, uint32_t alignment
);
2783 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2785 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2786 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2787 bool depth_clamp_enable
);
2788 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2790 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2791 struct anv_render_pass
*pass
,
2792 struct anv_framebuffer
*framebuffer
,
2793 const VkClearValue
*clear_values
);
2795 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2798 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2799 gl_shader_stage stage
);
2801 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2803 const struct anv_image_view
*
2804 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2807 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2808 uint32_t num_entries
,
2809 uint32_t *state_offset
,
2810 struct anv_state
*bt_state
);
2812 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2814 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2816 enum anv_fence_type
{
2817 ANV_FENCE_TYPE_NONE
= 0,
2819 ANV_FENCE_TYPE_WSI_BO
,
2820 ANV_FENCE_TYPE_SYNCOBJ
,
2824 enum anv_bo_fence_state
{
2825 /** Indicates that this is a new (or newly reset fence) */
2826 ANV_BO_FENCE_STATE_RESET
,
2828 /** Indicates that this fence has been submitted to the GPU but is still
2829 * (as far as we know) in use by the GPU.
2831 ANV_BO_FENCE_STATE_SUBMITTED
,
2833 ANV_BO_FENCE_STATE_SIGNALED
,
2836 struct anv_fence_impl
{
2837 enum anv_fence_type type
;
2840 /** Fence implementation for BO fences
2842 * These fences use a BO and a set of CPU-tracked state flags. The BO
2843 * is added to the object list of the last execbuf call in a QueueSubmit
2844 * and is marked EXEC_WRITE. The state flags track when the BO has been
2845 * submitted to the kernel. We need to do this because Vulkan lets you
2846 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2847 * will say it's idle in this case.
2851 enum anv_bo_fence_state state
;
2854 /** DRM syncobj handle for syncobj-based fences */
2858 struct wsi_fence
*fence_wsi
;
2863 /* Permanent fence state. Every fence has some form of permanent state
2864 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2865 * cross-process fences) or it could just be a dummy for use internally.
2867 struct anv_fence_impl permanent
;
2869 /* Temporary fence state. A fence *may* have temporary state. That state
2870 * is added to the fence by an import operation and is reset back to
2871 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2872 * state cannot be signaled because the fence must already be signaled
2873 * before the temporary state can be exported from the fence in the other
2874 * process and imported here.
2876 struct anv_fence_impl temporary
;
2879 void anv_fence_reset_temporary(struct anv_device
*device
,
2880 struct anv_fence
*fence
);
2884 struct anv_state state
;
2887 enum anv_semaphore_type
{
2888 ANV_SEMAPHORE_TYPE_NONE
= 0,
2889 ANV_SEMAPHORE_TYPE_DUMMY
,
2890 ANV_SEMAPHORE_TYPE_BO
,
2891 ANV_SEMAPHORE_TYPE_WSI_BO
,
2892 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2893 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2894 ANV_SEMAPHORE_TYPE_TIMELINE
,
2897 struct anv_timeline_point
{
2898 struct list_head link
;
2902 /* Number of waiter on this point, when > 0 the point should not be garbage
2907 /* BO used for synchronization. */
2911 struct anv_timeline
{
2912 pthread_mutex_t mutex
;
2913 pthread_cond_t cond
;
2915 uint64_t highest_past
;
2916 uint64_t highest_pending
;
2918 struct list_head points
;
2919 struct list_head free_points
;
2922 struct anv_semaphore_impl
{
2923 enum anv_semaphore_type type
;
2926 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
2927 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
2928 * object list on any execbuf2 calls for which this semaphore is used as
2929 * a wait or signal fence. When used as a signal fence or when type ==
2930 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
2934 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2935 * If the semaphore is in the unsignaled state due to either just being
2936 * created or because it has been used for a wait, fd will be -1.
2940 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2941 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2942 * import so we don't need to bother with a userspace cache.
2946 /* Non shareable timeline semaphore
2948 * Used when kernel don't have support for timeline semaphores.
2950 struct anv_timeline timeline
;
2954 struct anv_semaphore
{
2957 /* Permanent semaphore state. Every semaphore has some form of permanent
2958 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2959 * (for cross-process semaphores0 or it could just be a dummy for use
2962 struct anv_semaphore_impl permanent
;
2964 /* Temporary semaphore state. A semaphore *may* have temporary state.
2965 * That state is added to the semaphore by an import operation and is reset
2966 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2967 * semaphore with temporary state cannot be signaled because the semaphore
2968 * must already be signaled before the temporary state can be exported from
2969 * the semaphore in the other process and imported here.
2971 struct anv_semaphore_impl temporary
;
2974 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2975 struct anv_semaphore
*semaphore
);
2977 struct anv_shader_module
{
2978 unsigned char sha1
[20];
2983 static inline gl_shader_stage
2984 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2986 assert(__builtin_popcount(vk_stage
) == 1);
2987 return ffs(vk_stage
) - 1;
2990 static inline VkShaderStageFlagBits
2991 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2993 return (1 << mesa_stage
);
2996 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2998 #define anv_foreach_stage(stage, stage_bits) \
2999 for (gl_shader_stage stage, \
3000 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3001 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3002 __tmp &= ~(1 << (stage)))
3004 struct anv_pipeline_bind_map
{
3005 unsigned char surface_sha1
[20];
3006 unsigned char sampler_sha1
[20];
3007 unsigned char push_sha1
[20];
3009 uint32_t surface_count
;
3010 uint32_t sampler_count
;
3012 struct anv_pipeline_binding
* surface_to_descriptor
;
3013 struct anv_pipeline_binding
* sampler_to_descriptor
;
3015 struct anv_push_range push_ranges
[4];
3018 struct anv_shader_bin_key
{
3023 struct anv_shader_bin
{
3026 const struct anv_shader_bin_key
*key
;
3028 struct anv_state kernel
;
3029 uint32_t kernel_size
;
3031 struct anv_state constant_data
;
3032 uint32_t constant_data_size
;
3034 const struct brw_stage_prog_data
*prog_data
;
3035 uint32_t prog_data_size
;
3037 struct brw_compile_stats stats
[3];
3040 struct nir_xfb_info
*xfb_info
;
3042 struct anv_pipeline_bind_map bind_map
;
3045 struct anv_shader_bin
*
3046 anv_shader_bin_create(struct anv_device
*device
,
3047 const void *key
, uint32_t key_size
,
3048 const void *kernel
, uint32_t kernel_size
,
3049 const void *constant_data
, uint32_t constant_data_size
,
3050 const struct brw_stage_prog_data
*prog_data
,
3051 uint32_t prog_data_size
, const void *prog_data_param
,
3052 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
3053 const struct nir_xfb_info
*xfb_info
,
3054 const struct anv_pipeline_bind_map
*bind_map
);
3057 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3060 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3062 assert(shader
&& shader
->ref_cnt
>= 1);
3063 p_atomic_inc(&shader
->ref_cnt
);
3067 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3069 assert(shader
&& shader
->ref_cnt
>= 1);
3070 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3071 anv_shader_bin_destroy(device
, shader
);
3074 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
3075 #define MAX_PIPELINE_EXECUTABLES 7
3077 struct anv_pipeline_executable
{
3078 gl_shader_stage stage
;
3080 struct brw_compile_stats stats
;
3086 struct anv_pipeline
{
3087 struct anv_device
* device
;
3088 struct anv_batch batch
;
3089 uint32_t batch_data
[512];
3090 struct anv_reloc_list batch_relocs
;
3091 anv_cmd_dirty_mask_t dynamic_state_mask
;
3092 struct anv_dynamic_state dynamic_state
;
3096 VkPipelineCreateFlags flags
;
3097 struct anv_subpass
* subpass
;
3099 bool needs_data_cache
;
3101 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3103 uint32_t num_executables
;
3104 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
3107 const struct gen_l3_config
* l3_config
;
3108 uint32_t total_size
;
3111 VkShaderStageFlags active_stages
;
3112 struct anv_state blend_state
;
3115 struct anv_pipeline_vertex_binding
{
3118 uint32_t instance_divisor
;
3123 bool primitive_restart
;
3126 uint32_t cs_right_mask
;
3129 bool depth_test_enable
;
3130 bool writes_stencil
;
3131 bool stencil_test_enable
;
3132 bool depth_clamp_enable
;
3133 bool depth_clip_enable
;
3134 bool sample_shading_enable
;
3136 bool depth_bounds_test_enable
;
3140 uint32_t depth_stencil_state
[3];
3146 uint32_t wm_depth_stencil
[3];
3150 uint32_t wm_depth_stencil
[4];
3153 uint32_t interface_descriptor_data
[8];
3157 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
3158 gl_shader_stage stage
)
3160 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3163 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
3164 static inline const struct brw_##prefix##_prog_data * \
3165 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
3167 if (anv_pipeline_has_stage(pipeline, stage)) { \
3168 return (const struct brw_##prefix##_prog_data *) \
3169 pipeline->shaders[stage]->prog_data; \
3175 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3176 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3177 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3178 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3179 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3180 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
3182 static inline const struct brw_vue_prog_data
*
3183 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
3185 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3186 return &get_gs_prog_data(pipeline
)->base
;
3187 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3188 return &get_tes_prog_data(pipeline
)->base
;
3190 return &get_vs_prog_data(pipeline
)->base
;
3194 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
3195 struct anv_pipeline_cache
*cache
,
3196 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3197 const VkAllocationCallbacks
*alloc
);
3200 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
3201 struct anv_pipeline_cache
*cache
,
3202 const VkComputePipelineCreateInfo
*info
,
3203 const struct anv_shader_module
*module
,
3204 const char *entrypoint
,
3205 const VkSpecializationInfo
*spec_info
);
3207 struct anv_format_plane
{
3208 enum isl_format isl_format
:16;
3209 struct isl_swizzle swizzle
;
3211 /* Whether this plane contains chroma channels */
3214 /* For downscaling of YUV planes */
3215 uint8_t denominator_scales
[2];
3217 /* How to map sampled ycbcr planes to a single 4 component element. */
3218 struct isl_swizzle ycbcr_swizzle
;
3220 /* What aspect is associated to this plane */
3221 VkImageAspectFlags aspect
;
3226 struct anv_format_plane planes
[3];
3232 static inline uint32_t
3233 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3234 VkImageAspectFlags aspect_mask
)
3236 switch (aspect_mask
) {
3237 case VK_IMAGE_ASPECT_COLOR_BIT
:
3238 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3239 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3241 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3242 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3245 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3247 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3250 /* Purposefully assert with depth/stencil aspects. */
3251 unreachable("invalid image aspect");
3255 static inline VkImageAspectFlags
3256 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3259 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3260 if (util_bitcount(image_aspects
) > 1)
3261 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3262 return VK_IMAGE_ASPECT_COLOR_BIT
;
3264 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3265 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3266 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3267 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3270 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3271 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3273 const struct anv_format
*
3274 anv_get_format(VkFormat format
);
3276 static inline uint32_t
3277 anv_get_format_planes(VkFormat vk_format
)
3279 const struct anv_format
*format
= anv_get_format(vk_format
);
3281 return format
!= NULL
? format
->n_planes
: 0;
3284 struct anv_format_plane
3285 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3286 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3288 static inline enum isl_format
3289 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3290 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3292 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3295 bool anv_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
3296 VkImageCreateFlags create_flags
,
3298 VkImageTiling vk_tiling
,
3299 const VkImageFormatListCreateInfoKHR
*fmt_list
);
3301 static inline struct isl_swizzle
3302 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3304 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3305 * RGB as RGBA for texturing
3307 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3308 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3310 /* But it doesn't matter what we render to that channel */
3311 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3317 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3320 * Subsurface of an anv_image.
3322 struct anv_surface
{
3323 /** Valid only if isl_surf::size_B > 0. */
3324 struct isl_surf isl
;
3327 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3333 VkImageType type
; /**< VkImageCreateInfo::imageType */
3334 /* The original VkFormat provided by the client. This may not match any
3335 * of the actual surface formats.
3338 const struct anv_format
*format
;
3340 VkImageAspectFlags aspects
;
3343 uint32_t array_size
;
3344 uint32_t samples
; /**< VkImageCreateInfo::samples */
3346 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3347 VkImageUsageFlags stencil_usage
;
3348 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3349 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3351 /** True if this is needs to be bound to an appropriately tiled BO.
3353 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3354 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3355 * we require a dedicated allocation so that we can know to allocate a
3358 bool needs_set_tiling
;
3361 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3362 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3364 uint64_t drm_format_mod
;
3369 /* Whether the image is made of several underlying buffer objects rather a
3370 * single one with different offsets.
3374 /* All the formats that can be used when creating views of this image
3375 * are CCS_E compatible.
3377 bool ccs_e_compatible
;
3379 /* Image was created with external format. */
3380 bool external_format
;
3385 * For each foo, anv_image::planes[x].surface is valid if and only if
3386 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3387 * to figure the number associated with a given aspect.
3389 * The hardware requires that the depth buffer and stencil buffer be
3390 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3391 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3392 * allocate the depth and stencil buffers as separate surfaces in the same
3397 * -----------------------
3399 * ----------------------- |
3400 * | shadow surface0 | |
3401 * ----------------------- | Plane 0
3402 * | aux surface0 | |
3403 * ----------------------- |
3404 * | fast clear colors0 | \|/
3405 * -----------------------
3407 * ----------------------- |
3408 * | shadow surface1 | |
3409 * ----------------------- | Plane 1
3410 * | aux surface1 | |
3411 * ----------------------- |
3412 * | fast clear colors1 | \|/
3413 * -----------------------
3416 * -----------------------
3420 * Offset of the entire plane (whenever the image is disjoint this is
3428 struct anv_surface surface
;
3431 * A surface which shadows the main surface and may have different
3432 * tiling. This is used for sampling using a tiling that isn't supported
3433 * for other operations.
3435 struct anv_surface shadow_surface
;
3438 * For color images, this is the aux usage for this image when not used
3439 * as a color attachment.
3441 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3442 * image has a HiZ buffer.
3444 enum isl_aux_usage aux_usage
;
3446 struct anv_surface aux_surface
;
3449 * Offset of the fast clear state (used to compute the
3450 * fast_clear_state_offset of the following planes).
3452 uint32_t fast_clear_state_offset
;
3455 * BO associated with this plane, set when bound.
3457 struct anv_address address
;
3460 * Address of the main surface used to fill the aux map table. This is
3461 * used at destruction of the image since the Vulkan spec does not
3462 * guarantee that the address.bo field we still be valid at destruction.
3464 uint64_t aux_map_surface_address
;
3467 * When destroying the image, also free the bo.
3473 /* The ordering of this enum is important */
3474 enum anv_fast_clear_type
{
3475 /** Image does not have/support any fast-clear blocks */
3476 ANV_FAST_CLEAR_NONE
= 0,
3477 /** Image has/supports fast-clear but only to the default value */
3478 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3479 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3480 ANV_FAST_CLEAR_ANY
= 2,
3483 /* Returns the number of auxiliary buffer levels attached to an image. */
3484 static inline uint8_t
3485 anv_image_aux_levels(const struct anv_image
* const image
,
3486 VkImageAspectFlagBits aspect
)
3488 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3490 /* The Gen12 CCS aux surface is represented with only one level. */
3491 const uint8_t aux_logical_levels
=
3492 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3493 image
->planes
[plane
].surface
.isl
.levels
:
3494 image
->planes
[plane
].aux_surface
.isl
.levels
;
3496 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3497 aux_logical_levels
: 0;
3500 /* Returns the number of auxiliary buffer layers attached to an image. */
3501 static inline uint32_t
3502 anv_image_aux_layers(const struct anv_image
* const image
,
3503 VkImageAspectFlagBits aspect
,
3504 const uint8_t miplevel
)
3508 /* The miplevel must exist in the main buffer. */
3509 assert(miplevel
< image
->levels
);
3511 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3512 /* There are no layers with auxiliary data because the miplevel has no
3517 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3519 /* The Gen12 CCS aux surface is represented with only one layer. */
3520 const struct isl_extent4d
*aux_logical_level0_px
=
3521 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3522 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3523 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3525 return MAX2(aux_logical_level0_px
->array_len
,
3526 aux_logical_level0_px
->depth
>> miplevel
);
3530 static inline struct anv_address
3531 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3532 const struct anv_image
*image
,
3533 VkImageAspectFlagBits aspect
)
3535 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3537 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3538 return anv_address_add(image
->planes
[plane
].address
,
3539 image
->planes
[plane
].fast_clear_state_offset
);
3542 static inline struct anv_address
3543 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3544 const struct anv_image
*image
,
3545 VkImageAspectFlagBits aspect
)
3547 struct anv_address addr
=
3548 anv_image_get_clear_color_addr(device
, image
, aspect
);
3550 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3551 device
->isl_dev
.ss
.clear_color_state_size
:
3552 device
->isl_dev
.ss
.clear_value_size
;
3553 return anv_address_add(addr
, clear_color_state_size
);
3556 static inline struct anv_address
3557 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3558 const struct anv_image
*image
,
3559 VkImageAspectFlagBits aspect
,
3560 uint32_t level
, uint32_t array_layer
)
3562 assert(level
< anv_image_aux_levels(image
, aspect
));
3563 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3564 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3565 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3567 struct anv_address addr
=
3568 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3569 addr
.offset
+= 4; /* Go past the fast clear type */
3571 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3572 for (uint32_t l
= 0; l
< level
; l
++)
3573 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3575 addr
.offset
+= level
* image
->array_size
* 4;
3577 addr
.offset
+= array_layer
* 4;
3579 assert(addr
.offset
<
3580 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3584 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3586 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3587 const struct anv_image
*image
)
3589 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3592 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3593 * struct. There's documentation which suggests that this feature actually
3594 * reduces performance on BDW, but it has only been observed to help so
3595 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3596 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3598 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3601 return image
->samples
== 1;
3605 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3606 const struct anv_image
*image
,
3609 return device
->info
.has_aux_map
&&
3610 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3614 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3615 const struct anv_image
*image
,
3616 VkImageAspectFlagBits aspect
,
3617 enum isl_aux_usage aux_usage
,
3619 uint32_t base_layer
,
3620 uint32_t layer_count
);
3623 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3624 const struct anv_image
*image
,
3625 VkImageAspectFlagBits aspect
,
3626 enum isl_aux_usage aux_usage
,
3627 enum isl_format format
, struct isl_swizzle swizzle
,
3628 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3629 VkRect2D area
, union isl_color_value clear_color
);
3631 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3632 const struct anv_image
*image
,
3633 VkImageAspectFlags aspects
,
3634 enum isl_aux_usage depth_aux_usage
,
3636 uint32_t base_layer
, uint32_t layer_count
,
3638 float depth_value
, uint8_t stencil_value
);
3640 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3641 const struct anv_image
*src_image
,
3642 enum isl_aux_usage src_aux_usage
,
3643 uint32_t src_level
, uint32_t src_base_layer
,
3644 const struct anv_image
*dst_image
,
3645 enum isl_aux_usage dst_aux_usage
,
3646 uint32_t dst_level
, uint32_t dst_base_layer
,
3647 VkImageAspectFlagBits aspect
,
3648 uint32_t src_x
, uint32_t src_y
,
3649 uint32_t dst_x
, uint32_t dst_y
,
3650 uint32_t width
, uint32_t height
,
3651 uint32_t layer_count
,
3652 enum blorp_filter filter
);
3654 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3655 const struct anv_image
*image
,
3656 VkImageAspectFlagBits aspect
, uint32_t level
,
3657 uint32_t base_layer
, uint32_t layer_count
,
3658 enum isl_aux_op hiz_op
);
3660 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3661 const struct anv_image
*image
,
3662 VkImageAspectFlags aspects
,
3664 uint32_t base_layer
, uint32_t layer_count
,
3665 VkRect2D area
, uint8_t stencil_value
);
3667 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3668 const struct anv_image
*image
,
3669 enum isl_format format
,
3670 VkImageAspectFlagBits aspect
,
3671 uint32_t base_layer
, uint32_t layer_count
,
3672 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3675 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3676 const struct anv_image
*image
,
3677 enum isl_format format
,
3678 VkImageAspectFlagBits aspect
, uint32_t level
,
3679 uint32_t base_layer
, uint32_t layer_count
,
3680 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3684 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3685 const struct anv_image
*image
,
3686 VkImageAspectFlagBits aspect
,
3687 uint32_t base_level
, uint32_t level_count
,
3688 uint32_t base_layer
, uint32_t layer_count
);
3691 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3692 const struct anv_image
*image
,
3693 const VkImageAspectFlagBits aspect
,
3694 const VkImageLayout layout
);
3696 enum anv_fast_clear_type
3697 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3698 const struct anv_image
* const image
,
3699 const VkImageAspectFlagBits aspect
,
3700 const VkImageLayout layout
);
3702 /* This is defined as a macro so that it works for both
3703 * VkImageSubresourceRange and VkImageSubresourceLayers
3705 #define anv_get_layerCount(_image, _range) \
3706 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3707 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3709 static inline uint32_t
3710 anv_get_levelCount(const struct anv_image
*image
,
3711 const VkImageSubresourceRange
*range
)
3713 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3714 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3717 static inline VkImageAspectFlags
3718 anv_image_expand_aspects(const struct anv_image
*image
,
3719 VkImageAspectFlags aspects
)
3721 /* If the underlying image has color plane aspects and
3722 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3723 * the underlying image. */
3724 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3725 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3726 return image
->aspects
;
3732 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3733 VkImageAspectFlags aspects2
)
3735 if (aspects1
== aspects2
)
3738 /* Only 1 color aspects are compatibles. */
3739 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3740 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3741 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3747 struct anv_image_view
{
3748 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3750 VkImageAspectFlags aspect_mask
;
3752 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3756 uint32_t image_plane
;
3758 struct isl_view isl
;
3761 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3762 * image layout of SHADER_READ_ONLY_OPTIMAL or
3763 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3765 struct anv_surface_state optimal_sampler_surface_state
;
3768 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3769 * image layout of GENERAL.
3771 struct anv_surface_state general_sampler_surface_state
;
3774 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3775 * states for write-only and readable, using the real format for
3776 * write-only and the lowered format for readable.
3778 struct anv_surface_state storage_surface_state
;
3779 struct anv_surface_state writeonly_storage_surface_state
;
3781 struct brw_image_param storage_image_param
;
3785 enum anv_image_view_state_flags
{
3786 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3787 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3790 void anv_image_fill_surface_state(struct anv_device
*device
,
3791 const struct anv_image
*image
,
3792 VkImageAspectFlagBits aspect
,
3793 const struct isl_view
*view
,
3794 isl_surf_usage_flags_t view_usage
,
3795 enum isl_aux_usage aux_usage
,
3796 const union isl_color_value
*clear_color
,
3797 enum anv_image_view_state_flags flags
,
3798 struct anv_surface_state
*state_inout
,
3799 struct brw_image_param
*image_param_out
);
3801 struct anv_image_create_info
{
3802 const VkImageCreateInfo
*vk_info
;
3804 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3805 isl_tiling_flags_t isl_tiling_flags
;
3807 /** These flags will be added to any derived from VkImageCreateInfo. */
3808 isl_surf_usage_flags_t isl_extra_usage_flags
;
3811 bool external_format
;
3814 VkResult
anv_image_create(VkDevice _device
,
3815 const struct anv_image_create_info
*info
,
3816 const VkAllocationCallbacks
* alloc
,
3819 const struct anv_surface
*
3820 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3821 VkImageAspectFlags aspect_mask
);
3824 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3826 static inline VkExtent3D
3827 anv_sanitize_image_extent(const VkImageType imageType
,
3828 const VkExtent3D imageExtent
)
3830 switch (imageType
) {
3831 case VK_IMAGE_TYPE_1D
:
3832 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3833 case VK_IMAGE_TYPE_2D
:
3834 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3835 case VK_IMAGE_TYPE_3D
:
3838 unreachable("invalid image type");
3842 static inline VkOffset3D
3843 anv_sanitize_image_offset(const VkImageType imageType
,
3844 const VkOffset3D imageOffset
)
3846 switch (imageType
) {
3847 case VK_IMAGE_TYPE_1D
:
3848 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3849 case VK_IMAGE_TYPE_2D
:
3850 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3851 case VK_IMAGE_TYPE_3D
:
3854 unreachable("invalid image type");
3858 VkFormatFeatureFlags
3859 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3861 const struct anv_format
*anv_format
,
3862 VkImageTiling vk_tiling
);
3864 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3865 struct anv_state state
,
3866 enum isl_format format
,
3867 struct anv_address address
,
3868 uint32_t range
, uint32_t stride
);
3871 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3872 const struct anv_attachment_state
*att_state
,
3873 const struct anv_image_view
*iview
)
3875 const struct isl_format_layout
*view_fmtl
=
3876 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3878 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3879 if (view_fmtl->channels.c.bits) \
3880 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3882 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3883 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3884 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3885 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3887 #undef COPY_CLEAR_COLOR_CHANNEL
3891 struct anv_ycbcr_conversion
{
3892 const struct anv_format
* format
;
3893 VkSamplerYcbcrModelConversion ycbcr_model
;
3894 VkSamplerYcbcrRange ycbcr_range
;
3895 VkComponentSwizzle mapping
[4];
3896 VkChromaLocation chroma_offsets
[2];
3897 VkFilter chroma_filter
;
3898 bool chroma_reconstruction
;
3901 struct anv_sampler
{
3902 uint32_t state
[3][4];
3904 struct anv_ycbcr_conversion
*conversion
;
3906 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3907 * and with a 32-byte stride for use as bindless samplers.
3909 struct anv_state bindless_state
;
3912 struct anv_framebuffer
{
3917 uint32_t attachment_count
;
3918 struct anv_image_view
* attachments
[0];
3921 struct anv_subpass_attachment
{
3922 VkImageUsageFlagBits usage
;
3923 uint32_t attachment
;
3924 VkImageLayout layout
;
3926 /* Used only with attachment containing stencil data. */
3927 VkImageLayout stencil_layout
;
3930 struct anv_subpass
{
3931 uint32_t attachment_count
;
3934 * A pointer to all attachment references used in this subpass.
3935 * Only valid if ::attachment_count > 0.
3937 struct anv_subpass_attachment
* attachments
;
3938 uint32_t input_count
;
3939 struct anv_subpass_attachment
* input_attachments
;
3940 uint32_t color_count
;
3941 struct anv_subpass_attachment
* color_attachments
;
3942 struct anv_subpass_attachment
* resolve_attachments
;
3944 struct anv_subpass_attachment
* depth_stencil_attachment
;
3945 struct anv_subpass_attachment
* ds_resolve_attachment
;
3946 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3947 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3951 /** Subpass has a depth/stencil self-dependency */
3952 bool has_ds_self_dep
;
3954 /** Subpass has at least one color resolve attachment */
3955 bool has_color_resolve
;
3958 static inline unsigned
3959 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3961 return MAX2(1, util_bitcount(subpass
->view_mask
));
3964 struct anv_render_pass_attachment
{
3965 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3966 * its members individually.
3970 VkImageUsageFlags usage
;
3971 VkAttachmentLoadOp load_op
;
3972 VkAttachmentStoreOp store_op
;
3973 VkAttachmentLoadOp stencil_load_op
;
3974 VkImageLayout initial_layout
;
3975 VkImageLayout final_layout
;
3976 VkImageLayout first_subpass_layout
;
3978 VkImageLayout stencil_initial_layout
;
3979 VkImageLayout stencil_final_layout
;
3981 /* The subpass id in which the attachment will be used last. */
3982 uint32_t last_subpass_idx
;
3985 struct anv_render_pass
{
3986 uint32_t attachment_count
;
3987 uint32_t subpass_count
;
3988 /* An array of subpass_count+1 flushes, one per subpass boundary */
3989 enum anv_pipe_bits
* subpass_flushes
;
3990 struct anv_render_pass_attachment
* attachments
;
3991 struct anv_subpass subpasses
[0];
3994 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3996 struct anv_query_pool
{
3998 VkQueryPipelineStatisticFlags pipeline_statistics
;
3999 /** Stride between slots, in bytes */
4001 /** Number of slots in this query pool */
4006 int anv_get_instance_entrypoint_index(const char *name
);
4007 int anv_get_device_entrypoint_index(const char *name
);
4008 int anv_get_physical_device_entrypoint_index(const char *name
);
4010 const char *anv_get_instance_entry_name(int index
);
4011 const char *anv_get_physical_device_entry_name(int index
);
4012 const char *anv_get_device_entry_name(int index
);
4015 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
4016 const struct anv_instance_extension_table
*instance
);
4018 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4019 const struct anv_instance_extension_table
*instance
);
4021 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4022 const struct anv_instance_extension_table
*instance
,
4023 const struct anv_device_extension_table
*device
);
4025 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
4028 void anv_dump_image_to_ppm(struct anv_device
*device
,
4029 struct anv_image
*image
, unsigned miplevel
,
4030 unsigned array_layer
, VkImageAspectFlagBits aspect
,
4031 const char *filename
);
4033 enum anv_dump_action
{
4034 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
4037 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
4038 void anv_dump_finish(void);
4040 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
4042 static inline uint32_t
4043 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
4045 /* This function must be called from within a subpass. */
4046 assert(cmd_state
->pass
&& cmd_state
->subpass
);
4048 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
4050 /* The id of this subpass shouldn't exceed the number of subpasses in this
4051 * render pass minus 1.
4053 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
4057 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
4058 void anv_device_perf_init(struct anv_device
*device
);
4060 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
4062 static inline struct __anv_type * \
4063 __anv_type ## _from_handle(__VkType _handle) \
4065 return (struct __anv_type *) _handle; \
4068 static inline __VkType \
4069 __anv_type ## _to_handle(struct __anv_type *_obj) \
4071 return (__VkType) _obj; \
4074 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
4076 static inline struct __anv_type * \
4077 __anv_type ## _from_handle(__VkType _handle) \
4079 return (struct __anv_type *)(uintptr_t) _handle; \
4082 static inline __VkType \
4083 __anv_type ## _to_handle(struct __anv_type *_obj) \
4085 return (__VkType)(uintptr_t) _obj; \
4088 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4089 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
4091 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
4092 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
4093 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
4094 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
4095 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
4097 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
4098 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
4099 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
4100 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
4101 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
4102 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
4103 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
4104 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
4105 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
4106 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
4107 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
4108 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
4109 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
4110 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
4111 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
4112 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
4113 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
4114 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
4115 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
4116 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
4117 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
4118 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
4119 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
4121 /* Gen-specific function declarations */
4123 # include "anv_genX.h"
4125 # define genX(x) gen7_##x
4126 # include "anv_genX.h"
4128 # define genX(x) gen75_##x
4129 # include "anv_genX.h"
4131 # define genX(x) gen8_##x
4132 # include "anv_genX.h"
4134 # define genX(x) gen9_##x
4135 # include "anv_genX.h"
4137 # define genX(x) gen10_##x
4138 # include "anv_genX.h"
4140 # define genX(x) gen11_##x
4141 # include "anv_genX.h"
4143 # define genX(x) gen12_##x
4144 # include "anv_genX.h"
4148 #endif /* ANV_PRIVATE_H */