projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
anv: move canonical_address calculation into a separate function
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_gem.h"
46 #include "dev/gen_device_info.h"
47 #include "blorp/blorp.h"
48 #include "compiler/brw_compiler.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/u_atomic.h"
52 #include "util/u_vector.h"
53 #include "vk_alloc.h"
54 #include "vk_debug_report.h"
55
56 /* Pre-declarations needed for WSI entrypoints */
57 struct wl_surface;
58 struct wl_display;
59 typedef struct xcb_connection_t xcb_connection_t;
60 typedef uint32_t xcb_visualid_t;
61 typedef uint32_t xcb_window_t;
62
63 struct anv_buffer;
64 struct anv_buffer_view;
65 struct anv_image_view;
66 struct anv_instance;
67
68 struct gen_l3_config;
69
70 #include <vulkan/vulkan.h>
71 #include <vulkan/vulkan_intel.h>
72 #include <vulkan/vk_icd.h>
73 #include <vulkan/vk_android_native_buffer.h>
74
75 #include "anv_entrypoints.h"
76 #include "anv_extensions.h"
77 #include "isl/isl.h"
78
79 #include "common/gen_debug.h"
80 #include "common/intel_log.h"
81 #include "wsi_common.h"
82
83 /* Allowing different clear colors requires us to perform a depth resolve at
84 * the end of certain render passes. This is because while slow clears store
85 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
86 * See the PRMs for examples describing when additional resolves would be
87 * necessary. To enable fast clears without requiring extra resolves, we set
88 * the clear value to a globally-defined one. We could allow different values
89 * if the user doesn't expect coherent data during or after a render passes
90 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
91 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
92 * 1.0f seems to be the only value used. The only application that doesn't set
93 * this value does so through the usage of an seemingly uninitialized clear
94 * value.
95 */
96 #define ANV_HZ_FC_VAL 1.0f
97
98 #define MAX_VBS 28
99 #define MAX_SETS 8
100 #define MAX_RTS 8
101 #define MAX_VIEWPORTS 16
102 #define MAX_SCISSORS 16
103 #define MAX_PUSH_CONSTANTS_SIZE 128
104 #define MAX_DYNAMIC_BUFFERS 16
105 #define MAX_IMAGES 8
106 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
107
108 /* The kernel relocation API has a limitation of a 32-bit delta value
109 * applied to the address before it is written which, in spite of it being
110 * unsigned, is treated as signed . Because of the way that this maps to
111 * the Vulkan API, we cannot handle an offset into a buffer that does not
112 * fit into a signed 32 bits. The only mechanism we have for dealing with
113 * this at the moment is to limit all VkDeviceMemory objects to a maximum
114 * of 2GB each. The Vulkan spec allows us to do this:
115 *
116 * "Some platforms may have a limit on the maximum size of a single
117 * allocation. For example, certain systems may fail to create
118 * allocations with a size greater than or equal to 4GB. Such a limit is
119 * implementation-dependent, and if such a failure occurs then the error
120 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
121 *
122 * We don't use vk_error here because it's not an error so much as an
123 * indication to the application that the allocation is too large.
124 */
125 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
126
127 #define ANV_SVGS_VB_INDEX MAX_VBS
128 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
129
130 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
131
132 static inline uint32_t
133 align_down_npot_u32(uint32_t v, uint32_t a)
134 {
135 return v - (v % a);
136 }
137
138 static inline uint32_t
139 align_u32(uint32_t v, uint32_t a)
140 {
141 assert(a != 0 && a == (a & -a));
142 return (v + a - 1) & ~(a - 1);
143 }
144
145 static inline uint64_t
146 align_u64(uint64_t v, uint64_t a)
147 {
148 assert(a != 0 && a == (a & -a));
149 return (v + a - 1) & ~(a - 1);
150 }
151
152 static inline int32_t
153 align_i32(int32_t v, int32_t a)
154 {
155 assert(a != 0 && a == (a & -a));
156 return (v + a - 1) & ~(a - 1);
157 }
158
159 /** Alignment must be a power of 2. */
160 static inline bool
161 anv_is_aligned(uintmax_t n, uintmax_t a)
162 {
163 assert(a == (a & -a));
164 return (n & (a - 1)) == 0;
165 }
166
167 static inline uint32_t
168 anv_minify(uint32_t n, uint32_t levels)
169 {
170 if (unlikely(n == 0))
171 return 0;
172 else
173 return MAX2(n >> levels, 1);
174 }
175
176 static inline float
177 anv_clamp_f(float f, float min, float max)
178 {
179 assert(min < max);
180
181 if (f > max)
182 return max;
183 else if (f < min)
184 return min;
185 else
186 return f;
187 }
188
189 static inline bool
190 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
191 {
192 if (*inout_mask & clear_mask) {
193 *inout_mask &= ~clear_mask;
194 return true;
195 } else {
196 return false;
197 }
198 }
199
200 static inline union isl_color_value
201 vk_to_isl_color(VkClearColorValue color)
202 {
203 return (union isl_color_value) {
204 .u32 = {
205 color.uint32[0],
206 color.uint32[1],
207 color.uint32[2],
208 color.uint32[3],
209 },
210 };
211 }
212
213 #define for_each_bit(b, dword) \
214 for (uint32_t __dword = (dword); \
215 (b) = __builtin_ffs(__dword) - 1, __dword; \
216 __dword &= ~(1 << (b)))
217
218 #define typed_memcpy(dest, src, count) ({ \
219 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
220 memcpy((dest), (src), (count) * sizeof(*(src))); \
221 })
222
223 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
224 * to be added here in order to utilize mapping in debug/error/perf macros.
225 */
226 #define REPORT_OBJECT_TYPE(o) \
227 __builtin_choose_expr ( \
228 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
229 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
230 __builtin_choose_expr ( \
231 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
232 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
233 __builtin_choose_expr ( \
234 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
235 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
236 __builtin_choose_expr ( \
237 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
238 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
239 __builtin_choose_expr ( \
240 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
241 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
242 __builtin_choose_expr ( \
243 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
244 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
245 __builtin_choose_expr ( \
246 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
247 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
248 __builtin_choose_expr ( \
249 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
250 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
251 __builtin_choose_expr ( \
252 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
253 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
254 __builtin_choose_expr ( \
255 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
256 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
257 __builtin_choose_expr ( \
258 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
259 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
260 __builtin_choose_expr ( \
261 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
262 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
263 __builtin_choose_expr ( \
264 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
265 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
266 __builtin_choose_expr ( \
267 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
268 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
269 __builtin_choose_expr ( \
270 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
271 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
272 __builtin_choose_expr ( \
273 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
274 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
275 __builtin_choose_expr ( \
276 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
277 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
278 __builtin_choose_expr ( \
279 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
280 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
281 __builtin_choose_expr ( \
282 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
283 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
284 __builtin_choose_expr ( \
285 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
286 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
287 __builtin_choose_expr ( \
288 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
289 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
290 __builtin_choose_expr ( \
291 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
292 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
293 __builtin_choose_expr ( \
294 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
295 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
296 __builtin_choose_expr ( \
297 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
298 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
299 __builtin_choose_expr ( \
300 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
301 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
302 __builtin_choose_expr ( \
303 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
304 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
305 __builtin_choose_expr ( \
306 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
307 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
308 __builtin_choose_expr ( \
309 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
310 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
311 __builtin_choose_expr ( \
312 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
313 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
314 __builtin_choose_expr ( \
315 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
316 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
317 __builtin_choose_expr ( \
318 __builtin_types_compatible_p (__typeof (o), void*), \
319 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
320 /* The void expression results in a compile-time error \
321 when assigning the result to something. */ \
322 (void)0)))))))))))))))))))))))))))))))
323
324 /* Whenever we generate an error, pass it through this function. Useful for
325 * debugging, where we can break on it. Only call at error site, not when
326 * propagating errors. Might be useful to plug in a stack trace here.
327 */
328
329 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
330 VkDebugReportObjectTypeEXT type, VkResult error,
331 const char *file, int line, const char *format, ...);
332
333 #ifdef DEBUG
334 #define vk_error(error) __vk_errorf(NULL, NULL,\
335 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
336 error, __FILE__, __LINE__, NULL)
337 #define vk_errorf(instance, obj, error, format, ...)\
338 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
339 __FILE__, __LINE__, format, ## __VA_ARGS__)
340 #else
341 #define vk_error(error) error
342 #define vk_errorf(instance, obj, error, format, ...) error
343 #endif
344
345 /**
346 * Warn on ignored extension structs.
347 *
348 * The Vulkan spec requires us to ignore unsupported or unknown structs in
349 * a pNext chain. In debug mode, emitting warnings for ignored structs may
350 * help us discover structs that we should not have ignored.
351 *
352 *
353 * From the Vulkan 1.0.38 spec:
354 *
355 * Any component of the implementation (the loader, any enabled layers,
356 * and drivers) must skip over, without processing (other than reading the
357 * sType and pNext members) any chained structures with sType values not
358 * defined by extensions supported by that component.
359 */
360 #define anv_debug_ignored_stype(sType) \
361 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
362
363 void __anv_perf_warn(struct anv_instance *instance, const void *object,
364 VkDebugReportObjectTypeEXT type, const char *file,
365 int line, const char *format, ...)
366 anv_printflike(6, 7);
367 void anv_loge(const char *format, ...) anv_printflike(1, 2);
368 void anv_loge_v(const char *format, va_list va);
369
370 /**
371 * Print a FINISHME message, including its source location.
372 */
373 #define anv_finishme(format, ...) \
374 do { \
375 static bool reported = false; \
376 if (!reported) { \
377 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
378 ##__VA_ARGS__); \
379 reported = true; \
380 } \
381 } while (0)
382
383 /**
384 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
385 */
386 #define anv_perf_warn(instance, obj, format, ...) \
387 do { \
388 static bool reported = false; \
389 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
390 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
391 format, ##__VA_ARGS__); \
392 reported = true; \
393 } \
394 } while (0)
395
396 /* A non-fatal assert. Useful for debugging. */
397 #ifdef DEBUG
398 #define anv_assert(x) ({ \
399 if (unlikely(!(x))) \
400 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
401 })
402 #else
403 #define anv_assert(x)
404 #endif
405
406 /* A multi-pointer allocator
407 *
408 * When copying data structures from the user (such as a render pass), it's
409 * common to need to allocate data for a bunch of different things. Instead
410 * of doing several allocations and having to handle all of the error checking
411 * that entails, it can be easier to do a single allocation. This struct
412 * helps facilitate that. The intended usage looks like this:
413 *
414 * ANV_MULTIALLOC(ma)
415 * anv_multialloc_add(&ma, &main_ptr, 1);
416 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
417 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
418 *
419 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
420 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
421 */
422 struct anv_multialloc {
423 size_t size;
424 size_t align;
425
426 uint32_t ptr_count;
427 void **ptrs[8];
428 };
429
430 #define ANV_MULTIALLOC_INIT \
431 ((struct anv_multialloc) { 0, })
432
433 #define ANV_MULTIALLOC(_name) \
434 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
435
436 __attribute__((always_inline))
437 static inline void
438 _anv_multialloc_add(struct anv_multialloc *ma,
439 void **ptr, size_t size, size_t align)
440 {
441 size_t offset = align_u64(ma->size, align);
442 ma->size = offset + size;
443 ma->align = MAX2(ma->align, align);
444
445 /* Store the offset in the pointer. */
446 *ptr = (void *)(uintptr_t)offset;
447
448 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
449 ma->ptrs[ma->ptr_count++] = ptr;
450 }
451
452 #define anv_multialloc_add_size(_ma, _ptr, _size) \
453 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
454
455 #define anv_multialloc_add(_ma, _ptr, _count) \
456 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
457
458 __attribute__((always_inline))
459 static inline void *
460 anv_multialloc_alloc(struct anv_multialloc *ma,
461 const VkAllocationCallbacks *alloc,
462 VkSystemAllocationScope scope)
463 {
464 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
465 if (!ptr)
466 return NULL;
467
468 /* Fill out each of the pointers with their final value.
469 *
470 * for (uint32_t i = 0; i < ma->ptr_count; i++)
471 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
472 *
473 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
474 * constant, GCC is incapable of figuring this out and unrolling the loop
475 * so we have to give it a little help.
476 */
477 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
478 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
479 if ((_i) < ma->ptr_count) \
480 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
481 _ANV_MULTIALLOC_UPDATE_POINTER(0);
482 _ANV_MULTIALLOC_UPDATE_POINTER(1);
483 _ANV_MULTIALLOC_UPDATE_POINTER(2);
484 _ANV_MULTIALLOC_UPDATE_POINTER(3);
485 _ANV_MULTIALLOC_UPDATE_POINTER(4);
486 _ANV_MULTIALLOC_UPDATE_POINTER(5);
487 _ANV_MULTIALLOC_UPDATE_POINTER(6);
488 _ANV_MULTIALLOC_UPDATE_POINTER(7);
489 #undef _ANV_MULTIALLOC_UPDATE_POINTER
490
491 return ptr;
492 }
493
494 __attribute__((always_inline))
495 static inline void *
496 anv_multialloc_alloc2(struct anv_multialloc *ma,
497 const VkAllocationCallbacks *parent_alloc,
498 const VkAllocationCallbacks *alloc,
499 VkSystemAllocationScope scope)
500 {
501 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
502 }
503
504 struct anv_bo {
505 uint32_t gem_handle;
506
507 /* Index into the current validation list. This is used by the
508 * validation list building alrogithm to track which buffers are already
509 * in the validation list so that we can ensure uniqueness.
510 */
511 uint32_t index;
512
513 /* Last known offset. This value is provided by the kernel when we
514 * execbuf and is used as the presumed offset for the next bunch of
515 * relocations.
516 */
517 uint64_t offset;
518
519 uint64_t size;
520 void *map;
521
522 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
523 uint32_t flags;
524 };
525
526 static inline void
527 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
528 {
529 bo->gem_handle = gem_handle;
530 bo->index = 0;
531 bo->offset = -1;
532 bo->size = size;
533 bo->map = NULL;
534 bo->flags = 0;
535 }
536
537 /* Represents a lock-free linked list of "free" things. This is used by
538 * both the block pool and the state pools. Unfortunately, in order to
539 * solve the ABA problem, we can't use a single uint32_t head.
540 */
541 union anv_free_list {
542 struct {
543 int32_t offset;
544
545 /* A simple count that is incremented every time the head changes. */
546 uint32_t count;
547 };
548 uint64_t u64;
549 };
550
551 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
552
553 struct anv_block_state {
554 union {
555 struct {
556 uint32_t next;
557 uint32_t end;
558 };
559 uint64_t u64;
560 };
561 };
562
563 struct anv_block_pool {
564 struct anv_device *device;
565
566 uint64_t bo_flags;
567
568 struct anv_bo bo;
569
570 /* The offset from the start of the bo to the "center" of the block
571 * pool. Pointers to allocated blocks are given by
572 * bo.map + center_bo_offset + offsets.
573 */
574 uint32_t center_bo_offset;
575
576 /* Current memory map of the block pool. This pointer may or may not
577 * point to the actual beginning of the block pool memory. If
578 * anv_block_pool_alloc_back has ever been called, then this pointer
579 * will point to the "center" position of the buffer and all offsets
580 * (negative or positive) given out by the block pool alloc functions
581 * will be valid relative to this pointer.
582 *
583 * In particular, map == bo.map + center_offset
584 */
585 void *map;
586 int fd;
587
588 /**
589 * Array of mmaps and gem handles owned by the block pool, reclaimed when
590 * the block pool is destroyed.
591 */
592 struct u_vector mmap_cleanups;
593
594 struct anv_block_state state;
595
596 struct anv_block_state back_state;
597 };
598
599 /* Block pools are backed by a fixed-size 1GB memfd */
600 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
601
602 /* The center of the block pool is also the middle of the memfd. This may
603 * change in the future if we decide differently for some reason.
604 */
605 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
606
607 static inline uint32_t
608 anv_block_pool_size(struct anv_block_pool *pool)
609 {
610 return pool->state.end + pool->back_state.end;
611 }
612
613 struct anv_state {
614 int32_t offset;
615 uint32_t alloc_size;
616 void *map;
617 };
618
619 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
620
621 struct anv_fixed_size_state_pool {
622 union anv_free_list free_list;
623 struct anv_block_state block;
624 };
625
626 #define ANV_MIN_STATE_SIZE_LOG2 6
627 #define ANV_MAX_STATE_SIZE_LOG2 20
628
629 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
630
631 struct anv_state_pool {
632 struct anv_block_pool block_pool;
633
634 /* The size of blocks which will be allocated from the block pool */
635 uint32_t block_size;
636
637 /** Free list for "back" allocations */
638 union anv_free_list back_alloc_free_list;
639
640 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
641 };
642
643 struct anv_state_stream_block;
644
645 struct anv_state_stream {
646 struct anv_state_pool *state_pool;
647
648 /* The size of blocks to allocate from the state pool */
649 uint32_t block_size;
650
651 /* Current block we're allocating from */
652 struct anv_state block;
653
654 /* Offset into the current block at which to allocate the next state */
655 uint32_t next;
656
657 /* List of all blocks allocated from this pool */
658 struct anv_state_stream_block *block_list;
659 };
660
661 /* The block_pool functions exported for testing only. The block pool should
662 * only be used via a state pool (see below).
663 */
664 VkResult anv_block_pool_init(struct anv_block_pool *pool,
665 struct anv_device *device,
666 uint32_t initial_size,
667 uint64_t bo_flags);
668 void anv_block_pool_finish(struct anv_block_pool *pool);
669 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
670 uint32_t block_size);
671 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
672 uint32_t block_size);
673
674 VkResult anv_state_pool_init(struct anv_state_pool *pool,
675 struct anv_device *device,
676 uint32_t block_size,
677 uint64_t bo_flags);
678 void anv_state_pool_finish(struct anv_state_pool *pool);
679 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
680 uint32_t state_size, uint32_t alignment);
681 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
682 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
683 void anv_state_stream_init(struct anv_state_stream *stream,
684 struct anv_state_pool *state_pool,
685 uint32_t block_size);
686 void anv_state_stream_finish(struct anv_state_stream *stream);
687 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
688 uint32_t size, uint32_t alignment);
689
690 /**
691 * Implements a pool of re-usable BOs. The interface is identical to that
692 * of block_pool except that each block is its own BO.
693 */
694 struct anv_bo_pool {
695 struct anv_device *device;
696
697 uint64_t bo_flags;
698
699 void *free_list[16];
700 };
701
702 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
703 uint64_t bo_flags);
704 void anv_bo_pool_finish(struct anv_bo_pool *pool);
705 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
706 uint32_t size);
707 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
708
709 struct anv_scratch_bo {
710 bool exists;
711 struct anv_bo bo;
712 };
713
714 struct anv_scratch_pool {
715 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
716 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
717 };
718
719 void anv_scratch_pool_init(struct anv_device *device,
720 struct anv_scratch_pool *pool);
721 void anv_scratch_pool_finish(struct anv_device *device,
722 struct anv_scratch_pool *pool);
723 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
724 struct anv_scratch_pool *pool,
725 gl_shader_stage stage,
726 unsigned per_thread_scratch);
727
728 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
729 struct anv_bo_cache {
730 struct hash_table *bo_map;
731 pthread_mutex_t mutex;
732 };
733
734 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
735 void anv_bo_cache_finish(struct anv_bo_cache *cache);
736 VkResult anv_bo_cache_alloc(struct anv_device *device,
737 struct anv_bo_cache *cache,
738 uint64_t size, struct anv_bo **bo);
739 VkResult anv_bo_cache_import(struct anv_device *device,
740 struct anv_bo_cache *cache,
741 int fd, struct anv_bo **bo);
742 VkResult anv_bo_cache_export(struct anv_device *device,
743 struct anv_bo_cache *cache,
744 struct anv_bo *bo_in, int *fd_out);
745 void anv_bo_cache_release(struct anv_device *device,
746 struct anv_bo_cache *cache,
747 struct anv_bo *bo);
748
749 struct anv_memory_type {
750 /* Standard bits passed on to the client */
751 VkMemoryPropertyFlags propertyFlags;
752 uint32_t heapIndex;
753
754 /* Driver-internal book-keeping */
755 VkBufferUsageFlags valid_buffer_usage;
756 };
757
758 struct anv_memory_heap {
759 /* Standard bits passed on to the client */
760 VkDeviceSize size;
761 VkMemoryHeapFlags flags;
762
763 /* Driver-internal book-keeping */
764 bool supports_48bit_addresses;
765 };
766
767 struct anv_physical_device {
768 VK_LOADER_DATA _loader_data;
769
770 struct anv_instance * instance;
771 uint32_t chipset_id;
772 bool no_hw;
773 char path[20];
774 const char * name;
775 struct gen_device_info info;
776 /** Amount of "GPU memory" we want to advertise
777 *
778 * Clearly, this value is bogus since Intel is a UMA architecture. On
779 * gen7 platforms, we are limited by GTT size unless we want to implement
780 * fine-grained tracking and GTT splitting. On Broadwell and above we are
781 * practically unlimited. However, we will never report more than 3/4 of
782 * the total system ram to try and avoid running out of RAM.
783 */
784 bool supports_48bit_addresses;
785 struct brw_compiler * compiler;
786 struct isl_device isl_dev;
787 int cmd_parser_version;
788 bool has_exec_async;
789 bool has_exec_capture;
790 bool has_exec_fence;
791 bool has_syncobj;
792 bool has_syncobj_wait;
793 bool has_context_priority;
794
795 struct anv_device_extension_table supported_extensions;
796
797 uint32_t eu_total;
798 uint32_t subslice_total;
799
800 struct {
801 uint32_t type_count;
802 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
803 uint32_t heap_count;
804 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
805 } memory;
806
807 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
808 uint8_t driver_uuid[VK_UUID_SIZE];
809 uint8_t device_uuid[VK_UUID_SIZE];
810
811 struct wsi_device wsi_device;
812 int local_fd;
813 };
814
815 struct anv_instance {
816 VK_LOADER_DATA _loader_data;
817
818 VkAllocationCallbacks alloc;
819
820 uint32_t apiVersion;
821 struct anv_instance_extension_table enabled_extensions;
822 struct anv_dispatch_table dispatch;
823
824 int physicalDeviceCount;
825 struct anv_physical_device physicalDevice;
826
827 struct vk_debug_report_instance debug_report_callbacks;
828 };
829
830 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
831 void anv_finish_wsi(struct anv_physical_device *physical_device);
832
833 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
834 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
835 const char *name);
836
837 struct anv_queue {
838 VK_LOADER_DATA _loader_data;
839
840 struct anv_device * device;
841
842 VkDeviceQueueCreateFlags flags;
843 };
844
845 struct anv_pipeline_cache {
846 struct anv_device * device;
847 pthread_mutex_t mutex;
848
849 struct hash_table * cache;
850 };
851
852 struct anv_pipeline_bind_map;
853
854 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
855 struct anv_device *device,
856 bool cache_enabled);
857 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
858
859 struct anv_shader_bin *
860 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
861 const void *key, uint32_t key_size);
862 struct anv_shader_bin *
863 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
864 const void *key_data, uint32_t key_size,
865 const void *kernel_data, uint32_t kernel_size,
866 const struct brw_stage_prog_data *prog_data,
867 uint32_t prog_data_size,
868 const struct anv_pipeline_bind_map *bind_map);
869
870 struct anv_device {
871 VK_LOADER_DATA _loader_data;
872
873 VkAllocationCallbacks alloc;
874
875 struct anv_instance * instance;
876 uint32_t chipset_id;
877 bool no_hw;
878 struct gen_device_info info;
879 struct isl_device isl_dev;
880 int context_id;
881 int fd;
882 bool can_chain_batches;
883 bool robust_buffer_access;
884 struct anv_device_extension_table enabled_extensions;
885 struct anv_dispatch_table dispatch;
886
887 struct anv_bo_pool batch_bo_pool;
888
889 struct anv_bo_cache bo_cache;
890
891 struct anv_state_pool dynamic_state_pool;
892 struct anv_state_pool instruction_state_pool;
893 struct anv_state_pool surface_state_pool;
894
895 struct anv_bo workaround_bo;
896 struct anv_bo trivial_batch_bo;
897 struct anv_bo hiz_clear_bo;
898
899 struct anv_pipeline_cache blorp_shader_cache;
900 struct blorp_context blorp;
901
902 struct anv_state border_colors;
903
904 struct anv_queue queue;
905
906 struct anv_scratch_pool scratch_pool;
907
908 uint32_t default_mocs;
909
910 pthread_mutex_t mutex;
911 pthread_cond_t queue_submit;
912 bool lost;
913 };
914
915 static void inline
916 anv_state_flush(struct anv_device *device, struct anv_state state)
917 {
918 if (device->info.has_llc)
919 return;
920
921 gen_flush_range(state.map, state.alloc_size);
922 }
923
924 void anv_device_init_blorp(struct anv_device *device);
925 void anv_device_finish_blorp(struct anv_device *device);
926
927 VkResult anv_device_execbuf(struct anv_device *device,
928 struct drm_i915_gem_execbuffer2 *execbuf,
929 struct anv_bo **execbuf_bos);
930 VkResult anv_device_query_status(struct anv_device *device);
931 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
932 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
933 int64_t timeout);
934
935 void* anv_gem_mmap(struct anv_device *device,
936 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
937 void anv_gem_munmap(void *p, uint64_t size);
938 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
939 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
940 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
941 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
942 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
943 int anv_gem_execbuffer(struct anv_device *device,
944 struct drm_i915_gem_execbuffer2 *execbuf);
945 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
946 uint32_t stride, uint32_t tiling);
947 int anv_gem_create_context(struct anv_device *device);
948 bool anv_gem_has_context_priority(int fd);
949 int anv_gem_destroy_context(struct anv_device *device, int context);
950 int anv_gem_set_context_param(int fd, int context, uint32_t param,
951 uint64_t value);
952 int anv_gem_get_context_param(int fd, int context, uint32_t param,
953 uint64_t *value);
954 int anv_gem_get_param(int fd, uint32_t param);
955 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
956 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
957 int anv_gem_get_aperture(int fd, uint64_t *size);
958 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
959 uint32_t *active, uint32_t *pending);
960 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
961 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
962 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
963 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
964 uint32_t read_domains, uint32_t write_domain);
965 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
966 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
967 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
968 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
969 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
970 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
971 uint32_t handle);
972 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
973 uint32_t handle, int fd);
974 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
975 bool anv_gem_supports_syncobj_wait(int fd);
976 int anv_gem_syncobj_wait(struct anv_device *device,
977 uint32_t *handles, uint32_t num_handles,
978 int64_t abs_timeout_ns, bool wait_all);
979
980 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
981
982 struct anv_reloc_list {
983 uint32_t num_relocs;
984 uint32_t array_length;
985 struct drm_i915_gem_relocation_entry * relocs;
986 struct anv_bo ** reloc_bos;
987 };
988
989 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
990 const VkAllocationCallbacks *alloc);
991 void anv_reloc_list_finish(struct anv_reloc_list *list,
992 const VkAllocationCallbacks *alloc);
993
994 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
995 const VkAllocationCallbacks *alloc,
996 uint32_t offset, struct anv_bo *target_bo,
997 uint32_t delta);
998
999 struct anv_batch_bo {
1000 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1001 struct list_head link;
1002
1003 struct anv_bo bo;
1004
1005 /* Bytes actually consumed in this batch BO */
1006 uint32_t length;
1007
1008 struct anv_reloc_list relocs;
1009 };
1010
1011 struct anv_batch {
1012 const VkAllocationCallbacks * alloc;
1013
1014 void * start;
1015 void * end;
1016 void * next;
1017
1018 struct anv_reloc_list * relocs;
1019
1020 /* This callback is called (with the associated user data) in the event
1021 * that the batch runs out of space.
1022 */
1023 VkResult (*extend_cb)(struct anv_batch *, void *);
1024 void * user_data;
1025
1026 /**
1027 * Current error status of the command buffer. Used to track inconsistent
1028 * or incomplete command buffer states that are the consequence of run-time
1029 * errors such as out of memory scenarios. We want to track this in the
1030 * batch because the command buffer object is not visible to some parts
1031 * of the driver.
1032 */
1033 VkResult status;
1034 };
1035
1036 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1037 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1038 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1039 void *location, struct anv_bo *bo, uint32_t offset);
1040 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1041 struct anv_batch *batch);
1042
1043 static inline VkResult
1044 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1045 {
1046 assert(error != VK_SUCCESS);
1047 if (batch->status == VK_SUCCESS)
1048 batch->status = error;
1049 return batch->status;
1050 }
1051
1052 static inline bool
1053 anv_batch_has_error(struct anv_batch *batch)
1054 {
1055 return batch->status != VK_SUCCESS;
1056 }
1057
1058 struct anv_address {
1059 struct anv_bo *bo;
1060 uint32_t offset;
1061 };
1062
1063 static inline uint64_t
1064 _anv_combine_address(struct anv_batch *batch, void *location,
1065 const struct anv_address address, uint32_t delta)
1066 {
1067 if (address.bo == NULL) {
1068 return address.offset + delta;
1069 } else {
1070 assert(batch->start <= location && location < batch->end);
1071
1072 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1073 }
1074 }
1075
1076 #define __gen_address_type struct anv_address
1077 #define __gen_user_data struct anv_batch
1078 #define __gen_combine_address _anv_combine_address
1079
1080 /* Wrapper macros needed to work around preprocessor argument issues. In
1081 * particular, arguments don't get pre-evaluated if they are concatenated.
1082 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1083 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1084 * We can work around this easily enough with these helpers.
1085 */
1086 #define __anv_cmd_length(cmd) cmd ## _length
1087 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1088 #define __anv_cmd_header(cmd) cmd ## _header
1089 #define __anv_cmd_pack(cmd) cmd ## _pack
1090 #define __anv_reg_num(reg) reg ## _num
1091
1092 #define anv_pack_struct(dst, struc, ...) do { \
1093 struct struc __template = { \
1094 __VA_ARGS__ \
1095 }; \
1096 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1097 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1098 } while (0)
1099
1100 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1101 void *__dst = anv_batch_emit_dwords(batch, n); \
1102 if (__dst) { \
1103 struct cmd __template = { \
1104 __anv_cmd_header(cmd), \
1105 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1106 __VA_ARGS__ \
1107 }; \
1108 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1109 } \
1110 __dst; \
1111 })
1112
1113 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1114 do { \
1115 uint32_t *dw; \
1116 \
1117 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1118 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1119 if (!dw) \
1120 break; \
1121 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1122 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1123 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1124 } while (0)
1125
1126 #define anv_batch_emit(batch, cmd, name) \
1127 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1128 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1129 __builtin_expect(_dst != NULL, 1); \
1130 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1131 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1132 _dst = NULL; \
1133 }))
1134
1135 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1136 .GraphicsDataTypeGFDT = 0, \
1137 .LLCCacheabilityControlLLCCC = 0, \
1138 .L3CacheabilityControlL3CC = 1, \
1139 }
1140
1141 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1142 .LLCeLLCCacheabilityControlLLCCC = 0, \
1143 .L3CacheabilityControlL3CC = 1, \
1144 }
1145
1146 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1147 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1148 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1149 .AgeforQUADLRU = 0 \
1150 }
1151
1152 /* Skylake: MOCS is now an index into an array of 62 different caching
1153 * configurations programmed by the kernel.
1154 */
1155
1156 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1157 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1158 .IndextoMOCSTables = 2 \
1159 }
1160
1161 #define GEN9_MOCS_PTE { \
1162 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1163 .IndextoMOCSTables = 1 \
1164 }
1165
1166 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1167 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1168 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1169 .IndextoMOCSTables = 2 \
1170 }
1171
1172 #define GEN10_MOCS_PTE { \
1173 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1174 .IndextoMOCSTables = 1 \
1175 }
1176
1177 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1178 #define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1179 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1180 .IndextoMOCSTables = 2 \
1181 }
1182
1183 #define GEN11_MOCS_PTE { \
1184 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1185 .IndextoMOCSTables = 1 \
1186 }
1187
1188 struct anv_device_memory {
1189 struct anv_bo * bo;
1190 struct anv_memory_type * type;
1191 VkDeviceSize map_size;
1192 void * map;
1193 };
1194
1195 /**
1196 * Header for Vertex URB Entry (VUE)
1197 */
1198 struct anv_vue_header {
1199 uint32_t Reserved;
1200 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1201 uint32_t ViewportIndex;
1202 float PointWidth;
1203 };
1204
1205 struct anv_descriptor_set_binding_layout {
1206 #ifndef NDEBUG
1207 /* The type of the descriptors in this binding */
1208 VkDescriptorType type;
1209 #endif
1210
1211 /* Number of array elements in this binding */
1212 uint16_t array_size;
1213
1214 /* Index into the flattend descriptor set */
1215 uint16_t descriptor_index;
1216
1217 /* Index into the dynamic state array for a dynamic buffer */
1218 int16_t dynamic_offset_index;
1219
1220 /* Index into the descriptor set buffer views */
1221 int16_t buffer_index;
1222
1223 struct {
1224 /* Index into the binding table for the associated surface */
1225 int16_t surface_index;
1226
1227 /* Index into the sampler table for the associated sampler */
1228 int16_t sampler_index;
1229
1230 /* Index into the image table for the associated image */
1231 int16_t image_index;
1232 } stage[MESA_SHADER_STAGES];
1233
1234 /* Immutable samplers (or NULL if no immutable samplers) */
1235 struct anv_sampler **immutable_samplers;
1236 };
1237
1238 struct anv_descriptor_set_layout {
1239 /* Descriptor set layouts can be destroyed at almost any time */
1240 uint32_t ref_cnt;
1241
1242 /* Number of bindings in this descriptor set */
1243 uint16_t binding_count;
1244
1245 /* Total size of the descriptor set with room for all array entries */
1246 uint16_t size;
1247
1248 /* Shader stages affected by this descriptor set */
1249 uint16_t shader_stages;
1250
1251 /* Number of buffers in this descriptor set */
1252 uint16_t buffer_count;
1253
1254 /* Number of dynamic offsets used by this descriptor set */
1255 uint16_t dynamic_offset_count;
1256
1257 /* Bindings in this descriptor set */
1258 struct anv_descriptor_set_binding_layout binding[0];
1259 };
1260
1261 static inline void
1262 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
1263 {
1264 assert(layout && layout->ref_cnt >= 1);
1265 p_atomic_inc(&layout->ref_cnt);
1266 }
1267
1268 static inline void
1269 anv_descriptor_set_layout_unref(struct anv_device *device,
1270 struct anv_descriptor_set_layout *layout)
1271 {
1272 assert(layout && layout->ref_cnt >= 1);
1273 if (p_atomic_dec_zero(&layout->ref_cnt))
1274 vk_free(&device->alloc, layout);
1275 }
1276
1277 struct anv_descriptor {
1278 VkDescriptorType type;
1279
1280 union {
1281 struct {
1282 VkImageLayout layout;
1283 struct anv_image_view *image_view;
1284 struct anv_sampler *sampler;
1285 };
1286
1287 struct {
1288 struct anv_buffer *buffer;
1289 uint64_t offset;
1290 uint64_t range;
1291 };
1292
1293 struct anv_buffer_view *buffer_view;
1294 };
1295 };
1296
1297 struct anv_descriptor_set {
1298 struct anv_descriptor_set_layout *layout;
1299 uint32_t size;
1300 uint32_t buffer_count;
1301 struct anv_buffer_view *buffer_views;
1302 struct anv_descriptor descriptors[0];
1303 };
1304
1305 struct anv_buffer_view {
1306 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1307 struct anv_bo *bo;
1308 uint32_t offset; /**< Offset into bo. */
1309 uint64_t range; /**< VkBufferViewCreateInfo::range */
1310
1311 struct anv_state surface_state;
1312 struct anv_state storage_surface_state;
1313 struct anv_state writeonly_storage_surface_state;
1314
1315 struct brw_image_param storage_image_param;
1316 };
1317
1318 struct anv_push_descriptor_set {
1319 struct anv_descriptor_set set;
1320
1321 /* Put this field right behind anv_descriptor_set so it fills up the
1322 * descriptors[0] field. */
1323 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1324 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1325 };
1326
1327 struct anv_descriptor_pool {
1328 uint32_t size;
1329 uint32_t next;
1330 uint32_t free_list;
1331
1332 struct anv_state_stream surface_state_stream;
1333 void *surface_state_free_list;
1334
1335 char data[0];
1336 };
1337
1338 enum anv_descriptor_template_entry_type {
1339 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1340 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1341 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1342 };
1343
1344 struct anv_descriptor_template_entry {
1345 /* The type of descriptor in this entry */
1346 VkDescriptorType type;
1347
1348 /* Binding in the descriptor set */
1349 uint32_t binding;
1350
1351 /* Offset at which to write into the descriptor set binding */
1352 uint32_t array_element;
1353
1354 /* Number of elements to write into the descriptor set binding */
1355 uint32_t array_count;
1356
1357 /* Offset into the user provided data */
1358 size_t offset;
1359
1360 /* Stride between elements into the user provided data */
1361 size_t stride;
1362 };
1363
1364 struct anv_descriptor_update_template {
1365 VkPipelineBindPoint bind_point;
1366
1367 /* The descriptor set this template corresponds to. This value is only
1368 * valid if the template was created with the templateType
1369 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1370 */
1371 uint8_t set;
1372
1373 /* Number of entries in this template */
1374 uint32_t entry_count;
1375
1376 /* Entries of the template */
1377 struct anv_descriptor_template_entry entries[0];
1378 };
1379
1380 size_t
1381 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1382
1383 size_t
1384 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1385
1386 void
1387 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1388 const struct gen_device_info * const devinfo,
1389 const VkDescriptorImageInfo * const info,
1390 VkDescriptorType type,
1391 uint32_t binding,
1392 uint32_t element);
1393
1394 void
1395 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1396 VkDescriptorType type,
1397 struct anv_buffer_view *buffer_view,
1398 uint32_t binding,
1399 uint32_t element);
1400
1401 void
1402 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1403 struct anv_device *device,
1404 struct anv_state_stream *alloc_stream,
1405 VkDescriptorType type,
1406 struct anv_buffer *buffer,
1407 uint32_t binding,
1408 uint32_t element,
1409 VkDeviceSize offset,
1410 VkDeviceSize range);
1411
1412 void
1413 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1414 struct anv_device *device,
1415 struct anv_state_stream *alloc_stream,
1416 const struct anv_descriptor_update_template *template,
1417 const void *data);
1418
1419 VkResult
1420 anv_descriptor_set_create(struct anv_device *device,
1421 struct anv_descriptor_pool *pool,
1422 struct anv_descriptor_set_layout *layout,
1423 struct anv_descriptor_set **out_set);
1424
1425 void
1426 anv_descriptor_set_destroy(struct anv_device *device,
1427 struct anv_descriptor_pool *pool,
1428 struct anv_descriptor_set *set);
1429
1430 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1431
1432 struct anv_pipeline_binding {
1433 /* The descriptor set this surface corresponds to. The special value of
1434 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1435 * to a color attachment and not a regular descriptor.
1436 */
1437 uint8_t set;
1438
1439 /* Binding in the descriptor set */
1440 uint32_t binding;
1441
1442 /* Index in the binding */
1443 uint32_t index;
1444
1445 /* Plane in the binding index */
1446 uint8_t plane;
1447
1448 /* Input attachment index (relative to the subpass) */
1449 uint8_t input_attachment_index;
1450
1451 /* For a storage image, whether it is write-only */
1452 bool write_only;
1453 };
1454
1455 struct anv_pipeline_layout {
1456 struct {
1457 struct anv_descriptor_set_layout *layout;
1458 uint32_t dynamic_offset_start;
1459 } set[MAX_SETS];
1460
1461 uint32_t num_sets;
1462
1463 struct {
1464 bool has_dynamic_offsets;
1465 } stage[MESA_SHADER_STAGES];
1466
1467 unsigned char sha1[20];
1468 };
1469
1470 struct anv_buffer {
1471 struct anv_device * device;
1472 VkDeviceSize size;
1473
1474 VkBufferUsageFlags usage;
1475
1476 /* Set when bound */
1477 struct anv_bo * bo;
1478 VkDeviceSize offset;
1479 };
1480
1481 static inline uint64_t
1482 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1483 {
1484 assert(offset <= buffer->size);
1485 if (range == VK_WHOLE_SIZE) {
1486 return buffer->size - offset;
1487 } else {
1488 assert(range <= buffer->size);
1489 return range;
1490 }
1491 }
1492
1493 enum anv_cmd_dirty_bits {
1494 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1495 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1496 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1497 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1498 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1499 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1500 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1501 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1502 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1503 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1504 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1505 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1506 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1507 };
1508 typedef uint32_t anv_cmd_dirty_mask_t;
1509
1510 enum anv_pipe_bits {
1511 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1512 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1513 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1514 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1515 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1516 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1517 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1518 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1519 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1520 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1521 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1522
1523 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1524 * a flush has happened but not a CS stall. The next time we do any sort
1525 * of invalidation we need to insert a CS stall at that time. Otherwise,
1526 * we would have to CS stall on every flush which could be bad.
1527 */
1528 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1529 };
1530
1531 #define ANV_PIPE_FLUSH_BITS ( \
1532 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1533 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1534 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1535
1536 #define ANV_PIPE_STALL_BITS ( \
1537 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1538 ANV_PIPE_DEPTH_STALL_BIT | \
1539 ANV_PIPE_CS_STALL_BIT)
1540
1541 #define ANV_PIPE_INVALIDATE_BITS ( \
1542 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1543 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1544 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1545 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1546 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1547 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1548
1549 static inline enum anv_pipe_bits
1550 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1551 {
1552 enum anv_pipe_bits pipe_bits = 0;
1553
1554 unsigned b;
1555 for_each_bit(b, flags) {
1556 switch ((VkAccessFlagBits)(1 << b)) {
1557 case VK_ACCESS_SHADER_WRITE_BIT:
1558 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1559 break;
1560 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1561 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1562 break;
1563 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1564 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1565 break;
1566 case VK_ACCESS_TRANSFER_WRITE_BIT:
1567 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1568 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1569 break;
1570 default:
1571 break; /* Nothing to do */
1572 }
1573 }
1574
1575 return pipe_bits;
1576 }
1577
1578 static inline enum anv_pipe_bits
1579 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1580 {
1581 enum anv_pipe_bits pipe_bits = 0;
1582
1583 unsigned b;
1584 for_each_bit(b, flags) {
1585 switch ((VkAccessFlagBits)(1 << b)) {
1586 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1587 case VK_ACCESS_INDEX_READ_BIT:
1588 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1589 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1590 break;
1591 case VK_ACCESS_UNIFORM_READ_BIT:
1592 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1593 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1594 break;
1595 case VK_ACCESS_SHADER_READ_BIT:
1596 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1597 case VK_ACCESS_TRANSFER_READ_BIT:
1598 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1599 break;
1600 default:
1601 break; /* Nothing to do */
1602 }
1603 }
1604
1605 return pipe_bits;
1606 }
1607
1608 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1609 VK_IMAGE_ASPECT_COLOR_BIT | \
1610 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1611 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1612 VK_IMAGE_ASPECT_PLANE_2_BIT)
1613 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1614 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1615 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1616 VK_IMAGE_ASPECT_PLANE_2_BIT)
1617
1618 struct anv_vertex_binding {
1619 struct anv_buffer * buffer;
1620 VkDeviceSize offset;
1621 };
1622
1623 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1624 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1625
1626 struct anv_push_constants {
1627 /* Current allocated size of this push constants data structure.
1628 * Because a decent chunk of it may not be used (images on SKL, for
1629 * instance), we won't actually allocate the entire structure up-front.
1630 */
1631 uint32_t size;
1632
1633 /* Push constant data provided by the client through vkPushConstants */
1634 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1635
1636 /* Used for vkCmdDispatchBase */
1637 uint32_t base_work_group_id[3];
1638
1639 /* Image data for image_load_store on pre-SKL */
1640 struct brw_image_param images[MAX_IMAGES];
1641 };
1642
1643 struct anv_dynamic_state {
1644 struct {
1645 uint32_t count;
1646 VkViewport viewports[MAX_VIEWPORTS];
1647 } viewport;
1648
1649 struct {
1650 uint32_t count;
1651 VkRect2D scissors[MAX_SCISSORS];
1652 } scissor;
1653
1654 float line_width;
1655
1656 struct {
1657 float bias;
1658 float clamp;
1659 float slope;
1660 } depth_bias;
1661
1662 float blend_constants[4];
1663
1664 struct {
1665 float min;
1666 float max;
1667 } depth_bounds;
1668
1669 struct {
1670 uint32_t front;
1671 uint32_t back;
1672 } stencil_compare_mask;
1673
1674 struct {
1675 uint32_t front;
1676 uint32_t back;
1677 } stencil_write_mask;
1678
1679 struct {
1680 uint32_t front;
1681 uint32_t back;
1682 } stencil_reference;
1683 };
1684
1685 extern const struct anv_dynamic_state default_dynamic_state;
1686
1687 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1688 const struct anv_dynamic_state *src,
1689 uint32_t copy_mask);
1690
1691 struct anv_surface_state {
1692 struct anv_state state;
1693 /** Address of the surface referred to by this state
1694 *
1695 * This address is relative to the start of the BO.
1696 */
1697 uint64_t address;
1698 /* Address of the aux surface, if any
1699 *
1700 * This field is 0 if and only if no aux surface exists.
1701 *
1702 * This address is relative to the start of the BO. With the exception of
1703 * gen8, the bottom 12 bits of this address include extra aux information.
1704 */
1705 uint64_t aux_address;
1706 /* Address of the clear color, if any
1707 *
1708 * This address is relative to the start of the BO.
1709 */
1710 uint64_t clear_address;
1711 };
1712
1713 /**
1714 * Attachment state when recording a renderpass instance.
1715 *
1716 * The clear value is valid only if there exists a pending clear.
1717 */
1718 struct anv_attachment_state {
1719 enum isl_aux_usage aux_usage;
1720 enum isl_aux_usage input_aux_usage;
1721 struct anv_surface_state color;
1722 struct anv_surface_state input;
1723
1724 VkImageLayout current_layout;
1725 VkImageAspectFlags pending_clear_aspects;
1726 VkImageAspectFlags pending_load_aspects;
1727 bool fast_clear;
1728 VkClearValue clear_value;
1729 bool clear_color_is_zero_one;
1730 bool clear_color_is_zero;
1731
1732 /* When multiview is active, attachments with a renderpass clear
1733 * operation have their respective layers cleared on the first
1734 * subpass that uses them, and only in that subpass. We keep track
1735 * of this using a bitfield to indicate which layers of an attachment
1736 * have not been cleared yet when multiview is active.
1737 */
1738 uint32_t pending_clear_views;
1739 };
1740
1741 /** State tracking for particular pipeline bind point
1742 *
1743 * This struct is the base struct for anv_cmd_graphics_state and
1744 * anv_cmd_compute_state. These are used to track state which is bound to a
1745 * particular type of pipeline. Generic state that applies per-stage such as
1746 * binding table offsets and push constants is tracked generically with a
1747 * per-stage array in anv_cmd_state.
1748 */
1749 struct anv_cmd_pipeline_state {
1750 struct anv_pipeline *pipeline;
1751 struct anv_pipeline_layout *layout;
1752
1753 struct anv_descriptor_set *descriptors[MAX_SETS];
1754 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1755
1756 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
1757 };
1758
1759 /** State tracking for graphics pipeline
1760 *
1761 * This has anv_cmd_pipeline_state as a base struct to track things which get
1762 * bound to a graphics pipeline. Along with general pipeline bind point state
1763 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1764 * state which is graphics-specific.
1765 */
1766 struct anv_cmd_graphics_state {
1767 struct anv_cmd_pipeline_state base;
1768
1769 anv_cmd_dirty_mask_t dirty;
1770 uint32_t vb_dirty;
1771
1772 struct anv_dynamic_state dynamic;
1773
1774 struct {
1775 struct anv_buffer *index_buffer;
1776 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1777 uint32_t index_offset;
1778 } gen7;
1779 };
1780
1781 /** State tracking for compute pipeline
1782 *
1783 * This has anv_cmd_pipeline_state as a base struct to track things which get
1784 * bound to a compute pipeline. Along with general pipeline bind point state
1785 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1786 * state which is compute-specific.
1787 */
1788 struct anv_cmd_compute_state {
1789 struct anv_cmd_pipeline_state base;
1790
1791 bool pipeline_dirty;
1792
1793 struct anv_address num_workgroups;
1794 };
1795
1796 /** State required while building cmd buffer */
1797 struct anv_cmd_state {
1798 /* PIPELINE_SELECT.PipelineSelection */
1799 uint32_t current_pipeline;
1800 const struct gen_l3_config * current_l3_config;
1801
1802 struct anv_cmd_graphics_state gfx;
1803 struct anv_cmd_compute_state compute;
1804
1805 enum anv_pipe_bits pending_pipe_bits;
1806 VkShaderStageFlags descriptors_dirty;
1807 VkShaderStageFlags push_constants_dirty;
1808
1809 struct anv_framebuffer * framebuffer;
1810 struct anv_render_pass * pass;
1811 struct anv_subpass * subpass;
1812 VkRect2D render_area;
1813 uint32_t restart_index;
1814 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1815 VkShaderStageFlags push_constant_stages;
1816 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1817 struct anv_state binding_tables[MESA_SHADER_STAGES];
1818 struct anv_state samplers[MESA_SHADER_STAGES];
1819
1820 /**
1821 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1822 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1823 * and before invoking the secondary in ExecuteCommands.
1824 */
1825 bool pma_fix_enabled;
1826
1827 /**
1828 * Whether or not we know for certain that HiZ is enabled for the current
1829 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1830 * enabled or not, this will be false.
1831 */
1832 bool hiz_enabled;
1833
1834 /**
1835 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1836 * valid only when recording a render pass instance.
1837 */
1838 struct anv_attachment_state * attachments;
1839
1840 /**
1841 * Surface states for color render targets. These are stored in a single
1842 * flat array. For depth-stencil attachments, the surface state is simply
1843 * left blank.
1844 */
1845 struct anv_state render_pass_states;
1846
1847 /**
1848 * A null surface state of the right size to match the framebuffer. This
1849 * is one of the states in render_pass_states.
1850 */
1851 struct anv_state null_surface_state;
1852 };
1853
1854 struct anv_cmd_pool {
1855 VkAllocationCallbacks alloc;
1856 struct list_head cmd_buffers;
1857 };
1858
1859 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1860
1861 enum anv_cmd_buffer_exec_mode {
1862 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1863 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1864 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1865 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1866 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1867 };
1868
1869 struct anv_cmd_buffer {
1870 VK_LOADER_DATA _loader_data;
1871
1872 struct anv_device * device;
1873
1874 struct anv_cmd_pool * pool;
1875 struct list_head pool_link;
1876
1877 struct anv_batch batch;
1878
1879 /* Fields required for the actual chain of anv_batch_bo's.
1880 *
1881 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1882 */
1883 struct list_head batch_bos;
1884 enum anv_cmd_buffer_exec_mode exec_mode;
1885
1886 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1887 * referenced by this command buffer
1888 *
1889 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1890 */
1891 struct u_vector seen_bbos;
1892
1893 /* A vector of int32_t's for every block of binding tables.
1894 *
1895 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1896 */
1897 struct u_vector bt_block_states;
1898 uint32_t bt_next;
1899
1900 struct anv_reloc_list surface_relocs;
1901 /** Last seen surface state block pool center bo offset */
1902 uint32_t last_ss_pool_center;
1903
1904 /* Serial for tracking buffer completion */
1905 uint32_t serial;
1906
1907 /* Stream objects for storing temporary data */
1908 struct anv_state_stream surface_state_stream;
1909 struct anv_state_stream dynamic_state_stream;
1910
1911 VkCommandBufferUsageFlags usage_flags;
1912 VkCommandBufferLevel level;
1913
1914 struct anv_cmd_state state;
1915 };
1916
1917 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1918 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1919 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1920 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1921 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1922 struct anv_cmd_buffer *secondary);
1923 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1924 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1925 struct anv_cmd_buffer *cmd_buffer,
1926 const VkSemaphore *in_semaphores,
1927 uint32_t num_in_semaphores,
1928 const VkSemaphore *out_semaphores,
1929 uint32_t num_out_semaphores,
1930 VkFence fence);
1931
1932 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1933
1934 VkResult
1935 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1936 gl_shader_stage stage, uint32_t size);
1937 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1938 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1939 (offsetof(struct anv_push_constants, field) + \
1940 sizeof(cmd_buffer->state.push_constants[0]->field)))
1941
1942 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1943 const void *data, uint32_t size, uint32_t alignment);
1944 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1945 uint32_t *a, uint32_t *b,
1946 uint32_t dwords, uint32_t alignment);
1947
1948 struct anv_address
1949 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1950 struct anv_state
1951 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1952 uint32_t entries, uint32_t *state_offset);
1953 struct anv_state
1954 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1955 struct anv_state
1956 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1957 uint32_t size, uint32_t alignment);
1958
1959 VkResult
1960 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1961
1962 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1963 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1964 bool depth_clamp_enable);
1965 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1966
1967 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1968 struct anv_render_pass *pass,
1969 struct anv_framebuffer *framebuffer,
1970 const VkClearValue *clear_values);
1971
1972 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1973
1974 struct anv_state
1975 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1976 gl_shader_stage stage);
1977 struct anv_state
1978 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1979
1980 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1981
1982 const struct anv_image_view *
1983 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1984
1985 VkResult
1986 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1987 uint32_t num_entries,
1988 uint32_t *state_offset,
1989 struct anv_state *bt_state);
1990
1991 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1992
1993 enum anv_fence_type {
1994 ANV_FENCE_TYPE_NONE = 0,
1995 ANV_FENCE_TYPE_BO,
1996 ANV_FENCE_TYPE_SYNCOBJ,
1997 };
1998
1999 enum anv_bo_fence_state {
2000 /** Indicates that this is a new (or newly reset fence) */
2001 ANV_BO_FENCE_STATE_RESET,
2002
2003 /** Indicates that this fence has been submitted to the GPU but is still
2004 * (as far as we know) in use by the GPU.
2005 */
2006 ANV_BO_FENCE_STATE_SUBMITTED,
2007
2008 ANV_BO_FENCE_STATE_SIGNALED,
2009 };
2010
2011 struct anv_fence_impl {
2012 enum anv_fence_type type;
2013
2014 union {
2015 /** Fence implementation for BO fences
2016 *
2017 * These fences use a BO and a set of CPU-tracked state flags. The BO
2018 * is added to the object list of the last execbuf call in a QueueSubmit
2019 * and is marked EXEC_WRITE. The state flags track when the BO has been
2020 * submitted to the kernel. We need to do this because Vulkan lets you
2021 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2022 * will say it's idle in this case.
2023 */
2024 struct {
2025 struct anv_bo bo;
2026 enum anv_bo_fence_state state;
2027 } bo;
2028
2029 /** DRM syncobj handle for syncobj-based fences */
2030 uint32_t syncobj;
2031 };
2032 };
2033
2034 struct anv_fence {
2035 /* Permanent fence state. Every fence has some form of permanent state
2036 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2037 * cross-process fences) or it could just be a dummy for use internally.
2038 */
2039 struct anv_fence_impl permanent;
2040
2041 /* Temporary fence state. A fence *may* have temporary state. That state
2042 * is added to the fence by an import operation and is reset back to
2043 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2044 * state cannot be signaled because the fence must already be signaled
2045 * before the temporary state can be exported from the fence in the other
2046 * process and imported here.
2047 */
2048 struct anv_fence_impl temporary;
2049 };
2050
2051 struct anv_event {
2052 uint64_t semaphore;
2053 struct anv_state state;
2054 };
2055
2056 enum anv_semaphore_type {
2057 ANV_SEMAPHORE_TYPE_NONE = 0,
2058 ANV_SEMAPHORE_TYPE_DUMMY,
2059 ANV_SEMAPHORE_TYPE_BO,
2060 ANV_SEMAPHORE_TYPE_SYNC_FILE,
2061 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
2062 };
2063
2064 struct anv_semaphore_impl {
2065 enum anv_semaphore_type type;
2066
2067 union {
2068 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2069 * This BO will be added to the object list on any execbuf2 calls for
2070 * which this semaphore is used as a wait or signal fence. When used as
2071 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2072 */
2073 struct anv_bo *bo;
2074
2075 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2076 * If the semaphore is in the unsignaled state due to either just being
2077 * created or because it has been used for a wait, fd will be -1.
2078 */
2079 int fd;
2080
2081 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2082 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2083 * import so we don't need to bother with a userspace cache.
2084 */
2085 uint32_t syncobj;
2086 };
2087 };
2088
2089 struct anv_semaphore {
2090 /* Permanent semaphore state. Every semaphore has some form of permanent
2091 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2092 * (for cross-process semaphores0 or it could just be a dummy for use
2093 * internally.
2094 */
2095 struct anv_semaphore_impl permanent;
2096
2097 /* Temporary semaphore state. A semaphore *may* have temporary state.
2098 * That state is added to the semaphore by an import operation and is reset
2099 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2100 * semaphore with temporary state cannot be signaled because the semaphore
2101 * must already be signaled before the temporary state can be exported from
2102 * the semaphore in the other process and imported here.
2103 */
2104 struct anv_semaphore_impl temporary;
2105 };
2106
2107 void anv_semaphore_reset_temporary(struct anv_device *device,
2108 struct anv_semaphore *semaphore);
2109
2110 struct anv_shader_module {
2111 unsigned char sha1[20];
2112 uint32_t size;
2113 char data[0];
2114 };
2115
2116 static inline gl_shader_stage
2117 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2118 {
2119 assert(__builtin_popcount(vk_stage) == 1);
2120 return ffs(vk_stage) - 1;
2121 }
2122
2123 static inline VkShaderStageFlagBits
2124 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2125 {
2126 return (1 << mesa_stage);
2127 }
2128
2129 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2130
2131 #define anv_foreach_stage(stage, stage_bits) \
2132 for (gl_shader_stage stage, \
2133 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2134 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2135 __tmp &= ~(1 << (stage)))
2136
2137 struct anv_pipeline_bind_map {
2138 uint32_t surface_count;
2139 uint32_t sampler_count;
2140 uint32_t image_count;
2141
2142 struct anv_pipeline_binding * surface_to_descriptor;
2143 struct anv_pipeline_binding * sampler_to_descriptor;
2144 };
2145
2146 struct anv_shader_bin_key {
2147 uint32_t size;
2148 uint8_t data[0];
2149 };
2150
2151 struct anv_shader_bin {
2152 uint32_t ref_cnt;
2153
2154 const struct anv_shader_bin_key *key;
2155
2156 struct anv_state kernel;
2157 uint32_t kernel_size;
2158
2159 const struct brw_stage_prog_data *prog_data;
2160 uint32_t prog_data_size;
2161
2162 struct anv_pipeline_bind_map bind_map;
2163 };
2164
2165 struct anv_shader_bin *
2166 anv_shader_bin_create(struct anv_device *device,
2167 const void *key, uint32_t key_size,
2168 const void *kernel, uint32_t kernel_size,
2169 const struct brw_stage_prog_data *prog_data,
2170 uint32_t prog_data_size, const void *prog_data_param,
2171 const struct anv_pipeline_bind_map *bind_map);
2172
2173 void
2174 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2175
2176 static inline void
2177 anv_shader_bin_ref(struct anv_shader_bin *shader)
2178 {
2179 assert(shader && shader->ref_cnt >= 1);
2180 p_atomic_inc(&shader->ref_cnt);
2181 }
2182
2183 static inline void
2184 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2185 {
2186 assert(shader && shader->ref_cnt >= 1);
2187 if (p_atomic_dec_zero(&shader->ref_cnt))
2188 anv_shader_bin_destroy(device, shader);
2189 }
2190
2191 struct anv_pipeline {
2192 struct anv_device * device;
2193 struct anv_batch batch;
2194 uint32_t batch_data[512];
2195 struct anv_reloc_list batch_relocs;
2196 uint32_t dynamic_state_mask;
2197 struct anv_dynamic_state dynamic_state;
2198
2199 struct anv_subpass * subpass;
2200
2201 bool needs_data_cache;
2202
2203 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2204
2205 struct {
2206 const struct gen_l3_config * l3_config;
2207 uint32_t total_size;
2208 } urb;
2209
2210 VkShaderStageFlags active_stages;
2211 struct anv_state blend_state;
2212
2213 uint32_t vb_used;
2214 uint32_t binding_stride[MAX_VBS];
2215 bool instancing_enable[MAX_VBS];
2216 bool primitive_restart;
2217 uint32_t topology;
2218
2219 uint32_t cs_right_mask;
2220
2221 bool writes_depth;
2222 bool depth_test_enable;
2223 bool writes_stencil;
2224 bool stencil_test_enable;
2225 bool depth_clamp_enable;
2226 bool sample_shading_enable;
2227 bool kill_pixel;
2228
2229 struct {
2230 uint32_t sf[7];
2231 uint32_t depth_stencil_state[3];
2232 } gen7;
2233
2234 struct {
2235 uint32_t sf[4];
2236 uint32_t raster[5];
2237 uint32_t wm_depth_stencil[3];
2238 } gen8;
2239
2240 struct {
2241 uint32_t wm_depth_stencil[4];
2242 } gen9;
2243
2244 uint32_t interface_descriptor_data[8];
2245 };
2246
2247 static inline bool
2248 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2249 gl_shader_stage stage)
2250 {
2251 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2252 }
2253
2254 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2255 static inline const struct brw_##prefix##_prog_data * \
2256 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2257 { \
2258 if (anv_pipeline_has_stage(pipeline, stage)) { \
2259 return (const struct brw_##prefix##_prog_data *) \
2260 pipeline->shaders[stage]->prog_data; \
2261 } else { \
2262 return NULL; \
2263 } \
2264 }
2265
2266 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2267 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2268 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2269 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2270 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2271 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2272
2273 static inline const struct brw_vue_prog_data *
2274 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2275 {
2276 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2277 return &get_gs_prog_data(pipeline)->base;
2278 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2279 return &get_tes_prog_data(pipeline)->base;
2280 else
2281 return &get_vs_prog_data(pipeline)->base;
2282 }
2283
2284 VkResult
2285 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2286 struct anv_pipeline_cache *cache,
2287 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2288 const VkAllocationCallbacks *alloc);
2289
2290 VkResult
2291 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2292 struct anv_pipeline_cache *cache,
2293 const VkComputePipelineCreateInfo *info,
2294 struct anv_shader_module *module,
2295 const char *entrypoint,
2296 const VkSpecializationInfo *spec_info);
2297
2298 struct anv_format_plane {
2299 enum isl_format isl_format:16;
2300 struct isl_swizzle swizzle;
2301
2302 /* Whether this plane contains chroma channels */
2303 bool has_chroma;
2304
2305 /* For downscaling of YUV planes */
2306 uint8_t denominator_scales[2];
2307
2308 /* How to map sampled ycbcr planes to a single 4 component element. */
2309 struct isl_swizzle ycbcr_swizzle;
2310 };
2311
2312
2313 struct anv_format {
2314 struct anv_format_plane planes[3];
2315 uint8_t n_planes;
2316 bool can_ycbcr;
2317 };
2318
2319 static inline uint32_t
2320 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2321 VkImageAspectFlags aspect_mask)
2322 {
2323 switch (aspect_mask) {
2324 case VK_IMAGE_ASPECT_COLOR_BIT:
2325 case VK_IMAGE_ASPECT_DEPTH_BIT:
2326 case VK_IMAGE_ASPECT_PLANE_0_BIT:
2327 return 0;
2328 case VK_IMAGE_ASPECT_STENCIL_BIT:
2329 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2330 return 0;
2331 /* Fall-through */
2332 case VK_IMAGE_ASPECT_PLANE_1_BIT:
2333 return 1;
2334 case VK_IMAGE_ASPECT_PLANE_2_BIT:
2335 return 2;
2336 default:
2337 /* Purposefully assert with depth/stencil aspects. */
2338 unreachable("invalid image aspect");
2339 }
2340 }
2341
2342 static inline uint32_t
2343 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2344 {
2345 uint32_t planes = 0;
2346
2347 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2348 VK_IMAGE_ASPECT_DEPTH_BIT |
2349 VK_IMAGE_ASPECT_STENCIL_BIT |
2350 VK_IMAGE_ASPECT_PLANE_0_BIT))
2351 planes++;
2352 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT)
2353 planes++;
2354 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT)
2355 planes++;
2356
2357 if ((aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) != 0 &&
2358 (aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) != 0)
2359 planes++;
2360
2361 return planes;
2362 }
2363
2364 static inline VkImageAspectFlags
2365 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2366 uint32_t plane)
2367 {
2368 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2369 if (_mesa_bitcount(image_aspects) > 1)
2370 return VK_IMAGE_ASPECT_PLANE_0_BIT << plane;
2371 return VK_IMAGE_ASPECT_COLOR_BIT;
2372 }
2373 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2374 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2375 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2376 return VK_IMAGE_ASPECT_STENCIL_BIT;
2377 }
2378
2379 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2380 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2381
2382 const struct anv_format *
2383 anv_get_format(VkFormat format);
2384
2385 static inline uint32_t
2386 anv_get_format_planes(VkFormat vk_format)
2387 {
2388 const struct anv_format *format = anv_get_format(vk_format);
2389
2390 return format != NULL ? format->n_planes : 0;
2391 }
2392
2393 struct anv_format_plane
2394 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2395 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2396
2397 static inline enum isl_format
2398 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2399 VkImageAspectFlags aspect, VkImageTiling tiling)
2400 {
2401 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2402 }
2403
2404 static inline struct isl_swizzle
2405 anv_swizzle_for_render(struct isl_swizzle swizzle)
2406 {
2407 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2408 * RGB as RGBA for texturing
2409 */
2410 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2411 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2412
2413 /* But it doesn't matter what we render to that channel */
2414 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2415
2416 return swizzle;
2417 }
2418
2419 void
2420 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2421
2422 /**
2423 * Subsurface of an anv_image.
2424 */
2425 struct anv_surface {
2426 /** Valid only if isl_surf::size > 0. */
2427 struct isl_surf isl;
2428
2429 /**
2430 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2431 */
2432 uint32_t offset;
2433 };
2434
2435 struct anv_image {
2436 VkImageType type;
2437 /* The original VkFormat provided by the client. This may not match any
2438 * of the actual surface formats.
2439 */
2440 VkFormat vk_format;
2441 const struct anv_format *format;
2442
2443 VkImageAspectFlags aspects;
2444 VkExtent3D extent;
2445 uint32_t levels;
2446 uint32_t array_size;
2447 uint32_t samples; /**< VkImageCreateInfo::samples */
2448 uint32_t n_planes;
2449 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2450 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2451
2452 /** True if this is needs to be bound to an appropriately tiled BO.
2453 *
2454 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2455 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2456 * we require a dedicated allocation so that we can know to allocate a
2457 * tiled buffer.
2458 */
2459 bool needs_set_tiling;
2460
2461 /**
2462 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2463 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2464 */
2465 uint64_t drm_format_mod;
2466
2467 VkDeviceSize size;
2468 uint32_t alignment;
2469
2470 /* Whether the image is made of several underlying buffer objects rather a
2471 * single one with different offsets.
2472 */
2473 bool disjoint;
2474
2475 /**
2476 * Image subsurfaces
2477 *
2478 * For each foo, anv_image::planes[x].surface is valid if and only if
2479 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2480 * to figure the number associated with a given aspect.
2481 *
2482 * The hardware requires that the depth buffer and stencil buffer be
2483 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2484 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2485 * allocate the depth and stencil buffers as separate surfaces in the same
2486 * bo.
2487 *
2488 * Memory layout :
2489 *
2490 * -----------------------
2491 * | surface0 | /|\
2492 * ----------------------- |
2493 * | shadow surface0 | |
2494 * ----------------------- | Plane 0
2495 * | aux surface0 | |
2496 * ----------------------- |
2497 * | fast clear colors0 | \|/
2498 * -----------------------
2499 * | surface1 | /|\
2500 * ----------------------- |
2501 * | shadow surface1 | |
2502 * ----------------------- | Plane 1
2503 * | aux surface1 | |
2504 * ----------------------- |
2505 * | fast clear colors1 | \|/
2506 * -----------------------
2507 * | ... |
2508 * | |
2509 * -----------------------
2510 */
2511 struct {
2512 /**
2513 * Offset of the entire plane (whenever the image is disjoint this is
2514 * set to 0).
2515 */
2516 uint32_t offset;
2517
2518 VkDeviceSize size;
2519 uint32_t alignment;
2520
2521 struct anv_surface surface;
2522
2523 /**
2524 * A surface which shadows the main surface and may have different
2525 * tiling. This is used for sampling using a tiling that isn't supported
2526 * for other operations.
2527 */
2528 struct anv_surface shadow_surface;
2529
2530 /**
2531 * For color images, this is the aux usage for this image when not used
2532 * as a color attachment.
2533 *
2534 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2535 * image has a HiZ buffer.
2536 */
2537 enum isl_aux_usage aux_usage;
2538
2539 struct anv_surface aux_surface;
2540
2541 /**
2542 * Offset of the fast clear state (used to compute the
2543 * fast_clear_state_offset of the following planes).
2544 */
2545 uint32_t fast_clear_state_offset;
2546
2547 /**
2548 * BO associated with this plane, set when bound.
2549 */
2550 struct anv_bo *bo;
2551 VkDeviceSize bo_offset;
2552
2553 /**
2554 * When destroying the image, also free the bo.
2555 * */
2556 bool bo_is_owned;
2557 } planes[3];
2558 };
2559
2560 /* The ordering of this enum is important */
2561 enum anv_fast_clear_type {
2562 /** Image does not have/support any fast-clear blocks */
2563 ANV_FAST_CLEAR_NONE = 0,
2564 /** Image has/supports fast-clear but only to the default value */
2565 ANV_FAST_CLEAR_DEFAULT_VALUE = 1,
2566 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2567 ANV_FAST_CLEAR_ANY = 2,
2568 };
2569
2570 /* Returns the number of auxiliary buffer levels attached to an image. */
2571 static inline uint8_t
2572 anv_image_aux_levels(const struct anv_image * const image,
2573 VkImageAspectFlagBits aspect)
2574 {
2575 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2576 return image->planes[plane].aux_surface.isl.size > 0 ?
2577 image->planes[plane].aux_surface.isl.levels : 0;
2578 }
2579
2580 /* Returns the number of auxiliary buffer layers attached to an image. */
2581 static inline uint32_t
2582 anv_image_aux_layers(const struct anv_image * const image,
2583 VkImageAspectFlagBits aspect,
2584 const uint8_t miplevel)
2585 {
2586 assert(image);
2587
2588 /* The miplevel must exist in the main buffer. */
2589 assert(miplevel < image->levels);
2590
2591 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2592 /* There are no layers with auxiliary data because the miplevel has no
2593 * auxiliary data.
2594 */
2595 return 0;
2596 } else {
2597 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2598 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2599 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2600 }
2601 }
2602
2603 static inline struct anv_address
2604 anv_image_get_clear_color_addr(const struct anv_device *device,
2605 const struct anv_image *image,
2606 VkImageAspectFlagBits aspect)
2607 {
2608 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
2609
2610 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2611 return (struct anv_address) {
2612 .bo = image->planes[plane].bo,
2613 .offset = image->planes[plane].bo_offset +
2614 image->planes[plane].fast_clear_state_offset,
2615 };
2616 }
2617
2618 static inline struct anv_address
2619 anv_image_get_fast_clear_type_addr(const struct anv_device *device,
2620 const struct anv_image *image,
2621 VkImageAspectFlagBits aspect)
2622 {
2623 struct anv_address addr =
2624 anv_image_get_clear_color_addr(device, image, aspect);
2625
2626 const unsigned clear_color_state_size = device->info.gen >= 10 ?
2627 device->isl_dev.ss.clear_color_state_size :
2628 device->isl_dev.ss.clear_value_size;
2629 addr.offset += clear_color_state_size;
2630 return addr;
2631 }
2632
2633 static inline struct anv_address
2634 anv_image_get_compression_state_addr(const struct anv_device *device,
2635 const struct anv_image *image,
2636 VkImageAspectFlagBits aspect,
2637 uint32_t level, uint32_t array_layer)
2638 {
2639 assert(level < anv_image_aux_levels(image, aspect));
2640 assert(array_layer < anv_image_aux_layers(image, aspect, level));
2641 UNUSED uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2642 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E);
2643
2644 struct anv_address addr =
2645 anv_image_get_fast_clear_type_addr(device, image, aspect);
2646 addr.offset += 4; /* Go past the fast clear type */
2647
2648 if (image->type == VK_IMAGE_TYPE_3D) {
2649 for (uint32_t l = 0; l < level; l++)
2650 addr.offset += anv_minify(image->extent.depth, l) * 4;
2651 } else {
2652 addr.offset += level * image->array_size * 4;
2653 }
2654 addr.offset += array_layer * 4;
2655
2656 return addr;
2657 }
2658
2659 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2660 static inline bool
2661 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2662 const struct anv_image *image)
2663 {
2664 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2665 return false;
2666
2667 if (devinfo->gen < 8)
2668 return false;
2669
2670 return image->samples == 1;
2671 }
2672
2673 void
2674 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
2675 const struct anv_image *image,
2676 VkImageAspectFlagBits aspect,
2677 enum isl_aux_usage aux_usage,
2678 uint32_t level,
2679 uint32_t base_layer,
2680 uint32_t layer_count);
2681
2682 void
2683 anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
2684 const struct anv_image *image,
2685 VkImageAspectFlagBits aspect,
2686 enum isl_aux_usage aux_usage,
2687 enum isl_format format, struct isl_swizzle swizzle,
2688 uint32_t level, uint32_t base_layer, uint32_t layer_count,
2689 VkRect2D area, union isl_color_value clear_color);
2690 void
2691 anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
2692 const struct anv_image *image,
2693 VkImageAspectFlags aspects,
2694 enum isl_aux_usage depth_aux_usage,
2695 uint32_t level,
2696 uint32_t base_layer, uint32_t layer_count,
2697 VkRect2D area,
2698 float depth_value, uint8_t stencil_value);
2699 void
2700 anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
2701 const struct anv_image *image,
2702 VkImageAspectFlagBits aspect, uint32_t level,
2703 uint32_t base_layer, uint32_t layer_count,
2704 enum isl_aux_op hiz_op);
2705 void
2706 anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
2707 const struct anv_image *image,
2708 VkImageAspectFlags aspects,
2709 uint32_t level,
2710 uint32_t base_layer, uint32_t layer_count,
2711 VkRect2D area, uint8_t stencil_value);
2712 void
2713 anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
2714 const struct anv_image *image,
2715 VkImageAspectFlagBits aspect,
2716 uint32_t base_layer, uint32_t layer_count,
2717 enum isl_aux_op mcs_op, union isl_color_value *clear_value,
2718 bool predicate);
2719 void
2720 anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
2721 const struct anv_image *image,
2722 VkImageAspectFlagBits aspect, uint32_t level,
2723 uint32_t base_layer, uint32_t layer_count,
2724 enum isl_aux_op ccs_op, union isl_color_value *clear_value,
2725 bool predicate);
2726
2727 void
2728 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2729 const struct anv_image *image,
2730 uint32_t base_level, uint32_t level_count,
2731 uint32_t base_layer, uint32_t layer_count);
2732
2733 enum isl_aux_usage
2734 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2735 const struct anv_image *image,
2736 const VkImageAspectFlagBits aspect,
2737 const VkImageLayout layout);
2738
2739 enum anv_fast_clear_type
2740 anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
2741 const struct anv_image * const image,
2742 const VkImageAspectFlagBits aspect,
2743 const VkImageLayout layout);
2744
2745 /* This is defined as a macro so that it works for both
2746 * VkImageSubresourceRange and VkImageSubresourceLayers
2747 */
2748 #define anv_get_layerCount(_image, _range) \
2749 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2750 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2751
2752 static inline uint32_t
2753 anv_get_levelCount(const struct anv_image *image,
2754 const VkImageSubresourceRange *range)
2755 {
2756 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2757 image->levels - range->baseMipLevel : range->levelCount;
2758 }
2759
2760 static inline VkImageAspectFlags
2761 anv_image_expand_aspects(const struct anv_image *image,
2762 VkImageAspectFlags aspects)
2763 {
2764 /* If the underlying image has color plane aspects and
2765 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2766 * the underlying image. */
2767 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
2768 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2769 return image->aspects;
2770
2771 return aspects;
2772 }
2773
2774 static inline bool
2775 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2776 VkImageAspectFlags aspects2)
2777 {
2778 if (aspects1 == aspects2)
2779 return true;
2780
2781 /* Only 1 color aspects are compatibles. */
2782 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2783 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2784 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2785 return true;
2786
2787 return false;
2788 }
2789
2790 struct anv_image_view {
2791 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2792
2793 VkImageAspectFlags aspect_mask;
2794 VkFormat vk_format;
2795 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2796
2797 unsigned n_planes;
2798 struct {
2799 uint32_t image_plane;
2800
2801 struct isl_view isl;
2802
2803 /**
2804 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2805 * image layout of SHADER_READ_ONLY_OPTIMAL or
2806 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2807 */
2808 struct anv_surface_state optimal_sampler_surface_state;
2809
2810 /**
2811 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2812 * image layout of GENERAL.
2813 */
2814 struct anv_surface_state general_sampler_surface_state;
2815
2816 /**
2817 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2818 * states for write-only and readable, using the real format for
2819 * write-only and the lowered format for readable.
2820 */
2821 struct anv_surface_state storage_surface_state;
2822 struct anv_surface_state writeonly_storage_surface_state;
2823
2824 struct brw_image_param storage_image_param;
2825 } planes[3];
2826 };
2827
2828 enum anv_image_view_state_flags {
2829 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2830 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2831 };
2832
2833 void anv_image_fill_surface_state(struct anv_device *device,
2834 const struct anv_image *image,
2835 VkImageAspectFlagBits aspect,
2836 const struct isl_view *view,
2837 isl_surf_usage_flags_t view_usage,
2838 enum isl_aux_usage aux_usage,
2839 const union isl_color_value *clear_color,
2840 enum anv_image_view_state_flags flags,
2841 struct anv_surface_state *state_inout,
2842 struct brw_image_param *image_param_out);
2843
2844 struct anv_image_create_info {
2845 const VkImageCreateInfo *vk_info;
2846
2847 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2848 isl_tiling_flags_t isl_tiling_flags;
2849
2850 /** These flags will be added to any derived from VkImageCreateInfo. */
2851 isl_surf_usage_flags_t isl_extra_usage_flags;
2852
2853 uint32_t stride;
2854 };
2855
2856 VkResult anv_image_create(VkDevice _device,
2857 const struct anv_image_create_info *info,
2858 const VkAllocationCallbacks* alloc,
2859 VkImage *pImage);
2860
2861 #ifdef ANDROID
2862 VkResult anv_image_from_gralloc(VkDevice device_h,
2863 const VkImageCreateInfo *base_info,
2864 const VkNativeBufferANDROID *gralloc_info,
2865 const VkAllocationCallbacks *alloc,
2866 VkImage *pImage);
2867 #endif
2868
2869 const struct anv_surface *
2870 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2871 VkImageAspectFlags aspect_mask);
2872
2873 enum isl_format
2874 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2875
2876 static inline struct VkExtent3D
2877 anv_sanitize_image_extent(const VkImageType imageType,
2878 const struct VkExtent3D imageExtent)
2879 {
2880 switch (imageType) {
2881 case VK_IMAGE_TYPE_1D:
2882 return (VkExtent3D) { imageExtent.width, 1, 1 };
2883 case VK_IMAGE_TYPE_2D:
2884 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2885 case VK_IMAGE_TYPE_3D:
2886 return imageExtent;
2887 default:
2888 unreachable("invalid image type");
2889 }
2890 }
2891
2892 static inline struct VkOffset3D
2893 anv_sanitize_image_offset(const VkImageType imageType,
2894 const struct VkOffset3D imageOffset)
2895 {
2896 switch (imageType) {
2897 case VK_IMAGE_TYPE_1D:
2898 return (VkOffset3D) { imageOffset.x, 0, 0 };
2899 case VK_IMAGE_TYPE_2D:
2900 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2901 case VK_IMAGE_TYPE_3D:
2902 return imageOffset;
2903 default:
2904 unreachable("invalid image type");
2905 }
2906 }
2907
2908
2909 void anv_fill_buffer_surface_state(struct anv_device *device,
2910 struct anv_state state,
2911 enum isl_format format,
2912 uint32_t offset, uint32_t range,
2913 uint32_t stride);
2914
2915 static inline void
2916 anv_clear_color_from_att_state(union isl_color_value *clear_color,
2917 const struct anv_attachment_state *att_state,
2918 const struct anv_image_view *iview)
2919 {
2920 const struct isl_format_layout *view_fmtl =
2921 isl_format_get_layout(iview->planes[0].isl.format);
2922
2923 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
2924 if (view_fmtl->channels.c.bits) \
2925 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
2926
2927 COPY_CLEAR_COLOR_CHANNEL(r, 0);
2928 COPY_CLEAR_COLOR_CHANNEL(g, 1);
2929 COPY_CLEAR_COLOR_CHANNEL(b, 2);
2930 COPY_CLEAR_COLOR_CHANNEL(a, 3);
2931
2932 #undef COPY_CLEAR_COLOR_CHANNEL
2933 }
2934
2935
2936 struct anv_ycbcr_conversion {
2937 const struct anv_format * format;
2938 VkSamplerYcbcrModelConversion ycbcr_model;
2939 VkSamplerYcbcrRange ycbcr_range;
2940 VkComponentSwizzle mapping[4];
2941 VkChromaLocation chroma_offsets[2];
2942 VkFilter chroma_filter;
2943 bool chroma_reconstruction;
2944 };
2945
2946 struct anv_sampler {
2947 uint32_t state[3][4];
2948 uint32_t n_planes;
2949 struct anv_ycbcr_conversion *conversion;
2950 };
2951
2952 struct anv_framebuffer {
2953 uint32_t width;
2954 uint32_t height;
2955 uint32_t layers;
2956
2957 uint32_t attachment_count;
2958 struct anv_image_view * attachments[0];
2959 };
2960
2961 struct anv_subpass_attachment {
2962 VkImageUsageFlagBits usage;
2963 uint32_t attachment;
2964 VkImageLayout layout;
2965 };
2966
2967 struct anv_subpass {
2968 uint32_t attachment_count;
2969
2970 /**
2971 * A pointer to all attachment references used in this subpass.
2972 * Only valid if ::attachment_count > 0.
2973 */
2974 struct anv_subpass_attachment * attachments;
2975 uint32_t input_count;
2976 struct anv_subpass_attachment * input_attachments;
2977 uint32_t color_count;
2978 struct anv_subpass_attachment * color_attachments;
2979 struct anv_subpass_attachment * resolve_attachments;
2980
2981 struct anv_subpass_attachment depth_stencil_attachment;
2982
2983 uint32_t view_mask;
2984
2985 /** Subpass has a depth/stencil self-dependency */
2986 bool has_ds_self_dep;
2987
2988 /** Subpass has at least one resolve attachment */
2989 bool has_resolve;
2990 };
2991
2992 static inline unsigned
2993 anv_subpass_view_count(const struct anv_subpass *subpass)
2994 {
2995 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2996 }
2997
2998 struct anv_render_pass_attachment {
2999 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3000 * its members individually.
3001 */
3002 VkFormat format;
3003 uint32_t samples;
3004 VkImageUsageFlags usage;
3005 VkAttachmentLoadOp load_op;
3006 VkAttachmentStoreOp store_op;
3007 VkAttachmentLoadOp stencil_load_op;
3008 VkImageLayout initial_layout;
3009 VkImageLayout final_layout;
3010 VkImageLayout first_subpass_layout;
3011
3012 /* The subpass id in which the attachment will be used last. */
3013 uint32_t last_subpass_idx;
3014 };
3015
3016 struct anv_render_pass {
3017 uint32_t attachment_count;
3018 uint32_t subpass_count;
3019 /* An array of subpass_count+1 flushes, one per subpass boundary */
3020 enum anv_pipe_bits * subpass_flushes;
3021 struct anv_render_pass_attachment * attachments;
3022 struct anv_subpass subpasses[0];
3023 };
3024
3025 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3026
3027 struct anv_query_pool {
3028 VkQueryType type;
3029 VkQueryPipelineStatisticFlags pipeline_statistics;
3030 /** Stride between slots, in bytes */
3031 uint32_t stride;
3032 /** Number of slots in this query pool */
3033 uint32_t slots;
3034 struct anv_bo bo;
3035 };
3036
3037 int anv_get_entrypoint_index(const char *name);
3038
3039 bool
3040 anv_entrypoint_is_enabled(int index, uint32_t core_version,
3041 const struct anv_instance_extension_table *instance,
3042 const struct anv_device_extension_table *device);
3043
3044 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
3045 const char *name);
3046
3047 void anv_dump_image_to_ppm(struct anv_device *device,
3048 struct anv_image *image, unsigned miplevel,
3049 unsigned array_layer, VkImageAspectFlagBits aspect,
3050 const char *filename);
3051
3052 enum anv_dump_action {
3053 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
3054 };
3055
3056 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
3057 void anv_dump_finish(void);
3058
3059 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
3060 struct anv_framebuffer *fb);
3061
3062 static inline uint32_t
3063 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
3064 {
3065 /* This function must be called from within a subpass. */
3066 assert(cmd_state->pass && cmd_state->subpass);
3067
3068 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
3069
3070 /* The id of this subpass shouldn't exceed the number of subpasses in this
3071 * render pass minus 1.
3072 */
3073 assert(subpass_id < cmd_state->pass->subpass_count);
3074 return subpass_id;
3075 }
3076
3077 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3078 \
3079 static inline struct __anv_type * \
3080 __anv_type ## _from_handle(__VkType _handle) \
3081 { \
3082 return (struct __anv_type *) _handle; \
3083 } \
3084 \
3085 static inline __VkType \
3086 __anv_type ## _to_handle(struct __anv_type *_obj) \
3087 { \
3088 return (__VkType) _obj; \
3089 }
3090
3091 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3092 \
3093 static inline struct __anv_type * \
3094 __anv_type ## _from_handle(__VkType _handle) \
3095 { \
3096 return (struct __anv_type *)(uintptr_t) _handle; \
3097 } \
3098 \
3099 static inline __VkType \
3100 __anv_type ## _to_handle(struct __anv_type *_obj) \
3101 { \
3102 return (__VkType)(uintptr_t) _obj; \
3103 }
3104
3105 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3106 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3107
3108 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
3109 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
3110 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
3111 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
3112 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
3113
3114 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
3115 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
3116 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
3117 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
3118 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
3119 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
3120 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
3121 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
3122 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
3123 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
3124 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
3125 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
3126 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
3127 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
3128 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
3129 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
3130 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
3131 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
3132 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
3133 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
3134 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
3135 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback, VkDebugReportCallbackEXT)
3136 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversion)
3137
3138 /* Gen-specific function declarations */
3139 #ifdef genX
3140 # include "anv_genX.h"
3141 #else
3142 # define genX(x) gen7_##x
3143 # include "anv_genX.h"
3144 # undef genX
3145 # define genX(x) gen75_##x
3146 # include "anv_genX.h"
3147 # undef genX
3148 # define genX(x) gen8_##x
3149 # include "anv_genX.h"
3150 # undef genX
3151 # define genX(x) gen9_##x
3152 # include "anv_genX.h"
3153 # undef genX
3154 # define genX(x) gen10_##x
3155 # include "anv_genX.h"
3156 # undef genX
3157 # define genX(x) gen11_##x
3158 # include "anv_genX.h"
3159 # undef genX
3160 #endif
3161
3162 #endif /* ANV_PRIVATE_H */