2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
54 /* Pre-declarations needed for WSI entrypoints */
57 typedef struct xcb_connection_t xcb_connection_t
;
58 typedef uint32_t xcb_visualid_t
;
59 typedef uint32_t xcb_window_t
;
62 struct anv_buffer_view
;
63 struct anv_image_view
;
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
71 #include "anv_entrypoints.h"
74 #include "common/gen_debug.h"
75 #include "wsi_common.h"
77 /* Allowing different clear colors requires us to perform a depth resolve at
78 * the end of certain render passes. This is because while slow clears store
79 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
80 * See the PRMs for examples describing when additional resolves would be
81 * necessary. To enable fast clears without requiring extra resolves, we set
82 * the clear value to a globally-defined one. We could allow different values
83 * if the user doesn't expect coherent data during or after a render passes
84 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
85 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
86 * 1.0f seems to be the only value used. The only application that doesn't set
87 * this value does so through the usage of an seemingly uninitialized clear
90 #define ANV_HZ_FC_VAL 1.0f
95 #define MAX_VIEWPORTS 16
96 #define MAX_SCISSORS 16
97 #define MAX_PUSH_CONSTANTS_SIZE 128
98 #define MAX_DYNAMIC_BUFFERS 16
100 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
102 #define ANV_SVGS_VB_INDEX MAX_VBS
103 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
105 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
107 static inline uint32_t
108 align_down_npot_u32(uint32_t v
, uint32_t a
)
113 static inline uint32_t
114 align_u32(uint32_t v
, uint32_t a
)
116 assert(a
!= 0 && a
== (a
& -a
));
117 return (v
+ a
- 1) & ~(a
- 1);
120 static inline uint64_t
121 align_u64(uint64_t v
, uint64_t a
)
123 assert(a
!= 0 && a
== (a
& -a
));
124 return (v
+ a
- 1) & ~(a
- 1);
127 static inline int32_t
128 align_i32(int32_t v
, int32_t a
)
130 assert(a
!= 0 && a
== (a
& -a
));
131 return (v
+ a
- 1) & ~(a
- 1);
134 /** Alignment must be a power of 2. */
136 anv_is_aligned(uintmax_t n
, uintmax_t a
)
138 assert(a
== (a
& -a
));
139 return (n
& (a
- 1)) == 0;
142 static inline uint32_t
143 anv_minify(uint32_t n
, uint32_t levels
)
145 if (unlikely(n
== 0))
148 return MAX2(n
>> levels
, 1);
152 anv_clamp_f(float f
, float min
, float max
)
165 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
167 if (*inout_mask
& clear_mask
) {
168 *inout_mask
&= ~clear_mask
;
175 static inline union isl_color_value
176 vk_to_isl_color(VkClearColorValue color
)
178 return (union isl_color_value
) {
188 #define for_each_bit(b, dword) \
189 for (uint32_t __dword = (dword); \
190 (b) = __builtin_ffs(__dword) - 1, __dword; \
191 __dword &= ~(1 << (b)))
193 #define typed_memcpy(dest, src, count) ({ \
194 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
195 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 /* Whenever we generate an error, pass it through this function. Useful for
199 * debugging, where we can break on it. Only call at error site, not when
200 * propagating errors. Might be useful to plug in a stack trace here.
203 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
206 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
207 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
208 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
210 #define vk_error(error) error
211 #define vk_errorf(error, format, ...) error
212 #define anv_debug(format, ...)
216 * Warn on ignored extension structs.
218 * The Vulkan spec requires us to ignore unsupported or unknown structs in
219 * a pNext chain. In debug mode, emitting warnings for ignored structs may
220 * help us discover structs that we should not have ignored.
223 * From the Vulkan 1.0.38 spec:
225 * Any component of the implementation (the loader, any enabled layers,
226 * and drivers) must skip over, without processing (other than reading the
227 * sType and pNext members) any chained structures with sType values not
228 * defined by extensions supported by that component.
230 #define anv_debug_ignored_stype(sType) \
231 anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType))
233 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
234 anv_printflike(3, 4);
235 void __anv_perf_warn(const char *file
, int line
, const char *format
, ...)
236 anv_printflike(3, 4);
237 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
238 void anv_loge_v(const char *format
, va_list va
);
241 * Print a FINISHME message, including its source location.
243 #define anv_finishme(format, ...) \
245 static bool reported = false; \
247 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
253 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
255 #define anv_perf_warn(format, ...) \
257 static bool reported = false; \
258 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
259 __anv_perf_warn(__FILE__, __LINE__, format, ##__VA_ARGS__); \
264 /* A non-fatal assert. Useful for debugging. */
266 #define anv_assert(x) ({ \
267 if (unlikely(!(x))) \
268 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
271 #define anv_assert(x)
274 /* A multi-pointer allocator
276 * When copying data structures from the user (such as a render pass), it's
277 * common to need to allocate data for a bunch of different things. Instead
278 * of doing several allocations and having to handle all of the error checking
279 * that entails, it can be easier to do a single allocation. This struct
280 * helps facilitate that. The intended usage looks like this:
283 * anv_multialloc_add(&ma, &main_ptr, 1);
284 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
285 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
287 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
288 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
290 struct anv_multialloc
{
298 #define ANV_MULTIALLOC_INIT \
299 ((struct anv_multialloc) { 0, })
301 #define ANV_MULTIALLOC(_name) \
302 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
304 __attribute__((always_inline
))
306 _anv_multialloc_add(struct anv_multialloc
*ma
,
307 void **ptr
, size_t size
, size_t align
)
309 size_t offset
= align_u64(ma
->size
, align
);
310 ma
->size
= offset
+ size
;
311 ma
->align
= MAX2(ma
->align
, align
);
313 /* Store the offset in the pointer. */
314 *ptr
= (void *)(uintptr_t)offset
;
316 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
317 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
320 #define anv_multialloc_add(_ma, _ptr, _count) \
321 _anv_multialloc_add((_ma), (void **)(_ptr), \
322 (_count) * sizeof(**(_ptr)), __alignof__(**(_ptr)))
324 __attribute__((always_inline
))
326 anv_multialloc_alloc(struct anv_multialloc
*ma
,
327 const VkAllocationCallbacks
*alloc
,
328 VkSystemAllocationScope scope
)
330 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
334 /* Fill out each of the pointers with their final value.
336 * for (uint32_t i = 0; i < ma->ptr_count; i++)
337 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
339 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
340 * constant, GCC is incapable of figuring this out and unrolling the loop
341 * so we have to give it a little help.
343 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
344 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
345 if ((_i) < ma->ptr_count) \
346 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
347 _ANV_MULTIALLOC_UPDATE_POINTER(0);
348 _ANV_MULTIALLOC_UPDATE_POINTER(1);
349 _ANV_MULTIALLOC_UPDATE_POINTER(2);
350 _ANV_MULTIALLOC_UPDATE_POINTER(3);
351 _ANV_MULTIALLOC_UPDATE_POINTER(4);
352 _ANV_MULTIALLOC_UPDATE_POINTER(5);
353 _ANV_MULTIALLOC_UPDATE_POINTER(6);
354 _ANV_MULTIALLOC_UPDATE_POINTER(7);
355 #undef _ANV_MULTIALLOC_UPDATE_POINTER
360 __attribute__((always_inline
))
362 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
363 const VkAllocationCallbacks
*parent_alloc
,
364 const VkAllocationCallbacks
*alloc
,
365 VkSystemAllocationScope scope
)
367 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
371 * A dynamically growable, circular buffer. Elements are added at head and
372 * removed from tail. head and tail are free-running uint32_t indices and we
373 * only compute the modulo with size when accessing the array. This way,
374 * number of bytes in the queue is always head - tail, even in case of
381 /* Index into the current validation list. This is used by the
382 * validation list building alrogithm to track which buffers are already
383 * in the validation list so that we can ensure uniqueness.
387 /* Last known offset. This value is provided by the kernel when we
388 * execbuf and is used as the presumed offset for the next bunch of
396 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
401 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
403 bo
->gem_handle
= gem_handle
;
411 /* Represents a lock-free linked list of "free" things. This is used by
412 * both the block pool and the state pools. Unfortunately, in order to
413 * solve the ABA problem, we can't use a single uint32_t head.
415 union anv_free_list
{
419 /* A simple count that is incremented every time the head changes. */
425 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
427 struct anv_block_state
{
437 struct anv_block_pool
{
438 struct anv_device
*device
;
442 /* The offset from the start of the bo to the "center" of the block
443 * pool. Pointers to allocated blocks are given by
444 * bo.map + center_bo_offset + offsets.
446 uint32_t center_bo_offset
;
448 /* Current memory map of the block pool. This pointer may or may not
449 * point to the actual beginning of the block pool memory. If
450 * anv_block_pool_alloc_back has ever been called, then this pointer
451 * will point to the "center" position of the buffer and all offsets
452 * (negative or positive) given out by the block pool alloc functions
453 * will be valid relative to this pointer.
455 * In particular, map == bo.map + center_offset
461 * Array of mmaps and gem handles owned by the block pool, reclaimed when
462 * the block pool is destroyed.
464 struct u_vector mmap_cleanups
;
466 struct anv_block_state state
;
468 struct anv_block_state back_state
;
471 /* Block pools are backed by a fixed-size 1GB memfd */
472 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
474 /* The center of the block pool is also the middle of the memfd. This may
475 * change in the future if we decide differently for some reason.
477 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
479 static inline uint32_t
480 anv_block_pool_size(struct anv_block_pool
*pool
)
482 return pool
->state
.end
+ pool
->back_state
.end
;
491 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
493 struct anv_fixed_size_state_pool
{
494 union anv_free_list free_list
;
495 struct anv_block_state block
;
498 #define ANV_MIN_STATE_SIZE_LOG2 6
499 #define ANV_MAX_STATE_SIZE_LOG2 20
501 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
503 struct anv_state_pool
{
504 struct anv_block_pool block_pool
;
506 /* The size of blocks which will be allocated from the block pool */
509 /** Free list for "back" allocations */
510 union anv_free_list back_alloc_free_list
;
512 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
515 struct anv_state_stream_block
;
517 struct anv_state_stream
{
518 struct anv_state_pool
*state_pool
;
520 /* The size of blocks to allocate from the state pool */
523 /* Current block we're allocating from */
524 struct anv_state block
;
526 /* Offset into the current block at which to allocate the next state */
529 /* List of all blocks allocated from this pool */
530 struct anv_state_stream_block
*block_list
;
533 /* The block_pool functions exported for testing only. The block pool should
534 * only be used via a state pool (see below).
536 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
537 struct anv_device
*device
,
538 uint32_t initial_size
);
539 void anv_block_pool_finish(struct anv_block_pool
*pool
);
540 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
541 uint32_t block_size
);
542 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
543 uint32_t block_size
);
545 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
546 struct anv_device
*device
,
547 uint32_t block_size
);
548 void anv_state_pool_finish(struct anv_state_pool
*pool
);
549 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
550 uint32_t state_size
, uint32_t alignment
);
551 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
552 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
553 void anv_state_stream_init(struct anv_state_stream
*stream
,
554 struct anv_state_pool
*state_pool
,
555 uint32_t block_size
);
556 void anv_state_stream_finish(struct anv_state_stream
*stream
);
557 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
558 uint32_t size
, uint32_t alignment
);
561 * Implements a pool of re-usable BOs. The interface is identical to that
562 * of block_pool except that each block is its own BO.
565 struct anv_device
*device
;
570 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
571 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
572 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
574 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
576 struct anv_scratch_bo
{
581 struct anv_scratch_pool
{
582 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
583 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
586 void anv_scratch_pool_init(struct anv_device
*device
,
587 struct anv_scratch_pool
*pool
);
588 void anv_scratch_pool_finish(struct anv_device
*device
,
589 struct anv_scratch_pool
*pool
);
590 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
591 struct anv_scratch_pool
*pool
,
592 gl_shader_stage stage
,
593 unsigned per_thread_scratch
);
595 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
596 struct anv_bo_cache
{
597 struct hash_table
*bo_map
;
598 pthread_mutex_t mutex
;
601 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
602 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
603 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
604 struct anv_bo_cache
*cache
,
605 uint64_t size
, struct anv_bo
**bo
);
606 VkResult
anv_bo_cache_import(struct anv_device
*device
,
607 struct anv_bo_cache
*cache
,
608 int fd
, uint64_t size
, struct anv_bo
**bo
);
609 VkResult
anv_bo_cache_export(struct anv_device
*device
,
610 struct anv_bo_cache
*cache
,
611 struct anv_bo
*bo_in
, int *fd_out
);
612 void anv_bo_cache_release(struct anv_device
*device
,
613 struct anv_bo_cache
*cache
,
616 struct anv_memory_type
{
617 /* Standard bits passed on to the client */
618 VkMemoryPropertyFlags propertyFlags
;
621 /* Driver-internal book-keeping */
622 VkBufferUsageFlags valid_buffer_usage
;
625 struct anv_memory_heap
{
626 /* Standard bits passed on to the client */
628 VkMemoryHeapFlags flags
;
630 /* Driver-internal book-keeping */
631 bool supports_48bit_addresses
;
634 struct anv_physical_device
{
635 VK_LOADER_DATA _loader_data
;
637 struct anv_instance
* instance
;
641 struct gen_device_info info
;
642 /** Amount of "GPU memory" we want to advertise
644 * Clearly, this value is bogus since Intel is a UMA architecture. On
645 * gen7 platforms, we are limited by GTT size unless we want to implement
646 * fine-grained tracking and GTT splitting. On Broadwell and above we are
647 * practically unlimited. However, we will never report more than 3/4 of
648 * the total system ram to try and avoid running out of RAM.
650 bool supports_48bit_addresses
;
651 struct brw_compiler
* compiler
;
652 struct isl_device isl_dev
;
653 int cmd_parser_version
;
659 uint32_t subslice_total
;
663 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
665 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
668 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
669 uint8_t driver_uuid
[VK_UUID_SIZE
];
670 uint8_t device_uuid
[VK_UUID_SIZE
];
672 struct wsi_device wsi_device
;
676 struct anv_instance
{
677 VK_LOADER_DATA _loader_data
;
679 VkAllocationCallbacks alloc
;
682 int physicalDeviceCount
;
683 struct anv_physical_device physicalDevice
;
686 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
687 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
689 bool anv_instance_extension_supported(const char *name
);
690 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
691 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
695 VK_LOADER_DATA _loader_data
;
697 struct anv_device
* device
;
699 struct anv_state_pool
* pool
;
702 struct anv_pipeline_cache
{
703 struct anv_device
* device
;
704 pthread_mutex_t mutex
;
706 struct hash_table
* cache
;
709 struct anv_pipeline_bind_map
;
711 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
712 struct anv_device
*device
,
714 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
716 struct anv_shader_bin
*
717 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
718 const void *key
, uint32_t key_size
);
719 struct anv_shader_bin
*
720 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
721 const void *key_data
, uint32_t key_size
,
722 const void *kernel_data
, uint32_t kernel_size
,
723 const struct brw_stage_prog_data
*prog_data
,
724 uint32_t prog_data_size
,
725 const struct anv_pipeline_bind_map
*bind_map
);
728 VK_LOADER_DATA _loader_data
;
730 VkAllocationCallbacks alloc
;
732 struct anv_instance
* instance
;
734 struct gen_device_info info
;
735 struct isl_device isl_dev
;
738 bool can_chain_batches
;
739 bool robust_buffer_access
;
741 struct anv_bo_pool batch_bo_pool
;
743 struct anv_bo_cache bo_cache
;
745 struct anv_state_pool dynamic_state_pool
;
746 struct anv_state_pool instruction_state_pool
;
747 struct anv_state_pool surface_state_pool
;
749 struct anv_bo workaround_bo
;
750 struct anv_bo trivial_batch_bo
;
752 struct anv_pipeline_cache blorp_shader_cache
;
753 struct blorp_context blorp
;
755 struct anv_state border_colors
;
757 struct anv_queue queue
;
759 struct anv_scratch_pool scratch_pool
;
761 uint32_t default_mocs
;
763 pthread_mutex_t mutex
;
764 pthread_cond_t queue_submit
;
769 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
771 if (device
->info
.has_llc
)
774 gen_flush_range(state
.map
, state
.alloc_size
);
777 void anv_device_init_blorp(struct anv_device
*device
);
778 void anv_device_finish_blorp(struct anv_device
*device
);
780 VkResult
anv_device_execbuf(struct anv_device
*device
,
781 struct drm_i915_gem_execbuffer2
*execbuf
,
782 struct anv_bo
**execbuf_bos
);
783 VkResult
anv_device_query_status(struct anv_device
*device
);
784 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
785 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
788 void* anv_gem_mmap(struct anv_device
*device
,
789 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
790 void anv_gem_munmap(void *p
, uint64_t size
);
791 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
792 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
793 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
794 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
795 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
796 int anv_gem_execbuffer(struct anv_device
*device
,
797 struct drm_i915_gem_execbuffer2
*execbuf
);
798 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
799 uint32_t stride
, uint32_t tiling
);
800 int anv_gem_create_context(struct anv_device
*device
);
801 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
802 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
804 int anv_gem_get_param(int fd
, uint32_t param
);
805 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
806 int anv_gem_get_aperture(int fd
, uint64_t *size
);
807 bool anv_gem_supports_48b_addresses(int fd
);
808 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
809 uint32_t *active
, uint32_t *pending
);
810 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
811 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
812 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
813 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
814 uint32_t read_domains
, uint32_t write_domain
);
815 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
816 uint32_t anv_gem_syncobj_create(struct anv_device
*device
);
817 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
818 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
819 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
821 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
823 struct anv_reloc_list
{
825 uint32_t array_length
;
826 struct drm_i915_gem_relocation_entry
* relocs
;
827 struct anv_bo
** reloc_bos
;
830 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
831 const VkAllocationCallbacks
*alloc
);
832 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
833 const VkAllocationCallbacks
*alloc
);
835 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
836 const VkAllocationCallbacks
*alloc
,
837 uint32_t offset
, struct anv_bo
*target_bo
,
840 struct anv_batch_bo
{
841 /* Link in the anv_cmd_buffer.owned_batch_bos list */
842 struct list_head link
;
846 /* Bytes actually consumed in this batch BO */
849 struct anv_reloc_list relocs
;
853 const VkAllocationCallbacks
* alloc
;
859 struct anv_reloc_list
* relocs
;
861 /* This callback is called (with the associated user data) in the event
862 * that the batch runs out of space.
864 VkResult (*extend_cb
)(struct anv_batch
*, void *);
868 * Current error status of the command buffer. Used to track inconsistent
869 * or incomplete command buffer states that are the consequence of run-time
870 * errors such as out of memory scenarios. We want to track this in the
871 * batch because the command buffer object is not visible to some parts
877 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
878 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
879 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
880 void *location
, struct anv_bo
*bo
, uint32_t offset
);
881 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
882 struct anv_batch
*batch
);
884 static inline VkResult
885 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
887 assert(error
!= VK_SUCCESS
);
888 if (batch
->status
== VK_SUCCESS
)
889 batch
->status
= error
;
890 return batch
->status
;
894 anv_batch_has_error(struct anv_batch
*batch
)
896 return batch
->status
!= VK_SUCCESS
;
904 static inline uint64_t
905 _anv_combine_address(struct anv_batch
*batch
, void *location
,
906 const struct anv_address address
, uint32_t delta
)
908 if (address
.bo
== NULL
) {
909 return address
.offset
+ delta
;
911 assert(batch
->start
<= location
&& location
< batch
->end
);
913 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
917 #define __gen_address_type struct anv_address
918 #define __gen_user_data struct anv_batch
919 #define __gen_combine_address _anv_combine_address
921 /* Wrapper macros needed to work around preprocessor argument issues. In
922 * particular, arguments don't get pre-evaluated if they are concatenated.
923 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
924 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
925 * We can work around this easily enough with these helpers.
927 #define __anv_cmd_length(cmd) cmd ## _length
928 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
929 #define __anv_cmd_header(cmd) cmd ## _header
930 #define __anv_cmd_pack(cmd) cmd ## _pack
931 #define __anv_reg_num(reg) reg ## _num
933 #define anv_pack_struct(dst, struc, ...) do { \
934 struct struc __template = { \
937 __anv_cmd_pack(struc)(NULL, dst, &__template); \
938 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
941 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
942 void *__dst = anv_batch_emit_dwords(batch, n); \
944 struct cmd __template = { \
945 __anv_cmd_header(cmd), \
946 .DWordLength = n - __anv_cmd_length_bias(cmd), \
949 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
954 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
958 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
959 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
962 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
963 dw[i] = (dwords0)[i] | (dwords1)[i]; \
964 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
967 #define anv_batch_emit(batch, cmd, name) \
968 for (struct cmd name = { __anv_cmd_header(cmd) }, \
969 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
970 __builtin_expect(_dst != NULL, 1); \
971 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
972 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
976 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
977 .GraphicsDataTypeGFDT = 0, \
978 .LLCCacheabilityControlLLCCC = 0, \
979 .L3CacheabilityControlL3CC = 1, \
982 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
983 .LLCeLLCCacheabilityControlLLCCC = 0, \
984 .L3CacheabilityControlL3CC = 1, \
987 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
988 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
989 .TargetCache = L3DefertoPATforLLCeLLCselection, \
993 /* Skylake: MOCS is now an index into an array of 62 different caching
994 * configurations programmed by the kernel.
997 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
998 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
999 .IndextoMOCSTables = 2 \
1002 #define GEN9_MOCS_PTE { \
1003 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1004 .IndextoMOCSTables = 1 \
1007 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1008 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1009 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1010 .IndextoMOCSTables = 2 \
1013 #define GEN10_MOCS_PTE { \
1014 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1015 .IndextoMOCSTables = 1 \
1018 struct anv_device_memory
{
1020 struct anv_memory_type
* type
;
1021 VkDeviceSize map_size
;
1026 * Header for Vertex URB Entry (VUE)
1028 struct anv_vue_header
{
1030 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1031 uint32_t ViewportIndex
;
1035 struct anv_descriptor_set_binding_layout
{
1037 /* The type of the descriptors in this binding */
1038 VkDescriptorType type
;
1041 /* Number of array elements in this binding */
1042 uint16_t array_size
;
1044 /* Index into the flattend descriptor set */
1045 uint16_t descriptor_index
;
1047 /* Index into the dynamic state array for a dynamic buffer */
1048 int16_t dynamic_offset_index
;
1050 /* Index into the descriptor set buffer views */
1051 int16_t buffer_index
;
1054 /* Index into the binding table for the associated surface */
1055 int16_t surface_index
;
1057 /* Index into the sampler table for the associated sampler */
1058 int16_t sampler_index
;
1060 /* Index into the image table for the associated image */
1061 int16_t image_index
;
1062 } stage
[MESA_SHADER_STAGES
];
1064 /* Immutable samplers (or NULL if no immutable samplers) */
1065 struct anv_sampler
**immutable_samplers
;
1068 struct anv_descriptor_set_layout
{
1069 /* Number of bindings in this descriptor set */
1070 uint16_t binding_count
;
1072 /* Total size of the descriptor set with room for all array entries */
1075 /* Shader stages affected by this descriptor set */
1076 uint16_t shader_stages
;
1078 /* Number of buffers in this descriptor set */
1079 uint16_t buffer_count
;
1081 /* Number of dynamic offsets used by this descriptor set */
1082 uint16_t dynamic_offset_count
;
1084 /* Bindings in this descriptor set */
1085 struct anv_descriptor_set_binding_layout binding
[0];
1088 struct anv_descriptor
{
1089 VkDescriptorType type
;
1093 VkImageLayout layout
;
1094 struct anv_image_view
*image_view
;
1095 struct anv_sampler
*sampler
;
1099 struct anv_buffer
*buffer
;
1104 struct anv_buffer_view
*buffer_view
;
1108 struct anv_descriptor_set
{
1109 const struct anv_descriptor_set_layout
*layout
;
1111 uint32_t buffer_count
;
1112 struct anv_buffer_view
*buffer_views
;
1113 struct anv_descriptor descriptors
[0];
1116 struct anv_buffer_view
{
1117 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1119 uint32_t offset
; /**< Offset into bo. */
1120 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1122 struct anv_state surface_state
;
1123 struct anv_state storage_surface_state
;
1124 struct anv_state writeonly_storage_surface_state
;
1126 struct brw_image_param storage_image_param
;
1129 struct anv_push_descriptor_set
{
1130 struct anv_descriptor_set set
;
1132 /* Put this field right behind anv_descriptor_set so it fills up the
1133 * descriptors[0] field. */
1134 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1136 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1139 struct anv_descriptor_pool
{
1144 struct anv_state_stream surface_state_stream
;
1145 void *surface_state_free_list
;
1150 enum anv_descriptor_template_entry_type
{
1151 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1152 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1153 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1156 struct anv_descriptor_template_entry
{
1157 /* The type of descriptor in this entry */
1158 VkDescriptorType type
;
1160 /* Binding in the descriptor set */
1163 /* Offset at which to write into the descriptor set binding */
1164 uint32_t array_element
;
1166 /* Number of elements to write into the descriptor set binding */
1167 uint32_t array_count
;
1169 /* Offset into the user provided data */
1172 /* Stride between elements into the user provided data */
1176 struct anv_descriptor_update_template
{
1177 /* The descriptor set this template corresponds to. This value is only
1178 * valid if the template was created with the templateType
1179 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1183 /* Number of entries in this template */
1184 uint32_t entry_count
;
1186 /* Entries of the template */
1187 struct anv_descriptor_template_entry entries
[0];
1191 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1194 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1195 const struct gen_device_info
* const devinfo
,
1196 const VkDescriptorImageInfo
* const info
,
1197 VkDescriptorType type
,
1202 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1203 VkDescriptorType type
,
1204 struct anv_buffer_view
*buffer_view
,
1209 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1210 struct anv_device
*device
,
1211 struct anv_state_stream
*alloc_stream
,
1212 VkDescriptorType type
,
1213 struct anv_buffer
*buffer
,
1216 VkDeviceSize offset
,
1217 VkDeviceSize range
);
1220 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1221 struct anv_device
*device
,
1222 struct anv_state_stream
*alloc_stream
,
1223 const struct anv_descriptor_update_template
*template,
1227 anv_descriptor_set_create(struct anv_device
*device
,
1228 struct anv_descriptor_pool
*pool
,
1229 const struct anv_descriptor_set_layout
*layout
,
1230 struct anv_descriptor_set
**out_set
);
1233 anv_descriptor_set_destroy(struct anv_device
*device
,
1234 struct anv_descriptor_pool
*pool
,
1235 struct anv_descriptor_set
*set
);
1237 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1239 struct anv_pipeline_binding
{
1240 /* The descriptor set this surface corresponds to. The special value of
1241 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1242 * to a color attachment and not a regular descriptor.
1246 /* Binding in the descriptor set */
1249 /* Index in the binding */
1252 /* Input attachment index (relative to the subpass) */
1253 uint8_t input_attachment_index
;
1255 /* For a storage image, whether it is write-only */
1259 struct anv_pipeline_layout
{
1261 struct anv_descriptor_set_layout
*layout
;
1262 uint32_t dynamic_offset_start
;
1268 bool has_dynamic_offsets
;
1269 } stage
[MESA_SHADER_STAGES
];
1271 unsigned char sha1
[20];
1275 struct anv_device
* device
;
1278 VkBufferUsageFlags usage
;
1280 /* Set when bound */
1282 VkDeviceSize offset
;
1285 static inline uint64_t
1286 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1288 assert(offset
<= buffer
->size
);
1289 if (range
== VK_WHOLE_SIZE
) {
1290 return buffer
->size
- offset
;
1292 assert(range
<= buffer
->size
);
1297 enum anv_cmd_dirty_bits
{
1298 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1299 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1300 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1301 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1302 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1303 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1304 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1305 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1306 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1307 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1308 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1309 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1310 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1312 typedef uint32_t anv_cmd_dirty_mask_t
;
1314 enum anv_pipe_bits
{
1315 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1316 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1317 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1318 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1319 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1320 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1321 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1322 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1323 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1324 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1325 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1327 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1328 * a flush has happened but not a CS stall. The next time we do any sort
1329 * of invalidation we need to insert a CS stall at that time. Otherwise,
1330 * we would have to CS stall on every flush which could be bad.
1332 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1335 #define ANV_PIPE_FLUSH_BITS ( \
1336 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1337 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1338 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1340 #define ANV_PIPE_STALL_BITS ( \
1341 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1342 ANV_PIPE_DEPTH_STALL_BIT | \
1343 ANV_PIPE_CS_STALL_BIT)
1345 #define ANV_PIPE_INVALIDATE_BITS ( \
1346 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1347 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1348 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1349 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1350 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1351 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1353 static inline enum anv_pipe_bits
1354 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1356 enum anv_pipe_bits pipe_bits
= 0;
1359 for_each_bit(b
, flags
) {
1360 switch ((VkAccessFlagBits
)(1 << b
)) {
1361 case VK_ACCESS_SHADER_WRITE_BIT
:
1362 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1364 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1365 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1367 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1368 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1370 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1371 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1372 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1375 break; /* Nothing to do */
1382 static inline enum anv_pipe_bits
1383 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1385 enum anv_pipe_bits pipe_bits
= 0;
1388 for_each_bit(b
, flags
) {
1389 switch ((VkAccessFlagBits
)(1 << b
)) {
1390 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1391 case VK_ACCESS_INDEX_READ_BIT
:
1392 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1393 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1395 case VK_ACCESS_UNIFORM_READ_BIT
:
1396 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1397 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1399 case VK_ACCESS_SHADER_READ_BIT
:
1400 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1401 case VK_ACCESS_TRANSFER_READ_BIT
:
1402 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1405 break; /* Nothing to do */
1412 struct anv_vertex_binding
{
1413 struct anv_buffer
* buffer
;
1414 VkDeviceSize offset
;
1417 struct anv_push_constants
{
1418 /* Current allocated size of this push constants data structure.
1419 * Because a decent chunk of it may not be used (images on SKL, for
1420 * instance), we won't actually allocate the entire structure up-front.
1424 /* Push constant data provided by the client through vkPushConstants */
1425 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1427 /* Our hardware only provides zero-based vertex and instance id so, in
1428 * order to satisfy the vulkan requirements, we may have to push one or
1429 * both of these into the shader.
1431 uint32_t base_vertex
;
1432 uint32_t base_instance
;
1434 /* Image data for image_load_store on pre-SKL */
1435 struct brw_image_param images
[MAX_IMAGES
];
1438 struct anv_dynamic_state
{
1441 VkViewport viewports
[MAX_VIEWPORTS
];
1446 VkRect2D scissors
[MAX_SCISSORS
];
1457 float blend_constants
[4];
1467 } stencil_compare_mask
;
1472 } stencil_write_mask
;
1477 } stencil_reference
;
1480 extern const struct anv_dynamic_state default_dynamic_state
;
1482 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1483 const struct anv_dynamic_state
*src
,
1484 uint32_t copy_mask
);
1487 * Attachment state when recording a renderpass instance.
1489 * The clear value is valid only if there exists a pending clear.
1491 struct anv_attachment_state
{
1492 enum isl_aux_usage aux_usage
;
1493 enum isl_aux_usage input_aux_usage
;
1494 struct anv_state color_rt_state
;
1495 struct anv_state input_att_state
;
1497 VkImageLayout current_layout
;
1498 VkImageAspectFlags pending_clear_aspects
;
1500 VkClearValue clear_value
;
1501 bool clear_color_is_zero_one
;
1502 bool clear_color_is_zero
;
1505 /** State required while building cmd buffer */
1506 struct anv_cmd_state
{
1507 /* PIPELINE_SELECT.PipelineSelection */
1508 uint32_t current_pipeline
;
1509 const struct gen_l3_config
* current_l3_config
;
1511 anv_cmd_dirty_mask_t dirty
;
1512 anv_cmd_dirty_mask_t compute_dirty
;
1513 enum anv_pipe_bits pending_pipe_bits
;
1514 uint32_t num_workgroups_offset
;
1515 struct anv_bo
*num_workgroups_bo
;
1516 VkShaderStageFlags descriptors_dirty
;
1517 VkShaderStageFlags push_constants_dirty
;
1518 uint32_t scratch_size
;
1519 struct anv_pipeline
* pipeline
;
1520 struct anv_pipeline
* compute_pipeline
;
1521 struct anv_framebuffer
* framebuffer
;
1522 struct anv_render_pass
* pass
;
1523 struct anv_subpass
* subpass
;
1524 VkRect2D render_area
;
1525 uint32_t restart_index
;
1526 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1527 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1528 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
1529 VkShaderStageFlags push_constant_stages
;
1530 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1531 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1532 struct anv_state samplers
[MESA_SHADER_STAGES
];
1533 struct anv_dynamic_state dynamic
;
1536 struct anv_push_descriptor_set push_descriptor
;
1539 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1540 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1541 * and before invoking the secondary in ExecuteCommands.
1543 bool pma_fix_enabled
;
1546 * Whether or not we know for certain that HiZ is enabled for the current
1547 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1548 * enabled or not, this will be false.
1553 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1554 * valid only when recording a render pass instance.
1556 struct anv_attachment_state
* attachments
;
1559 * Surface states for color render targets. These are stored in a single
1560 * flat array. For depth-stencil attachments, the surface state is simply
1563 struct anv_state render_pass_states
;
1566 * A null surface state of the right size to match the framebuffer. This
1567 * is one of the states in render_pass_states.
1569 struct anv_state null_surface_state
;
1572 struct anv_buffer
* index_buffer
;
1573 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1574 uint32_t index_offset
;
1578 struct anv_cmd_pool
{
1579 VkAllocationCallbacks alloc
;
1580 struct list_head cmd_buffers
;
1583 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1585 enum anv_cmd_buffer_exec_mode
{
1586 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1587 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1588 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1589 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1590 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1593 struct anv_cmd_buffer
{
1594 VK_LOADER_DATA _loader_data
;
1596 struct anv_device
* device
;
1598 struct anv_cmd_pool
* pool
;
1599 struct list_head pool_link
;
1601 struct anv_batch batch
;
1603 /* Fields required for the actual chain of anv_batch_bo's.
1605 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1607 struct list_head batch_bos
;
1608 enum anv_cmd_buffer_exec_mode exec_mode
;
1610 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1611 * referenced by this command buffer
1613 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1615 struct u_vector seen_bbos
;
1617 /* A vector of int32_t's for every block of binding tables.
1619 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1621 struct u_vector bt_block_states
;
1624 struct anv_reloc_list surface_relocs
;
1625 /** Last seen surface state block pool center bo offset */
1626 uint32_t last_ss_pool_center
;
1628 /* Serial for tracking buffer completion */
1631 /* Stream objects for storing temporary data */
1632 struct anv_state_stream surface_state_stream
;
1633 struct anv_state_stream dynamic_state_stream
;
1635 VkCommandBufferUsageFlags usage_flags
;
1636 VkCommandBufferLevel level
;
1638 struct anv_cmd_state state
;
1641 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1642 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1643 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1644 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1645 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1646 struct anv_cmd_buffer
*secondary
);
1647 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1648 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1649 struct anv_cmd_buffer
*cmd_buffer
,
1650 const VkSemaphore
*in_semaphores
,
1651 uint32_t num_in_semaphores
,
1652 const VkSemaphore
*out_semaphores
,
1653 uint32_t num_out_semaphores
);
1655 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1658 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1659 gl_shader_stage stage
, uint32_t size
);
1660 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1661 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1662 (offsetof(struct anv_push_constants, field) + \
1663 sizeof(cmd_buffer->state.push_constants[0]->field)))
1665 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1666 const void *data
, uint32_t size
, uint32_t alignment
);
1667 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1668 uint32_t *a
, uint32_t *b
,
1669 uint32_t dwords
, uint32_t alignment
);
1672 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1674 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1675 uint32_t entries
, uint32_t *state_offset
);
1677 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1679 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1680 uint32_t size
, uint32_t alignment
);
1683 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1685 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1686 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1687 bool depth_clamp_enable
);
1688 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1690 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1691 struct anv_render_pass
*pass
,
1692 struct anv_framebuffer
*framebuffer
,
1693 const VkClearValue
*clear_values
);
1695 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1698 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1699 gl_shader_stage stage
);
1701 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1703 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1704 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1706 const struct anv_image_view
*
1707 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1710 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1711 uint32_t num_entries
,
1712 uint32_t *state_offset
,
1713 struct anv_state
*bt_state
);
1715 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1717 enum anv_fence_state
{
1718 /** Indicates that this is a new (or newly reset fence) */
1719 ANV_FENCE_STATE_RESET
,
1721 /** Indicates that this fence has been submitted to the GPU but is still
1722 * (as far as we know) in use by the GPU.
1724 ANV_FENCE_STATE_SUBMITTED
,
1726 ANV_FENCE_STATE_SIGNALED
,
1731 struct drm_i915_gem_execbuffer2 execbuf
;
1732 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1733 enum anv_fence_state state
;
1738 struct anv_state state
;
1741 enum anv_semaphore_type
{
1742 ANV_SEMAPHORE_TYPE_NONE
= 0,
1743 ANV_SEMAPHORE_TYPE_DUMMY
,
1744 ANV_SEMAPHORE_TYPE_BO
,
1745 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
1746 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
1749 struct anv_semaphore_impl
{
1750 enum anv_semaphore_type type
;
1753 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1754 * This BO will be added to the object list on any execbuf2 calls for
1755 * which this semaphore is used as a wait or signal fence. When used as
1756 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1760 /* The sync file descriptor when type == AKV_SEMAPHORE_TYPE_SYNC_FILE.
1761 * If the semaphore is in the unsignaled state due to either just being
1762 * created or because it has been used for a wait, fd will be -1.
1766 /* Sync object handle when type == AKV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
1767 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
1768 * import so we don't need to bother with a userspace cache.
1774 struct anv_semaphore
{
1775 /* Permanent semaphore state. Every semaphore has some form of permanent
1776 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1777 * (for cross-process semaphores0 or it could just be a dummy for use
1780 struct anv_semaphore_impl permanent
;
1782 /* Temporary semaphore state. A semaphore *may* have temporary state.
1783 * That state is added to the semaphore by an import operation and is reset
1784 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1785 * semaphore with temporary state cannot be signaled because the semaphore
1786 * must already be signaled before the temporary state can be exported from
1787 * the semaphore in the other process and imported here.
1789 struct anv_semaphore_impl temporary
;
1792 void anv_semaphore_reset_temporary(struct anv_device
*device
,
1793 struct anv_semaphore
*semaphore
);
1795 struct anv_shader_module
{
1796 unsigned char sha1
[20];
1801 static inline gl_shader_stage
1802 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1804 assert(__builtin_popcount(vk_stage
) == 1);
1805 return ffs(vk_stage
) - 1;
1808 static inline VkShaderStageFlagBits
1809 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1811 return (1 << mesa_stage
);
1814 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1816 #define anv_foreach_stage(stage, stage_bits) \
1817 for (gl_shader_stage stage, \
1818 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1819 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1820 __tmp &= ~(1 << (stage)))
1822 struct anv_pipeline_bind_map
{
1823 uint32_t surface_count
;
1824 uint32_t sampler_count
;
1825 uint32_t image_count
;
1827 struct anv_pipeline_binding
* surface_to_descriptor
;
1828 struct anv_pipeline_binding
* sampler_to_descriptor
;
1831 struct anv_shader_bin_key
{
1836 struct anv_shader_bin
{
1839 const struct anv_shader_bin_key
*key
;
1841 struct anv_state kernel
;
1842 uint32_t kernel_size
;
1844 const struct brw_stage_prog_data
*prog_data
;
1845 uint32_t prog_data_size
;
1847 struct anv_pipeline_bind_map bind_map
;
1849 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1852 struct anv_shader_bin
*
1853 anv_shader_bin_create(struct anv_device
*device
,
1854 const void *key
, uint32_t key_size
,
1855 const void *kernel
, uint32_t kernel_size
,
1856 const struct brw_stage_prog_data
*prog_data
,
1857 uint32_t prog_data_size
, const void *prog_data_param
,
1858 const struct anv_pipeline_bind_map
*bind_map
);
1861 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1864 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1866 assert(shader
&& shader
->ref_cnt
>= 1);
1867 p_atomic_inc(&shader
->ref_cnt
);
1871 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1873 assert(shader
&& shader
->ref_cnt
>= 1);
1874 if (p_atomic_dec_zero(&shader
->ref_cnt
))
1875 anv_shader_bin_destroy(device
, shader
);
1878 struct anv_pipeline
{
1879 struct anv_device
* device
;
1880 struct anv_batch batch
;
1881 uint32_t batch_data
[512];
1882 struct anv_reloc_list batch_relocs
;
1883 uint32_t dynamic_state_mask
;
1884 struct anv_dynamic_state dynamic_state
;
1886 struct anv_subpass
* subpass
;
1887 struct anv_pipeline_layout
* layout
;
1889 bool needs_data_cache
;
1891 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1894 const struct gen_l3_config
* l3_config
;
1895 uint32_t total_size
;
1898 VkShaderStageFlags active_stages
;
1899 struct anv_state blend_state
;
1902 uint32_t binding_stride
[MAX_VBS
];
1903 bool instancing_enable
[MAX_VBS
];
1904 bool primitive_restart
;
1907 uint32_t cs_right_mask
;
1910 bool depth_test_enable
;
1911 bool writes_stencil
;
1912 bool stencil_test_enable
;
1913 bool depth_clamp_enable
;
1914 bool sample_shading_enable
;
1919 uint32_t depth_stencil_state
[3];
1925 uint32_t wm_depth_stencil
[3];
1929 uint32_t wm_depth_stencil
[4];
1932 uint32_t interface_descriptor_data
[8];
1936 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1937 gl_shader_stage stage
)
1939 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1942 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1943 static inline const struct brw_##prefix##_prog_data * \
1944 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1946 if (anv_pipeline_has_stage(pipeline, stage)) { \
1947 return (const struct brw_##prefix##_prog_data *) \
1948 pipeline->shaders[stage]->prog_data; \
1954 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1955 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
1956 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
1957 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1958 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1959 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1961 static inline const struct brw_vue_prog_data
*
1962 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
1964 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1965 return &get_gs_prog_data(pipeline
)->base
;
1966 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1967 return &get_tes_prog_data(pipeline
)->base
;
1969 return &get_vs_prog_data(pipeline
)->base
;
1973 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1974 struct anv_pipeline_cache
*cache
,
1975 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1976 const VkAllocationCallbacks
*alloc
);
1979 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1980 struct anv_pipeline_cache
*cache
,
1981 const VkComputePipelineCreateInfo
*info
,
1982 struct anv_shader_module
*module
,
1983 const char *entrypoint
,
1984 const VkSpecializationInfo
*spec_info
);
1987 enum isl_format isl_format
:16;
1988 struct isl_swizzle swizzle
;
1992 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1993 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1995 static inline enum isl_format
1996 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1997 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1999 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
2002 static inline struct isl_swizzle
2003 anv_swizzle_for_render(struct isl_swizzle swizzle
)
2005 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2006 * RGB as RGBA for texturing
2008 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
2009 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
2011 /* But it doesn't matter what we render to that channel */
2012 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
2018 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
2021 * Subsurface of an anv_image.
2023 struct anv_surface
{
2024 /** Valid only if isl_surf::size > 0. */
2025 struct isl_surf isl
;
2028 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2035 /* The original VkFormat provided by the client. This may not match any
2036 * of the actual surface formats.
2039 VkImageAspectFlags aspects
;
2042 uint32_t array_size
;
2043 uint32_t samples
; /**< VkImageCreateInfo::samples */
2044 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2045 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2050 /* Set when bound */
2052 VkDeviceSize offset
;
2057 * For each foo, anv_image::foo_surface is valid if and only if
2058 * anv_image::aspects has a foo aspect.
2060 * The hardware requires that the depth buffer and stencil buffer be
2061 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2062 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2063 * allocate the depth and stencil buffers as separate surfaces in the same
2067 struct anv_surface color_surface
;
2070 struct anv_surface depth_surface
;
2071 struct anv_surface stencil_surface
;
2076 * For color images, this is the aux usage for this image when not used as a
2079 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
2082 enum isl_aux_usage aux_usage
;
2084 struct anv_surface aux_surface
;
2087 /* Returns the number of auxiliary buffer levels attached to an image. */
2088 static inline uint8_t
2089 anv_image_aux_levels(const struct anv_image
* const image
)
2092 return image
->aux_surface
.isl
.size
> 0 ? image
->aux_surface
.isl
.levels
: 0;
2095 /* Returns the number of auxiliary buffer layers attached to an image. */
2096 static inline uint32_t
2097 anv_image_aux_layers(const struct anv_image
* const image
,
2098 const uint8_t miplevel
)
2102 /* The miplevel must exist in the main buffer. */
2103 assert(miplevel
< image
->levels
);
2105 if (miplevel
>= anv_image_aux_levels(image
)) {
2106 /* There are no layers with auxiliary data because the miplevel has no
2111 return MAX2(image
->aux_surface
.isl
.logical_level0_px
.array_len
,
2112 image
->aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
2116 static inline unsigned
2117 anv_fast_clear_state_entry_size(const struct anv_device
*device
)
2121 * +--------------------------------------------+
2122 * | clear value dword(s) | needs resolve dword |
2123 * +--------------------------------------------+
2126 /* Ensure that the needs resolve dword is in fact dword-aligned to enable
2127 * GPU memcpy operations.
2129 assert(device
->isl_dev
.ss
.clear_value_size
% 4 == 0);
2130 return device
->isl_dev
.ss
.clear_value_size
+ 4;
2133 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2135 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
2136 const VkImageAspectFlags aspect_mask
,
2137 const uint32_t samples
)
2139 /* Validate the inputs. */
2140 assert(devinfo
&& aspect_mask
&& samples
);
2141 return devinfo
->gen
>= 8 && (aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
2146 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
2147 const struct anv_image
*image
,
2148 enum blorp_hiz_op op
);
2150 anv_ccs_resolve(struct anv_cmd_buffer
* const cmd_buffer
,
2151 const struct anv_state surface_state
,
2152 const struct anv_image
* const image
,
2153 const uint8_t level
, const uint32_t layer_count
,
2154 const enum blorp_fast_clear_op op
);
2157 anv_image_fast_clear(struct anv_cmd_buffer
*cmd_buffer
,
2158 const struct anv_image
*image
,
2159 const uint32_t base_level
, const uint32_t level_count
,
2160 const uint32_t base_layer
, uint32_t layer_count
);
2163 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
2164 const struct anv_image
*image
,
2165 const VkImageAspectFlags aspects
,
2166 const VkImageLayout layout
);
2168 /* This is defined as a macro so that it works for both
2169 * VkImageSubresourceRange and VkImageSubresourceLayers
2171 #define anv_get_layerCount(_image, _range) \
2172 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2173 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2175 static inline uint32_t
2176 anv_get_levelCount(const struct anv_image
*image
,
2177 const VkImageSubresourceRange
*range
)
2179 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
2180 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
2184 struct anv_image_view
{
2185 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
2187 uint32_t offset
; /**< Offset into bo. */
2189 struct isl_view isl
;
2191 VkImageAspectFlags aspect_mask
;
2193 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2196 * RENDER_SURFACE_STATE when using image as a sampler surface with an image
2197 * layout of SHADER_READ_ONLY_OPTIMAL or DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2199 enum isl_aux_usage optimal_sampler_aux_usage
;
2200 struct anv_state optimal_sampler_surface_state
;
2203 * RENDER_SURFACE_STATE when using image as a sampler surface with an image
2204 * layout of GENERAL.
2206 enum isl_aux_usage general_sampler_aux_usage
;
2207 struct anv_state general_sampler_surface_state
;
2210 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
2211 * for write-only and readable, using the real format for write-only and the
2212 * lowered format for readable.
2214 struct anv_state storage_surface_state
;
2215 struct anv_state writeonly_storage_surface_state
;
2217 struct brw_image_param storage_image_param
;
2220 struct anv_image_create_info
{
2221 const VkImageCreateInfo
*vk_info
;
2223 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2224 isl_tiling_flags_t isl_tiling_flags
;
2229 VkResult
anv_image_create(VkDevice _device
,
2230 const struct anv_image_create_info
*info
,
2231 const VkAllocationCallbacks
* alloc
,
2234 const struct anv_surface
*
2235 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
2236 VkImageAspectFlags aspect_mask
);
2239 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
2241 static inline struct VkExtent3D
2242 anv_sanitize_image_extent(const VkImageType imageType
,
2243 const struct VkExtent3D imageExtent
)
2245 switch (imageType
) {
2246 case VK_IMAGE_TYPE_1D
:
2247 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2248 case VK_IMAGE_TYPE_2D
:
2249 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2250 case VK_IMAGE_TYPE_3D
:
2253 unreachable("invalid image type");
2257 static inline struct VkOffset3D
2258 anv_sanitize_image_offset(const VkImageType imageType
,
2259 const struct VkOffset3D imageOffset
)
2261 switch (imageType
) {
2262 case VK_IMAGE_TYPE_1D
:
2263 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2264 case VK_IMAGE_TYPE_2D
:
2265 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2266 case VK_IMAGE_TYPE_3D
:
2269 unreachable("invalid image type");
2274 void anv_fill_buffer_surface_state(struct anv_device
*device
,
2275 struct anv_state state
,
2276 enum isl_format format
,
2277 uint32_t offset
, uint32_t range
,
2280 struct anv_sampler
{
2284 struct anv_framebuffer
{
2289 uint32_t attachment_count
;
2290 struct anv_image_view
* attachments
[0];
2293 struct anv_subpass
{
2294 uint32_t attachment_count
;
2297 * A pointer to all attachment references used in this subpass.
2298 * Only valid if ::attachment_count > 0.
2300 VkAttachmentReference
* attachments
;
2301 uint32_t input_count
;
2302 VkAttachmentReference
* input_attachments
;
2303 uint32_t color_count
;
2304 VkAttachmentReference
* color_attachments
;
2305 VkAttachmentReference
* resolve_attachments
;
2307 VkAttachmentReference depth_stencil_attachment
;
2311 /** Subpass has a depth/stencil self-dependency */
2312 bool has_ds_self_dep
;
2314 /** Subpass has at least one resolve attachment */
2318 static inline unsigned
2319 anv_subpass_view_count(const struct anv_subpass
*subpass
)
2321 return MAX2(1, _mesa_bitcount(subpass
->view_mask
));
2324 struct anv_render_pass_attachment
{
2325 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2326 * its members individually.
2330 VkImageUsageFlags usage
;
2331 VkAttachmentLoadOp load_op
;
2332 VkAttachmentStoreOp store_op
;
2333 VkAttachmentLoadOp stencil_load_op
;
2334 VkImageLayout initial_layout
;
2335 VkImageLayout final_layout
;
2336 VkImageLayout first_subpass_layout
;
2338 /* The subpass id in which the attachment will be used last. */
2339 uint32_t last_subpass_idx
;
2342 struct anv_render_pass
{
2343 uint32_t attachment_count
;
2344 uint32_t subpass_count
;
2345 /* An array of subpass_count+1 flushes, one per subpass boundary */
2346 enum anv_pipe_bits
* subpass_flushes
;
2347 struct anv_render_pass_attachment
* attachments
;
2348 struct anv_subpass subpasses
[0];
2351 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2353 struct anv_query_pool
{
2355 VkQueryPipelineStatisticFlags pipeline_statistics
;
2356 /** Stride between slots, in bytes */
2358 /** Number of slots in this query pool */
2363 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
2366 void anv_dump_image_to_ppm(struct anv_device
*device
,
2367 struct anv_image
*image
, unsigned miplevel
,
2368 unsigned array_layer
, VkImageAspectFlagBits aspect
,
2369 const char *filename
);
2371 enum anv_dump_action
{
2372 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
2375 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
2376 void anv_dump_finish(void);
2378 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
2379 struct anv_framebuffer
*fb
);
2381 static inline uint32_t
2382 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
2384 /* This function must be called from within a subpass. */
2385 assert(cmd_state
->pass
&& cmd_state
->subpass
);
2387 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
2389 /* The id of this subpass shouldn't exceed the number of subpasses in this
2390 * render pass minus 1.
2392 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
2396 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2398 static inline struct __anv_type * \
2399 __anv_type ## _from_handle(__VkType _handle) \
2401 return (struct __anv_type *) _handle; \
2404 static inline __VkType \
2405 __anv_type ## _to_handle(struct __anv_type *_obj) \
2407 return (__VkType) _obj; \
2410 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2412 static inline struct __anv_type * \
2413 __anv_type ## _from_handle(__VkType _handle) \
2415 return (struct __anv_type *)(uintptr_t) _handle; \
2418 static inline __VkType \
2419 __anv_type ## _to_handle(struct __anv_type *_obj) \
2421 return (__VkType)(uintptr_t) _obj; \
2424 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2425 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2427 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
2428 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
2429 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
2430 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
2431 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
2433 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
2434 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
2435 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
2436 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
2437 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
2438 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
2439 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
2440 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
2441 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
2442 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
2443 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
2444 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
2445 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
2446 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
2447 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
2448 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
2449 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
2450 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
2451 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
2452 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
2453 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
2455 /* Gen-specific function declarations */
2457 # include "anv_genX.h"
2459 # define genX(x) gen7_##x
2460 # include "anv_genX.h"
2462 # define genX(x) gen75_##x
2463 # include "anv_genX.h"
2465 # define genX(x) gen8_##x
2466 # include "anv_genX.h"
2468 # define genX(x) gen9_##x
2469 # include "anv_genX.h"
2471 # define genX(x) gen10_##x
2472 # include "anv_genX.h"
2476 #endif /* ANV_PRIVATE_H */