2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
52 /* Pre-declarations needed for WSI entrypoints */
55 typedef struct xcb_connection_t xcb_connection_t
;
56 typedef uint32_t xcb_visualid_t
;
57 typedef uint32_t xcb_window_t
;
61 #include <vulkan/vulkan.h>
62 #include <vulkan/vulkan_intel.h>
63 #include <vulkan/vk_icd.h>
65 #include "anv_entrypoints.h"
66 #include "brw_context.h"
69 #include "wsi_common.h"
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
83 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
85 #define anv_noreturn __attribute__((__noreturn__))
86 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
88 static inline uint32_t
89 align_down_npot_u32(uint32_t v
, uint32_t a
)
94 static inline uint32_t
95 align_u32(uint32_t v
, uint32_t a
)
97 assert(a
!= 0 && a
== (a
& -a
));
98 return (v
+ a
- 1) & ~(a
- 1);
101 static inline uint64_t
102 align_u64(uint64_t v
, uint64_t a
)
104 assert(a
!= 0 && a
== (a
& -a
));
105 return (v
+ a
- 1) & ~(a
- 1);
108 static inline int32_t
109 align_i32(int32_t v
, int32_t a
)
111 assert(a
!= 0 && a
== (a
& -a
));
112 return (v
+ a
- 1) & ~(a
- 1);
115 /** Alignment must be a power of 2. */
117 anv_is_aligned(uintmax_t n
, uintmax_t a
)
119 assert(a
== (a
& -a
));
120 return (n
& (a
- 1)) == 0;
123 static inline uint32_t
124 anv_minify(uint32_t n
, uint32_t levels
)
126 if (unlikely(n
== 0))
129 return MAX2(n
>> levels
, 1);
133 anv_clamp_f(float f
, float min
, float max
)
146 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
148 if (*inout_mask
& clear_mask
) {
149 *inout_mask
&= ~clear_mask
;
156 static inline union isl_color_value
157 vk_to_isl_color(VkClearColorValue color
)
159 return (union isl_color_value
) {
169 #define for_each_bit(b, dword) \
170 for (uint32_t __dword = (dword); \
171 (b) = __builtin_ffs(__dword) - 1, __dword; \
172 __dword &= ~(1 << (b)))
174 #define typed_memcpy(dest, src, count) ({ \
175 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
176 memcpy((dest), (src), (count) * sizeof(*(src))); \
179 /* Whenever we generate an error, pass it through this function. Useful for
180 * debugging, where we can break on it. Only call at error site, not when
181 * propagating errors. Might be useful to plug in a stack trace here.
184 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
187 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
188 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
190 #define vk_error(error) error
191 #define vk_errorf(error, format, ...) error
194 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
195 anv_printflike(3, 4);
196 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
197 void anv_loge_v(const char *format
, va_list va
);
200 * Print a FINISHME message, including its source location.
202 #define anv_finishme(format, ...) \
204 static bool reported = false; \
206 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
211 /* A non-fatal assert. Useful for debugging. */
213 #define anv_assert(x) ({ \
214 if (unlikely(!(x))) \
215 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
218 #define anv_assert(x)
222 * If a block of code is annotated with anv_validate, then the block runs only
226 #define anv_validate if (1)
228 #define anv_validate if (0)
231 void anv_abortf(const char *format
, ...) anv_noreturn
anv_printflike(1, 2);
232 void anv_abortfv(const char *format
, va_list va
) anv_noreturn
;
234 #define stub_return(v) \
236 anv_finishme("stub %s", __func__); \
242 anv_finishme("stub %s", __func__); \
247 * A dynamically growable, circular buffer. Elements are added at head and
248 * removed from tail. head and tail are free-running uint32_t indices and we
249 * only compute the modulo with size when accessing the array. This way,
250 * number of bytes in the queue is always head - tail, even in case of
257 /* Index into the current validation list. This is used by the
258 * validation list building alrogithm to track which buffers are already
259 * in the validation list so that we can ensure uniqueness.
263 /* Last known offset. This value is provided by the kernel when we
264 * execbuf and is used as the presumed offset for the next bunch of
272 /* We need to set the WRITE flag on winsys bos so GEM will know we're
273 * writing to them and synchronize uses on other rings (eg if the display
274 * server uses the blitter ring).
280 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
282 bo
->gem_handle
= gem_handle
;
287 bo
->is_winsys_bo
= false;
290 /* Represents a lock-free linked list of "free" things. This is used by
291 * both the block pool and the state pools. Unfortunately, in order to
292 * solve the ABA problem, we can't use a single uint32_t head.
294 union anv_free_list
{
298 /* A simple count that is incremented every time the head changes. */
304 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
306 struct anv_block_state
{
316 struct anv_block_pool
{
317 struct anv_device
*device
;
321 /* The offset from the start of the bo to the "center" of the block
322 * pool. Pointers to allocated blocks are given by
323 * bo.map + center_bo_offset + offsets.
325 uint32_t center_bo_offset
;
327 /* Current memory map of the block pool. This pointer may or may not
328 * point to the actual beginning of the block pool memory. If
329 * anv_block_pool_alloc_back has ever been called, then this pointer
330 * will point to the "center" position of the buffer and all offsets
331 * (negative or positive) given out by the block pool alloc functions
332 * will be valid relative to this pointer.
334 * In particular, map == bo.map + center_offset
340 * Array of mmaps and gem handles owned by the block pool, reclaimed when
341 * the block pool is destroyed.
343 struct u_vector mmap_cleanups
;
347 union anv_free_list free_list
;
348 struct anv_block_state state
;
350 union anv_free_list back_free_list
;
351 struct anv_block_state back_state
;
354 /* Block pools are backed by a fixed-size 2GB memfd */
355 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
357 /* The center of the block pool is also the middle of the memfd. This may
358 * change in the future if we decide differently for some reason.
360 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
362 static inline uint32_t
363 anv_block_pool_size(struct anv_block_pool
*pool
)
365 return pool
->state
.end
+ pool
->back_state
.end
;
374 struct anv_fixed_size_state_pool
{
376 union anv_free_list free_list
;
377 struct anv_block_state block
;
380 #define ANV_MIN_STATE_SIZE_LOG2 6
381 #define ANV_MAX_STATE_SIZE_LOG2 17
383 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
385 struct anv_state_pool
{
386 struct anv_block_pool
*block_pool
;
387 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
390 struct anv_state_stream_block
;
392 struct anv_state_stream
{
393 struct anv_block_pool
*block_pool
;
395 /* The current working block */
396 struct anv_state_stream_block
*block
;
398 /* Offset at which the current block starts */
400 /* Offset at which to allocate the next state */
402 /* Offset at which the current block ends */
406 #define CACHELINE_SIZE 64
407 #define CACHELINE_MASK 63
410 anv_clflush_range(void *start
, size_t size
)
412 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
413 void *end
= start
+ size
;
415 __builtin_ia32_mfence();
417 __builtin_ia32_clflush(p
);
423 anv_state_clflush(struct anv_state state
)
425 anv_clflush_range(state
.map
, state
.alloc_size
);
428 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
429 struct anv_device
*device
, uint32_t block_size
);
430 void anv_block_pool_finish(struct anv_block_pool
*pool
);
431 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
);
432 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
);
433 void anv_block_pool_free(struct anv_block_pool
*pool
, int32_t offset
);
434 void anv_state_pool_init(struct anv_state_pool
*pool
,
435 struct anv_block_pool
*block_pool
);
436 void anv_state_pool_finish(struct anv_state_pool
*pool
);
437 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
438 size_t state_size
, size_t alignment
);
439 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
440 void anv_state_stream_init(struct anv_state_stream
*stream
,
441 struct anv_block_pool
*block_pool
);
442 void anv_state_stream_finish(struct anv_state_stream
*stream
);
443 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
444 uint32_t size
, uint32_t alignment
);
447 * Implements a pool of re-usable BOs. The interface is identical to that
448 * of block_pool except that each block is its own BO.
451 struct anv_device
*device
;
456 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
457 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
458 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
460 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
462 struct anv_scratch_bo
{
467 struct anv_scratch_pool
{
468 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
469 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
472 void anv_scratch_pool_init(struct anv_device
*device
,
473 struct anv_scratch_pool
*pool
);
474 void anv_scratch_pool_finish(struct anv_device
*device
,
475 struct anv_scratch_pool
*pool
);
476 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
477 struct anv_scratch_pool
*pool
,
478 gl_shader_stage stage
,
479 unsigned per_thread_scratch
);
481 extern struct anv_dispatch_table dtable
;
483 #define VK_ICD_WSI_PLATFORM_MAX 5
485 struct anv_physical_device
{
486 VK_LOADER_DATA _loader_data
;
488 struct anv_instance
* instance
;
492 struct gen_device_info info
;
493 uint64_t aperture_size
;
494 struct brw_compiler
* compiler
;
495 struct isl_device isl_dev
;
496 int cmd_parser_version
;
499 uint32_t subslice_total
;
501 uint8_t uuid
[VK_UUID_SIZE
];
503 struct wsi_device wsi_device
;
506 struct anv_instance
{
507 VK_LOADER_DATA _loader_data
;
509 VkAllocationCallbacks alloc
;
512 int physicalDeviceCount
;
513 struct anv_physical_device physicalDevice
;
516 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
517 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
520 VK_LOADER_DATA _loader_data
;
522 struct anv_device
* device
;
524 struct anv_state_pool
* pool
;
527 struct anv_pipeline_cache
{
528 struct anv_device
* device
;
529 pthread_mutex_t mutex
;
531 struct hash_table
* cache
;
534 struct anv_pipeline_bind_map
;
536 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
537 struct anv_device
*device
,
539 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
541 struct anv_shader_bin
*
542 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
543 const void *key
, uint32_t key_size
);
544 struct anv_shader_bin
*
545 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
546 const void *key_data
, uint32_t key_size
,
547 const void *kernel_data
, uint32_t kernel_size
,
548 const struct brw_stage_prog_data
*prog_data
,
549 uint32_t prog_data_size
,
550 const struct anv_pipeline_bind_map
*bind_map
);
553 VK_LOADER_DATA _loader_data
;
555 VkAllocationCallbacks alloc
;
557 struct anv_instance
* instance
;
559 struct gen_device_info info
;
560 struct isl_device isl_dev
;
563 bool can_chain_batches
;
564 bool robust_buffer_access
;
566 struct anv_bo_pool batch_bo_pool
;
568 struct anv_block_pool dynamic_state_block_pool
;
569 struct anv_state_pool dynamic_state_pool
;
571 struct anv_block_pool instruction_block_pool
;
572 struct anv_state_pool instruction_state_pool
;
574 struct anv_block_pool surface_state_block_pool
;
575 struct anv_state_pool surface_state_pool
;
577 struct anv_bo workaround_bo
;
579 struct anv_pipeline_cache blorp_shader_cache
;
580 struct blorp_context blorp
;
582 struct anv_state border_colors
;
584 struct anv_queue queue
;
586 struct anv_scratch_pool scratch_pool
;
588 uint32_t default_mocs
;
590 pthread_mutex_t mutex
;
591 pthread_cond_t queue_submit
;
594 void anv_device_init_blorp(struct anv_device
*device
);
595 void anv_device_finish_blorp(struct anv_device
*device
);
597 VkResult
anv_device_execbuf(struct anv_device
*device
,
598 struct drm_i915_gem_execbuffer2
*execbuf
,
599 struct anv_bo
**execbuf_bos
);
601 void* anv_gem_mmap(struct anv_device
*device
,
602 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
603 void anv_gem_munmap(void *p
, uint64_t size
);
604 uint32_t anv_gem_create(struct anv_device
*device
, size_t size
);
605 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
606 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
607 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
608 int anv_gem_execbuffer(struct anv_device
*device
,
609 struct drm_i915_gem_execbuffer2
*execbuf
);
610 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
611 uint32_t stride
, uint32_t tiling
);
612 int anv_gem_create_context(struct anv_device
*device
);
613 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
614 int anv_gem_get_param(int fd
, uint32_t param
);
615 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
616 int anv_gem_get_aperture(int fd
, uint64_t *size
);
617 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
618 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
619 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
620 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
621 uint32_t read_domains
, uint32_t write_domain
);
623 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
625 struct anv_reloc_list
{
628 struct drm_i915_gem_relocation_entry
* relocs
;
629 struct anv_bo
** reloc_bos
;
632 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
633 const VkAllocationCallbacks
*alloc
);
634 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
635 const VkAllocationCallbacks
*alloc
);
637 uint64_t anv_reloc_list_add(struct anv_reloc_list
*list
,
638 const VkAllocationCallbacks
*alloc
,
639 uint32_t offset
, struct anv_bo
*target_bo
,
642 struct anv_batch_bo
{
643 /* Link in the anv_cmd_buffer.owned_batch_bos list */
644 struct list_head link
;
648 /* Bytes actually consumed in this batch BO */
651 struct anv_reloc_list relocs
;
655 const VkAllocationCallbacks
* alloc
;
661 struct anv_reloc_list
* relocs
;
663 /* This callback is called (with the associated user data) in the event
664 * that the batch runs out of space.
666 VkResult (*extend_cb
)(struct anv_batch
*, void *);
670 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
671 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
672 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
673 void *location
, struct anv_bo
*bo
, uint32_t offset
);
674 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
675 struct anv_batch
*batch
);
682 static inline uint64_t
683 _anv_combine_address(struct anv_batch
*batch
, void *location
,
684 const struct anv_address address
, uint32_t delta
)
686 if (address
.bo
== NULL
) {
687 return address
.offset
+ delta
;
689 assert(batch
->start
<= location
&& location
< batch
->end
);
691 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
695 #define __gen_address_type struct anv_address
696 #define __gen_user_data struct anv_batch
697 #define __gen_combine_address _anv_combine_address
699 /* Wrapper macros needed to work around preprocessor argument issues. In
700 * particular, arguments don't get pre-evaluated if they are concatenated.
701 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
702 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
703 * We can work around this easily enough with these helpers.
705 #define __anv_cmd_length(cmd) cmd ## _length
706 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
707 #define __anv_cmd_header(cmd) cmd ## _header
708 #define __anv_cmd_pack(cmd) cmd ## _pack
709 #define __anv_reg_num(reg) reg ## _num
711 #define anv_pack_struct(dst, struc, ...) do { \
712 struct struc __template = { \
715 __anv_cmd_pack(struc)(NULL, dst, &__template); \
716 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
719 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
720 void *__dst = anv_batch_emit_dwords(batch, n); \
721 struct cmd __template = { \
722 __anv_cmd_header(cmd), \
723 .DWordLength = n - __anv_cmd_length_bias(cmd), \
726 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
730 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
734 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
735 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
736 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
737 dw[i] = (dwords0)[i] | (dwords1)[i]; \
738 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
741 #define anv_batch_emit(batch, cmd, name) \
742 for (struct cmd name = { __anv_cmd_header(cmd) }, \
743 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
744 __builtin_expect(_dst != NULL, 1); \
745 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
746 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
750 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
751 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
752 struct anv_state __state = \
753 anv_state_pool_alloc((pool), __size, align); \
754 struct cmd __template = { \
757 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
758 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
759 if (!(pool)->block_pool->device->info.has_llc) \
760 anv_state_clflush(__state); \
764 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
765 .GraphicsDataTypeGFDT = 0, \
766 .LLCCacheabilityControlLLCCC = 0, \
767 .L3CacheabilityControlL3CC = 1, \
770 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
771 .LLCeLLCCacheabilityControlLLCCC = 0, \
772 .L3CacheabilityControlL3CC = 1, \
775 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
776 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
777 .TargetCache = L3DefertoPATforLLCeLLCselection, \
781 /* Skylake: MOCS is now an index into an array of 62 different caching
782 * configurations programmed by the kernel.
785 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
786 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
787 .IndextoMOCSTables = 2 \
790 #define GEN9_MOCS_PTE { \
791 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
792 .IndextoMOCSTables = 1 \
795 struct anv_device_memory
{
798 VkDeviceSize map_size
;
803 * Header for Vertex URB Entry (VUE)
805 struct anv_vue_header
{
807 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
808 uint32_t ViewportIndex
;
812 struct anv_descriptor_set_binding_layout
{
814 /* The type of the descriptors in this binding */
815 VkDescriptorType type
;
818 /* Number of array elements in this binding */
821 /* Index into the flattend descriptor set */
822 uint16_t descriptor_index
;
824 /* Index into the dynamic state array for a dynamic buffer */
825 int16_t dynamic_offset_index
;
827 /* Index into the descriptor set buffer views */
828 int16_t buffer_index
;
831 /* Index into the binding table for the associated surface */
832 int16_t surface_index
;
834 /* Index into the sampler table for the associated sampler */
835 int16_t sampler_index
;
837 /* Index into the image table for the associated image */
839 } stage
[MESA_SHADER_STAGES
];
841 /* Immutable samplers (or NULL if no immutable samplers) */
842 struct anv_sampler
**immutable_samplers
;
845 struct anv_descriptor_set_layout
{
846 /* Number of bindings in this descriptor set */
847 uint16_t binding_count
;
849 /* Total size of the descriptor set with room for all array entries */
852 /* Shader stages affected by this descriptor set */
853 uint16_t shader_stages
;
855 /* Number of buffers in this descriptor set */
856 uint16_t buffer_count
;
858 /* Number of dynamic offsets used by this descriptor set */
859 uint16_t dynamic_offset_count
;
861 /* Bindings in this descriptor set */
862 struct anv_descriptor_set_binding_layout binding
[0];
865 struct anv_descriptor
{
866 VkDescriptorType type
;
870 struct anv_image_view
*image_view
;
871 struct anv_sampler
*sampler
;
874 struct anv_buffer_view
*buffer_view
;
878 struct anv_descriptor_set
{
879 const struct anv_descriptor_set_layout
*layout
;
881 uint32_t buffer_count
;
882 struct anv_buffer_view
*buffer_views
;
883 struct anv_descriptor descriptors
[0];
886 struct anv_descriptor_pool
{
891 struct anv_state_stream surface_state_stream
;
892 void *surface_state_free_list
;
898 anv_descriptor_set_create(struct anv_device
*device
,
899 struct anv_descriptor_pool
*pool
,
900 const struct anv_descriptor_set_layout
*layout
,
901 struct anv_descriptor_set
**out_set
);
904 anv_descriptor_set_destroy(struct anv_device
*device
,
905 struct anv_descriptor_pool
*pool
,
906 struct anv_descriptor_set
*set
);
908 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
910 struct anv_pipeline_binding
{
911 /* The descriptor set this surface corresponds to. The special value of
912 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
913 * to a color attachment and not a regular descriptor.
917 /* Binding in the descriptor set */
920 /* Index in the binding */
923 /* Input attachment index (relative to the subpass) */
924 uint8_t input_attachment_index
;
927 struct anv_pipeline_layout
{
929 struct anv_descriptor_set_layout
*layout
;
930 uint32_t dynamic_offset_start
;
936 bool has_dynamic_offsets
;
937 } stage
[MESA_SHADER_STAGES
];
939 unsigned char sha1
[20];
943 struct anv_device
* device
;
946 VkBufferUsageFlags usage
;
953 enum anv_cmd_dirty_bits
{
954 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
955 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
956 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
957 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
958 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
959 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
960 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
961 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
962 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
963 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
964 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
965 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
966 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
968 typedef uint32_t anv_cmd_dirty_mask_t
;
971 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
972 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
973 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
974 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
975 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
976 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
977 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
978 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
979 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
980 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
981 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
983 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
984 * a flush has happened but not a CS stall. The next time we do any sort
985 * of invalidation we need to insert a CS stall at that time. Otherwise,
986 * we would have to CS stall on every flush which could be bad.
988 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
991 #define ANV_PIPE_FLUSH_BITS ( \
992 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
993 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
994 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
996 #define ANV_PIPE_STALL_BITS ( \
997 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
998 ANV_PIPE_DEPTH_STALL_BIT | \
999 ANV_PIPE_CS_STALL_BIT)
1001 #define ANV_PIPE_INVALIDATE_BITS ( \
1002 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1003 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1004 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1005 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1006 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1007 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1009 struct anv_vertex_binding
{
1010 struct anv_buffer
* buffer
;
1011 VkDeviceSize offset
;
1014 struct anv_push_constants
{
1015 /* Current allocated size of this push constants data structure.
1016 * Because a decent chunk of it may not be used (images on SKL, for
1017 * instance), we won't actually allocate the entire structure up-front.
1021 /* Push constant data provided by the client through vkPushConstants */
1022 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1024 /* Our hardware only provides zero-based vertex and instance id so, in
1025 * order to satisfy the vulkan requirements, we may have to push one or
1026 * both of these into the shader.
1028 uint32_t base_vertex
;
1029 uint32_t base_instance
;
1031 /* Offsets and ranges for dynamically bound buffers */
1035 } dynamic
[MAX_DYNAMIC_BUFFERS
];
1037 /* Image data for image_load_store on pre-SKL */
1038 struct brw_image_param images
[MAX_IMAGES
];
1041 struct anv_dynamic_state
{
1044 VkViewport viewports
[MAX_VIEWPORTS
];
1049 VkRect2D scissors
[MAX_SCISSORS
];
1060 float blend_constants
[4];
1070 } stencil_compare_mask
;
1075 } stencil_write_mask
;
1080 } stencil_reference
;
1083 extern const struct anv_dynamic_state default_dynamic_state
;
1085 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1086 const struct anv_dynamic_state
*src
,
1087 uint32_t copy_mask
);
1090 * Attachment state when recording a renderpass instance.
1092 * The clear value is valid only if there exists a pending clear.
1094 struct anv_attachment_state
{
1095 enum isl_aux_usage aux_usage
;
1096 enum isl_aux_usage input_aux_usage
;
1097 struct anv_state color_rt_state
;
1098 struct anv_state input_att_state
;
1100 VkImageAspectFlags pending_clear_aspects
;
1102 VkClearValue clear_value
;
1103 bool clear_color_is_zero_one
;
1106 /** State required while building cmd buffer */
1107 struct anv_cmd_state
{
1108 /* PIPELINE_SELECT.PipelineSelection */
1109 uint32_t current_pipeline
;
1110 const struct gen_l3_config
* current_l3_config
;
1112 anv_cmd_dirty_mask_t dirty
;
1113 anv_cmd_dirty_mask_t compute_dirty
;
1114 enum anv_pipe_bits pending_pipe_bits
;
1115 uint32_t num_workgroups_offset
;
1116 struct anv_bo
*num_workgroups_bo
;
1117 VkShaderStageFlags descriptors_dirty
;
1118 VkShaderStageFlags push_constants_dirty
;
1119 uint32_t scratch_size
;
1120 struct anv_pipeline
* pipeline
;
1121 struct anv_pipeline
* compute_pipeline
;
1122 struct anv_framebuffer
* framebuffer
;
1123 struct anv_render_pass
* pass
;
1124 struct anv_subpass
* subpass
;
1125 VkRect2D render_area
;
1126 uint32_t restart_index
;
1127 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1128 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1129 VkShaderStageFlags push_constant_stages
;
1130 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1131 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1132 struct anv_state samplers
[MESA_SHADER_STAGES
];
1133 struct anv_dynamic_state dynamic
;
1137 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1138 * valid only when recording a render pass instance.
1140 struct anv_attachment_state
* attachments
;
1143 * Surface states for color render targets. These are stored in a single
1144 * flat array. For depth-stencil attachments, the surface state is simply
1147 struct anv_state render_pass_states
;
1150 * A null surface state of the right size to match the framebuffer. This
1151 * is one of the states in render_pass_states.
1153 struct anv_state null_surface_state
;
1156 struct anv_buffer
* index_buffer
;
1157 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1158 uint32_t index_offset
;
1162 struct anv_cmd_pool
{
1163 VkAllocationCallbacks alloc
;
1164 struct list_head cmd_buffers
;
1167 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1169 enum anv_cmd_buffer_exec_mode
{
1170 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1171 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1172 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1173 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1174 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1177 struct anv_cmd_buffer
{
1178 VK_LOADER_DATA _loader_data
;
1180 struct anv_device
* device
;
1182 struct anv_cmd_pool
* pool
;
1183 struct list_head pool_link
;
1185 struct anv_batch batch
;
1187 /* Fields required for the actual chain of anv_batch_bo's.
1189 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1191 struct list_head batch_bos
;
1192 enum anv_cmd_buffer_exec_mode exec_mode
;
1194 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1195 * referenced by this command buffer
1197 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1199 struct u_vector seen_bbos
;
1201 /* A vector of int32_t's for every block of binding tables.
1203 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1205 struct u_vector bt_blocks
;
1208 struct anv_reloc_list surface_relocs
;
1209 /** Last seen surface state block pool center bo offset */
1210 uint32_t last_ss_pool_center
;
1212 /* Serial for tracking buffer completion */
1215 /* Stream objects for storing temporary data */
1216 struct anv_state_stream surface_state_stream
;
1217 struct anv_state_stream dynamic_state_stream
;
1219 VkCommandBufferUsageFlags usage_flags
;
1220 VkCommandBufferLevel level
;
1222 struct anv_cmd_state state
;
1225 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1226 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1227 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1228 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1229 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1230 struct anv_cmd_buffer
*secondary
);
1231 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1232 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1233 struct anv_cmd_buffer
*cmd_buffer
);
1235 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1238 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1239 gl_shader_stage stage
, uint32_t size
);
1240 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1241 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1242 (offsetof(struct anv_push_constants, field) + \
1243 sizeof(cmd_buffer->state.push_constants[0]->field)))
1245 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1246 const void *data
, uint32_t size
, uint32_t alignment
);
1247 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1248 uint32_t *a
, uint32_t *b
,
1249 uint32_t dwords
, uint32_t alignment
);
1252 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1254 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1255 uint32_t entries
, uint32_t *state_offset
);
1257 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1259 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1260 uint32_t size
, uint32_t alignment
);
1263 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1265 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1266 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1267 bool depth_clamp_enable
);
1268 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1270 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1271 struct anv_render_pass
*pass
,
1272 struct anv_framebuffer
*framebuffer
,
1273 const VkClearValue
*clear_values
);
1275 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1278 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1279 gl_shader_stage stage
);
1281 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1283 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1284 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1286 const struct anv_image_view
*
1287 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1290 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1291 uint32_t num_entries
,
1292 uint32_t *state_offset
);
1294 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1296 enum anv_fence_state
{
1297 /** Indicates that this is a new (or newly reset fence) */
1298 ANV_FENCE_STATE_RESET
,
1300 /** Indicates that this fence has been submitted to the GPU but is still
1301 * (as far as we know) in use by the GPU.
1303 ANV_FENCE_STATE_SUBMITTED
,
1305 ANV_FENCE_STATE_SIGNALED
,
1310 struct drm_i915_gem_execbuffer2 execbuf
;
1311 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1312 enum anv_fence_state state
;
1317 struct anv_state state
;
1320 struct anv_shader_module
{
1321 unsigned char sha1
[20];
1326 void anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
1327 struct anv_shader_module
*module
,
1328 const char *entrypoint
,
1329 const struct anv_pipeline_layout
*pipeline_layout
,
1330 const VkSpecializationInfo
*spec_info
);
1332 static inline gl_shader_stage
1333 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1335 assert(__builtin_popcount(vk_stage
) == 1);
1336 return ffs(vk_stage
) - 1;
1339 static inline VkShaderStageFlagBits
1340 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1342 return (1 << mesa_stage
);
1345 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1347 #define anv_foreach_stage(stage, stage_bits) \
1348 for (gl_shader_stage stage, \
1349 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1350 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1351 __tmp &= ~(1 << (stage)))
1353 struct anv_pipeline_bind_map
{
1354 uint32_t surface_count
;
1355 uint32_t sampler_count
;
1356 uint32_t image_count
;
1358 struct anv_pipeline_binding
* surface_to_descriptor
;
1359 struct anv_pipeline_binding
* sampler_to_descriptor
;
1362 struct anv_shader_bin_key
{
1367 struct anv_shader_bin
{
1370 const struct anv_shader_bin_key
*key
;
1372 struct anv_state kernel
;
1373 uint32_t kernel_size
;
1375 const struct brw_stage_prog_data
*prog_data
;
1376 uint32_t prog_data_size
;
1378 struct anv_pipeline_bind_map bind_map
;
1380 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1383 struct anv_shader_bin
*
1384 anv_shader_bin_create(struct anv_device
*device
,
1385 const void *key
, uint32_t key_size
,
1386 const void *kernel
, uint32_t kernel_size
,
1387 const struct brw_stage_prog_data
*prog_data
,
1388 uint32_t prog_data_size
, const void *prog_data_param
,
1389 const struct anv_pipeline_bind_map
*bind_map
);
1392 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1395 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1397 assert(shader
->ref_cnt
>= 1);
1398 __sync_fetch_and_add(&shader
->ref_cnt
, 1);
1402 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1404 assert(shader
->ref_cnt
>= 1);
1405 if (__sync_fetch_and_add(&shader
->ref_cnt
, -1) == 1)
1406 anv_shader_bin_destroy(device
, shader
);
1409 struct anv_pipeline
{
1410 struct anv_device
* device
;
1411 struct anv_batch batch
;
1412 uint32_t batch_data
[512];
1413 struct anv_reloc_list batch_relocs
;
1414 uint32_t dynamic_state_mask
;
1415 struct anv_dynamic_state dynamic_state
;
1417 struct anv_pipeline_layout
* layout
;
1419 bool needs_data_cache
;
1421 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1424 const struct gen_l3_config
* l3_config
;
1425 uint32_t total_size
;
1428 VkShaderStageFlags active_stages
;
1429 struct anv_state blend_state
;
1432 uint32_t binding_stride
[MAX_VBS
];
1433 bool instancing_enable
[MAX_VBS
];
1434 bool primitive_restart
;
1437 uint32_t cs_right_mask
;
1439 bool depth_clamp_enable
;
1443 uint32_t depth_stencil_state
[3];
1449 uint32_t wm_depth_stencil
[3];
1453 uint32_t wm_depth_stencil
[4];
1456 uint32_t interface_descriptor_data
[8];
1460 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1461 gl_shader_stage stage
)
1463 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1466 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1467 static inline const struct brw_##prefix##_prog_data * \
1468 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1470 if (anv_pipeline_has_stage(pipeline, stage)) { \
1471 return (const struct brw_##prefix##_prog_data *) \
1472 pipeline->shaders[stage]->prog_data; \
1478 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1479 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
1480 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
1481 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1482 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1483 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1486 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1487 struct anv_pipeline_cache
*cache
,
1488 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1489 const VkAllocationCallbacks
*alloc
);
1492 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1493 struct anv_pipeline_cache
*cache
,
1494 const VkComputePipelineCreateInfo
*info
,
1495 struct anv_shader_module
*module
,
1496 const char *entrypoint
,
1497 const VkSpecializationInfo
*spec_info
);
1500 enum isl_format isl_format
:16;
1501 struct isl_swizzle swizzle
;
1505 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1506 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1508 static inline enum isl_format
1509 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1510 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1512 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1516 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
1519 * Subsurface of an anv_image.
1521 struct anv_surface
{
1522 /** Valid only if isl_surf::size > 0. */
1523 struct isl_surf isl
;
1526 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1533 /* The original VkFormat provided by the client. This may not match any
1534 * of the actual surface formats.
1537 VkImageAspectFlags aspects
;
1540 uint32_t array_size
;
1541 uint32_t samples
; /**< VkImageCreateInfo::samples */
1542 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1543 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1548 /* Set when bound */
1550 VkDeviceSize offset
;
1555 * For each foo, anv_image::foo_surface is valid if and only if
1556 * anv_image::aspects has a foo aspect.
1558 * The hardware requires that the depth buffer and stencil buffer be
1559 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1560 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1561 * allocate the depth and stencil buffers as separate surfaces in the same
1565 struct anv_surface color_surface
;
1568 struct anv_surface depth_surface
;
1569 struct anv_surface stencil_surface
;
1573 /** The aux usage for this surface when outside a render pass */
1574 enum isl_aux_usage aux_usage
;
1576 struct anv_surface aux_surface
;
1579 static inline uint32_t
1580 anv_get_layerCount(const struct anv_image
*image
,
1581 const VkImageSubresourceRange
*range
)
1583 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1584 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1587 static inline uint32_t
1588 anv_get_levelCount(const struct anv_image
*image
,
1589 const VkImageSubresourceRange
*range
)
1591 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1592 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1596 struct anv_image_view
{
1597 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
1599 uint32_t offset
; /**< Offset into bo. */
1601 struct isl_view isl
;
1603 VkImageAspectFlags aspect_mask
;
1605 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1607 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1608 struct anv_state sampler_surface_state
;
1610 /** RENDER_SURFACE_STATE when using image as a storage image. */
1611 struct anv_state storage_surface_state
;
1613 struct brw_image_param storage_image_param
;
1616 struct anv_image_create_info
{
1617 const VkImageCreateInfo
*vk_info
;
1619 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1620 isl_tiling_flags_t isl_tiling_flags
;
1625 VkResult
anv_image_create(VkDevice _device
,
1626 const struct anv_image_create_info
*info
,
1627 const VkAllocationCallbacks
* alloc
,
1630 const struct anv_surface
*
1631 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1632 VkImageAspectFlags aspect_mask
);
1635 anv_image_has_hiz(const struct anv_image
*image
)
1637 /* We must check the aspect because anv_image::aux_surface may be used for
1638 * any type of auxiliary surface, not just HiZ.
1640 return (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1641 image
->aux_surface
.isl
.size
> 0;
1644 struct anv_buffer_view
{
1645 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1647 uint32_t offset
; /**< Offset into bo. */
1648 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1650 struct anv_state surface_state
;
1651 struct anv_state storage_surface_state
;
1653 struct brw_image_param storage_image_param
;
1657 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
1659 static inline struct VkExtent3D
1660 anv_sanitize_image_extent(const VkImageType imageType
,
1661 const struct VkExtent3D imageExtent
)
1663 switch (imageType
) {
1664 case VK_IMAGE_TYPE_1D
:
1665 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1666 case VK_IMAGE_TYPE_2D
:
1667 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1668 case VK_IMAGE_TYPE_3D
:
1671 unreachable("invalid image type");
1675 static inline struct VkOffset3D
1676 anv_sanitize_image_offset(const VkImageType imageType
,
1677 const struct VkOffset3D imageOffset
)
1679 switch (imageType
) {
1680 case VK_IMAGE_TYPE_1D
:
1681 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1682 case VK_IMAGE_TYPE_2D
:
1683 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1684 case VK_IMAGE_TYPE_3D
:
1687 unreachable("invalid image type");
1692 void anv_fill_buffer_surface_state(struct anv_device
*device
,
1693 struct anv_state state
,
1694 enum isl_format format
,
1695 uint32_t offset
, uint32_t range
,
1698 void anv_image_view_fill_image_param(struct anv_device
*device
,
1699 struct anv_image_view
*view
,
1700 struct brw_image_param
*param
);
1701 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
1702 struct anv_buffer_view
*view
,
1703 struct brw_image_param
*param
);
1705 struct anv_sampler
{
1709 struct anv_framebuffer
{
1714 uint32_t attachment_count
;
1715 struct anv_image_view
* attachments
[0];
1718 struct anv_subpass
{
1719 uint32_t input_count
;
1720 uint32_t * input_attachments
;
1721 uint32_t color_count
;
1722 uint32_t * color_attachments
;
1723 uint32_t * resolve_attachments
;
1724 uint32_t depth_stencil_attachment
;
1726 /** Subpass has a depth/stencil self-dependency */
1727 bool has_ds_self_dep
;
1729 /** Subpass has at least one resolve attachment */
1733 enum anv_subpass_usage
{
1734 ANV_SUBPASS_USAGE_DRAW
= (1 << 0),
1735 ANV_SUBPASS_USAGE_INPUT
= (1 << 1),
1736 ANV_SUBPASS_USAGE_RESOLVE_SRC
= (1 << 2),
1737 ANV_SUBPASS_USAGE_RESOLVE_DST
= (1 << 3),
1740 struct anv_render_pass_attachment
{
1743 VkImageUsageFlags usage
;
1744 VkAttachmentLoadOp load_op
;
1745 VkAttachmentStoreOp store_op
;
1746 VkAttachmentLoadOp stencil_load_op
;
1748 /* An array, indexed by subpass id, of how the attachment will be used. */
1749 enum anv_subpass_usage
* subpass_usage
;
1752 struct anv_render_pass
{
1753 uint32_t attachment_count
;
1754 uint32_t subpass_count
;
1755 uint32_t * subpass_attachments
;
1756 enum anv_subpass_usage
* subpass_usages
;
1757 struct anv_render_pass_attachment
* attachments
;
1758 struct anv_subpass subpasses
[0];
1761 struct anv_query_pool_slot
{
1767 struct anv_query_pool
{
1773 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
1776 void anv_dump_image_to_ppm(struct anv_device
*device
,
1777 struct anv_image
*image
, unsigned miplevel
,
1778 unsigned array_layer
, VkImageAspectFlagBits aspect
,
1779 const char *filename
);
1781 enum anv_dump_action
{
1782 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
1785 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
1786 void anv_dump_finish(void);
1788 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
1789 struct anv_framebuffer
*fb
);
1791 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1793 static inline struct __anv_type * \
1794 __anv_type ## _from_handle(__VkType _handle) \
1796 return (struct __anv_type *) _handle; \
1799 static inline __VkType \
1800 __anv_type ## _to_handle(struct __anv_type *_obj) \
1802 return (__VkType) _obj; \
1805 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1807 static inline struct __anv_type * \
1808 __anv_type ## _from_handle(__VkType _handle) \
1810 return (struct __anv_type *)(uintptr_t) _handle; \
1813 static inline __VkType \
1814 __anv_type ## _to_handle(struct __anv_type *_obj) \
1816 return (__VkType)(uintptr_t) _obj; \
1819 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1820 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1822 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
1823 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
1824 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
1825 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
1826 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
1828 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
1829 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
1830 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
1831 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
1832 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
1833 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
1834 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
1835 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
1836 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
1837 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
1838 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
1839 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
1840 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
1841 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
1842 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
1843 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
1844 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
1845 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
1846 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
1848 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1850 static inline const __VkType * \
1851 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1853 return (const __VkType *) __anv_obj; \
1856 /* Gen-specific function declarations */
1858 # include "anv_genX.h"
1860 # define genX(x) gen7_##x
1861 # include "anv_genX.h"
1863 # define genX(x) gen75_##x
1864 # include "anv_genX.h"
1866 # define genX(x) gen8_##x
1867 # include "anv_genX.h"
1869 # define genX(x) gen9_##x
1870 # include "anv_genX.h"
1878 #endif /* ANV_PRIVATE_H */