2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
46 #include "common/gen_clflush.h"
47 #include "common/gen_gem.h"
48 #include "dev/gen_device_info.h"
49 #include "blorp/blorp.h"
50 #include "compiler/brw_compiler.h"
51 #include "util/macros.h"
52 #include "util/hash_table.h"
53 #include "util/list.h"
55 #include "util/u_atomic.h"
56 #include "util/u_vector.h"
57 #include "util/u_math.h"
60 #include "vk_debug_report.h"
62 /* Pre-declarations needed for WSI entrypoints */
65 typedef struct xcb_connection_t xcb_connection_t
;
66 typedef uint32_t xcb_visualid_t
;
67 typedef uint32_t xcb_window_t
;
70 struct anv_buffer_view
;
71 struct anv_image_view
;
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
81 #include "anv_entrypoints.h"
82 #include "anv_extensions.h"
85 #include "common/gen_debug.h"
86 #include "common/intel_log.h"
87 #include "wsi_common.h"
89 /* anv Virtual Memory Layout
90 * =========================
92 * When the anv driver is determining the virtual graphics addresses of memory
93 * objects itself using the softpin mechanism, the following memory ranges
96 * Three special considerations to notice:
98 * (1) the dynamic state pool is located within the same 4 GiB as the low
99 * heap. This is to work around a VF cache issue described in a comment in
100 * anv_physical_device_init_heaps.
102 * (2) the binding table pool is located at lower addresses than the surface
103 * state pool, within a 4 GiB range. This allows surface state base addresses
104 * to cover both binding tables (16 bit offsets) and surface states (32 bit
107 * (3) the last 4 GiB of the address space is withheld from the high
108 * heap. Various hardware units will read past the end of an object for
109 * various reasons. This healthy margin prevents reads from wrapping around
112 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
113 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
114 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
115 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
116 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
117 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
118 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
119 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
120 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
121 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
122 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
123 #define HIGH_HEAP_MAX_ADDRESS 0xfffeffffffffULL
125 #define LOW_HEAP_SIZE \
126 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
127 #define HIGH_HEAP_SIZE \
128 (HIGH_HEAP_MAX_ADDRESS - HIGH_HEAP_MIN_ADDRESS + 1)
129 #define DYNAMIC_STATE_POOL_SIZE \
130 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
131 #define BINDING_TABLE_POOL_SIZE \
132 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
133 #define SURFACE_STATE_POOL_SIZE \
134 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
135 #define INSTRUCTION_STATE_POOL_SIZE \
136 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
138 /* Allowing different clear colors requires us to perform a depth resolve at
139 * the end of certain render passes. This is because while slow clears store
140 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
141 * See the PRMs for examples describing when additional resolves would be
142 * necessary. To enable fast clears without requiring extra resolves, we set
143 * the clear value to a globally-defined one. We could allow different values
144 * if the user doesn't expect coherent data during or after a render passes
145 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
146 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
147 * 1.0f seems to be the only value used. The only application that doesn't set
148 * this value does so through the usage of an seemingly uninitialized clear
151 #define ANV_HZ_FC_VAL 1.0f
156 #define MAX_VIEWPORTS 16
157 #define MAX_SCISSORS 16
158 #define MAX_PUSH_CONSTANTS_SIZE 128
159 #define MAX_DYNAMIC_BUFFERS 16
161 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
163 /* The kernel relocation API has a limitation of a 32-bit delta value
164 * applied to the address before it is written which, in spite of it being
165 * unsigned, is treated as signed . Because of the way that this maps to
166 * the Vulkan API, we cannot handle an offset into a buffer that does not
167 * fit into a signed 32 bits. The only mechanism we have for dealing with
168 * this at the moment is to limit all VkDeviceMemory objects to a maximum
169 * of 2GB each. The Vulkan spec allows us to do this:
171 * "Some platforms may have a limit on the maximum size of a single
172 * allocation. For example, certain systems may fail to create
173 * allocations with a size greater than or equal to 4GB. Such a limit is
174 * implementation-dependent, and if such a failure occurs then the error
175 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
177 * We don't use vk_error here because it's not an error so much as an
178 * indication to the application that the allocation is too large.
180 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
182 #define ANV_SVGS_VB_INDEX MAX_VBS
183 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
185 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
187 static inline uint32_t
188 align_down_npot_u32(uint32_t v
, uint32_t a
)
193 static inline uint32_t
194 align_u32(uint32_t v
, uint32_t a
)
196 assert(a
!= 0 && a
== (a
& -a
));
197 return (v
+ a
- 1) & ~(a
- 1);
200 static inline uint64_t
201 align_u64(uint64_t v
, uint64_t a
)
203 assert(a
!= 0 && a
== (a
& -a
));
204 return (v
+ a
- 1) & ~(a
- 1);
207 static inline int32_t
208 align_i32(int32_t v
, int32_t a
)
210 assert(a
!= 0 && a
== (a
& -a
));
211 return (v
+ a
- 1) & ~(a
- 1);
214 /** Alignment must be a power of 2. */
216 anv_is_aligned(uintmax_t n
, uintmax_t a
)
218 assert(a
== (a
& -a
));
219 return (n
& (a
- 1)) == 0;
222 static inline uint32_t
223 anv_minify(uint32_t n
, uint32_t levels
)
225 if (unlikely(n
== 0))
228 return MAX2(n
>> levels
, 1);
232 anv_clamp_f(float f
, float min
, float max
)
245 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
247 if (*inout_mask
& clear_mask
) {
248 *inout_mask
&= ~clear_mask
;
255 static inline union isl_color_value
256 vk_to_isl_color(VkClearColorValue color
)
258 return (union isl_color_value
) {
268 #define for_each_bit(b, dword) \
269 for (uint32_t __dword = (dword); \
270 (b) = __builtin_ffs(__dword) - 1, __dword; \
271 __dword &= ~(1 << (b)))
273 #define typed_memcpy(dest, src, count) ({ \
274 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
275 memcpy((dest), (src), (count) * sizeof(*(src))); \
278 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
279 * to be added here in order to utilize mapping in debug/error/perf macros.
281 #define REPORT_OBJECT_TYPE(o) \
282 __builtin_choose_expr ( \
283 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
284 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
285 __builtin_choose_expr ( \
286 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
287 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
288 __builtin_choose_expr ( \
289 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
290 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
291 __builtin_choose_expr ( \
292 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
293 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
294 __builtin_choose_expr ( \
295 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
296 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
297 __builtin_choose_expr ( \
298 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
299 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
300 __builtin_choose_expr ( \
301 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
302 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
303 __builtin_choose_expr ( \
304 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
305 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
306 __builtin_choose_expr ( \
307 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
308 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
309 __builtin_choose_expr ( \
310 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
311 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
312 __builtin_choose_expr ( \
313 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
314 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
315 __builtin_choose_expr ( \
316 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
317 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
318 __builtin_choose_expr ( \
319 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
320 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
321 __builtin_choose_expr ( \
322 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
323 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
324 __builtin_choose_expr ( \
325 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
326 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
327 __builtin_choose_expr ( \
328 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
329 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
330 __builtin_choose_expr ( \
331 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
332 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
333 __builtin_choose_expr ( \
334 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
335 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
336 __builtin_choose_expr ( \
337 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
338 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
339 __builtin_choose_expr ( \
340 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
341 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
342 __builtin_choose_expr ( \
343 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
344 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
345 __builtin_choose_expr ( \
346 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
347 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
348 __builtin_choose_expr ( \
349 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
350 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
351 __builtin_choose_expr ( \
352 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
353 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
354 __builtin_choose_expr ( \
355 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
356 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
357 __builtin_choose_expr ( \
358 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
359 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
360 __builtin_choose_expr ( \
361 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
362 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
363 __builtin_choose_expr ( \
364 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
365 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
366 __builtin_choose_expr ( \
367 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
368 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
369 __builtin_choose_expr ( \
370 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
371 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
372 __builtin_choose_expr ( \
373 __builtin_types_compatible_p (__typeof (o), void*), \
374 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
375 /* The void expression results in a compile-time error \
376 when assigning the result to something. */ \
377 (void)0)))))))))))))))))))))))))))))))
379 /* Whenever we generate an error, pass it through this function. Useful for
380 * debugging, where we can break on it. Only call at error site, not when
381 * propagating errors. Might be useful to plug in a stack trace here.
384 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
385 VkDebugReportObjectTypeEXT type
, VkResult error
,
386 const char *file
, int line
, const char *format
, ...);
389 #define vk_error(error) __vk_errorf(NULL, NULL,\
390 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
391 error, __FILE__, __LINE__, NULL)
392 #define vk_errorf(instance, obj, error, format, ...)\
393 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
394 __FILE__, __LINE__, format, ## __VA_ARGS__)
396 #define vk_error(error) error
397 #define vk_errorf(instance, obj, error, format, ...) error
401 * Warn on ignored extension structs.
403 * The Vulkan spec requires us to ignore unsupported or unknown structs in
404 * a pNext chain. In debug mode, emitting warnings for ignored structs may
405 * help us discover structs that we should not have ignored.
408 * From the Vulkan 1.0.38 spec:
410 * Any component of the implementation (the loader, any enabled layers,
411 * and drivers) must skip over, without processing (other than reading the
412 * sType and pNext members) any chained structures with sType values not
413 * defined by extensions supported by that component.
415 #define anv_debug_ignored_stype(sType) \
416 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
418 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
419 VkDebugReportObjectTypeEXT type
, const char *file
,
420 int line
, const char *format
, ...)
421 anv_printflike(6, 7);
422 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
423 void anv_loge_v(const char *format
, va_list va
);
426 * Print a FINISHME message, including its source location.
428 #define anv_finishme(format, ...) \
430 static bool reported = false; \
432 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
439 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
441 #define anv_perf_warn(instance, obj, format, ...) \
443 static bool reported = false; \
444 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
445 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
446 format, ##__VA_ARGS__); \
451 /* A non-fatal assert. Useful for debugging. */
453 #define anv_assert(x) ({ \
454 if (unlikely(!(x))) \
455 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
458 #define anv_assert(x)
461 /* A multi-pointer allocator
463 * When copying data structures from the user (such as a render pass), it's
464 * common to need to allocate data for a bunch of different things. Instead
465 * of doing several allocations and having to handle all of the error checking
466 * that entails, it can be easier to do a single allocation. This struct
467 * helps facilitate that. The intended usage looks like this:
470 * anv_multialloc_add(&ma, &main_ptr, 1);
471 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
472 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
474 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
475 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
477 struct anv_multialloc
{
485 #define ANV_MULTIALLOC_INIT \
486 ((struct anv_multialloc) { 0, })
488 #define ANV_MULTIALLOC(_name) \
489 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
491 __attribute__((always_inline
))
493 _anv_multialloc_add(struct anv_multialloc
*ma
,
494 void **ptr
, size_t size
, size_t align
)
496 size_t offset
= align_u64(ma
->size
, align
);
497 ma
->size
= offset
+ size
;
498 ma
->align
= MAX2(ma
->align
, align
);
500 /* Store the offset in the pointer. */
501 *ptr
= (void *)(uintptr_t)offset
;
503 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
504 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
507 #define anv_multialloc_add_size(_ma, _ptr, _size) \
508 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
510 #define anv_multialloc_add(_ma, _ptr, _count) \
511 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
513 __attribute__((always_inline
))
515 anv_multialloc_alloc(struct anv_multialloc
*ma
,
516 const VkAllocationCallbacks
*alloc
,
517 VkSystemAllocationScope scope
)
519 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
523 /* Fill out each of the pointers with their final value.
525 * for (uint32_t i = 0; i < ma->ptr_count; i++)
526 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
528 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
529 * constant, GCC is incapable of figuring this out and unrolling the loop
530 * so we have to give it a little help.
532 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
533 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
534 if ((_i) < ma->ptr_count) \
535 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
536 _ANV_MULTIALLOC_UPDATE_POINTER(0);
537 _ANV_MULTIALLOC_UPDATE_POINTER(1);
538 _ANV_MULTIALLOC_UPDATE_POINTER(2);
539 _ANV_MULTIALLOC_UPDATE_POINTER(3);
540 _ANV_MULTIALLOC_UPDATE_POINTER(4);
541 _ANV_MULTIALLOC_UPDATE_POINTER(5);
542 _ANV_MULTIALLOC_UPDATE_POINTER(6);
543 _ANV_MULTIALLOC_UPDATE_POINTER(7);
544 #undef _ANV_MULTIALLOC_UPDATE_POINTER
549 __attribute__((always_inline
))
551 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
552 const VkAllocationCallbacks
*parent_alloc
,
553 const VkAllocationCallbacks
*alloc
,
554 VkSystemAllocationScope scope
)
556 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
559 /* Extra ANV-defined BO flags which won't be passed to the kernel */
560 #define ANV_BO_EXTERNAL (1ull << 31)
561 #define ANV_BO_FLAG_MASK (1ull << 31)
566 /* Index into the current validation list. This is used by the
567 * validation list building alrogithm to track which buffers are already
568 * in the validation list so that we can ensure uniqueness.
572 /* Last known offset. This value is provided by the kernel when we
573 * execbuf and is used as the presumed offset for the next bunch of
581 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
586 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
588 bo
->gem_handle
= gem_handle
;
596 /* Represents a lock-free linked list of "free" things. This is used by
597 * both the block pool and the state pools. Unfortunately, in order to
598 * solve the ABA problem, we can't use a single uint32_t head.
600 union anv_free_list
{
604 /* A simple count that is incremented every time the head changes. */
610 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
612 struct anv_block_state
{
622 struct anv_block_pool
{
623 struct anv_device
*device
;
629 /* The address where the start of the pool is pinned. The various bos that
630 * are created as the pool grows will have addresses in the range
631 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
633 uint64_t start_address
;
635 /* The offset from the start of the bo to the "center" of the block
636 * pool. Pointers to allocated blocks are given by
637 * bo.map + center_bo_offset + offsets.
639 uint32_t center_bo_offset
;
641 /* Current memory map of the block pool. This pointer may or may not
642 * point to the actual beginning of the block pool memory. If
643 * anv_block_pool_alloc_back has ever been called, then this pointer
644 * will point to the "center" position of the buffer and all offsets
645 * (negative or positive) given out by the block pool alloc functions
646 * will be valid relative to this pointer.
648 * In particular, map == bo.map + center_offset
654 * Array of mmaps and gem handles owned by the block pool, reclaimed when
655 * the block pool is destroyed.
657 struct u_vector mmap_cleanups
;
659 struct anv_block_state state
;
661 struct anv_block_state back_state
;
664 /* Block pools are backed by a fixed-size 1GB memfd */
665 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
667 /* The center of the block pool is also the middle of the memfd. This may
668 * change in the future if we decide differently for some reason.
670 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
672 static inline uint32_t
673 anv_block_pool_size(struct anv_block_pool
*pool
)
675 return pool
->state
.end
+ pool
->back_state
.end
;
684 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
686 struct anv_fixed_size_state_pool
{
687 union anv_free_list free_list
;
688 struct anv_block_state block
;
691 #define ANV_MIN_STATE_SIZE_LOG2 6
692 #define ANV_MAX_STATE_SIZE_LOG2 20
694 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
696 struct anv_state_pool
{
697 struct anv_block_pool block_pool
;
699 /* The size of blocks which will be allocated from the block pool */
702 /** Free list for "back" allocations */
703 union anv_free_list back_alloc_free_list
;
705 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
708 struct anv_state_stream_block
;
710 struct anv_state_stream
{
711 struct anv_state_pool
*state_pool
;
713 /* The size of blocks to allocate from the state pool */
716 /* Current block we're allocating from */
717 struct anv_state block
;
719 /* Offset into the current block at which to allocate the next state */
722 /* List of all blocks allocated from this pool */
723 struct anv_state_stream_block
*block_list
;
726 /* The block_pool functions exported for testing only. The block pool should
727 * only be used via a state pool (see below).
729 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
730 struct anv_device
*device
,
731 uint64_t start_address
,
732 uint32_t initial_size
,
734 void anv_block_pool_finish(struct anv_block_pool
*pool
);
735 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
736 uint32_t block_size
);
737 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
738 uint32_t block_size
);
740 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
741 struct anv_device
*device
,
742 uint64_t start_address
,
745 void anv_state_pool_finish(struct anv_state_pool
*pool
);
746 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
747 uint32_t state_size
, uint32_t alignment
);
748 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
749 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
750 void anv_state_stream_init(struct anv_state_stream
*stream
,
751 struct anv_state_pool
*state_pool
,
752 uint32_t block_size
);
753 void anv_state_stream_finish(struct anv_state_stream
*stream
);
754 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
755 uint32_t size
, uint32_t alignment
);
758 * Implements a pool of re-usable BOs. The interface is identical to that
759 * of block_pool except that each block is its own BO.
762 struct anv_device
*device
;
769 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
771 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
772 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
774 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
776 struct anv_scratch_bo
{
781 struct anv_scratch_pool
{
782 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
783 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
786 void anv_scratch_pool_init(struct anv_device
*device
,
787 struct anv_scratch_pool
*pool
);
788 void anv_scratch_pool_finish(struct anv_device
*device
,
789 struct anv_scratch_pool
*pool
);
790 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
791 struct anv_scratch_pool
*pool
,
792 gl_shader_stage stage
,
793 unsigned per_thread_scratch
);
795 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
796 struct anv_bo_cache
{
797 struct hash_table
*bo_map
;
798 pthread_mutex_t mutex
;
801 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
802 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
803 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
804 struct anv_bo_cache
*cache
,
805 uint64_t size
, uint64_t bo_flags
,
807 VkResult
anv_bo_cache_import(struct anv_device
*device
,
808 struct anv_bo_cache
*cache
,
809 int fd
, uint64_t bo_flags
,
811 VkResult
anv_bo_cache_export(struct anv_device
*device
,
812 struct anv_bo_cache
*cache
,
813 struct anv_bo
*bo_in
, int *fd_out
);
814 void anv_bo_cache_release(struct anv_device
*device
,
815 struct anv_bo_cache
*cache
,
818 struct anv_memory_type
{
819 /* Standard bits passed on to the client */
820 VkMemoryPropertyFlags propertyFlags
;
823 /* Driver-internal book-keeping */
824 VkBufferUsageFlags valid_buffer_usage
;
827 struct anv_memory_heap
{
828 /* Standard bits passed on to the client */
830 VkMemoryHeapFlags flags
;
832 /* Driver-internal book-keeping */
833 bool supports_48bit_addresses
;
836 struct anv_physical_device
{
837 VK_LOADER_DATA _loader_data
;
839 struct anv_instance
* instance
;
850 struct gen_device_info info
;
851 /** Amount of "GPU memory" we want to advertise
853 * Clearly, this value is bogus since Intel is a UMA architecture. On
854 * gen7 platforms, we are limited by GTT size unless we want to implement
855 * fine-grained tracking and GTT splitting. On Broadwell and above we are
856 * practically unlimited. However, we will never report more than 3/4 of
857 * the total system ram to try and avoid running out of RAM.
859 bool supports_48bit_addresses
;
860 struct brw_compiler
* compiler
;
861 struct isl_device isl_dev
;
862 int cmd_parser_version
;
864 bool has_exec_capture
;
867 bool has_syncobj_wait
;
868 bool has_context_priority
;
870 bool has_context_isolation
;
872 struct anv_device_extension_table supported_extensions
;
875 uint32_t subslice_total
;
879 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
881 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
884 uint8_t driver_build_sha1
[20];
885 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
886 uint8_t driver_uuid
[VK_UUID_SIZE
];
887 uint8_t device_uuid
[VK_UUID_SIZE
];
889 struct disk_cache
* disk_cache
;
891 struct wsi_device wsi_device
;
896 struct anv_app_info
{
897 const char* app_name
;
898 uint32_t app_version
;
899 const char* engine_name
;
900 uint32_t engine_version
;
901 uint32_t api_version
;
904 struct anv_instance
{
905 VK_LOADER_DATA _loader_data
;
907 VkAllocationCallbacks alloc
;
909 struct anv_app_info app_info
;
911 struct anv_instance_extension_table enabled_extensions
;
912 struct anv_instance_dispatch_table dispatch
;
913 struct anv_device_dispatch_table device_dispatch
;
915 int physicalDeviceCount
;
916 struct anv_physical_device physicalDevice
;
918 bool pipeline_cache_enabled
;
920 struct vk_debug_report_instance debug_report_callbacks
;
923 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
924 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
926 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
927 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
931 VK_LOADER_DATA _loader_data
;
933 struct anv_device
* device
;
935 VkDeviceQueueCreateFlags flags
;
938 struct anv_pipeline_cache
{
939 struct anv_device
* device
;
940 pthread_mutex_t mutex
;
942 struct hash_table
* cache
;
945 struct anv_pipeline_bind_map
;
947 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
948 struct anv_device
*device
,
950 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
952 struct anv_shader_bin
*
953 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
954 const void *key
, uint32_t key_size
);
955 struct anv_shader_bin
*
956 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
957 const void *key_data
, uint32_t key_size
,
958 const void *kernel_data
, uint32_t kernel_size
,
959 const void *constant_data
,
960 uint32_t constant_data_size
,
961 const struct brw_stage_prog_data
*prog_data
,
962 uint32_t prog_data_size
,
963 const struct anv_pipeline_bind_map
*bind_map
);
965 struct anv_shader_bin
*
966 anv_device_search_for_kernel(struct anv_device
*device
,
967 struct anv_pipeline_cache
*cache
,
968 const void *key_data
, uint32_t key_size
);
970 struct anv_shader_bin
*
971 anv_device_upload_kernel(struct anv_device
*device
,
972 struct anv_pipeline_cache
*cache
,
973 const void *key_data
, uint32_t key_size
,
974 const void *kernel_data
, uint32_t kernel_size
,
975 const void *constant_data
,
976 uint32_t constant_data_size
,
977 const struct brw_stage_prog_data
*prog_data
,
978 uint32_t prog_data_size
,
979 const struct anv_pipeline_bind_map
*bind_map
);
982 VK_LOADER_DATA _loader_data
;
984 VkAllocationCallbacks alloc
;
986 struct anv_instance
* instance
;
989 struct gen_device_info info
;
990 struct isl_device isl_dev
;
993 bool can_chain_batches
;
994 bool robust_buffer_access
;
995 struct anv_device_extension_table enabled_extensions
;
996 struct anv_device_dispatch_table dispatch
;
998 pthread_mutex_t vma_mutex
;
999 struct util_vma_heap vma_lo
;
1000 struct util_vma_heap vma_hi
;
1001 uint64_t vma_lo_available
;
1002 uint64_t vma_hi_available
;
1004 struct anv_bo_pool batch_bo_pool
;
1006 struct anv_bo_cache bo_cache
;
1008 struct anv_state_pool dynamic_state_pool
;
1009 struct anv_state_pool instruction_state_pool
;
1010 struct anv_state_pool binding_table_pool
;
1011 struct anv_state_pool surface_state_pool
;
1013 struct anv_bo workaround_bo
;
1014 struct anv_bo trivial_batch_bo
;
1015 struct anv_bo hiz_clear_bo
;
1017 struct anv_pipeline_cache default_pipeline_cache
;
1018 struct blorp_context blorp
;
1020 struct anv_state border_colors
;
1022 struct anv_queue queue
;
1024 struct anv_scratch_pool scratch_pool
;
1026 uint32_t default_mocs
;
1027 uint32_t external_mocs
;
1029 pthread_mutex_t mutex
;
1030 pthread_cond_t queue_submit
;
1034 static inline struct anv_state_pool
*
1035 anv_binding_table_pool(struct anv_device
*device
)
1037 if (device
->instance
->physicalDevice
.use_softpin
)
1038 return &device
->binding_table_pool
;
1040 return &device
->surface_state_pool
;
1043 static inline struct anv_state
1044 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1045 if (device
->instance
->physicalDevice
.use_softpin
)
1046 return anv_state_pool_alloc(&device
->binding_table_pool
,
1047 device
->binding_table_pool
.block_size
, 0);
1049 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1053 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1054 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1057 static inline uint32_t
1058 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1060 if (bo
->flags
& ANV_BO_EXTERNAL
)
1061 return device
->external_mocs
;
1063 return device
->default_mocs
;
1067 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
1069 if (device
->info
.has_llc
)
1072 gen_flush_range(state
.map
, state
.alloc_size
);
1075 void anv_device_init_blorp(struct anv_device
*device
);
1076 void anv_device_finish_blorp(struct anv_device
*device
);
1078 VkResult
anv_device_execbuf(struct anv_device
*device
,
1079 struct drm_i915_gem_execbuffer2
*execbuf
,
1080 struct anv_bo
**execbuf_bos
);
1081 VkResult
anv_device_query_status(struct anv_device
*device
);
1082 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1083 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1086 void* anv_gem_mmap(struct anv_device
*device
,
1087 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1088 void anv_gem_munmap(void *p
, uint64_t size
);
1089 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1090 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1091 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1092 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1093 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1094 int anv_gem_execbuffer(struct anv_device
*device
,
1095 struct drm_i915_gem_execbuffer2
*execbuf
);
1096 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1097 uint32_t stride
, uint32_t tiling
);
1098 int anv_gem_create_context(struct anv_device
*device
);
1099 bool anv_gem_has_context_priority(int fd
);
1100 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1101 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1103 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1105 int anv_gem_get_param(int fd
, uint32_t param
);
1106 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1107 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1108 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1109 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1110 uint32_t *active
, uint32_t *pending
);
1111 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1112 int anv_gem_reg_read(struct anv_device
*device
,
1113 uint32_t offset
, uint64_t *result
);
1114 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1115 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1116 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1117 uint32_t read_domains
, uint32_t write_domain
);
1118 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1119 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1120 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1121 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1122 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1123 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1125 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1126 uint32_t handle
, int fd
);
1127 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1128 bool anv_gem_supports_syncobj_wait(int fd
);
1129 int anv_gem_syncobj_wait(struct anv_device
*device
,
1130 uint32_t *handles
, uint32_t num_handles
,
1131 int64_t abs_timeout_ns
, bool wait_all
);
1133 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1134 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1136 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1138 struct anv_reloc_list
{
1139 uint32_t num_relocs
;
1140 uint32_t array_length
;
1141 struct drm_i915_gem_relocation_entry
* relocs
;
1142 struct anv_bo
** reloc_bos
;
1146 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1147 const VkAllocationCallbacks
*alloc
);
1148 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1149 const VkAllocationCallbacks
*alloc
);
1151 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1152 const VkAllocationCallbacks
*alloc
,
1153 uint32_t offset
, struct anv_bo
*target_bo
,
1156 struct anv_batch_bo
{
1157 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1158 struct list_head link
;
1162 /* Bytes actually consumed in this batch BO */
1165 struct anv_reloc_list relocs
;
1169 const VkAllocationCallbacks
* alloc
;
1175 struct anv_reloc_list
* relocs
;
1177 /* This callback is called (with the associated user data) in the event
1178 * that the batch runs out of space.
1180 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1184 * Current error status of the command buffer. Used to track inconsistent
1185 * or incomplete command buffer states that are the consequence of run-time
1186 * errors such as out of memory scenarios. We want to track this in the
1187 * batch because the command buffer object is not visible to some parts
1193 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1194 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1195 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1196 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1197 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1198 struct anv_batch
*batch
);
1200 static inline VkResult
1201 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1203 assert(error
!= VK_SUCCESS
);
1204 if (batch
->status
== VK_SUCCESS
)
1205 batch
->status
= error
;
1206 return batch
->status
;
1210 anv_batch_has_error(struct anv_batch
*batch
)
1212 return batch
->status
!= VK_SUCCESS
;
1215 struct anv_address
{
1220 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1223 anv_address_is_null(struct anv_address addr
)
1225 return addr
.bo
== NULL
&& addr
.offset
== 0;
1228 static inline uint64_t
1229 anv_address_physical(struct anv_address addr
)
1231 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1232 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1234 return gen_canonical_address(addr
.offset
);
1237 static inline struct anv_address
1238 anv_address_add(struct anv_address addr
, uint64_t offset
)
1240 addr
.offset
+= offset
;
1245 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1247 unsigned reloc_size
= 0;
1248 if (device
->info
.gen
>= 8) {
1249 reloc_size
= sizeof(uint64_t);
1250 *(uint64_t *)p
= gen_canonical_address(v
);
1252 reloc_size
= sizeof(uint32_t);
1256 if (flush
&& !device
->info
.has_llc
)
1257 gen_flush_range(p
, reloc_size
);
1260 static inline uint64_t
1261 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1262 const struct anv_address address
, uint32_t delta
)
1264 if (address
.bo
== NULL
) {
1265 return address
.offset
+ delta
;
1267 assert(batch
->start
<= location
&& location
< batch
->end
);
1269 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1273 #define __gen_address_type struct anv_address
1274 #define __gen_user_data struct anv_batch
1275 #define __gen_combine_address _anv_combine_address
1277 /* Wrapper macros needed to work around preprocessor argument issues. In
1278 * particular, arguments don't get pre-evaluated if they are concatenated.
1279 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1280 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1281 * We can work around this easily enough with these helpers.
1283 #define __anv_cmd_length(cmd) cmd ## _length
1284 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1285 #define __anv_cmd_header(cmd) cmd ## _header
1286 #define __anv_cmd_pack(cmd) cmd ## _pack
1287 #define __anv_reg_num(reg) reg ## _num
1289 #define anv_pack_struct(dst, struc, ...) do { \
1290 struct struc __template = { \
1293 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1294 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1297 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1298 void *__dst = anv_batch_emit_dwords(batch, n); \
1300 struct cmd __template = { \
1301 __anv_cmd_header(cmd), \
1302 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1305 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1310 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1314 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1315 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1318 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1319 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1320 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1323 #define anv_batch_emit(batch, cmd, name) \
1324 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1325 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1326 __builtin_expect(_dst != NULL, 1); \
1327 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1328 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1332 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1333 .GraphicsDataTypeGFDT = 0, \
1334 .LLCCacheabilityControlLLCCC = 0, \
1335 .L3CacheabilityControlL3CC = 1, \
1338 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1339 .LLCeLLCCacheabilityControlLLCCC = 0, \
1340 .L3CacheabilityControlL3CC = 1, \
1343 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1344 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1345 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1346 .AgeforQUADLRU = 0 \
1349 #define GEN8_EXTERNAL_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1350 .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle, \
1351 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1352 .AgeforQUADLRU = 0 \
1355 /* Skylake: MOCS is now an index into an array of 62 different caching
1356 * configurations programmed by the kernel.
1359 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1360 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1361 .IndextoMOCSTables = 2 \
1364 #define GEN9_EXTERNAL_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1365 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1366 .IndextoMOCSTables = 1 \
1369 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1370 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1371 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1372 .IndextoMOCSTables = 2 \
1375 #define GEN10_EXTERNAL_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1376 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1377 .IndextoMOCSTables = 1 \
1380 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1381 #define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1382 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1383 .IndextoMOCSTables = 2 \
1386 #define GEN11_EXTERNAL_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1387 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1388 .IndextoMOCSTables = 1 \
1391 struct anv_device_memory
{
1393 struct anv_memory_type
* type
;
1394 VkDeviceSize map_size
;
1399 * Header for Vertex URB Entry (VUE)
1401 struct anv_vue_header
{
1403 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1404 uint32_t ViewportIndex
;
1408 struct anv_descriptor_set_binding_layout
{
1410 /* The type of the descriptors in this binding */
1411 VkDescriptorType type
;
1414 /* Number of array elements in this binding */
1415 uint16_t array_size
;
1417 /* Index into the flattend descriptor set */
1418 uint16_t descriptor_index
;
1420 /* Index into the dynamic state array for a dynamic buffer */
1421 int16_t dynamic_offset_index
;
1423 /* Index into the descriptor set buffer views */
1424 int16_t buffer_index
;
1427 /* Index into the binding table for the associated surface */
1428 int16_t surface_index
;
1430 /* Index into the sampler table for the associated sampler */
1431 int16_t sampler_index
;
1433 /* Index into the image table for the associated image */
1434 int16_t image_index
;
1435 } stage
[MESA_SHADER_STAGES
];
1437 /* Immutable samplers (or NULL if no immutable samplers) */
1438 struct anv_sampler
**immutable_samplers
;
1441 struct anv_descriptor_set_layout
{
1442 /* Descriptor set layouts can be destroyed at almost any time */
1445 /* Number of bindings in this descriptor set */
1446 uint16_t binding_count
;
1448 /* Total size of the descriptor set with room for all array entries */
1451 /* Shader stages affected by this descriptor set */
1452 uint16_t shader_stages
;
1454 /* Number of buffers in this descriptor set */
1455 uint16_t buffer_count
;
1457 /* Number of dynamic offsets used by this descriptor set */
1458 uint16_t dynamic_offset_count
;
1460 /* Bindings in this descriptor set */
1461 struct anv_descriptor_set_binding_layout binding
[0];
1465 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1467 assert(layout
&& layout
->ref_cnt
>= 1);
1468 p_atomic_inc(&layout
->ref_cnt
);
1472 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1473 struct anv_descriptor_set_layout
*layout
)
1475 assert(layout
&& layout
->ref_cnt
>= 1);
1476 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1477 vk_free(&device
->alloc
, layout
);
1480 struct anv_descriptor
{
1481 VkDescriptorType type
;
1485 VkImageLayout layout
;
1486 struct anv_image_view
*image_view
;
1487 struct anv_sampler
*sampler
;
1491 struct anv_buffer
*buffer
;
1496 struct anv_buffer_view
*buffer_view
;
1500 struct anv_descriptor_set
{
1501 struct anv_descriptor_set_layout
*layout
;
1503 uint32_t buffer_count
;
1504 struct anv_buffer_view
*buffer_views
;
1505 struct anv_descriptor descriptors
[0];
1508 struct anv_buffer_view
{
1509 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1510 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1512 struct anv_address address
;
1514 struct anv_state surface_state
;
1515 struct anv_state storage_surface_state
;
1516 struct anv_state writeonly_storage_surface_state
;
1518 struct brw_image_param storage_image_param
;
1521 struct anv_push_descriptor_set
{
1522 struct anv_descriptor_set set
;
1524 /* Put this field right behind anv_descriptor_set so it fills up the
1525 * descriptors[0] field. */
1526 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1527 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1530 struct anv_descriptor_pool
{
1535 struct anv_state_stream surface_state_stream
;
1536 void *surface_state_free_list
;
1541 enum anv_descriptor_template_entry_type
{
1542 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1543 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1544 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1547 struct anv_descriptor_template_entry
{
1548 /* The type of descriptor in this entry */
1549 VkDescriptorType type
;
1551 /* Binding in the descriptor set */
1554 /* Offset at which to write into the descriptor set binding */
1555 uint32_t array_element
;
1557 /* Number of elements to write into the descriptor set binding */
1558 uint32_t array_count
;
1560 /* Offset into the user provided data */
1563 /* Stride between elements into the user provided data */
1567 struct anv_descriptor_update_template
{
1568 VkPipelineBindPoint bind_point
;
1570 /* The descriptor set this template corresponds to. This value is only
1571 * valid if the template was created with the templateType
1572 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1576 /* Number of entries in this template */
1577 uint32_t entry_count
;
1579 /* Entries of the template */
1580 struct anv_descriptor_template_entry entries
[0];
1584 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1587 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1588 const struct gen_device_info
* const devinfo
,
1589 const VkDescriptorImageInfo
* const info
,
1590 VkDescriptorType type
,
1595 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1596 VkDescriptorType type
,
1597 struct anv_buffer_view
*buffer_view
,
1602 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1603 struct anv_device
*device
,
1604 struct anv_state_stream
*alloc_stream
,
1605 VkDescriptorType type
,
1606 struct anv_buffer
*buffer
,
1609 VkDeviceSize offset
,
1610 VkDeviceSize range
);
1613 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1614 struct anv_device
*device
,
1615 struct anv_state_stream
*alloc_stream
,
1616 const struct anv_descriptor_update_template
*template,
1620 anv_descriptor_set_create(struct anv_device
*device
,
1621 struct anv_descriptor_pool
*pool
,
1622 struct anv_descriptor_set_layout
*layout
,
1623 struct anv_descriptor_set
**out_set
);
1626 anv_descriptor_set_destroy(struct anv_device
*device
,
1627 struct anv_descriptor_pool
*pool
,
1628 struct anv_descriptor_set
*set
);
1630 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1631 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1633 struct anv_pipeline_binding
{
1634 /* The descriptor set this surface corresponds to. The special value of
1635 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1636 * to a color attachment and not a regular descriptor.
1640 /* Binding in the descriptor set */
1643 /* Index in the binding */
1646 /* Plane in the binding index */
1649 /* Input attachment index (relative to the subpass) */
1650 uint8_t input_attachment_index
;
1652 /* For a storage image, whether it is write-only */
1656 struct anv_pipeline_layout
{
1658 struct anv_descriptor_set_layout
*layout
;
1659 uint32_t dynamic_offset_start
;
1665 bool has_dynamic_offsets
;
1666 } stage
[MESA_SHADER_STAGES
];
1668 unsigned char sha1
[20];
1672 struct anv_device
* device
;
1675 VkBufferUsageFlags usage
;
1677 /* Set when bound */
1678 struct anv_address address
;
1681 static inline uint64_t
1682 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1684 assert(offset
<= buffer
->size
);
1685 if (range
== VK_WHOLE_SIZE
) {
1686 return buffer
->size
- offset
;
1688 assert(range
<= buffer
->size
);
1693 enum anv_cmd_dirty_bits
{
1694 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1695 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1696 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1697 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1698 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1699 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1700 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1701 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1702 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1703 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1704 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1705 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1706 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1708 typedef uint32_t anv_cmd_dirty_mask_t
;
1710 enum anv_pipe_bits
{
1711 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1712 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1713 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1714 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1715 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1716 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1717 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1718 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1719 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1720 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1721 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1723 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1724 * a flush has happened but not a CS stall. The next time we do any sort
1725 * of invalidation we need to insert a CS stall at that time. Otherwise,
1726 * we would have to CS stall on every flush which could be bad.
1728 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1731 #define ANV_PIPE_FLUSH_BITS ( \
1732 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1733 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1734 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1736 #define ANV_PIPE_STALL_BITS ( \
1737 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1738 ANV_PIPE_DEPTH_STALL_BIT | \
1739 ANV_PIPE_CS_STALL_BIT)
1741 #define ANV_PIPE_INVALIDATE_BITS ( \
1742 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1743 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1744 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1745 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1746 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1747 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1749 static inline enum anv_pipe_bits
1750 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1752 enum anv_pipe_bits pipe_bits
= 0;
1755 for_each_bit(b
, flags
) {
1756 switch ((VkAccessFlagBits
)(1 << b
)) {
1757 case VK_ACCESS_SHADER_WRITE_BIT
:
1758 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1760 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1761 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1763 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1764 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1766 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1767 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1768 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1770 case VK_ACCESS_MEMORY_WRITE_BIT
:
1771 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
1774 break; /* Nothing to do */
1781 static inline enum anv_pipe_bits
1782 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1784 enum anv_pipe_bits pipe_bits
= 0;
1787 for_each_bit(b
, flags
) {
1788 switch ((VkAccessFlagBits
)(1 << b
)) {
1789 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1790 case VK_ACCESS_INDEX_READ_BIT
:
1791 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1792 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1794 case VK_ACCESS_UNIFORM_READ_BIT
:
1795 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1796 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1798 case VK_ACCESS_SHADER_READ_BIT
:
1799 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1800 case VK_ACCESS_TRANSFER_READ_BIT
:
1801 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1803 case VK_ACCESS_MEMORY_READ_BIT
:
1804 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
1806 case VK_ACCESS_MEMORY_WRITE_BIT
:
1807 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
1810 break; /* Nothing to do */
1817 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1818 VK_IMAGE_ASPECT_COLOR_BIT | \
1819 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1820 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1821 VK_IMAGE_ASPECT_PLANE_2_BIT)
1822 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1823 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1824 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1825 VK_IMAGE_ASPECT_PLANE_2_BIT)
1827 struct anv_vertex_binding
{
1828 struct anv_buffer
* buffer
;
1829 VkDeviceSize offset
;
1832 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1833 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1835 struct anv_push_constants
{
1836 /* Current allocated size of this push constants data structure.
1837 * Because a decent chunk of it may not be used (images on SKL, for
1838 * instance), we won't actually allocate the entire structure up-front.
1842 /* Push constant data provided by the client through vkPushConstants */
1843 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1845 /* Used for vkCmdDispatchBase */
1846 uint32_t base_work_group_id
[3];
1848 /* Image data for image_load_store on pre-SKL */
1849 struct brw_image_param images
[MAX_IMAGES
];
1852 struct anv_dynamic_state
{
1855 VkViewport viewports
[MAX_VIEWPORTS
];
1860 VkRect2D scissors
[MAX_SCISSORS
];
1871 float blend_constants
[4];
1881 } stencil_compare_mask
;
1886 } stencil_write_mask
;
1891 } stencil_reference
;
1894 extern const struct anv_dynamic_state default_dynamic_state
;
1896 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1897 const struct anv_dynamic_state
*src
,
1898 uint32_t copy_mask
);
1900 struct anv_surface_state
{
1901 struct anv_state state
;
1902 /** Address of the surface referred to by this state
1904 * This address is relative to the start of the BO.
1906 struct anv_address address
;
1907 /* Address of the aux surface, if any
1909 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
1911 * With the exception of gen8, the bottom 12 bits of this address' offset
1912 * include extra aux information.
1914 struct anv_address aux_address
;
1915 /* Address of the clear color, if any
1917 * This address is relative to the start of the BO.
1919 struct anv_address clear_address
;
1923 * Attachment state when recording a renderpass instance.
1925 * The clear value is valid only if there exists a pending clear.
1927 struct anv_attachment_state
{
1928 enum isl_aux_usage aux_usage
;
1929 enum isl_aux_usage input_aux_usage
;
1930 struct anv_surface_state color
;
1931 struct anv_surface_state input
;
1933 VkImageLayout current_layout
;
1934 VkImageAspectFlags pending_clear_aspects
;
1935 VkImageAspectFlags pending_load_aspects
;
1937 VkClearValue clear_value
;
1938 bool clear_color_is_zero_one
;
1939 bool clear_color_is_zero
;
1941 /* When multiview is active, attachments with a renderpass clear
1942 * operation have their respective layers cleared on the first
1943 * subpass that uses them, and only in that subpass. We keep track
1944 * of this using a bitfield to indicate which layers of an attachment
1945 * have not been cleared yet when multiview is active.
1947 uint32_t pending_clear_views
;
1950 /** State tracking for particular pipeline bind point
1952 * This struct is the base struct for anv_cmd_graphics_state and
1953 * anv_cmd_compute_state. These are used to track state which is bound to a
1954 * particular type of pipeline. Generic state that applies per-stage such as
1955 * binding table offsets and push constants is tracked generically with a
1956 * per-stage array in anv_cmd_state.
1958 struct anv_cmd_pipeline_state
{
1959 struct anv_pipeline
*pipeline
;
1960 struct anv_pipeline_layout
*layout
;
1962 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
1963 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
1965 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
1968 /** State tracking for graphics pipeline
1970 * This has anv_cmd_pipeline_state as a base struct to track things which get
1971 * bound to a graphics pipeline. Along with general pipeline bind point state
1972 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1973 * state which is graphics-specific.
1975 struct anv_cmd_graphics_state
{
1976 struct anv_cmd_pipeline_state base
;
1978 anv_cmd_dirty_mask_t dirty
;
1981 struct anv_dynamic_state dynamic
;
1984 struct anv_buffer
*index_buffer
;
1985 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1986 uint32_t index_offset
;
1990 /** State tracking for compute pipeline
1992 * This has anv_cmd_pipeline_state as a base struct to track things which get
1993 * bound to a compute pipeline. Along with general pipeline bind point state
1994 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1995 * state which is compute-specific.
1997 struct anv_cmd_compute_state
{
1998 struct anv_cmd_pipeline_state base
;
2000 bool pipeline_dirty
;
2002 struct anv_address num_workgroups
;
2005 /** State required while building cmd buffer */
2006 struct anv_cmd_state
{
2007 /* PIPELINE_SELECT.PipelineSelection */
2008 uint32_t current_pipeline
;
2009 const struct gen_l3_config
* current_l3_config
;
2011 struct anv_cmd_graphics_state gfx
;
2012 struct anv_cmd_compute_state compute
;
2014 enum anv_pipe_bits pending_pipe_bits
;
2015 VkShaderStageFlags descriptors_dirty
;
2016 VkShaderStageFlags push_constants_dirty
;
2018 struct anv_framebuffer
* framebuffer
;
2019 struct anv_render_pass
* pass
;
2020 struct anv_subpass
* subpass
;
2021 VkRect2D render_area
;
2022 uint32_t restart_index
;
2023 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2024 VkShaderStageFlags push_constant_stages
;
2025 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
2026 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2027 struct anv_state samplers
[MESA_SHADER_STAGES
];
2030 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2031 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2032 * and before invoking the secondary in ExecuteCommands.
2034 bool pma_fix_enabled
;
2037 * Whether or not we know for certain that HiZ is enabled for the current
2038 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2039 * enabled or not, this will be false.
2044 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2045 * valid only when recording a render pass instance.
2047 struct anv_attachment_state
* attachments
;
2050 * Surface states for color render targets. These are stored in a single
2051 * flat array. For depth-stencil attachments, the surface state is simply
2054 struct anv_state render_pass_states
;
2057 * A null surface state of the right size to match the framebuffer. This
2058 * is one of the states in render_pass_states.
2060 struct anv_state null_surface_state
;
2063 struct anv_cmd_pool
{
2064 VkAllocationCallbacks alloc
;
2065 struct list_head cmd_buffers
;
2068 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2070 enum anv_cmd_buffer_exec_mode
{
2071 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2072 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2073 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2074 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2075 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2078 struct anv_cmd_buffer
{
2079 VK_LOADER_DATA _loader_data
;
2081 struct anv_device
* device
;
2083 struct anv_cmd_pool
* pool
;
2084 struct list_head pool_link
;
2086 struct anv_batch batch
;
2088 /* Fields required for the actual chain of anv_batch_bo's.
2090 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2092 struct list_head batch_bos
;
2093 enum anv_cmd_buffer_exec_mode exec_mode
;
2095 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2096 * referenced by this command buffer
2098 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2100 struct u_vector seen_bbos
;
2102 /* A vector of int32_t's for every block of binding tables.
2104 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2106 struct u_vector bt_block_states
;
2109 struct anv_reloc_list surface_relocs
;
2110 /** Last seen surface state block pool center bo offset */
2111 uint32_t last_ss_pool_center
;
2113 /* Serial for tracking buffer completion */
2116 /* Stream objects for storing temporary data */
2117 struct anv_state_stream surface_state_stream
;
2118 struct anv_state_stream dynamic_state_stream
;
2120 VkCommandBufferUsageFlags usage_flags
;
2121 VkCommandBufferLevel level
;
2123 struct anv_cmd_state state
;
2126 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2127 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2128 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2129 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2130 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2131 struct anv_cmd_buffer
*secondary
);
2132 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2133 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2134 struct anv_cmd_buffer
*cmd_buffer
,
2135 const VkSemaphore
*in_semaphores
,
2136 uint32_t num_in_semaphores
,
2137 const VkSemaphore
*out_semaphores
,
2138 uint32_t num_out_semaphores
,
2141 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2144 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
2145 gl_shader_stage stage
, uint32_t size
);
2146 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
2147 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
2148 (offsetof(struct anv_push_constants, field) + \
2149 sizeof(cmd_buffer->state.push_constants[0]->field)))
2151 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2152 const void *data
, uint32_t size
, uint32_t alignment
);
2153 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2154 uint32_t *a
, uint32_t *b
,
2155 uint32_t dwords
, uint32_t alignment
);
2158 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2160 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2161 uint32_t entries
, uint32_t *state_offset
);
2163 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2165 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2166 uint32_t size
, uint32_t alignment
);
2169 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2171 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2172 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2173 bool depth_clamp_enable
);
2174 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2176 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2177 struct anv_render_pass
*pass
,
2178 struct anv_framebuffer
*framebuffer
,
2179 const VkClearValue
*clear_values
);
2181 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2184 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2185 gl_shader_stage stage
);
2187 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2189 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
2191 const struct anv_image_view
*
2192 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2195 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2196 uint32_t num_entries
,
2197 uint32_t *state_offset
,
2198 struct anv_state
*bt_state
);
2200 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2202 enum anv_fence_type
{
2203 ANV_FENCE_TYPE_NONE
= 0,
2205 ANV_FENCE_TYPE_SYNCOBJ
,
2209 enum anv_bo_fence_state
{
2210 /** Indicates that this is a new (or newly reset fence) */
2211 ANV_BO_FENCE_STATE_RESET
,
2213 /** Indicates that this fence has been submitted to the GPU but is still
2214 * (as far as we know) in use by the GPU.
2216 ANV_BO_FENCE_STATE_SUBMITTED
,
2218 ANV_BO_FENCE_STATE_SIGNALED
,
2221 struct anv_fence_impl
{
2222 enum anv_fence_type type
;
2225 /** Fence implementation for BO fences
2227 * These fences use a BO and a set of CPU-tracked state flags. The BO
2228 * is added to the object list of the last execbuf call in a QueueSubmit
2229 * and is marked EXEC_WRITE. The state flags track when the BO has been
2230 * submitted to the kernel. We need to do this because Vulkan lets you
2231 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2232 * will say it's idle in this case.
2236 enum anv_bo_fence_state state
;
2239 /** DRM syncobj handle for syncobj-based fences */
2243 struct wsi_fence
*fence_wsi
;
2248 /* Permanent fence state. Every fence has some form of permanent state
2249 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2250 * cross-process fences) or it could just be a dummy for use internally.
2252 struct anv_fence_impl permanent
;
2254 /* Temporary fence state. A fence *may* have temporary state. That state
2255 * is added to the fence by an import operation and is reset back to
2256 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2257 * state cannot be signaled because the fence must already be signaled
2258 * before the temporary state can be exported from the fence in the other
2259 * process and imported here.
2261 struct anv_fence_impl temporary
;
2266 struct anv_state state
;
2269 enum anv_semaphore_type
{
2270 ANV_SEMAPHORE_TYPE_NONE
= 0,
2271 ANV_SEMAPHORE_TYPE_DUMMY
,
2272 ANV_SEMAPHORE_TYPE_BO
,
2273 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2274 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2277 struct anv_semaphore_impl
{
2278 enum anv_semaphore_type type
;
2281 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2282 * This BO will be added to the object list on any execbuf2 calls for
2283 * which this semaphore is used as a wait or signal fence. When used as
2284 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2288 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2289 * If the semaphore is in the unsignaled state due to either just being
2290 * created or because it has been used for a wait, fd will be -1.
2294 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2295 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2296 * import so we don't need to bother with a userspace cache.
2302 struct anv_semaphore
{
2303 /* Permanent semaphore state. Every semaphore has some form of permanent
2304 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2305 * (for cross-process semaphores0 or it could just be a dummy for use
2308 struct anv_semaphore_impl permanent
;
2310 /* Temporary semaphore state. A semaphore *may* have temporary state.
2311 * That state is added to the semaphore by an import operation and is reset
2312 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2313 * semaphore with temporary state cannot be signaled because the semaphore
2314 * must already be signaled before the temporary state can be exported from
2315 * the semaphore in the other process and imported here.
2317 struct anv_semaphore_impl temporary
;
2320 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2321 struct anv_semaphore
*semaphore
);
2323 struct anv_shader_module
{
2324 unsigned char sha1
[20];
2329 static inline gl_shader_stage
2330 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2332 assert(__builtin_popcount(vk_stage
) == 1);
2333 return ffs(vk_stage
) - 1;
2336 static inline VkShaderStageFlagBits
2337 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2339 return (1 << mesa_stage
);
2342 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2344 #define anv_foreach_stage(stage, stage_bits) \
2345 for (gl_shader_stage stage, \
2346 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2347 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2348 __tmp &= ~(1 << (stage)))
2350 struct anv_pipeline_bind_map
{
2351 uint32_t surface_count
;
2352 uint32_t sampler_count
;
2353 uint32_t image_count
;
2355 struct anv_pipeline_binding
* surface_to_descriptor
;
2356 struct anv_pipeline_binding
* sampler_to_descriptor
;
2359 struct anv_shader_bin_key
{
2364 struct anv_shader_bin
{
2367 const struct anv_shader_bin_key
*key
;
2369 struct anv_state kernel
;
2370 uint32_t kernel_size
;
2372 struct anv_state constant_data
;
2373 uint32_t constant_data_size
;
2375 const struct brw_stage_prog_data
*prog_data
;
2376 uint32_t prog_data_size
;
2378 struct anv_pipeline_bind_map bind_map
;
2381 struct anv_shader_bin
*
2382 anv_shader_bin_create(struct anv_device
*device
,
2383 const void *key
, uint32_t key_size
,
2384 const void *kernel
, uint32_t kernel_size
,
2385 const void *constant_data
, uint32_t constant_data_size
,
2386 const struct brw_stage_prog_data
*prog_data
,
2387 uint32_t prog_data_size
, const void *prog_data_param
,
2388 const struct anv_pipeline_bind_map
*bind_map
);
2391 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2394 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2396 assert(shader
&& shader
->ref_cnt
>= 1);
2397 p_atomic_inc(&shader
->ref_cnt
);
2401 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2403 assert(shader
&& shader
->ref_cnt
>= 1);
2404 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2405 anv_shader_bin_destroy(device
, shader
);
2408 struct anv_pipeline
{
2409 struct anv_device
* device
;
2410 struct anv_batch batch
;
2411 uint32_t batch_data
[512];
2412 struct anv_reloc_list batch_relocs
;
2413 uint32_t dynamic_state_mask
;
2414 struct anv_dynamic_state dynamic_state
;
2416 struct anv_subpass
* subpass
;
2418 bool needs_data_cache
;
2420 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2423 const struct gen_l3_config
* l3_config
;
2424 uint32_t total_size
;
2427 VkShaderStageFlags active_stages
;
2428 struct anv_state blend_state
;
2431 struct anv_pipeline_vertex_binding
{
2434 uint32_t instance_divisor
;
2437 bool primitive_restart
;
2440 uint32_t cs_right_mask
;
2443 bool depth_test_enable
;
2444 bool writes_stencil
;
2445 bool stencil_test_enable
;
2446 bool depth_clamp_enable
;
2447 bool sample_shading_enable
;
2452 uint32_t depth_stencil_state
[3];
2458 uint32_t wm_depth_stencil
[3];
2462 uint32_t wm_depth_stencil
[4];
2465 uint32_t interface_descriptor_data
[8];
2469 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2470 gl_shader_stage stage
)
2472 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2475 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2476 static inline const struct brw_##prefix##_prog_data * \
2477 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2479 if (anv_pipeline_has_stage(pipeline, stage)) { \
2480 return (const struct brw_##prefix##_prog_data *) \
2481 pipeline->shaders[stage]->prog_data; \
2487 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2488 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2489 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2490 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2491 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2492 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2494 static inline const struct brw_vue_prog_data
*
2495 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2497 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2498 return &get_gs_prog_data(pipeline
)->base
;
2499 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2500 return &get_tes_prog_data(pipeline
)->base
;
2502 return &get_vs_prog_data(pipeline
)->base
;
2506 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2507 struct anv_pipeline_cache
*cache
,
2508 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2509 const VkAllocationCallbacks
*alloc
);
2512 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2513 struct anv_pipeline_cache
*cache
,
2514 const VkComputePipelineCreateInfo
*info
,
2515 const struct anv_shader_module
*module
,
2516 const char *entrypoint
,
2517 const VkSpecializationInfo
*spec_info
);
2519 struct anv_format_plane
{
2520 enum isl_format isl_format
:16;
2521 struct isl_swizzle swizzle
;
2523 /* Whether this plane contains chroma channels */
2526 /* For downscaling of YUV planes */
2527 uint8_t denominator_scales
[2];
2529 /* How to map sampled ycbcr planes to a single 4 component element. */
2530 struct isl_swizzle ycbcr_swizzle
;
2535 struct anv_format_plane planes
[3];
2540 static inline uint32_t
2541 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2542 VkImageAspectFlags aspect_mask
)
2544 switch (aspect_mask
) {
2545 case VK_IMAGE_ASPECT_COLOR_BIT
:
2546 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2547 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2549 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2550 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2553 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2555 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2558 /* Purposefully assert with depth/stencil aspects. */
2559 unreachable("invalid image aspect");
2563 static inline uint32_t
2564 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask
)
2566 uint32_t planes
= 0;
2568 if (aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
|
2569 VK_IMAGE_ASPECT_DEPTH_BIT
|
2570 VK_IMAGE_ASPECT_STENCIL_BIT
|
2571 VK_IMAGE_ASPECT_PLANE_0_BIT
))
2573 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_1_BIT
)
2575 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_2_BIT
)
2578 if ((aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) != 0 &&
2579 (aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) != 0)
2585 static inline VkImageAspectFlags
2586 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
2589 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2590 if (util_bitcount(image_aspects
) > 1)
2591 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
2592 return VK_IMAGE_ASPECT_COLOR_BIT
;
2594 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
2595 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
2596 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
2597 return VK_IMAGE_ASPECT_STENCIL_BIT
;
2600 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2601 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2603 const struct anv_format
*
2604 anv_get_format(VkFormat format
);
2606 static inline uint32_t
2607 anv_get_format_planes(VkFormat vk_format
)
2609 const struct anv_format
*format
= anv_get_format(vk_format
);
2611 return format
!= NULL
? format
->n_planes
: 0;
2614 struct anv_format_plane
2615 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2616 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
2618 static inline enum isl_format
2619 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2620 VkImageAspectFlags aspect
, VkImageTiling tiling
)
2622 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
2625 static inline struct isl_swizzle
2626 anv_swizzle_for_render(struct isl_swizzle swizzle
)
2628 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2629 * RGB as RGBA for texturing
2631 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
2632 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
2634 /* But it doesn't matter what we render to that channel */
2635 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
2641 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
2644 * Subsurface of an anv_image.
2646 struct anv_surface
{
2647 /** Valid only if isl_surf::size_B > 0. */
2648 struct isl_surf isl
;
2651 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2658 /* The original VkFormat provided by the client. This may not match any
2659 * of the actual surface formats.
2662 const struct anv_format
*format
;
2664 VkImageAspectFlags aspects
;
2667 uint32_t array_size
;
2668 uint32_t samples
; /**< VkImageCreateInfo::samples */
2670 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2671 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2673 /** True if this is needs to be bound to an appropriately tiled BO.
2675 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2676 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2677 * we require a dedicated allocation so that we can know to allocate a
2680 bool needs_set_tiling
;
2683 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2684 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2686 uint64_t drm_format_mod
;
2691 /* Whether the image is made of several underlying buffer objects rather a
2692 * single one with different offsets.
2699 * For each foo, anv_image::planes[x].surface is valid if and only if
2700 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2701 * to figure the number associated with a given aspect.
2703 * The hardware requires that the depth buffer and stencil buffer be
2704 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2705 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2706 * allocate the depth and stencil buffers as separate surfaces in the same
2711 * -----------------------
2713 * ----------------------- |
2714 * | shadow surface0 | |
2715 * ----------------------- | Plane 0
2716 * | aux surface0 | |
2717 * ----------------------- |
2718 * | fast clear colors0 | \|/
2719 * -----------------------
2721 * ----------------------- |
2722 * | shadow surface1 | |
2723 * ----------------------- | Plane 1
2724 * | aux surface1 | |
2725 * ----------------------- |
2726 * | fast clear colors1 | \|/
2727 * -----------------------
2730 * -----------------------
2734 * Offset of the entire plane (whenever the image is disjoint this is
2742 struct anv_surface surface
;
2745 * A surface which shadows the main surface and may have different
2746 * tiling. This is used for sampling using a tiling that isn't supported
2747 * for other operations.
2749 struct anv_surface shadow_surface
;
2752 * For color images, this is the aux usage for this image when not used
2753 * as a color attachment.
2755 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2756 * image has a HiZ buffer.
2758 enum isl_aux_usage aux_usage
;
2760 struct anv_surface aux_surface
;
2763 * Offset of the fast clear state (used to compute the
2764 * fast_clear_state_offset of the following planes).
2766 uint32_t fast_clear_state_offset
;
2769 * BO associated with this plane, set when bound.
2771 struct anv_address address
;
2774 * When destroying the image, also free the bo.
2780 /* The ordering of this enum is important */
2781 enum anv_fast_clear_type
{
2782 /** Image does not have/support any fast-clear blocks */
2783 ANV_FAST_CLEAR_NONE
= 0,
2784 /** Image has/supports fast-clear but only to the default value */
2785 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
2786 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2787 ANV_FAST_CLEAR_ANY
= 2,
2790 /* Returns the number of auxiliary buffer levels attached to an image. */
2791 static inline uint8_t
2792 anv_image_aux_levels(const struct anv_image
* const image
,
2793 VkImageAspectFlagBits aspect
)
2795 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2796 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
2797 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
2800 /* Returns the number of auxiliary buffer layers attached to an image. */
2801 static inline uint32_t
2802 anv_image_aux_layers(const struct anv_image
* const image
,
2803 VkImageAspectFlagBits aspect
,
2804 const uint8_t miplevel
)
2808 /* The miplevel must exist in the main buffer. */
2809 assert(miplevel
< image
->levels
);
2811 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
2812 /* There are no layers with auxiliary data because the miplevel has no
2817 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2818 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
2819 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
2823 static inline struct anv_address
2824 anv_image_get_clear_color_addr(const struct anv_device
*device
,
2825 const struct anv_image
*image
,
2826 VkImageAspectFlagBits aspect
)
2828 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
2830 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2831 return anv_address_add(image
->planes
[plane
].address
,
2832 image
->planes
[plane
].fast_clear_state_offset
);
2835 static inline struct anv_address
2836 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
2837 const struct anv_image
*image
,
2838 VkImageAspectFlagBits aspect
)
2840 struct anv_address addr
=
2841 anv_image_get_clear_color_addr(device
, image
, aspect
);
2843 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
2844 device
->isl_dev
.ss
.clear_color_state_size
:
2845 device
->isl_dev
.ss
.clear_value_size
;
2846 addr
.offset
+= clear_color_state_size
;
2850 static inline struct anv_address
2851 anv_image_get_compression_state_addr(const struct anv_device
*device
,
2852 const struct anv_image
*image
,
2853 VkImageAspectFlagBits aspect
,
2854 uint32_t level
, uint32_t array_layer
)
2856 assert(level
< anv_image_aux_levels(image
, aspect
));
2857 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
2858 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2859 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
2861 struct anv_address addr
=
2862 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
2863 addr
.offset
+= 4; /* Go past the fast clear type */
2865 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2866 for (uint32_t l
= 0; l
< level
; l
++)
2867 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
2869 addr
.offset
+= level
* image
->array_size
* 4;
2871 addr
.offset
+= array_layer
* 4;
2876 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2878 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
2879 const struct anv_image
*image
)
2881 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
2884 if (devinfo
->gen
< 8)
2887 return image
->samples
== 1;
2891 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
2892 const struct anv_image
*image
,
2893 VkImageAspectFlagBits aspect
,
2894 enum isl_aux_usage aux_usage
,
2896 uint32_t base_layer
,
2897 uint32_t layer_count
);
2900 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
2901 const struct anv_image
*image
,
2902 VkImageAspectFlagBits aspect
,
2903 enum isl_aux_usage aux_usage
,
2904 enum isl_format format
, struct isl_swizzle swizzle
,
2905 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
2906 VkRect2D area
, union isl_color_value clear_color
);
2908 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
2909 const struct anv_image
*image
,
2910 VkImageAspectFlags aspects
,
2911 enum isl_aux_usage depth_aux_usage
,
2913 uint32_t base_layer
, uint32_t layer_count
,
2915 float depth_value
, uint8_t stencil_value
);
2917 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
2918 const struct anv_image
*image
,
2919 VkImageAspectFlagBits aspect
, uint32_t level
,
2920 uint32_t base_layer
, uint32_t layer_count
,
2921 enum isl_aux_op hiz_op
);
2923 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
2924 const struct anv_image
*image
,
2925 VkImageAspectFlags aspects
,
2927 uint32_t base_layer
, uint32_t layer_count
,
2928 VkRect2D area
, uint8_t stencil_value
);
2930 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
2931 const struct anv_image
*image
,
2932 VkImageAspectFlagBits aspect
,
2933 uint32_t base_layer
, uint32_t layer_count
,
2934 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
2937 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
2938 const struct anv_image
*image
,
2939 VkImageAspectFlagBits aspect
, uint32_t level
,
2940 uint32_t base_layer
, uint32_t layer_count
,
2941 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
2945 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
2946 const struct anv_image
*image
,
2947 uint32_t base_level
, uint32_t level_count
,
2948 uint32_t base_layer
, uint32_t layer_count
);
2951 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
2952 const struct anv_image
*image
,
2953 const VkImageAspectFlagBits aspect
,
2954 const VkImageLayout layout
);
2956 enum anv_fast_clear_type
2957 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
2958 const struct anv_image
* const image
,
2959 const VkImageAspectFlagBits aspect
,
2960 const VkImageLayout layout
);
2962 /* This is defined as a macro so that it works for both
2963 * VkImageSubresourceRange and VkImageSubresourceLayers
2965 #define anv_get_layerCount(_image, _range) \
2966 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2967 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2969 static inline uint32_t
2970 anv_get_levelCount(const struct anv_image
*image
,
2971 const VkImageSubresourceRange
*range
)
2973 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
2974 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
2977 static inline VkImageAspectFlags
2978 anv_image_expand_aspects(const struct anv_image
*image
,
2979 VkImageAspectFlags aspects
)
2981 /* If the underlying image has color plane aspects and
2982 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2983 * the underlying image. */
2984 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
2985 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
2986 return image
->aspects
;
2992 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
2993 VkImageAspectFlags aspects2
)
2995 if (aspects1
== aspects2
)
2998 /* Only 1 color aspects are compatibles. */
2999 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3000 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3001 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3007 struct anv_image_view
{
3008 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3010 VkImageAspectFlags aspect_mask
;
3012 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3016 uint32_t image_plane
;
3018 struct isl_view isl
;
3021 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3022 * image layout of SHADER_READ_ONLY_OPTIMAL or
3023 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3025 struct anv_surface_state optimal_sampler_surface_state
;
3028 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3029 * image layout of GENERAL.
3031 struct anv_surface_state general_sampler_surface_state
;
3034 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3035 * states for write-only and readable, using the real format for
3036 * write-only and the lowered format for readable.
3038 struct anv_surface_state storage_surface_state
;
3039 struct anv_surface_state writeonly_storage_surface_state
;
3041 struct brw_image_param storage_image_param
;
3045 enum anv_image_view_state_flags
{
3046 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3047 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3050 void anv_image_fill_surface_state(struct anv_device
*device
,
3051 const struct anv_image
*image
,
3052 VkImageAspectFlagBits aspect
,
3053 const struct isl_view
*view
,
3054 isl_surf_usage_flags_t view_usage
,
3055 enum isl_aux_usage aux_usage
,
3056 const union isl_color_value
*clear_color
,
3057 enum anv_image_view_state_flags flags
,
3058 struct anv_surface_state
*state_inout
,
3059 struct brw_image_param
*image_param_out
);
3061 struct anv_image_create_info
{
3062 const VkImageCreateInfo
*vk_info
;
3064 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3065 isl_tiling_flags_t isl_tiling_flags
;
3067 /** These flags will be added to any derived from VkImageCreateInfo. */
3068 isl_surf_usage_flags_t isl_extra_usage_flags
;
3073 VkResult
anv_image_create(VkDevice _device
,
3074 const struct anv_image_create_info
*info
,
3075 const VkAllocationCallbacks
* alloc
,
3079 VkResult
anv_image_from_gralloc(VkDevice device_h
,
3080 const VkImageCreateInfo
*base_info
,
3081 const VkNativeBufferANDROID
*gralloc_info
,
3082 const VkAllocationCallbacks
*alloc
,
3086 const struct anv_surface
*
3087 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3088 VkImageAspectFlags aspect_mask
);
3091 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3093 static inline struct VkExtent3D
3094 anv_sanitize_image_extent(const VkImageType imageType
,
3095 const struct VkExtent3D imageExtent
)
3097 switch (imageType
) {
3098 case VK_IMAGE_TYPE_1D
:
3099 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3100 case VK_IMAGE_TYPE_2D
:
3101 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3102 case VK_IMAGE_TYPE_3D
:
3105 unreachable("invalid image type");
3109 static inline struct VkOffset3D
3110 anv_sanitize_image_offset(const VkImageType imageType
,
3111 const struct VkOffset3D imageOffset
)
3113 switch (imageType
) {
3114 case VK_IMAGE_TYPE_1D
:
3115 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3116 case VK_IMAGE_TYPE_2D
:
3117 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3118 case VK_IMAGE_TYPE_3D
:
3121 unreachable("invalid image type");
3126 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3127 struct anv_state state
,
3128 enum isl_format format
,
3129 struct anv_address address
,
3130 uint32_t range
, uint32_t stride
);
3133 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3134 const struct anv_attachment_state
*att_state
,
3135 const struct anv_image_view
*iview
)
3137 const struct isl_format_layout
*view_fmtl
=
3138 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3140 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3141 if (view_fmtl->channels.c.bits) \
3142 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3144 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3145 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3146 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3147 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3149 #undef COPY_CLEAR_COLOR_CHANNEL
3153 struct anv_ycbcr_conversion
{
3154 const struct anv_format
* format
;
3155 VkSamplerYcbcrModelConversion ycbcr_model
;
3156 VkSamplerYcbcrRange ycbcr_range
;
3157 VkComponentSwizzle mapping
[4];
3158 VkChromaLocation chroma_offsets
[2];
3159 VkFilter chroma_filter
;
3160 bool chroma_reconstruction
;
3163 struct anv_sampler
{
3164 uint32_t state
[3][4];
3166 struct anv_ycbcr_conversion
*conversion
;
3169 struct anv_framebuffer
{
3174 uint32_t attachment_count
;
3175 struct anv_image_view
* attachments
[0];
3178 struct anv_subpass_attachment
{
3179 VkImageUsageFlagBits usage
;
3180 uint32_t attachment
;
3181 VkImageLayout layout
;
3184 struct anv_subpass
{
3185 uint32_t attachment_count
;
3188 * A pointer to all attachment references used in this subpass.
3189 * Only valid if ::attachment_count > 0.
3191 struct anv_subpass_attachment
* attachments
;
3192 uint32_t input_count
;
3193 struct anv_subpass_attachment
* input_attachments
;
3194 uint32_t color_count
;
3195 struct anv_subpass_attachment
* color_attachments
;
3196 struct anv_subpass_attachment
* resolve_attachments
;
3198 struct anv_subpass_attachment
* depth_stencil_attachment
;
3202 /** Subpass has a depth/stencil self-dependency */
3203 bool has_ds_self_dep
;
3205 /** Subpass has at least one resolve attachment */
3209 static inline unsigned
3210 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3212 return MAX2(1, util_bitcount(subpass
->view_mask
));
3215 struct anv_render_pass_attachment
{
3216 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3217 * its members individually.
3221 VkImageUsageFlags usage
;
3222 VkAttachmentLoadOp load_op
;
3223 VkAttachmentStoreOp store_op
;
3224 VkAttachmentLoadOp stencil_load_op
;
3225 VkImageLayout initial_layout
;
3226 VkImageLayout final_layout
;
3227 VkImageLayout first_subpass_layout
;
3229 /* The subpass id in which the attachment will be used last. */
3230 uint32_t last_subpass_idx
;
3233 struct anv_render_pass
{
3234 uint32_t attachment_count
;
3235 uint32_t subpass_count
;
3236 /* An array of subpass_count+1 flushes, one per subpass boundary */
3237 enum anv_pipe_bits
* subpass_flushes
;
3238 struct anv_render_pass_attachment
* attachments
;
3239 struct anv_subpass subpasses
[0];
3242 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3244 struct anv_query_pool
{
3246 VkQueryPipelineStatisticFlags pipeline_statistics
;
3247 /** Stride between slots, in bytes */
3249 /** Number of slots in this query pool */
3254 int anv_get_instance_entrypoint_index(const char *name
);
3255 int anv_get_device_entrypoint_index(const char *name
);
3258 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3259 const struct anv_instance_extension_table
*instance
);
3262 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3263 const struct anv_instance_extension_table
*instance
,
3264 const struct anv_device_extension_table
*device
);
3266 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3269 void anv_dump_image_to_ppm(struct anv_device
*device
,
3270 struct anv_image
*image
, unsigned miplevel
,
3271 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3272 const char *filename
);
3274 enum anv_dump_action
{
3275 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3278 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3279 void anv_dump_finish(void);
3281 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
3282 struct anv_framebuffer
*fb
);
3284 static inline uint32_t
3285 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3287 /* This function must be called from within a subpass. */
3288 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3290 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3292 /* The id of this subpass shouldn't exceed the number of subpasses in this
3293 * render pass minus 1.
3295 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3299 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3301 static inline struct __anv_type * \
3302 __anv_type ## _from_handle(__VkType _handle) \
3304 return (struct __anv_type *) _handle; \
3307 static inline __VkType \
3308 __anv_type ## _to_handle(struct __anv_type *_obj) \
3310 return (__VkType) _obj; \
3313 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3315 static inline struct __anv_type * \
3316 __anv_type ## _from_handle(__VkType _handle) \
3318 return (struct __anv_type *)(uintptr_t) _handle; \
3321 static inline __VkType \
3322 __anv_type ## _to_handle(struct __anv_type *_obj) \
3324 return (__VkType)(uintptr_t) _obj; \
3327 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3328 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3330 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3331 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3332 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3333 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3334 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3336 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3337 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3338 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3339 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3340 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3341 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3342 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
3343 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3344 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3345 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3346 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3347 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3348 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3349 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3350 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3351 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3352 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3353 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3354 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3355 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3356 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3357 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3358 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3360 /* Gen-specific function declarations */
3362 # include "anv_genX.h"
3364 # define genX(x) gen7_##x
3365 # include "anv_genX.h"
3367 # define genX(x) gen75_##x
3368 # include "anv_genX.h"
3370 # define genX(x) gen8_##x
3371 # include "anv_genX.h"
3373 # define genX(x) gen9_##x
3374 # include "anv_genX.h"
3376 # define genX(x) gen10_##x
3377 # include "anv_genX.h"
3379 # define genX(x) gen11_##x
3380 # include "anv_genX.h"
3384 #endif /* ANV_PRIVATE_H */