2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
52 /* Pre-declarations needed for WSI entrypoints */
55 typedef struct xcb_connection_t xcb_connection_t
;
56 typedef uint32_t xcb_visualid_t
;
57 typedef uint32_t xcb_window_t
;
61 #include <vulkan/vulkan.h>
62 #include <vulkan/vulkan_intel.h>
63 #include <vulkan/vk_icd.h>
65 #include "anv_entrypoints.h"
66 #include "brw_context.h"
69 #include "wsi_common.h"
71 /* Allowing different clear colors requires us to perform a depth resolve at
72 * the end of certain render passes. This is because while slow clears store
73 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
74 * See the PRMs for examples describing when additional resolves would be
75 * necessary. To enable fast clears without requiring extra resolves, we set
76 * the clear value to a globally-defined one. We could allow different values
77 * if the user doesn't expect coherent data during or after a render passes
78 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
79 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
80 * 1.0f seems to be the only value used. The only application that doesn't set
81 * this value does so through the usage of an seemingly uninitialized clear
84 #define ANV_HZ_FC_VAL 1.0f
89 #define MAX_VIEWPORTS 16
90 #define MAX_SCISSORS 16
91 #define MAX_PUSH_CONSTANTS_SIZE 128
92 #define MAX_DYNAMIC_BUFFERS 16
95 #define ANV_SVGS_VB_INDEX MAX_VBS
96 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
98 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
100 static inline uint32_t
101 align_down_npot_u32(uint32_t v
, uint32_t a
)
106 static inline uint32_t
107 align_u32(uint32_t v
, uint32_t a
)
109 assert(a
!= 0 && a
== (a
& -a
));
110 return (v
+ a
- 1) & ~(a
- 1);
113 static inline uint64_t
114 align_u64(uint64_t v
, uint64_t a
)
116 assert(a
!= 0 && a
== (a
& -a
));
117 return (v
+ a
- 1) & ~(a
- 1);
120 static inline int32_t
121 align_i32(int32_t v
, int32_t a
)
123 assert(a
!= 0 && a
== (a
& -a
));
124 return (v
+ a
- 1) & ~(a
- 1);
127 /** Alignment must be a power of 2. */
129 anv_is_aligned(uintmax_t n
, uintmax_t a
)
131 assert(a
== (a
& -a
));
132 return (n
& (a
- 1)) == 0;
135 static inline uint32_t
136 anv_minify(uint32_t n
, uint32_t levels
)
138 if (unlikely(n
== 0))
141 return MAX2(n
>> levels
, 1);
145 anv_clamp_f(float f
, float min
, float max
)
158 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
160 if (*inout_mask
& clear_mask
) {
161 *inout_mask
&= ~clear_mask
;
168 static inline union isl_color_value
169 vk_to_isl_color(VkClearColorValue color
)
171 return (union isl_color_value
) {
181 #define for_each_bit(b, dword) \
182 for (uint32_t __dword = (dword); \
183 (b) = __builtin_ffs(__dword) - 1, __dword; \
184 __dword &= ~(1 << (b)))
186 #define typed_memcpy(dest, src, count) ({ \
187 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
188 memcpy((dest), (src), (count) * sizeof(*(src))); \
191 /* Whenever we generate an error, pass it through this function. Useful for
192 * debugging, where we can break on it. Only call at error site, not when
193 * propagating errors. Might be useful to plug in a stack trace here.
196 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
199 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
200 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
201 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
203 #define vk_error(error) error
204 #define vk_errorf(error, format, ...) error
205 #define anv_debug(format, ...)
209 * Warn on ignored extension structs.
211 * The Vulkan spec requires us to ignore unsupported or unknown structs in
212 * a pNext chain. In debug mode, emitting warnings for ignored structs may
213 * help us discover structs that we should not have ignored.
216 * From the Vulkan 1.0.38 spec:
218 * Any component of the implementation (the loader, any enabled layers,
219 * and drivers) must skip over, without processing (other than reading the
220 * sType and pNext members) any chained structures with sType values not
221 * defined by extensions supported by that component.
223 #define anv_debug_ignored_stype(sType) \
224 anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType))
226 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
227 anv_printflike(3, 4);
228 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
229 void anv_loge_v(const char *format
, va_list va
);
232 * Print a FINISHME message, including its source location.
234 #define anv_finishme(format, ...) \
236 static bool reported = false; \
238 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
243 /* A non-fatal assert. Useful for debugging. */
245 #define anv_assert(x) ({ \
246 if (unlikely(!(x))) \
247 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
250 #define anv_assert(x)
254 * If a block of code is annotated with anv_validate, then the block runs only
258 #define anv_validate if (1)
260 #define anv_validate if (0)
263 #define stub_return(v) \
265 anv_finishme("stub %s", __func__); \
271 anv_finishme("stub %s", __func__); \
276 * A dynamically growable, circular buffer. Elements are added at head and
277 * removed from tail. head and tail are free-running uint32_t indices and we
278 * only compute the modulo with size when accessing the array. This way,
279 * number of bytes in the queue is always head - tail, even in case of
286 /* Index into the current validation list. This is used by the
287 * validation list building alrogithm to track which buffers are already
288 * in the validation list so that we can ensure uniqueness.
292 /* Last known offset. This value is provided by the kernel when we
293 * execbuf and is used as the presumed offset for the next bunch of
301 /* We need to set the WRITE flag on winsys bos so GEM will know we're
302 * writing to them and synchronize uses on other rings (eg if the display
303 * server uses the blitter ring).
309 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
311 bo
->gem_handle
= gem_handle
;
316 bo
->is_winsys_bo
= false;
319 /* Represents a lock-free linked list of "free" things. This is used by
320 * both the block pool and the state pools. Unfortunately, in order to
321 * solve the ABA problem, we can't use a single uint32_t head.
323 union anv_free_list
{
327 /* A simple count that is incremented every time the head changes. */
333 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
335 struct anv_block_state
{
345 struct anv_block_pool
{
346 struct anv_device
*device
;
350 /* The offset from the start of the bo to the "center" of the block
351 * pool. Pointers to allocated blocks are given by
352 * bo.map + center_bo_offset + offsets.
354 uint32_t center_bo_offset
;
356 /* Current memory map of the block pool. This pointer may or may not
357 * point to the actual beginning of the block pool memory. If
358 * anv_block_pool_alloc_back has ever been called, then this pointer
359 * will point to the "center" position of the buffer and all offsets
360 * (negative or positive) given out by the block pool alloc functions
361 * will be valid relative to this pointer.
363 * In particular, map == bo.map + center_offset
369 * Array of mmaps and gem handles owned by the block pool, reclaimed when
370 * the block pool is destroyed.
372 struct u_vector mmap_cleanups
;
376 union anv_free_list free_list
;
377 struct anv_block_state state
;
379 union anv_free_list back_free_list
;
380 struct anv_block_state back_state
;
383 /* Block pools are backed by a fixed-size 2GB memfd */
384 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
386 /* The center of the block pool is also the middle of the memfd. This may
387 * change in the future if we decide differently for some reason.
389 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
391 static inline uint32_t
392 anv_block_pool_size(struct anv_block_pool
*pool
)
394 return pool
->state
.end
+ pool
->back_state
.end
;
403 struct anv_fixed_size_state_pool
{
405 union anv_free_list free_list
;
406 struct anv_block_state block
;
409 #define ANV_MIN_STATE_SIZE_LOG2 6
410 #define ANV_MAX_STATE_SIZE_LOG2 20
412 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
414 struct anv_state_pool
{
415 struct anv_block_pool
*block_pool
;
416 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
419 struct anv_state_stream_block
;
421 struct anv_state_stream
{
422 struct anv_block_pool
*block_pool
;
424 /* The current working block */
425 struct anv_state_stream_block
*block
;
427 /* Offset at which the current block starts */
429 /* Offset at which to allocate the next state */
431 /* Offset at which the current block ends */
435 #define CACHELINE_SIZE 64
436 #define CACHELINE_MASK 63
439 anv_clflush_range(void *start
, size_t size
)
441 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
442 void *end
= start
+ size
;
444 __builtin_ia32_mfence();
446 __builtin_ia32_clflush(p
);
452 anv_invalidate_range(void *start
, size_t size
)
454 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
455 void *end
= start
+ size
;
458 __builtin_ia32_clflush(p
);
461 __builtin_ia32_mfence();
465 anv_state_clflush(struct anv_state state
)
467 anv_clflush_range(state
.map
, state
.alloc_size
);
470 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
471 struct anv_device
*device
, uint32_t block_size
);
472 void anv_block_pool_finish(struct anv_block_pool
*pool
);
473 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
);
474 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
);
475 void anv_block_pool_free(struct anv_block_pool
*pool
, int32_t offset
);
476 void anv_state_pool_init(struct anv_state_pool
*pool
,
477 struct anv_block_pool
*block_pool
);
478 void anv_state_pool_finish(struct anv_state_pool
*pool
);
479 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
480 size_t state_size
, size_t alignment
);
481 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
482 void anv_state_stream_init(struct anv_state_stream
*stream
,
483 struct anv_block_pool
*block_pool
);
484 void anv_state_stream_finish(struct anv_state_stream
*stream
);
485 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
486 uint32_t size
, uint32_t alignment
);
489 * Implements a pool of re-usable BOs. The interface is identical to that
490 * of block_pool except that each block is its own BO.
493 struct anv_device
*device
;
498 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
499 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
500 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
502 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
504 struct anv_scratch_bo
{
509 struct anv_scratch_pool
{
510 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
511 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
514 void anv_scratch_pool_init(struct anv_device
*device
,
515 struct anv_scratch_pool
*pool
);
516 void anv_scratch_pool_finish(struct anv_device
*device
,
517 struct anv_scratch_pool
*pool
);
518 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
519 struct anv_scratch_pool
*pool
,
520 gl_shader_stage stage
,
521 unsigned per_thread_scratch
);
523 struct anv_physical_device
{
524 VK_LOADER_DATA _loader_data
;
526 struct anv_instance
* instance
;
530 struct gen_device_info info
;
531 uint64_t aperture_size
;
532 struct brw_compiler
* compiler
;
533 struct isl_device isl_dev
;
534 int cmd_parser_version
;
537 uint32_t subslice_total
;
539 uint8_t uuid
[VK_UUID_SIZE
];
541 struct wsi_device wsi_device
;
545 struct anv_instance
{
546 VK_LOADER_DATA _loader_data
;
548 VkAllocationCallbacks alloc
;
551 int physicalDeviceCount
;
552 struct anv_physical_device physicalDevice
;
555 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
556 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
559 VK_LOADER_DATA _loader_data
;
561 struct anv_device
* device
;
563 struct anv_state_pool
* pool
;
566 struct anv_pipeline_cache
{
567 struct anv_device
* device
;
568 pthread_mutex_t mutex
;
570 struct hash_table
* cache
;
573 struct anv_pipeline_bind_map
;
575 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
576 struct anv_device
*device
,
578 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
580 struct anv_shader_bin
*
581 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
582 const void *key
, uint32_t key_size
);
583 struct anv_shader_bin
*
584 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
585 const void *key_data
, uint32_t key_size
,
586 const void *kernel_data
, uint32_t kernel_size
,
587 const struct brw_stage_prog_data
*prog_data
,
588 uint32_t prog_data_size
,
589 const struct anv_pipeline_bind_map
*bind_map
);
592 VK_LOADER_DATA _loader_data
;
594 VkAllocationCallbacks alloc
;
596 struct anv_instance
* instance
;
598 struct gen_device_info info
;
599 struct isl_device isl_dev
;
602 bool can_chain_batches
;
603 bool robust_buffer_access
;
605 struct anv_bo_pool batch_bo_pool
;
607 struct anv_block_pool dynamic_state_block_pool
;
608 struct anv_state_pool dynamic_state_pool
;
610 struct anv_block_pool instruction_block_pool
;
611 struct anv_state_pool instruction_state_pool
;
613 struct anv_block_pool surface_state_block_pool
;
614 struct anv_state_pool surface_state_pool
;
616 struct anv_bo workaround_bo
;
618 struct anv_pipeline_cache blorp_shader_cache
;
619 struct blorp_context blorp
;
621 struct anv_state border_colors
;
623 struct anv_queue queue
;
625 struct anv_scratch_pool scratch_pool
;
627 uint32_t default_mocs
;
629 pthread_mutex_t mutex
;
630 pthread_cond_t queue_submit
;
633 void anv_device_init_blorp(struct anv_device
*device
);
634 void anv_device_finish_blorp(struct anv_device
*device
);
636 VkResult
anv_device_execbuf(struct anv_device
*device
,
637 struct drm_i915_gem_execbuffer2
*execbuf
,
638 struct anv_bo
**execbuf_bos
);
640 void* anv_gem_mmap(struct anv_device
*device
,
641 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
642 void anv_gem_munmap(void *p
, uint64_t size
);
643 uint32_t anv_gem_create(struct anv_device
*device
, size_t size
);
644 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
645 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
646 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
647 int anv_gem_execbuffer(struct anv_device
*device
,
648 struct drm_i915_gem_execbuffer2
*execbuf
);
649 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
650 uint32_t stride
, uint32_t tiling
);
651 int anv_gem_create_context(struct anv_device
*device
);
652 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
653 int anv_gem_get_param(int fd
, uint32_t param
);
654 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
655 int anv_gem_get_aperture(int fd
, uint64_t *size
);
656 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
657 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
658 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
659 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
660 uint32_t read_domains
, uint32_t write_domain
);
662 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
664 struct anv_reloc_list
{
667 struct drm_i915_gem_relocation_entry
* relocs
;
668 struct anv_bo
** reloc_bos
;
671 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
672 const VkAllocationCallbacks
*alloc
);
673 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
674 const VkAllocationCallbacks
*alloc
);
676 uint64_t anv_reloc_list_add(struct anv_reloc_list
*list
,
677 const VkAllocationCallbacks
*alloc
,
678 uint32_t offset
, struct anv_bo
*target_bo
,
681 struct anv_batch_bo
{
682 /* Link in the anv_cmd_buffer.owned_batch_bos list */
683 struct list_head link
;
687 /* Bytes actually consumed in this batch BO */
690 struct anv_reloc_list relocs
;
694 const VkAllocationCallbacks
* alloc
;
700 struct anv_reloc_list
* relocs
;
702 /* This callback is called (with the associated user data) in the event
703 * that the batch runs out of space.
705 VkResult (*extend_cb
)(struct anv_batch
*, void *);
709 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
710 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
711 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
712 void *location
, struct anv_bo
*bo
, uint32_t offset
);
713 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
714 struct anv_batch
*batch
);
721 static inline uint64_t
722 _anv_combine_address(struct anv_batch
*batch
, void *location
,
723 const struct anv_address address
, uint32_t delta
)
725 if (address
.bo
== NULL
) {
726 return address
.offset
+ delta
;
728 assert(batch
->start
<= location
&& location
< batch
->end
);
730 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
734 #define __gen_address_type struct anv_address
735 #define __gen_user_data struct anv_batch
736 #define __gen_combine_address _anv_combine_address
738 /* Wrapper macros needed to work around preprocessor argument issues. In
739 * particular, arguments don't get pre-evaluated if they are concatenated.
740 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
741 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
742 * We can work around this easily enough with these helpers.
744 #define __anv_cmd_length(cmd) cmd ## _length
745 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
746 #define __anv_cmd_header(cmd) cmd ## _header
747 #define __anv_cmd_pack(cmd) cmd ## _pack
748 #define __anv_reg_num(reg) reg ## _num
750 #define anv_pack_struct(dst, struc, ...) do { \
751 struct struc __template = { \
754 __anv_cmd_pack(struc)(NULL, dst, &__template); \
755 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
758 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
759 void *__dst = anv_batch_emit_dwords(batch, n); \
760 struct cmd __template = { \
761 __anv_cmd_header(cmd), \
762 .DWordLength = n - __anv_cmd_length_bias(cmd), \
765 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
769 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
773 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
774 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
775 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
776 dw[i] = (dwords0)[i] | (dwords1)[i]; \
777 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
780 #define anv_batch_emit(batch, cmd, name) \
781 for (struct cmd name = { __anv_cmd_header(cmd) }, \
782 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
783 __builtin_expect(_dst != NULL, 1); \
784 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
785 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
789 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
790 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
791 struct anv_state __state = \
792 anv_state_pool_alloc((pool), __size, align); \
793 struct cmd __template = { \
796 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
797 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
798 if (!(pool)->block_pool->device->info.has_llc) \
799 anv_state_clflush(__state); \
803 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
804 .GraphicsDataTypeGFDT = 0, \
805 .LLCCacheabilityControlLLCCC = 0, \
806 .L3CacheabilityControlL3CC = 1, \
809 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
810 .LLCeLLCCacheabilityControlLLCCC = 0, \
811 .L3CacheabilityControlL3CC = 1, \
814 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
815 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
816 .TargetCache = L3DefertoPATforLLCeLLCselection, \
820 /* Skylake: MOCS is now an index into an array of 62 different caching
821 * configurations programmed by the kernel.
824 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
825 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
826 .IndextoMOCSTables = 2 \
829 #define GEN9_MOCS_PTE { \
830 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
831 .IndextoMOCSTables = 1 \
834 struct anv_device_memory
{
837 VkDeviceSize map_size
;
842 * Header for Vertex URB Entry (VUE)
844 struct anv_vue_header
{
846 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
847 uint32_t ViewportIndex
;
851 struct anv_descriptor_set_binding_layout
{
853 /* The type of the descriptors in this binding */
854 VkDescriptorType type
;
857 /* Number of array elements in this binding */
860 /* Index into the flattend descriptor set */
861 uint16_t descriptor_index
;
863 /* Index into the dynamic state array for a dynamic buffer */
864 int16_t dynamic_offset_index
;
866 /* Index into the descriptor set buffer views */
867 int16_t buffer_index
;
870 /* Index into the binding table for the associated surface */
871 int16_t surface_index
;
873 /* Index into the sampler table for the associated sampler */
874 int16_t sampler_index
;
876 /* Index into the image table for the associated image */
878 } stage
[MESA_SHADER_STAGES
];
880 /* Immutable samplers (or NULL if no immutable samplers) */
881 struct anv_sampler
**immutable_samplers
;
884 struct anv_descriptor_set_layout
{
885 /* Number of bindings in this descriptor set */
886 uint16_t binding_count
;
888 /* Total size of the descriptor set with room for all array entries */
891 /* Shader stages affected by this descriptor set */
892 uint16_t shader_stages
;
894 /* Number of buffers in this descriptor set */
895 uint16_t buffer_count
;
897 /* Number of dynamic offsets used by this descriptor set */
898 uint16_t dynamic_offset_count
;
900 /* Bindings in this descriptor set */
901 struct anv_descriptor_set_binding_layout binding
[0];
904 struct anv_descriptor
{
905 VkDescriptorType type
;
909 struct anv_image_view
*image_view
;
910 struct anv_sampler
*sampler
;
913 struct anv_buffer_view
*buffer_view
;
917 struct anv_descriptor_set
{
918 const struct anv_descriptor_set_layout
*layout
;
920 uint32_t buffer_count
;
921 struct anv_buffer_view
*buffer_views
;
922 struct anv_descriptor descriptors
[0];
925 struct anv_descriptor_pool
{
930 struct anv_state_stream surface_state_stream
;
931 void *surface_state_free_list
;
937 anv_descriptor_set_create(struct anv_device
*device
,
938 struct anv_descriptor_pool
*pool
,
939 const struct anv_descriptor_set_layout
*layout
,
940 struct anv_descriptor_set
**out_set
);
943 anv_descriptor_set_destroy(struct anv_device
*device
,
944 struct anv_descriptor_pool
*pool
,
945 struct anv_descriptor_set
*set
);
947 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
949 struct anv_pipeline_binding
{
950 /* The descriptor set this surface corresponds to. The special value of
951 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
952 * to a color attachment and not a regular descriptor.
956 /* Binding in the descriptor set */
959 /* Index in the binding */
962 /* Input attachment index (relative to the subpass) */
963 uint8_t input_attachment_index
;
965 /* For a storage image, whether it is write-only */
969 struct anv_pipeline_layout
{
971 struct anv_descriptor_set_layout
*layout
;
972 uint32_t dynamic_offset_start
;
978 bool has_dynamic_offsets
;
979 } stage
[MESA_SHADER_STAGES
];
981 unsigned char sha1
[20];
985 struct anv_device
* device
;
988 VkBufferUsageFlags usage
;
995 enum anv_cmd_dirty_bits
{
996 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
997 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
998 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
999 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1000 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1001 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1002 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1003 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1004 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1005 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1006 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1007 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1008 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1010 typedef uint32_t anv_cmd_dirty_mask_t
;
1012 enum anv_pipe_bits
{
1013 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1014 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1015 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1016 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1017 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1018 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1019 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1020 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1021 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1022 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1023 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1025 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1026 * a flush has happened but not a CS stall. The next time we do any sort
1027 * of invalidation we need to insert a CS stall at that time. Otherwise,
1028 * we would have to CS stall on every flush which could be bad.
1030 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1033 #define ANV_PIPE_FLUSH_BITS ( \
1034 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1035 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1036 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1038 #define ANV_PIPE_STALL_BITS ( \
1039 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1040 ANV_PIPE_DEPTH_STALL_BIT | \
1041 ANV_PIPE_CS_STALL_BIT)
1043 #define ANV_PIPE_INVALIDATE_BITS ( \
1044 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1045 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1046 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1047 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1048 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1049 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1051 struct anv_vertex_binding
{
1052 struct anv_buffer
* buffer
;
1053 VkDeviceSize offset
;
1056 struct anv_push_constants
{
1057 /* Current allocated size of this push constants data structure.
1058 * Because a decent chunk of it may not be used (images on SKL, for
1059 * instance), we won't actually allocate the entire structure up-front.
1063 /* Push constant data provided by the client through vkPushConstants */
1064 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1066 /* Our hardware only provides zero-based vertex and instance id so, in
1067 * order to satisfy the vulkan requirements, we may have to push one or
1068 * both of these into the shader.
1070 uint32_t base_vertex
;
1071 uint32_t base_instance
;
1073 /* Offsets and ranges for dynamically bound buffers */
1077 } dynamic
[MAX_DYNAMIC_BUFFERS
];
1079 /* Image data for image_load_store on pre-SKL */
1080 struct brw_image_param images
[MAX_IMAGES
];
1083 struct anv_dynamic_state
{
1086 VkViewport viewports
[MAX_VIEWPORTS
];
1091 VkRect2D scissors
[MAX_SCISSORS
];
1102 float blend_constants
[4];
1112 } stencil_compare_mask
;
1117 } stencil_write_mask
;
1122 } stencil_reference
;
1125 extern const struct anv_dynamic_state default_dynamic_state
;
1127 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1128 const struct anv_dynamic_state
*src
,
1129 uint32_t copy_mask
);
1132 * Attachment state when recording a renderpass instance.
1134 * The clear value is valid only if there exists a pending clear.
1136 struct anv_attachment_state
{
1137 enum isl_aux_usage aux_usage
;
1138 enum isl_aux_usage input_aux_usage
;
1139 struct anv_state color_rt_state
;
1140 struct anv_state input_att_state
;
1142 VkImageLayout current_layout
;
1143 VkImageAspectFlags pending_clear_aspects
;
1145 VkClearValue clear_value
;
1146 bool clear_color_is_zero_one
;
1149 /** State required while building cmd buffer */
1150 struct anv_cmd_state
{
1151 /* PIPELINE_SELECT.PipelineSelection */
1152 uint32_t current_pipeline
;
1153 const struct gen_l3_config
* current_l3_config
;
1155 anv_cmd_dirty_mask_t dirty
;
1156 anv_cmd_dirty_mask_t compute_dirty
;
1157 enum anv_pipe_bits pending_pipe_bits
;
1158 uint32_t num_workgroups_offset
;
1159 struct anv_bo
*num_workgroups_bo
;
1160 VkShaderStageFlags descriptors_dirty
;
1161 VkShaderStageFlags push_constants_dirty
;
1162 uint32_t scratch_size
;
1163 struct anv_pipeline
* pipeline
;
1164 struct anv_pipeline
* compute_pipeline
;
1165 struct anv_framebuffer
* framebuffer
;
1166 struct anv_render_pass
* pass
;
1167 struct anv_subpass
* subpass
;
1168 VkRect2D render_area
;
1169 uint32_t restart_index
;
1170 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1171 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1172 VkShaderStageFlags push_constant_stages
;
1173 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1174 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1175 struct anv_state samplers
[MESA_SHADER_STAGES
];
1176 struct anv_dynamic_state dynamic
;
1180 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1181 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1182 * and before invoking the secondary in ExecuteCommands.
1184 bool pma_fix_enabled
;
1187 * Whether or not we know for certain that HiZ is enabled for the current
1188 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1189 * enabled or not, this will be false.
1194 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1195 * valid only when recording a render pass instance.
1197 struct anv_attachment_state
* attachments
;
1200 * Surface states for color render targets. These are stored in a single
1201 * flat array. For depth-stencil attachments, the surface state is simply
1204 struct anv_state render_pass_states
;
1207 * A null surface state of the right size to match the framebuffer. This
1208 * is one of the states in render_pass_states.
1210 struct anv_state null_surface_state
;
1213 struct anv_buffer
* index_buffer
;
1214 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1215 uint32_t index_offset
;
1219 struct anv_cmd_pool
{
1220 VkAllocationCallbacks alloc
;
1221 struct list_head cmd_buffers
;
1224 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1226 enum anv_cmd_buffer_exec_mode
{
1227 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1228 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1229 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1230 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1231 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1234 struct anv_cmd_buffer
{
1235 VK_LOADER_DATA _loader_data
;
1237 struct anv_device
* device
;
1239 struct anv_cmd_pool
* pool
;
1240 struct list_head pool_link
;
1242 struct anv_batch batch
;
1244 /* Fields required for the actual chain of anv_batch_bo's.
1246 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1248 struct list_head batch_bos
;
1249 enum anv_cmd_buffer_exec_mode exec_mode
;
1251 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1252 * referenced by this command buffer
1254 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1256 struct u_vector seen_bbos
;
1258 /* A vector of int32_t's for every block of binding tables.
1260 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1262 struct u_vector bt_blocks
;
1265 struct anv_reloc_list surface_relocs
;
1266 /** Last seen surface state block pool center bo offset */
1267 uint32_t last_ss_pool_center
;
1269 /* Serial for tracking buffer completion */
1272 /* Stream objects for storing temporary data */
1273 struct anv_state_stream surface_state_stream
;
1274 struct anv_state_stream dynamic_state_stream
;
1276 VkCommandBufferUsageFlags usage_flags
;
1277 VkCommandBufferLevel level
;
1279 struct anv_cmd_state state
;
1282 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1283 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1284 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1285 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1286 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1287 struct anv_cmd_buffer
*secondary
);
1288 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1289 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1290 struct anv_cmd_buffer
*cmd_buffer
);
1292 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1295 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1296 gl_shader_stage stage
, uint32_t size
);
1297 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1298 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1299 (offsetof(struct anv_push_constants, field) + \
1300 sizeof(cmd_buffer->state.push_constants[0]->field)))
1302 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1303 const void *data
, uint32_t size
, uint32_t alignment
);
1304 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1305 uint32_t *a
, uint32_t *b
,
1306 uint32_t dwords
, uint32_t alignment
);
1309 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1311 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1312 uint32_t entries
, uint32_t *state_offset
);
1314 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1316 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1317 uint32_t size
, uint32_t alignment
);
1320 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1322 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1323 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1324 bool depth_clamp_enable
);
1325 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1327 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1328 struct anv_render_pass
*pass
,
1329 struct anv_framebuffer
*framebuffer
,
1330 const VkClearValue
*clear_values
);
1332 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1335 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1336 gl_shader_stage stage
);
1338 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1340 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1341 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1343 const struct anv_image_view
*
1344 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1347 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1348 uint32_t num_entries
,
1349 uint32_t *state_offset
);
1351 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1353 enum anv_fence_state
{
1354 /** Indicates that this is a new (or newly reset fence) */
1355 ANV_FENCE_STATE_RESET
,
1357 /** Indicates that this fence has been submitted to the GPU but is still
1358 * (as far as we know) in use by the GPU.
1360 ANV_FENCE_STATE_SUBMITTED
,
1362 ANV_FENCE_STATE_SIGNALED
,
1367 struct drm_i915_gem_execbuffer2 execbuf
;
1368 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1369 enum anv_fence_state state
;
1374 struct anv_state state
;
1377 struct anv_shader_module
{
1378 unsigned char sha1
[20];
1383 void anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
1384 struct anv_shader_module
*module
,
1385 const char *entrypoint
,
1386 const struct anv_pipeline_layout
*pipeline_layout
,
1387 const VkSpecializationInfo
*spec_info
);
1389 static inline gl_shader_stage
1390 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1392 assert(__builtin_popcount(vk_stage
) == 1);
1393 return ffs(vk_stage
) - 1;
1396 static inline VkShaderStageFlagBits
1397 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1399 return (1 << mesa_stage
);
1402 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1404 #define anv_foreach_stage(stage, stage_bits) \
1405 for (gl_shader_stage stage, \
1406 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1407 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1408 __tmp &= ~(1 << (stage)))
1410 struct anv_pipeline_bind_map
{
1411 uint32_t surface_count
;
1412 uint32_t sampler_count
;
1413 uint32_t image_count
;
1415 struct anv_pipeline_binding
* surface_to_descriptor
;
1416 struct anv_pipeline_binding
* sampler_to_descriptor
;
1419 struct anv_shader_bin_key
{
1424 struct anv_shader_bin
{
1427 const struct anv_shader_bin_key
*key
;
1429 struct anv_state kernel
;
1430 uint32_t kernel_size
;
1432 const struct brw_stage_prog_data
*prog_data
;
1433 uint32_t prog_data_size
;
1435 struct anv_pipeline_bind_map bind_map
;
1437 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1440 struct anv_shader_bin
*
1441 anv_shader_bin_create(struct anv_device
*device
,
1442 const void *key
, uint32_t key_size
,
1443 const void *kernel
, uint32_t kernel_size
,
1444 const struct brw_stage_prog_data
*prog_data
,
1445 uint32_t prog_data_size
, const void *prog_data_param
,
1446 const struct anv_pipeline_bind_map
*bind_map
);
1449 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1452 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1454 assert(shader
->ref_cnt
>= 1);
1455 __sync_fetch_and_add(&shader
->ref_cnt
, 1);
1459 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1461 assert(shader
->ref_cnt
>= 1);
1462 if (__sync_fetch_and_add(&shader
->ref_cnt
, -1) == 1)
1463 anv_shader_bin_destroy(device
, shader
);
1466 struct anv_pipeline
{
1467 struct anv_device
* device
;
1468 struct anv_batch batch
;
1469 uint32_t batch_data
[512];
1470 struct anv_reloc_list batch_relocs
;
1471 uint32_t dynamic_state_mask
;
1472 struct anv_dynamic_state dynamic_state
;
1474 struct anv_pipeline_layout
* layout
;
1476 bool needs_data_cache
;
1478 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1481 const struct gen_l3_config
* l3_config
;
1482 uint32_t total_size
;
1485 VkShaderStageFlags active_stages
;
1486 struct anv_state blend_state
;
1489 uint32_t binding_stride
[MAX_VBS
];
1490 bool instancing_enable
[MAX_VBS
];
1491 bool primitive_restart
;
1494 uint32_t cs_right_mask
;
1497 bool depth_test_enable
;
1498 bool writes_stencil
;
1499 bool stencil_test_enable
;
1500 bool depth_clamp_enable
;
1505 uint32_t depth_stencil_state
[3];
1511 uint32_t wm_depth_stencil
[3];
1515 uint32_t wm_depth_stencil
[4];
1518 uint32_t interface_descriptor_data
[8];
1522 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1523 gl_shader_stage stage
)
1525 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1528 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1529 static inline const struct brw_##prefix##_prog_data * \
1530 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1532 if (anv_pipeline_has_stage(pipeline, stage)) { \
1533 return (const struct brw_##prefix##_prog_data *) \
1534 pipeline->shaders[stage]->prog_data; \
1540 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1541 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
1542 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
1543 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1544 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1545 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1547 static inline const struct brw_vue_prog_data
*
1548 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
1550 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1551 return &get_gs_prog_data(pipeline
)->base
;
1552 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1553 return &get_tes_prog_data(pipeline
)->base
;
1555 return &get_vs_prog_data(pipeline
)->base
;
1559 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1560 struct anv_pipeline_cache
*cache
,
1561 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1562 const VkAllocationCallbacks
*alloc
);
1565 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1566 struct anv_pipeline_cache
*cache
,
1567 const VkComputePipelineCreateInfo
*info
,
1568 struct anv_shader_module
*module
,
1569 const char *entrypoint
,
1570 const VkSpecializationInfo
*spec_info
);
1573 enum isl_format isl_format
:16;
1574 struct isl_swizzle swizzle
;
1578 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1579 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1581 static inline enum isl_format
1582 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1583 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1585 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1588 static inline struct isl_swizzle
1589 anv_swizzle_for_render(struct isl_swizzle swizzle
)
1591 /* Sometimes the swizzle will have alpha map to one. We do this to fake
1592 * RGB as RGBA for texturing
1594 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
1595 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
1597 /* But it doesn't matter what we render to that channel */
1598 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
1604 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
1607 * Subsurface of an anv_image.
1609 struct anv_surface
{
1610 /** Valid only if isl_surf::size > 0. */
1611 struct isl_surf isl
;
1614 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1621 /* The original VkFormat provided by the client. This may not match any
1622 * of the actual surface formats.
1625 VkImageAspectFlags aspects
;
1628 uint32_t array_size
;
1629 uint32_t samples
; /**< VkImageCreateInfo::samples */
1630 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1631 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1636 /* Set when bound */
1638 VkDeviceSize offset
;
1643 * For each foo, anv_image::foo_surface is valid if and only if
1644 * anv_image::aspects has a foo aspect.
1646 * The hardware requires that the depth buffer and stencil buffer be
1647 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1648 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1649 * allocate the depth and stencil buffers as separate surfaces in the same
1653 struct anv_surface color_surface
;
1656 struct anv_surface depth_surface
;
1657 struct anv_surface stencil_surface
;
1662 * For color images, this is the aux usage for this image when not used as a
1665 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
1668 enum isl_aux_usage aux_usage
;
1670 struct anv_surface aux_surface
;
1673 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
1675 anv_can_sample_with_hiz(uint8_t gen
, uint32_t samples
)
1677 return gen
>= 8 && samples
== 1;
1681 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
1682 const struct anv_image
*image
,
1683 enum blorp_hiz_op op
);
1685 static inline uint32_t
1686 anv_get_layerCount(const struct anv_image
*image
,
1687 const VkImageSubresourceRange
*range
)
1689 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1690 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1693 static inline uint32_t
1694 anv_get_levelCount(const struct anv_image
*image
,
1695 const VkImageSubresourceRange
*range
)
1697 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1698 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1702 struct anv_image_view
{
1703 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
1705 uint32_t offset
; /**< Offset into bo. */
1707 struct isl_view isl
;
1709 VkImageAspectFlags aspect_mask
;
1711 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1713 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1714 struct anv_state sampler_surface_state
;
1717 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
1718 * for write-only and readable, using the real format for write-only and the
1719 * lowered format for readable.
1721 struct anv_state storage_surface_state
;
1722 struct anv_state writeonly_storage_surface_state
;
1724 struct brw_image_param storage_image_param
;
1727 struct anv_image_create_info
{
1728 const VkImageCreateInfo
*vk_info
;
1730 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1731 isl_tiling_flags_t isl_tiling_flags
;
1736 VkResult
anv_image_create(VkDevice _device
,
1737 const struct anv_image_create_info
*info
,
1738 const VkAllocationCallbacks
* alloc
,
1741 const struct anv_surface
*
1742 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1743 VkImageAspectFlags aspect_mask
);
1745 struct anv_buffer_view
{
1746 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1748 uint32_t offset
; /**< Offset into bo. */
1749 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1751 struct anv_state surface_state
;
1752 struct anv_state storage_surface_state
;
1753 struct anv_state writeonly_storage_surface_state
;
1755 struct brw_image_param storage_image_param
;
1759 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
1761 static inline struct VkExtent3D
1762 anv_sanitize_image_extent(const VkImageType imageType
,
1763 const struct VkExtent3D imageExtent
)
1765 switch (imageType
) {
1766 case VK_IMAGE_TYPE_1D
:
1767 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1768 case VK_IMAGE_TYPE_2D
:
1769 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1770 case VK_IMAGE_TYPE_3D
:
1773 unreachable("invalid image type");
1777 static inline struct VkOffset3D
1778 anv_sanitize_image_offset(const VkImageType imageType
,
1779 const struct VkOffset3D imageOffset
)
1781 switch (imageType
) {
1782 case VK_IMAGE_TYPE_1D
:
1783 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1784 case VK_IMAGE_TYPE_2D
:
1785 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1786 case VK_IMAGE_TYPE_3D
:
1789 unreachable("invalid image type");
1794 void anv_fill_buffer_surface_state(struct anv_device
*device
,
1795 struct anv_state state
,
1796 enum isl_format format
,
1797 uint32_t offset
, uint32_t range
,
1800 void anv_image_view_fill_image_param(struct anv_device
*device
,
1801 struct anv_image_view
*view
,
1802 struct brw_image_param
*param
);
1803 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
1804 struct anv_buffer_view
*view
,
1805 struct brw_image_param
*param
);
1807 struct anv_sampler
{
1811 struct anv_framebuffer
{
1816 uint32_t attachment_count
;
1817 struct anv_image_view
* attachments
[0];
1820 struct anv_subpass
{
1821 uint32_t input_count
;
1822 uint32_t * input_attachments
;
1823 uint32_t color_count
;
1824 uint32_t * color_attachments
;
1825 uint32_t * resolve_attachments
;
1827 /* TODO: Consider storing the depth/stencil VkAttachmentReference
1828 * instead of its two structure members (below) individually.
1830 uint32_t depth_stencil_attachment
;
1831 VkImageLayout depth_stencil_layout
;
1833 /** Subpass has a depth/stencil self-dependency */
1834 bool has_ds_self_dep
;
1836 /** Subpass has at least one resolve attachment */
1840 enum anv_subpass_usage
{
1841 ANV_SUBPASS_USAGE_DRAW
= (1 << 0),
1842 ANV_SUBPASS_USAGE_INPUT
= (1 << 1),
1843 ANV_SUBPASS_USAGE_RESOLVE_SRC
= (1 << 2),
1844 ANV_SUBPASS_USAGE_RESOLVE_DST
= (1 << 3),
1847 struct anv_render_pass_attachment
{
1848 /* TODO: Consider using VkAttachmentDescription instead of storing each of
1849 * its members individually.
1853 VkImageUsageFlags usage
;
1854 VkAttachmentLoadOp load_op
;
1855 VkAttachmentStoreOp store_op
;
1856 VkAttachmentLoadOp stencil_load_op
;
1857 VkImageLayout initial_layout
;
1858 VkImageLayout final_layout
;
1860 /* An array, indexed by subpass id, of how the attachment will be used. */
1861 enum anv_subpass_usage
* subpass_usage
;
1863 /* The subpass id in which the attachment will be used last. */
1864 uint32_t last_subpass_idx
;
1867 struct anv_render_pass
{
1868 uint32_t attachment_count
;
1869 uint32_t subpass_count
;
1870 uint32_t * subpass_attachments
;
1871 enum anv_subpass_usage
* subpass_usages
;
1872 struct anv_render_pass_attachment
* attachments
;
1873 struct anv_subpass subpasses
[0];
1876 struct anv_query_pool_slot
{
1882 struct anv_query_pool
{
1888 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
1891 void anv_dump_image_to_ppm(struct anv_device
*device
,
1892 struct anv_image
*image
, unsigned miplevel
,
1893 unsigned array_layer
, VkImageAspectFlagBits aspect
,
1894 const char *filename
);
1896 enum anv_dump_action
{
1897 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
1900 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
1901 void anv_dump_finish(void);
1903 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
1904 struct anv_framebuffer
*fb
);
1906 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1908 static inline struct __anv_type * \
1909 __anv_type ## _from_handle(__VkType _handle) \
1911 return (struct __anv_type *) _handle; \
1914 static inline __VkType \
1915 __anv_type ## _to_handle(struct __anv_type *_obj) \
1917 return (__VkType) _obj; \
1920 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1922 static inline struct __anv_type * \
1923 __anv_type ## _from_handle(__VkType _handle) \
1925 return (struct __anv_type *)(uintptr_t) _handle; \
1928 static inline __VkType \
1929 __anv_type ## _to_handle(struct __anv_type *_obj) \
1931 return (__VkType)(uintptr_t) _obj; \
1934 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1935 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1937 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
1938 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
1939 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
1940 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
1941 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
1943 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
1944 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
1945 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
1946 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
1947 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
1948 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
1949 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
1950 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
1951 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
1952 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
1953 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
1954 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
1955 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
1956 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
1957 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
1958 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
1959 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
1960 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
1961 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
1963 /* Gen-specific function declarations */
1965 # include "anv_genX.h"
1967 # define genX(x) gen7_##x
1968 # include "anv_genX.h"
1970 # define genX(x) gen75_##x
1971 # include "anv_genX.h"
1973 # define genX(x) gen8_##x
1974 # include "anv_genX.h"
1976 # define genX(x) gen9_##x
1977 # include "anv_genX.h"
1981 #endif /* ANV_PRIVATE_H */