2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
52 /* Pre-declarations needed for WSI entrypoints */
55 typedef struct xcb_connection_t xcb_connection_t
;
56 typedef uint32_t xcb_visualid_t
;
57 typedef uint32_t xcb_window_t
;
61 #include <vulkan/vulkan.h>
62 #include <vulkan/vulkan_intel.h>
63 #include <vulkan/vk_icd.h>
65 #include "anv_entrypoints.h"
66 #include "brw_context.h"
69 #include "wsi_common.h"
75 /* Allowing different clear colors requires us to perform a depth resolve at
76 * the end of certain render passes. This is because while slow clears store
77 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
78 * See the PRMs for examples describing when additional resolves would be
79 * necessary. To enable fast clears without requiring extra resolves, we set
80 * the clear value to a globally-defined one. We could allow different values
81 * if the user doesn't expect coherent data during or after a render passes
82 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
83 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
84 * 1.0f seems to be the only value used. The only application that doesn't set
85 * this value does so through the usage of an seemingly uninitialized clear
88 #define ANV_HZ_FC_VAL 1.0f
93 #define MAX_VIEWPORTS 16
94 #define MAX_SCISSORS 16
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_DYNAMIC_BUFFERS 16
99 #define ANV_SVGS_VB_INDEX MAX_VBS
100 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
102 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
104 static inline uint32_t
105 align_down_npot_u32(uint32_t v
, uint32_t a
)
110 static inline uint32_t
111 align_u32(uint32_t v
, uint32_t a
)
113 assert(a
!= 0 && a
== (a
& -a
));
114 return (v
+ a
- 1) & ~(a
- 1);
117 static inline uint64_t
118 align_u64(uint64_t v
, uint64_t a
)
120 assert(a
!= 0 && a
== (a
& -a
));
121 return (v
+ a
- 1) & ~(a
- 1);
124 static inline int32_t
125 align_i32(int32_t v
, int32_t a
)
127 assert(a
!= 0 && a
== (a
& -a
));
128 return (v
+ a
- 1) & ~(a
- 1);
131 /** Alignment must be a power of 2. */
133 anv_is_aligned(uintmax_t n
, uintmax_t a
)
135 assert(a
== (a
& -a
));
136 return (n
& (a
- 1)) == 0;
139 static inline uint32_t
140 anv_minify(uint32_t n
, uint32_t levels
)
142 if (unlikely(n
== 0))
145 return MAX2(n
>> levels
, 1);
149 anv_clamp_f(float f
, float min
, float max
)
162 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
164 if (*inout_mask
& clear_mask
) {
165 *inout_mask
&= ~clear_mask
;
172 static inline union isl_color_value
173 vk_to_isl_color(VkClearColorValue color
)
175 return (union isl_color_value
) {
185 #define for_each_bit(b, dword) \
186 for (uint32_t __dword = (dword); \
187 (b) = __builtin_ffs(__dword) - 1, __dword; \
188 __dword &= ~(1 << (b)))
190 #define typed_memcpy(dest, src, count) ({ \
191 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
192 memcpy((dest), (src), (count) * sizeof(*(src))); \
195 /* Whenever we generate an error, pass it through this function. Useful for
196 * debugging, where we can break on it. Only call at error site, not when
197 * propagating errors. Might be useful to plug in a stack trace here.
200 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
203 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
204 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
205 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
207 #define vk_error(error) error
208 #define vk_errorf(error, format, ...) error
209 #define anv_debug(format, ...)
213 * Warn on ignored extension structs.
215 * The Vulkan spec requires us to ignore unsupported or unknown structs in
216 * a pNext chain. In debug mode, emitting warnings for ignored structs may
217 * help us discover structs that we should not have ignored.
220 * From the Vulkan 1.0.38 spec:
222 * Any component of the implementation (the loader, any enabled layers,
223 * and drivers) must skip over, without processing (other than reading the
224 * sType and pNext members) any chained structures with sType values not
225 * defined by extensions supported by that component.
227 #define anv_debug_ignored_stype(sType) \
228 anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType))
230 void __anv_finishme(const char *file
, int line
, const char *format
, ...)
231 anv_printflike(3, 4);
232 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
233 void anv_loge_v(const char *format
, va_list va
);
236 * Print a FINISHME message, including its source location.
238 #define anv_finishme(format, ...) \
240 static bool reported = false; \
242 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
247 /* A non-fatal assert. Useful for debugging. */
249 #define anv_assert(x) ({ \
250 if (unlikely(!(x))) \
251 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
254 #define anv_assert(x)
258 * If a block of code is annotated with anv_validate, then the block runs only
262 #define anv_validate if (1)
264 #define anv_validate if (0)
267 #define stub_return(v) \
269 anv_finishme("stub %s", __func__); \
275 anv_finishme("stub %s", __func__); \
280 * A dynamically growable, circular buffer. Elements are added at head and
281 * removed from tail. head and tail are free-running uint32_t indices and we
282 * only compute the modulo with size when accessing the array. This way,
283 * number of bytes in the queue is always head - tail, even in case of
290 /* Index into the current validation list. This is used by the
291 * validation list building alrogithm to track which buffers are already
292 * in the validation list so that we can ensure uniqueness.
296 /* Last known offset. This value is provided by the kernel when we
297 * execbuf and is used as the presumed offset for the next bunch of
305 /* We need to set the WRITE flag on winsys bos so GEM will know we're
306 * writing to them and synchronize uses on other rings (eg if the display
307 * server uses the blitter ring).
313 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
315 bo
->gem_handle
= gem_handle
;
320 bo
->is_winsys_bo
= false;
323 /* Represents a lock-free linked list of "free" things. This is used by
324 * both the block pool and the state pools. Unfortunately, in order to
325 * solve the ABA problem, we can't use a single uint32_t head.
327 union anv_free_list
{
331 /* A simple count that is incremented every time the head changes. */
337 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
339 struct anv_block_state
{
349 struct anv_block_pool
{
350 struct anv_device
*device
;
354 /* The offset from the start of the bo to the "center" of the block
355 * pool. Pointers to allocated blocks are given by
356 * bo.map + center_bo_offset + offsets.
358 uint32_t center_bo_offset
;
360 /* Current memory map of the block pool. This pointer may or may not
361 * point to the actual beginning of the block pool memory. If
362 * anv_block_pool_alloc_back has ever been called, then this pointer
363 * will point to the "center" position of the buffer and all offsets
364 * (negative or positive) given out by the block pool alloc functions
365 * will be valid relative to this pointer.
367 * In particular, map == bo.map + center_offset
373 * Array of mmaps and gem handles owned by the block pool, reclaimed when
374 * the block pool is destroyed.
376 struct u_vector mmap_cleanups
;
380 union anv_free_list free_list
;
381 struct anv_block_state state
;
383 union anv_free_list back_free_list
;
384 struct anv_block_state back_state
;
387 /* Block pools are backed by a fixed-size 2GB memfd */
388 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
390 /* The center of the block pool is also the middle of the memfd. This may
391 * change in the future if we decide differently for some reason.
393 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
395 static inline uint32_t
396 anv_block_pool_size(struct anv_block_pool
*pool
)
398 return pool
->state
.end
+ pool
->back_state
.end
;
407 struct anv_fixed_size_state_pool
{
409 union anv_free_list free_list
;
410 struct anv_block_state block
;
413 #define ANV_MIN_STATE_SIZE_LOG2 6
414 #define ANV_MAX_STATE_SIZE_LOG2 20
416 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
418 struct anv_state_pool
{
419 struct anv_block_pool
*block_pool
;
420 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
423 struct anv_state_stream_block
;
425 struct anv_state_stream
{
426 struct anv_block_pool
*block_pool
;
428 /* The current working block */
429 struct anv_state_stream_block
*block
;
431 /* Offset at which the current block starts */
433 /* Offset at which to allocate the next state */
435 /* Offset at which the current block ends */
439 #define CACHELINE_SIZE 64
440 #define CACHELINE_MASK 63
443 anv_clflush_range(void *start
, size_t size
)
445 void *p
= (void *) (((uintptr_t) start
) & ~CACHELINE_MASK
);
446 void *end
= start
+ size
;
448 __builtin_ia32_mfence();
450 __builtin_ia32_clflush(p
);
456 anv_state_clflush(struct anv_state state
)
458 anv_clflush_range(state
.map
, state
.alloc_size
);
461 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
462 struct anv_device
*device
, uint32_t block_size
);
463 void anv_block_pool_finish(struct anv_block_pool
*pool
);
464 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
);
465 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
);
466 void anv_block_pool_free(struct anv_block_pool
*pool
, int32_t offset
);
467 void anv_state_pool_init(struct anv_state_pool
*pool
,
468 struct anv_block_pool
*block_pool
);
469 void anv_state_pool_finish(struct anv_state_pool
*pool
);
470 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
471 size_t state_size
, size_t alignment
);
472 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
473 void anv_state_stream_init(struct anv_state_stream
*stream
,
474 struct anv_block_pool
*block_pool
);
475 void anv_state_stream_finish(struct anv_state_stream
*stream
);
476 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
477 uint32_t size
, uint32_t alignment
);
480 * Implements a pool of re-usable BOs. The interface is identical to that
481 * of block_pool except that each block is its own BO.
484 struct anv_device
*device
;
489 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
490 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
491 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
493 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
495 struct anv_scratch_bo
{
500 struct anv_scratch_pool
{
501 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
502 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
505 void anv_scratch_pool_init(struct anv_device
*device
,
506 struct anv_scratch_pool
*pool
);
507 void anv_scratch_pool_finish(struct anv_device
*device
,
508 struct anv_scratch_pool
*pool
);
509 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
510 struct anv_scratch_pool
*pool
,
511 gl_shader_stage stage
,
512 unsigned per_thread_scratch
);
514 extern struct anv_dispatch_table dtable
;
516 struct anv_physical_device
{
517 VK_LOADER_DATA _loader_data
;
519 struct anv_instance
* instance
;
523 struct gen_device_info info
;
524 uint64_t aperture_size
;
525 struct brw_compiler
* compiler
;
526 struct isl_device isl_dev
;
527 int cmd_parser_version
;
530 uint32_t subslice_total
;
532 uint8_t uuid
[VK_UUID_SIZE
];
534 struct wsi_device wsi_device
;
537 struct anv_instance
{
538 VK_LOADER_DATA _loader_data
;
540 VkAllocationCallbacks alloc
;
543 int physicalDeviceCount
;
544 struct anv_physical_device physicalDevice
;
547 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
548 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
551 VK_LOADER_DATA _loader_data
;
553 struct anv_device
* device
;
555 struct anv_state_pool
* pool
;
558 struct anv_pipeline_cache
{
559 struct anv_device
* device
;
560 pthread_mutex_t mutex
;
562 struct hash_table
* cache
;
565 struct anv_pipeline_bind_map
;
567 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
568 struct anv_device
*device
,
570 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
572 struct anv_shader_bin
*
573 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
574 const void *key
, uint32_t key_size
);
575 struct anv_shader_bin
*
576 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
577 const void *key_data
, uint32_t key_size
,
578 const void *kernel_data
, uint32_t kernel_size
,
579 const struct brw_stage_prog_data
*prog_data
,
580 uint32_t prog_data_size
,
581 const struct anv_pipeline_bind_map
*bind_map
);
584 VK_LOADER_DATA _loader_data
;
586 VkAllocationCallbacks alloc
;
588 struct anv_instance
* instance
;
590 struct gen_device_info info
;
591 struct isl_device isl_dev
;
594 bool can_chain_batches
;
595 bool robust_buffer_access
;
597 struct anv_bo_pool batch_bo_pool
;
599 struct anv_block_pool dynamic_state_block_pool
;
600 struct anv_state_pool dynamic_state_pool
;
602 struct anv_block_pool instruction_block_pool
;
603 struct anv_state_pool instruction_state_pool
;
605 struct anv_block_pool surface_state_block_pool
;
606 struct anv_state_pool surface_state_pool
;
608 struct anv_bo workaround_bo
;
610 struct anv_pipeline_cache blorp_shader_cache
;
611 struct blorp_context blorp
;
613 struct anv_state border_colors
;
615 struct anv_queue queue
;
617 struct anv_scratch_pool scratch_pool
;
619 uint32_t default_mocs
;
621 pthread_mutex_t mutex
;
622 pthread_cond_t queue_submit
;
625 void anv_device_init_blorp(struct anv_device
*device
);
626 void anv_device_finish_blorp(struct anv_device
*device
);
628 VkResult
anv_device_execbuf(struct anv_device
*device
,
629 struct drm_i915_gem_execbuffer2
*execbuf
,
630 struct anv_bo
**execbuf_bos
);
632 void* anv_gem_mmap(struct anv_device
*device
,
633 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
634 void anv_gem_munmap(void *p
, uint64_t size
);
635 uint32_t anv_gem_create(struct anv_device
*device
, size_t size
);
636 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
637 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
638 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
639 int anv_gem_execbuffer(struct anv_device
*device
,
640 struct drm_i915_gem_execbuffer2
*execbuf
);
641 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
642 uint32_t stride
, uint32_t tiling
);
643 int anv_gem_create_context(struct anv_device
*device
);
644 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
645 int anv_gem_get_param(int fd
, uint32_t param
);
646 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
647 int anv_gem_get_aperture(int fd
, uint64_t *size
);
648 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
649 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
650 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
651 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
652 uint32_t read_domains
, uint32_t write_domain
);
654 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
656 struct anv_reloc_list
{
659 struct drm_i915_gem_relocation_entry
* relocs
;
660 struct anv_bo
** reloc_bos
;
663 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
664 const VkAllocationCallbacks
*alloc
);
665 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
666 const VkAllocationCallbacks
*alloc
);
668 uint64_t anv_reloc_list_add(struct anv_reloc_list
*list
,
669 const VkAllocationCallbacks
*alloc
,
670 uint32_t offset
, struct anv_bo
*target_bo
,
673 struct anv_batch_bo
{
674 /* Link in the anv_cmd_buffer.owned_batch_bos list */
675 struct list_head link
;
679 /* Bytes actually consumed in this batch BO */
682 struct anv_reloc_list relocs
;
686 const VkAllocationCallbacks
* alloc
;
692 struct anv_reloc_list
* relocs
;
694 /* This callback is called (with the associated user data) in the event
695 * that the batch runs out of space.
697 VkResult (*extend_cb
)(struct anv_batch
*, void *);
701 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
702 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
703 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
704 void *location
, struct anv_bo
*bo
, uint32_t offset
);
705 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
706 struct anv_batch
*batch
);
713 static inline uint64_t
714 _anv_combine_address(struct anv_batch
*batch
, void *location
,
715 const struct anv_address address
, uint32_t delta
)
717 if (address
.bo
== NULL
) {
718 return address
.offset
+ delta
;
720 assert(batch
->start
<= location
&& location
< batch
->end
);
722 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
726 #define __gen_address_type struct anv_address
727 #define __gen_user_data struct anv_batch
728 #define __gen_combine_address _anv_combine_address
730 /* Wrapper macros needed to work around preprocessor argument issues. In
731 * particular, arguments don't get pre-evaluated if they are concatenated.
732 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
733 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
734 * We can work around this easily enough with these helpers.
736 #define __anv_cmd_length(cmd) cmd ## _length
737 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
738 #define __anv_cmd_header(cmd) cmd ## _header
739 #define __anv_cmd_pack(cmd) cmd ## _pack
740 #define __anv_reg_num(reg) reg ## _num
742 #define anv_pack_struct(dst, struc, ...) do { \
743 struct struc __template = { \
746 __anv_cmd_pack(struc)(NULL, dst, &__template); \
747 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
750 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
751 void *__dst = anv_batch_emit_dwords(batch, n); \
752 struct cmd __template = { \
753 __anv_cmd_header(cmd), \
754 .DWordLength = n - __anv_cmd_length_bias(cmd), \
757 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
761 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
765 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
766 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
767 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
768 dw[i] = (dwords0)[i] | (dwords1)[i]; \
769 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
772 #define anv_batch_emit(batch, cmd, name) \
773 for (struct cmd name = { __anv_cmd_header(cmd) }, \
774 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
775 __builtin_expect(_dst != NULL, 1); \
776 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
777 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
781 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
782 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
783 struct anv_state __state = \
784 anv_state_pool_alloc((pool), __size, align); \
785 struct cmd __template = { \
788 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
789 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
790 if (!(pool)->block_pool->device->info.has_llc) \
791 anv_state_clflush(__state); \
795 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
796 .GraphicsDataTypeGFDT = 0, \
797 .LLCCacheabilityControlLLCCC = 0, \
798 .L3CacheabilityControlL3CC = 1, \
801 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
802 .LLCeLLCCacheabilityControlLLCCC = 0, \
803 .L3CacheabilityControlL3CC = 1, \
806 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
807 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
808 .TargetCache = L3DefertoPATforLLCeLLCselection, \
812 /* Skylake: MOCS is now an index into an array of 62 different caching
813 * configurations programmed by the kernel.
816 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
817 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
818 .IndextoMOCSTables = 2 \
821 #define GEN9_MOCS_PTE { \
822 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
823 .IndextoMOCSTables = 1 \
826 struct anv_device_memory
{
829 VkDeviceSize map_size
;
834 * Header for Vertex URB Entry (VUE)
836 struct anv_vue_header
{
838 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
839 uint32_t ViewportIndex
;
843 struct anv_descriptor_set_binding_layout
{
845 /* The type of the descriptors in this binding */
846 VkDescriptorType type
;
849 /* Number of array elements in this binding */
852 /* Index into the flattend descriptor set */
853 uint16_t descriptor_index
;
855 /* Index into the dynamic state array for a dynamic buffer */
856 int16_t dynamic_offset_index
;
858 /* Index into the descriptor set buffer views */
859 int16_t buffer_index
;
862 /* Index into the binding table for the associated surface */
863 int16_t surface_index
;
865 /* Index into the sampler table for the associated sampler */
866 int16_t sampler_index
;
868 /* Index into the image table for the associated image */
870 } stage
[MESA_SHADER_STAGES
];
872 /* Immutable samplers (or NULL if no immutable samplers) */
873 struct anv_sampler
**immutable_samplers
;
876 struct anv_descriptor_set_layout
{
877 /* Number of bindings in this descriptor set */
878 uint16_t binding_count
;
880 /* Total size of the descriptor set with room for all array entries */
883 /* Shader stages affected by this descriptor set */
884 uint16_t shader_stages
;
886 /* Number of buffers in this descriptor set */
887 uint16_t buffer_count
;
889 /* Number of dynamic offsets used by this descriptor set */
890 uint16_t dynamic_offset_count
;
892 /* Bindings in this descriptor set */
893 struct anv_descriptor_set_binding_layout binding
[0];
896 struct anv_descriptor
{
897 VkDescriptorType type
;
901 struct anv_image_view
*image_view
;
902 struct anv_sampler
*sampler
;
905 struct anv_buffer_view
*buffer_view
;
909 struct anv_descriptor_set
{
910 const struct anv_descriptor_set_layout
*layout
;
912 uint32_t buffer_count
;
913 struct anv_buffer_view
*buffer_views
;
914 struct anv_descriptor descriptors
[0];
917 struct anv_descriptor_pool
{
922 struct anv_state_stream surface_state_stream
;
923 void *surface_state_free_list
;
929 anv_descriptor_set_create(struct anv_device
*device
,
930 struct anv_descriptor_pool
*pool
,
931 const struct anv_descriptor_set_layout
*layout
,
932 struct anv_descriptor_set
**out_set
);
935 anv_descriptor_set_destroy(struct anv_device
*device
,
936 struct anv_descriptor_pool
*pool
,
937 struct anv_descriptor_set
*set
);
939 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
941 struct anv_pipeline_binding
{
942 /* The descriptor set this surface corresponds to. The special value of
943 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
944 * to a color attachment and not a regular descriptor.
948 /* Binding in the descriptor set */
951 /* Index in the binding */
954 /* Input attachment index (relative to the subpass) */
955 uint8_t input_attachment_index
;
957 /* For a storage image, whether it is write-only */
961 struct anv_pipeline_layout
{
963 struct anv_descriptor_set_layout
*layout
;
964 uint32_t dynamic_offset_start
;
970 bool has_dynamic_offsets
;
971 } stage
[MESA_SHADER_STAGES
];
973 unsigned char sha1
[20];
977 struct anv_device
* device
;
980 VkBufferUsageFlags usage
;
987 enum anv_cmd_dirty_bits
{
988 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
989 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
990 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
991 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
992 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
993 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
994 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
995 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
996 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
997 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
998 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
999 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1000 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1002 typedef uint32_t anv_cmd_dirty_mask_t
;
1004 enum anv_pipe_bits
{
1005 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1006 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1007 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1008 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1009 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1010 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1011 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1012 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1013 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1014 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1015 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1017 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1018 * a flush has happened but not a CS stall. The next time we do any sort
1019 * of invalidation we need to insert a CS stall at that time. Otherwise,
1020 * we would have to CS stall on every flush which could be bad.
1022 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1025 #define ANV_PIPE_FLUSH_BITS ( \
1026 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1027 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1028 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1030 #define ANV_PIPE_STALL_BITS ( \
1031 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1032 ANV_PIPE_DEPTH_STALL_BIT | \
1033 ANV_PIPE_CS_STALL_BIT)
1035 #define ANV_PIPE_INVALIDATE_BITS ( \
1036 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1037 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1038 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1039 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1040 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1041 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1043 struct anv_vertex_binding
{
1044 struct anv_buffer
* buffer
;
1045 VkDeviceSize offset
;
1048 struct anv_push_constants
{
1049 /* Current allocated size of this push constants data structure.
1050 * Because a decent chunk of it may not be used (images on SKL, for
1051 * instance), we won't actually allocate the entire structure up-front.
1055 /* Push constant data provided by the client through vkPushConstants */
1056 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1058 /* Our hardware only provides zero-based vertex and instance id so, in
1059 * order to satisfy the vulkan requirements, we may have to push one or
1060 * both of these into the shader.
1062 uint32_t base_vertex
;
1063 uint32_t base_instance
;
1065 /* Offsets and ranges for dynamically bound buffers */
1069 } dynamic
[MAX_DYNAMIC_BUFFERS
];
1071 /* Image data for image_load_store on pre-SKL */
1072 struct brw_image_param images
[MAX_IMAGES
];
1075 struct anv_dynamic_state
{
1078 VkViewport viewports
[MAX_VIEWPORTS
];
1083 VkRect2D scissors
[MAX_SCISSORS
];
1094 float blend_constants
[4];
1104 } stencil_compare_mask
;
1109 } stencil_write_mask
;
1114 } stencil_reference
;
1117 extern const struct anv_dynamic_state default_dynamic_state
;
1119 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1120 const struct anv_dynamic_state
*src
,
1121 uint32_t copy_mask
);
1124 * Attachment state when recording a renderpass instance.
1126 * The clear value is valid only if there exists a pending clear.
1128 struct anv_attachment_state
{
1129 enum isl_aux_usage aux_usage
;
1130 enum isl_aux_usage input_aux_usage
;
1131 struct anv_state color_rt_state
;
1132 struct anv_state input_att_state
;
1134 VkImageLayout current_layout
;
1135 VkImageAspectFlags pending_clear_aspects
;
1137 VkClearValue clear_value
;
1138 bool clear_color_is_zero_one
;
1141 /** State required while building cmd buffer */
1142 struct anv_cmd_state
{
1143 /* PIPELINE_SELECT.PipelineSelection */
1144 uint32_t current_pipeline
;
1145 const struct gen_l3_config
* current_l3_config
;
1147 anv_cmd_dirty_mask_t dirty
;
1148 anv_cmd_dirty_mask_t compute_dirty
;
1149 enum anv_pipe_bits pending_pipe_bits
;
1150 uint32_t num_workgroups_offset
;
1151 struct anv_bo
*num_workgroups_bo
;
1152 VkShaderStageFlags descriptors_dirty
;
1153 VkShaderStageFlags push_constants_dirty
;
1154 uint32_t scratch_size
;
1155 struct anv_pipeline
* pipeline
;
1156 struct anv_pipeline
* compute_pipeline
;
1157 struct anv_framebuffer
* framebuffer
;
1158 struct anv_render_pass
* pass
;
1159 struct anv_subpass
* subpass
;
1160 VkRect2D render_area
;
1161 uint32_t restart_index
;
1162 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1163 struct anv_descriptor_set
* descriptors
[MAX_SETS
];
1164 VkShaderStageFlags push_constant_stages
;
1165 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1166 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1167 struct anv_state samplers
[MESA_SHADER_STAGES
];
1168 struct anv_dynamic_state dynamic
;
1172 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1173 * valid only when recording a render pass instance.
1175 struct anv_attachment_state
* attachments
;
1178 * Surface states for color render targets. These are stored in a single
1179 * flat array. For depth-stencil attachments, the surface state is simply
1182 struct anv_state render_pass_states
;
1185 * A null surface state of the right size to match the framebuffer. This
1186 * is one of the states in render_pass_states.
1188 struct anv_state null_surface_state
;
1191 struct anv_buffer
* index_buffer
;
1192 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1193 uint32_t index_offset
;
1197 struct anv_cmd_pool
{
1198 VkAllocationCallbacks alloc
;
1199 struct list_head cmd_buffers
;
1202 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1204 enum anv_cmd_buffer_exec_mode
{
1205 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1206 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1207 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1208 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1209 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1212 struct anv_cmd_buffer
{
1213 VK_LOADER_DATA _loader_data
;
1215 struct anv_device
* device
;
1217 struct anv_cmd_pool
* pool
;
1218 struct list_head pool_link
;
1220 struct anv_batch batch
;
1222 /* Fields required for the actual chain of anv_batch_bo's.
1224 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1226 struct list_head batch_bos
;
1227 enum anv_cmd_buffer_exec_mode exec_mode
;
1229 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1230 * referenced by this command buffer
1232 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1234 struct u_vector seen_bbos
;
1236 /* A vector of int32_t's for every block of binding tables.
1238 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1240 struct u_vector bt_blocks
;
1243 struct anv_reloc_list surface_relocs
;
1244 /** Last seen surface state block pool center bo offset */
1245 uint32_t last_ss_pool_center
;
1247 /* Serial for tracking buffer completion */
1250 /* Stream objects for storing temporary data */
1251 struct anv_state_stream surface_state_stream
;
1252 struct anv_state_stream dynamic_state_stream
;
1254 VkCommandBufferUsageFlags usage_flags
;
1255 VkCommandBufferLevel level
;
1257 struct anv_cmd_state state
;
1260 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1261 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1262 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
1263 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
1264 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
1265 struct anv_cmd_buffer
*secondary
);
1266 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
1267 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
1268 struct anv_cmd_buffer
*cmd_buffer
);
1270 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
1273 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
1274 gl_shader_stage stage
, uint32_t size
);
1275 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1276 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1277 (offsetof(struct anv_push_constants, field) + \
1278 sizeof(cmd_buffer->state.push_constants[0]->field)))
1280 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1281 const void *data
, uint32_t size
, uint32_t alignment
);
1282 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
1283 uint32_t *a
, uint32_t *b
,
1284 uint32_t dwords
, uint32_t alignment
);
1287 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1289 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1290 uint32_t entries
, uint32_t *state_offset
);
1292 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
1294 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
1295 uint32_t size
, uint32_t alignment
);
1298 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
1300 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
1301 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
1302 bool depth_clamp_enable
);
1303 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
1305 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1306 struct anv_render_pass
*pass
,
1307 struct anv_framebuffer
*framebuffer
,
1308 const VkClearValue
*clear_values
);
1310 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
1313 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1314 gl_shader_stage stage
);
1316 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
1318 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1319 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
1321 const struct anv_image_view
*
1322 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
1325 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1326 uint32_t num_entries
,
1327 uint32_t *state_offset
);
1329 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
1331 enum anv_fence_state
{
1332 /** Indicates that this is a new (or newly reset fence) */
1333 ANV_FENCE_STATE_RESET
,
1335 /** Indicates that this fence has been submitted to the GPU but is still
1336 * (as far as we know) in use by the GPU.
1338 ANV_FENCE_STATE_SUBMITTED
,
1340 ANV_FENCE_STATE_SIGNALED
,
1345 struct drm_i915_gem_execbuffer2 execbuf
;
1346 struct drm_i915_gem_exec_object2 exec2_objects
[1];
1347 enum anv_fence_state state
;
1352 struct anv_state state
;
1355 struct anv_shader_module
{
1356 unsigned char sha1
[20];
1361 void anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
1362 struct anv_shader_module
*module
,
1363 const char *entrypoint
,
1364 const struct anv_pipeline_layout
*pipeline_layout
,
1365 const VkSpecializationInfo
*spec_info
);
1367 static inline gl_shader_stage
1368 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1370 assert(__builtin_popcount(vk_stage
) == 1);
1371 return ffs(vk_stage
) - 1;
1374 static inline VkShaderStageFlagBits
1375 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1377 return (1 << mesa_stage
);
1380 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1382 #define anv_foreach_stage(stage, stage_bits) \
1383 for (gl_shader_stage stage, \
1384 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1385 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1386 __tmp &= ~(1 << (stage)))
1388 struct anv_pipeline_bind_map
{
1389 uint32_t surface_count
;
1390 uint32_t sampler_count
;
1391 uint32_t image_count
;
1393 struct anv_pipeline_binding
* surface_to_descriptor
;
1394 struct anv_pipeline_binding
* sampler_to_descriptor
;
1397 struct anv_shader_bin_key
{
1402 struct anv_shader_bin
{
1405 const struct anv_shader_bin_key
*key
;
1407 struct anv_state kernel
;
1408 uint32_t kernel_size
;
1410 const struct brw_stage_prog_data
*prog_data
;
1411 uint32_t prog_data_size
;
1413 struct anv_pipeline_bind_map bind_map
;
1415 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1418 struct anv_shader_bin
*
1419 anv_shader_bin_create(struct anv_device
*device
,
1420 const void *key
, uint32_t key_size
,
1421 const void *kernel
, uint32_t kernel_size
,
1422 const struct brw_stage_prog_data
*prog_data
,
1423 uint32_t prog_data_size
, const void *prog_data_param
,
1424 const struct anv_pipeline_bind_map
*bind_map
);
1427 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
1430 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
1432 assert(shader
->ref_cnt
>= 1);
1433 __sync_fetch_and_add(&shader
->ref_cnt
, 1);
1437 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
1439 assert(shader
->ref_cnt
>= 1);
1440 if (__sync_fetch_and_add(&shader
->ref_cnt
, -1) == 1)
1441 anv_shader_bin_destroy(device
, shader
);
1444 struct anv_pipeline
{
1445 struct anv_device
* device
;
1446 struct anv_batch batch
;
1447 uint32_t batch_data
[512];
1448 struct anv_reloc_list batch_relocs
;
1449 uint32_t dynamic_state_mask
;
1450 struct anv_dynamic_state dynamic_state
;
1452 struct anv_pipeline_layout
* layout
;
1454 bool needs_data_cache
;
1456 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
1459 const struct gen_l3_config
* l3_config
;
1460 uint32_t total_size
;
1463 VkShaderStageFlags active_stages
;
1464 struct anv_state blend_state
;
1467 uint32_t binding_stride
[MAX_VBS
];
1468 bool instancing_enable
[MAX_VBS
];
1469 bool primitive_restart
;
1472 uint32_t cs_right_mask
;
1474 bool depth_clamp_enable
;
1478 uint32_t depth_stencil_state
[3];
1484 uint32_t wm_depth_stencil
[3];
1488 uint32_t wm_depth_stencil
[4];
1491 uint32_t interface_descriptor_data
[8];
1495 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
1496 gl_shader_stage stage
)
1498 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
1501 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1502 static inline const struct brw_##prefix##_prog_data * \
1503 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1505 if (anv_pipeline_has_stage(pipeline, stage)) { \
1506 return (const struct brw_##prefix##_prog_data *) \
1507 pipeline->shaders[stage]->prog_data; \
1513 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
1514 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
1515 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
1516 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
1517 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
1518 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
1520 static inline const struct brw_vue_prog_data
*
1521 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
1523 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1524 return &get_gs_prog_data(pipeline
)->base
;
1525 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1526 return &get_tes_prog_data(pipeline
)->base
;
1528 return &get_vs_prog_data(pipeline
)->base
;
1532 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
1533 struct anv_pipeline_cache
*cache
,
1534 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1535 const VkAllocationCallbacks
*alloc
);
1538 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1539 struct anv_pipeline_cache
*cache
,
1540 const VkComputePipelineCreateInfo
*info
,
1541 struct anv_shader_module
*module
,
1542 const char *entrypoint
,
1543 const VkSpecializationInfo
*spec_info
);
1546 enum isl_format isl_format
:16;
1547 struct isl_swizzle swizzle
;
1551 anv_get_format(const struct gen_device_info
*devinfo
, VkFormat format
,
1552 VkImageAspectFlags aspect
, VkImageTiling tiling
);
1554 static inline enum isl_format
1555 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
1556 VkImageAspectFlags aspect
, VkImageTiling tiling
)
1558 return anv_get_format(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
1561 static inline struct isl_swizzle
1562 anv_swizzle_for_render(struct isl_swizzle swizzle
)
1564 /* Sometimes the swizzle will have alpha map to one. We do this to fake
1565 * RGB as RGBA for texturing
1567 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
1568 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
1570 /* But it doesn't matter what we render to that channel */
1571 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
1577 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
1580 * Subsurface of an anv_image.
1582 struct anv_surface
{
1583 /** Valid only if isl_surf::size > 0. */
1584 struct isl_surf isl
;
1587 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1594 /* The original VkFormat provided by the client. This may not match any
1595 * of the actual surface formats.
1598 VkImageAspectFlags aspects
;
1601 uint32_t array_size
;
1602 uint32_t samples
; /**< VkImageCreateInfo::samples */
1603 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1604 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1609 /* Set when bound */
1611 VkDeviceSize offset
;
1616 * For each foo, anv_image::foo_surface is valid if and only if
1617 * anv_image::aspects has a foo aspect.
1619 * The hardware requires that the depth buffer and stencil buffer be
1620 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1621 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1622 * allocate the depth and stencil buffers as separate surfaces in the same
1626 struct anv_surface color_surface
;
1629 struct anv_surface depth_surface
;
1630 struct anv_surface stencil_surface
;
1635 * For color images, this is the aux usage for this image when not used as a
1638 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
1641 enum isl_aux_usage aux_usage
;
1643 struct anv_surface aux_surface
;
1646 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
1648 anv_can_sample_with_hiz(uint8_t gen
, uint32_t samples
)
1650 return gen
>= 8 && samples
== 1;
1654 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
1655 const struct anv_image
*image
,
1656 enum blorp_hiz_op op
);
1658 static inline uint32_t
1659 anv_get_layerCount(const struct anv_image
*image
,
1660 const VkImageSubresourceRange
*range
)
1662 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1663 image
->array_size
- range
->baseArrayLayer
: range
->layerCount
;
1666 static inline uint32_t
1667 anv_get_levelCount(const struct anv_image
*image
,
1668 const VkImageSubresourceRange
*range
)
1670 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1671 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
1675 struct anv_image_view
{
1676 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
1678 uint32_t offset
; /**< Offset into bo. */
1680 struct isl_view isl
;
1682 VkImageAspectFlags aspect_mask
;
1684 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1686 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1687 struct anv_state sampler_surface_state
;
1690 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
1691 * for write-only and readable, using the real format for write-only and the
1692 * lowered format for readable.
1694 struct anv_state storage_surface_state
;
1695 struct anv_state writeonly_storage_surface_state
;
1697 struct brw_image_param storage_image_param
;
1700 struct anv_image_create_info
{
1701 const VkImageCreateInfo
*vk_info
;
1703 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1704 isl_tiling_flags_t isl_tiling_flags
;
1709 VkResult
anv_image_create(VkDevice _device
,
1710 const struct anv_image_create_info
*info
,
1711 const VkAllocationCallbacks
* alloc
,
1714 const struct anv_surface
*
1715 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1716 VkImageAspectFlags aspect_mask
);
1718 struct anv_buffer_view
{
1719 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1721 uint32_t offset
; /**< Offset into bo. */
1722 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1724 struct anv_state surface_state
;
1725 struct anv_state storage_surface_state
;
1726 struct anv_state writeonly_storage_surface_state
;
1728 struct brw_image_param storage_image_param
;
1732 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
1734 static inline struct VkExtent3D
1735 anv_sanitize_image_extent(const VkImageType imageType
,
1736 const struct VkExtent3D imageExtent
)
1738 switch (imageType
) {
1739 case VK_IMAGE_TYPE_1D
:
1740 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1741 case VK_IMAGE_TYPE_2D
:
1742 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1743 case VK_IMAGE_TYPE_3D
:
1746 unreachable("invalid image type");
1750 static inline struct VkOffset3D
1751 anv_sanitize_image_offset(const VkImageType imageType
,
1752 const struct VkOffset3D imageOffset
)
1754 switch (imageType
) {
1755 case VK_IMAGE_TYPE_1D
:
1756 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1757 case VK_IMAGE_TYPE_2D
:
1758 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1759 case VK_IMAGE_TYPE_3D
:
1762 unreachable("invalid image type");
1767 void anv_fill_buffer_surface_state(struct anv_device
*device
,
1768 struct anv_state state
,
1769 enum isl_format format
,
1770 uint32_t offset
, uint32_t range
,
1773 void anv_image_view_fill_image_param(struct anv_device
*device
,
1774 struct anv_image_view
*view
,
1775 struct brw_image_param
*param
);
1776 void anv_buffer_view_fill_image_param(struct anv_device
*device
,
1777 struct anv_buffer_view
*view
,
1778 struct brw_image_param
*param
);
1780 struct anv_sampler
{
1784 struct anv_framebuffer
{
1789 uint32_t attachment_count
;
1790 struct anv_image_view
* attachments
[0];
1793 struct anv_subpass
{
1794 uint32_t input_count
;
1795 uint32_t * input_attachments
;
1796 uint32_t color_count
;
1797 uint32_t * color_attachments
;
1798 uint32_t * resolve_attachments
;
1800 /* TODO: Consider storing the depth/stencil VkAttachmentReference
1801 * instead of its two structure members (below) individually.
1803 uint32_t depth_stencil_attachment
;
1804 VkImageLayout depth_stencil_layout
;
1806 /** Subpass has a depth/stencil self-dependency */
1807 bool has_ds_self_dep
;
1809 /** Subpass has at least one resolve attachment */
1813 enum anv_subpass_usage
{
1814 ANV_SUBPASS_USAGE_DRAW
= (1 << 0),
1815 ANV_SUBPASS_USAGE_INPUT
= (1 << 1),
1816 ANV_SUBPASS_USAGE_RESOLVE_SRC
= (1 << 2),
1817 ANV_SUBPASS_USAGE_RESOLVE_DST
= (1 << 3),
1820 struct anv_render_pass_attachment
{
1821 /* TODO: Consider using VkAttachmentDescription instead of storing each of
1822 * its members individually.
1826 VkImageUsageFlags usage
;
1827 VkAttachmentLoadOp load_op
;
1828 VkAttachmentStoreOp store_op
;
1829 VkAttachmentLoadOp stencil_load_op
;
1830 VkImageLayout initial_layout
;
1831 VkImageLayout final_layout
;
1833 /* An array, indexed by subpass id, of how the attachment will be used. */
1834 enum anv_subpass_usage
* subpass_usage
;
1836 /* The subpass id in which the attachment will be used last. */
1837 uint32_t last_subpass_idx
;
1840 struct anv_render_pass
{
1841 uint32_t attachment_count
;
1842 uint32_t subpass_count
;
1843 uint32_t * subpass_attachments
;
1844 enum anv_subpass_usage
* subpass_usages
;
1845 struct anv_render_pass_attachment
* attachments
;
1846 struct anv_subpass subpasses
[0];
1849 struct anv_query_pool_slot
{
1855 struct anv_query_pool
{
1861 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
1864 void anv_dump_image_to_ppm(struct anv_device
*device
,
1865 struct anv_image
*image
, unsigned miplevel
,
1866 unsigned array_layer
, VkImageAspectFlagBits aspect
,
1867 const char *filename
);
1869 enum anv_dump_action
{
1870 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
1873 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
1874 void anv_dump_finish(void);
1876 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
1877 struct anv_framebuffer
*fb
);
1880 VkStructureType sType
;
1881 struct anv_common
*pNext
;
1884 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1886 static inline struct __anv_type * \
1887 __anv_type ## _from_handle(__VkType _handle) \
1889 return (struct __anv_type *) _handle; \
1892 static inline __VkType \
1893 __anv_type ## _to_handle(struct __anv_type *_obj) \
1895 return (__VkType) _obj; \
1898 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1900 static inline struct __anv_type * \
1901 __anv_type ## _from_handle(__VkType _handle) \
1903 return (struct __anv_type *)(uintptr_t) _handle; \
1906 static inline __VkType \
1907 __anv_type ## _to_handle(struct __anv_type *_obj) \
1909 return (__VkType)(uintptr_t) _obj; \
1912 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1913 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1915 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
1916 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
1917 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
1918 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
1919 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
1921 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
1922 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
1923 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
1924 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
1925 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
1926 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
1927 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
1928 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
1929 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
1930 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
1931 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
1932 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
1933 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
1934 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
1935 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
1936 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
1937 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
1938 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
1939 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
1941 /* Gen-specific function declarations */
1943 # include "anv_genX.h"
1945 # define genX(x) gen7_##x
1946 # include "anv_genX.h"
1948 # define genX(x) gen75_##x
1949 # include "anv_genX.h"
1951 # define genX(x) gen8_##x
1952 # include "anv_genX.h"
1954 # define genX(x) gen9_##x
1955 # include "anv_genX.h"
1963 #endif /* ANV_PRIVATE_H */