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anv: Move size check from anv_bo_cache_import() to caller (v2)
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "common/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53
54 /* Pre-declarations needed for WSI entrypoints */
55 struct wl_surface;
56 struct wl_display;
57 typedef struct xcb_connection_t xcb_connection_t;
58 typedef uint32_t xcb_visualid_t;
59 typedef uint32_t xcb_window_t;
60
61 struct anv_buffer;
62 struct anv_buffer_view;
63 struct anv_image_view;
64 struct anv_instance;
65 struct anv_debug_report_callback;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "anv_entrypoints.h"
74 #include "isl/isl.h"
75
76 #include "common/gen_debug.h"
77 #include "common/intel_log.h"
78 #include "wsi_common.h"
79
80 /* Allowing different clear colors requires us to perform a depth resolve at
81 * the end of certain render passes. This is because while slow clears store
82 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
83 * See the PRMs for examples describing when additional resolves would be
84 * necessary. To enable fast clears without requiring extra resolves, we set
85 * the clear value to a globally-defined one. We could allow different values
86 * if the user doesn't expect coherent data during or after a render passes
87 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
88 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
89 * 1.0f seems to be the only value used. The only application that doesn't set
90 * this value does so through the usage of an seemingly uninitialized clear
91 * value.
92 */
93 #define ANV_HZ_FC_VAL 1.0f
94
95 #define MAX_VBS 28
96 #define MAX_SETS 8
97 #define MAX_RTS 8
98 #define MAX_VIEWPORTS 16
99 #define MAX_SCISSORS 16
100 #define MAX_PUSH_CONSTANTS_SIZE 128
101 #define MAX_DYNAMIC_BUFFERS 16
102 #define MAX_IMAGES 8
103 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
104
105 #define ANV_SVGS_VB_INDEX MAX_VBS
106 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
107
108 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
109
110 static inline uint32_t
111 align_down_npot_u32(uint32_t v, uint32_t a)
112 {
113 return v - (v % a);
114 }
115
116 static inline uint32_t
117 align_u32(uint32_t v, uint32_t a)
118 {
119 assert(a != 0 && a == (a & -a));
120 return (v + a - 1) & ~(a - 1);
121 }
122
123 static inline uint64_t
124 align_u64(uint64_t v, uint64_t a)
125 {
126 assert(a != 0 && a == (a & -a));
127 return (v + a - 1) & ~(a - 1);
128 }
129
130 static inline int32_t
131 align_i32(int32_t v, int32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 /** Alignment must be a power of 2. */
138 static inline bool
139 anv_is_aligned(uintmax_t n, uintmax_t a)
140 {
141 assert(a == (a & -a));
142 return (n & (a - 1)) == 0;
143 }
144
145 static inline uint32_t
146 anv_minify(uint32_t n, uint32_t levels)
147 {
148 if (unlikely(n == 0))
149 return 0;
150 else
151 return MAX2(n >> levels, 1);
152 }
153
154 static inline float
155 anv_clamp_f(float f, float min, float max)
156 {
157 assert(min < max);
158
159 if (f > max)
160 return max;
161 else if (f < min)
162 return min;
163 else
164 return f;
165 }
166
167 static inline bool
168 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
169 {
170 if (*inout_mask & clear_mask) {
171 *inout_mask &= ~clear_mask;
172 return true;
173 } else {
174 return false;
175 }
176 }
177
178 static inline union isl_color_value
179 vk_to_isl_color(VkClearColorValue color)
180 {
181 return (union isl_color_value) {
182 .u32 = {
183 color.uint32[0],
184 color.uint32[1],
185 color.uint32[2],
186 color.uint32[3],
187 },
188 };
189 }
190
191 #define for_each_bit(b, dword) \
192 for (uint32_t __dword = (dword); \
193 (b) = __builtin_ffs(__dword) - 1, __dword; \
194 __dword &= ~(1 << (b)))
195
196 #define typed_memcpy(dest, src, count) ({ \
197 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
198 memcpy((dest), (src), (count) * sizeof(*(src))); \
199 })
200
201 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
202 * to be added here in order to utilize mapping in debug/error/perf macros.
203 */
204 #define REPORT_OBJECT_TYPE(o) \
205 __builtin_choose_expr ( \
206 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
207 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
208 __builtin_choose_expr ( \
209 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
210 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
211 __builtin_choose_expr ( \
212 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
213 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
214 __builtin_choose_expr ( \
215 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
216 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
217 __builtin_choose_expr ( \
218 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
219 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
220 __builtin_choose_expr ( \
221 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
222 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
223 __builtin_choose_expr ( \
224 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
225 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
226 __builtin_choose_expr ( \
227 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
228 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
229 __builtin_choose_expr ( \
230 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
231 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
232 __builtin_choose_expr ( \
233 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
234 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
235 __builtin_choose_expr ( \
236 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
237 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
238 __builtin_choose_expr ( \
239 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
240 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
241 __builtin_choose_expr ( \
242 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
243 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
244 __builtin_choose_expr ( \
245 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
246 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
247 __builtin_choose_expr ( \
248 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
249 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
250 __builtin_choose_expr ( \
251 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
252 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
253 __builtin_choose_expr ( \
254 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
255 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
256 __builtin_choose_expr ( \
257 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
258 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
259 __builtin_choose_expr ( \
260 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
261 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
262 __builtin_choose_expr ( \
263 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
264 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
265 __builtin_choose_expr ( \
266 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
267 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
268 __builtin_choose_expr ( \
269 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
270 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
271 __builtin_choose_expr ( \
272 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
273 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
274 __builtin_choose_expr ( \
275 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
276 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
277 __builtin_choose_expr ( \
278 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
279 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
280 __builtin_choose_expr ( \
281 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
282 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
283 __builtin_choose_expr ( \
284 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
285 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
286 __builtin_choose_expr ( \
287 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
288 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
289 __builtin_choose_expr ( \
290 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
291 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
292 __builtin_choose_expr ( \
293 __builtin_types_compatible_p (__typeof (o), struct anv_debug_callback*), \
294 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
295 __builtin_choose_expr ( \
296 __builtin_types_compatible_p (__typeof (o), void*), \
297 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
298 /* The void expression results in a compile-time error \
299 when assigning the result to something. */ \
300 (void)0)))))))))))))))))))))))))))))))
301
302 /* Whenever we generate an error, pass it through this function. Useful for
303 * debugging, where we can break on it. Only call at error site, not when
304 * propagating errors. Might be useful to plug in a stack trace here.
305 */
306
307 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
308 VkDebugReportObjectTypeEXT type, VkResult error,
309 const char *file, int line, const char *format, ...);
310
311 #ifdef DEBUG
312 #define vk_error(error) __vk_errorf(NULL, NULL,\
313 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
314 error, __FILE__, __LINE__, NULL);
315 #define vk_errorf(instance, obj, error, format, ...)\
316 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
317 __FILE__, __LINE__, format, ## __VA_ARGS__);
318 #else
319 #define vk_error(error) error
320 #define vk_errorf(instance, obj, error, format, ...) error
321 #endif
322
323 /**
324 * Warn on ignored extension structs.
325 *
326 * The Vulkan spec requires us to ignore unsupported or unknown structs in
327 * a pNext chain. In debug mode, emitting warnings for ignored structs may
328 * help us discover structs that we should not have ignored.
329 *
330 *
331 * From the Vulkan 1.0.38 spec:
332 *
333 * Any component of the implementation (the loader, any enabled layers,
334 * and drivers) must skip over, without processing (other than reading the
335 * sType and pNext members) any chained structures with sType values not
336 * defined by extensions supported by that component.
337 */
338 #define anv_debug_ignored_stype(sType) \
339 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
340
341 void __anv_perf_warn(struct anv_instance *instance, const void *object,
342 VkDebugReportObjectTypeEXT type, const char *file,
343 int line, const char *format, ...)
344 anv_printflike(6, 7);
345 void anv_loge(const char *format, ...) anv_printflike(1, 2);
346 void anv_loge_v(const char *format, va_list va);
347
348 void anv_debug_report(struct anv_instance *instance,
349 VkDebugReportFlagsEXT flags,
350 VkDebugReportObjectTypeEXT object_type,
351 uint64_t handle,
352 size_t location,
353 int32_t messageCode,
354 const char* pLayerPrefix,
355 const char *pMessage);
356
357 /**
358 * Print a FINISHME message, including its source location.
359 */
360 #define anv_finishme(format, ...) \
361 do { \
362 static bool reported = false; \
363 if (!reported) { \
364 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
365 ##__VA_ARGS__); \
366 reported = true; \
367 } \
368 } while (0)
369
370 /**
371 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
372 */
373 #define anv_perf_warn(instance, obj, format, ...) \
374 do { \
375 static bool reported = false; \
376 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
377 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
378 format, ##__VA_ARGS__); \
379 reported = true; \
380 } \
381 } while (0)
382
383 /* A non-fatal assert. Useful for debugging. */
384 #ifdef DEBUG
385 #define anv_assert(x) ({ \
386 if (unlikely(!(x))) \
387 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
388 })
389 #else
390 #define anv_assert(x)
391 #endif
392
393 /* A multi-pointer allocator
394 *
395 * When copying data structures from the user (such as a render pass), it's
396 * common to need to allocate data for a bunch of different things. Instead
397 * of doing several allocations and having to handle all of the error checking
398 * that entails, it can be easier to do a single allocation. This struct
399 * helps facilitate that. The intended usage looks like this:
400 *
401 * ANV_MULTIALLOC(ma)
402 * anv_multialloc_add(&ma, &main_ptr, 1);
403 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
404 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
405 *
406 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
407 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
408 */
409 struct anv_multialloc {
410 size_t size;
411 size_t align;
412
413 uint32_t ptr_count;
414 void **ptrs[8];
415 };
416
417 #define ANV_MULTIALLOC_INIT \
418 ((struct anv_multialloc) { 0, })
419
420 #define ANV_MULTIALLOC(_name) \
421 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
422
423 __attribute__((always_inline))
424 static inline void
425 _anv_multialloc_add(struct anv_multialloc *ma,
426 void **ptr, size_t size, size_t align)
427 {
428 size_t offset = align_u64(ma->size, align);
429 ma->size = offset + size;
430 ma->align = MAX2(ma->align, align);
431
432 /* Store the offset in the pointer. */
433 *ptr = (void *)(uintptr_t)offset;
434
435 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
436 ma->ptrs[ma->ptr_count++] = ptr;
437 }
438
439 #define anv_multialloc_add_size(_ma, _ptr, _size) \
440 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
441
442 #define anv_multialloc_add(_ma, _ptr, _count) \
443 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
444
445 __attribute__((always_inline))
446 static inline void *
447 anv_multialloc_alloc(struct anv_multialloc *ma,
448 const VkAllocationCallbacks *alloc,
449 VkSystemAllocationScope scope)
450 {
451 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
452 if (!ptr)
453 return NULL;
454
455 /* Fill out each of the pointers with their final value.
456 *
457 * for (uint32_t i = 0; i < ma->ptr_count; i++)
458 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
459 *
460 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
461 * constant, GCC is incapable of figuring this out and unrolling the loop
462 * so we have to give it a little help.
463 */
464 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
465 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
466 if ((_i) < ma->ptr_count) \
467 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
468 _ANV_MULTIALLOC_UPDATE_POINTER(0);
469 _ANV_MULTIALLOC_UPDATE_POINTER(1);
470 _ANV_MULTIALLOC_UPDATE_POINTER(2);
471 _ANV_MULTIALLOC_UPDATE_POINTER(3);
472 _ANV_MULTIALLOC_UPDATE_POINTER(4);
473 _ANV_MULTIALLOC_UPDATE_POINTER(5);
474 _ANV_MULTIALLOC_UPDATE_POINTER(6);
475 _ANV_MULTIALLOC_UPDATE_POINTER(7);
476 #undef _ANV_MULTIALLOC_UPDATE_POINTER
477
478 return ptr;
479 }
480
481 __attribute__((always_inline))
482 static inline void *
483 anv_multialloc_alloc2(struct anv_multialloc *ma,
484 const VkAllocationCallbacks *parent_alloc,
485 const VkAllocationCallbacks *alloc,
486 VkSystemAllocationScope scope)
487 {
488 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
489 }
490
491 struct anv_bo {
492 uint32_t gem_handle;
493
494 /* Index into the current validation list. This is used by the
495 * validation list building alrogithm to track which buffers are already
496 * in the validation list so that we can ensure uniqueness.
497 */
498 uint32_t index;
499
500 /* Last known offset. This value is provided by the kernel when we
501 * execbuf and is used as the presumed offset for the next bunch of
502 * relocations.
503 */
504 uint64_t offset;
505
506 uint64_t size;
507 void *map;
508
509 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
510 uint32_t flags;
511 };
512
513 static inline void
514 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
515 {
516 bo->gem_handle = gem_handle;
517 bo->index = 0;
518 bo->offset = -1;
519 bo->size = size;
520 bo->map = NULL;
521 bo->flags = 0;
522 }
523
524 /* Represents a lock-free linked list of "free" things. This is used by
525 * both the block pool and the state pools. Unfortunately, in order to
526 * solve the ABA problem, we can't use a single uint32_t head.
527 */
528 union anv_free_list {
529 struct {
530 int32_t offset;
531
532 /* A simple count that is incremented every time the head changes. */
533 uint32_t count;
534 };
535 uint64_t u64;
536 };
537
538 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
539
540 struct anv_block_state {
541 union {
542 struct {
543 uint32_t next;
544 uint32_t end;
545 };
546 uint64_t u64;
547 };
548 };
549
550 struct anv_block_pool {
551 struct anv_device *device;
552
553 struct anv_bo bo;
554
555 /* The offset from the start of the bo to the "center" of the block
556 * pool. Pointers to allocated blocks are given by
557 * bo.map + center_bo_offset + offsets.
558 */
559 uint32_t center_bo_offset;
560
561 /* Current memory map of the block pool. This pointer may or may not
562 * point to the actual beginning of the block pool memory. If
563 * anv_block_pool_alloc_back has ever been called, then this pointer
564 * will point to the "center" position of the buffer and all offsets
565 * (negative or positive) given out by the block pool alloc functions
566 * will be valid relative to this pointer.
567 *
568 * In particular, map == bo.map + center_offset
569 */
570 void *map;
571 int fd;
572
573 /**
574 * Array of mmaps and gem handles owned by the block pool, reclaimed when
575 * the block pool is destroyed.
576 */
577 struct u_vector mmap_cleanups;
578
579 struct anv_block_state state;
580
581 struct anv_block_state back_state;
582 };
583
584 /* Block pools are backed by a fixed-size 1GB memfd */
585 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
586
587 /* The center of the block pool is also the middle of the memfd. This may
588 * change in the future if we decide differently for some reason.
589 */
590 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
591
592 static inline uint32_t
593 anv_block_pool_size(struct anv_block_pool *pool)
594 {
595 return pool->state.end + pool->back_state.end;
596 }
597
598 struct anv_state {
599 int32_t offset;
600 uint32_t alloc_size;
601 void *map;
602 };
603
604 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
605
606 struct anv_fixed_size_state_pool {
607 union anv_free_list free_list;
608 struct anv_block_state block;
609 };
610
611 #define ANV_MIN_STATE_SIZE_LOG2 6
612 #define ANV_MAX_STATE_SIZE_LOG2 20
613
614 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
615
616 struct anv_state_pool {
617 struct anv_block_pool block_pool;
618
619 /* The size of blocks which will be allocated from the block pool */
620 uint32_t block_size;
621
622 /** Free list for "back" allocations */
623 union anv_free_list back_alloc_free_list;
624
625 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
626 };
627
628 struct anv_state_stream_block;
629
630 struct anv_state_stream {
631 struct anv_state_pool *state_pool;
632
633 /* The size of blocks to allocate from the state pool */
634 uint32_t block_size;
635
636 /* Current block we're allocating from */
637 struct anv_state block;
638
639 /* Offset into the current block at which to allocate the next state */
640 uint32_t next;
641
642 /* List of all blocks allocated from this pool */
643 struct anv_state_stream_block *block_list;
644 };
645
646 /* The block_pool functions exported for testing only. The block pool should
647 * only be used via a state pool (see below).
648 */
649 VkResult anv_block_pool_init(struct anv_block_pool *pool,
650 struct anv_device *device,
651 uint32_t initial_size);
652 void anv_block_pool_finish(struct anv_block_pool *pool);
653 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
654 uint32_t block_size);
655 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
656 uint32_t block_size);
657
658 VkResult anv_state_pool_init(struct anv_state_pool *pool,
659 struct anv_device *device,
660 uint32_t block_size);
661 void anv_state_pool_finish(struct anv_state_pool *pool);
662 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
663 uint32_t state_size, uint32_t alignment);
664 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
665 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
666 void anv_state_stream_init(struct anv_state_stream *stream,
667 struct anv_state_pool *state_pool,
668 uint32_t block_size);
669 void anv_state_stream_finish(struct anv_state_stream *stream);
670 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
671 uint32_t size, uint32_t alignment);
672
673 /**
674 * Implements a pool of re-usable BOs. The interface is identical to that
675 * of block_pool except that each block is its own BO.
676 */
677 struct anv_bo_pool {
678 struct anv_device *device;
679
680 void *free_list[16];
681 };
682
683 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
684 void anv_bo_pool_finish(struct anv_bo_pool *pool);
685 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
686 uint32_t size);
687 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
688
689 struct anv_scratch_bo {
690 bool exists;
691 struct anv_bo bo;
692 };
693
694 struct anv_scratch_pool {
695 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
696 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
697 };
698
699 void anv_scratch_pool_init(struct anv_device *device,
700 struct anv_scratch_pool *pool);
701 void anv_scratch_pool_finish(struct anv_device *device,
702 struct anv_scratch_pool *pool);
703 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
704 struct anv_scratch_pool *pool,
705 gl_shader_stage stage,
706 unsigned per_thread_scratch);
707
708 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
709 struct anv_bo_cache {
710 struct hash_table *bo_map;
711 pthread_mutex_t mutex;
712 };
713
714 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
715 void anv_bo_cache_finish(struct anv_bo_cache *cache);
716 VkResult anv_bo_cache_alloc(struct anv_device *device,
717 struct anv_bo_cache *cache,
718 uint64_t size, struct anv_bo **bo);
719 VkResult anv_bo_cache_import(struct anv_device *device,
720 struct anv_bo_cache *cache,
721 int fd, struct anv_bo **bo);
722 VkResult anv_bo_cache_export(struct anv_device *device,
723 struct anv_bo_cache *cache,
724 struct anv_bo *bo_in, int *fd_out);
725 void anv_bo_cache_release(struct anv_device *device,
726 struct anv_bo_cache *cache,
727 struct anv_bo *bo);
728
729 struct anv_memory_type {
730 /* Standard bits passed on to the client */
731 VkMemoryPropertyFlags propertyFlags;
732 uint32_t heapIndex;
733
734 /* Driver-internal book-keeping */
735 VkBufferUsageFlags valid_buffer_usage;
736 };
737
738 struct anv_memory_heap {
739 /* Standard bits passed on to the client */
740 VkDeviceSize size;
741 VkMemoryHeapFlags flags;
742
743 /* Driver-internal book-keeping */
744 bool supports_48bit_addresses;
745 };
746
747 struct anv_physical_device {
748 VK_LOADER_DATA _loader_data;
749
750 struct anv_instance * instance;
751 uint32_t chipset_id;
752 char path[20];
753 const char * name;
754 struct gen_device_info info;
755 /** Amount of "GPU memory" we want to advertise
756 *
757 * Clearly, this value is bogus since Intel is a UMA architecture. On
758 * gen7 platforms, we are limited by GTT size unless we want to implement
759 * fine-grained tracking and GTT splitting. On Broadwell and above we are
760 * practically unlimited. However, we will never report more than 3/4 of
761 * the total system ram to try and avoid running out of RAM.
762 */
763 bool supports_48bit_addresses;
764 struct brw_compiler * compiler;
765 struct isl_device isl_dev;
766 int cmd_parser_version;
767 bool has_exec_async;
768 bool has_exec_fence;
769 bool has_syncobj;
770 bool has_syncobj_wait;
771
772 uint32_t eu_total;
773 uint32_t subslice_total;
774
775 struct {
776 uint32_t type_count;
777 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
778 uint32_t heap_count;
779 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
780 } memory;
781
782 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
783 uint8_t driver_uuid[VK_UUID_SIZE];
784 uint8_t device_uuid[VK_UUID_SIZE];
785
786 struct wsi_device wsi_device;
787 int local_fd;
788 };
789
790 struct anv_debug_report_callback {
791 /* Link in the 'callbacks' list in anv_instance struct. */
792 struct list_head link;
793 VkDebugReportFlagsEXT flags;
794 PFN_vkDebugReportCallbackEXT callback;
795 void * data;
796 };
797
798 struct anv_instance {
799 VK_LOADER_DATA _loader_data;
800
801 VkAllocationCallbacks alloc;
802
803 uint32_t apiVersion;
804 int physicalDeviceCount;
805 struct anv_physical_device physicalDevice;
806
807 /* VK_EXT_debug_report debug callbacks */
808 pthread_mutex_t callbacks_mutex;
809 struct list_head callbacks;
810 struct anv_debug_report_callback destroy_debug_cb;
811 };
812
813 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
814 void anv_finish_wsi(struct anv_physical_device *physical_device);
815
816 bool anv_instance_extension_supported(const char *name);
817 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
818 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
819 const char *name);
820
821 struct anv_queue {
822 VK_LOADER_DATA _loader_data;
823
824 struct anv_device * device;
825
826 struct anv_state_pool * pool;
827 };
828
829 struct anv_pipeline_cache {
830 struct anv_device * device;
831 pthread_mutex_t mutex;
832
833 struct hash_table * cache;
834 };
835
836 struct anv_pipeline_bind_map;
837
838 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
839 struct anv_device *device,
840 bool cache_enabled);
841 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
842
843 struct anv_shader_bin *
844 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
845 const void *key, uint32_t key_size);
846 struct anv_shader_bin *
847 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
848 const void *key_data, uint32_t key_size,
849 const void *kernel_data, uint32_t kernel_size,
850 const struct brw_stage_prog_data *prog_data,
851 uint32_t prog_data_size,
852 const struct anv_pipeline_bind_map *bind_map);
853
854 struct anv_device {
855 VK_LOADER_DATA _loader_data;
856
857 VkAllocationCallbacks alloc;
858
859 struct anv_instance * instance;
860 uint32_t chipset_id;
861 struct gen_device_info info;
862 struct isl_device isl_dev;
863 int context_id;
864 int fd;
865 bool can_chain_batches;
866 bool robust_buffer_access;
867
868 struct anv_bo_pool batch_bo_pool;
869
870 struct anv_bo_cache bo_cache;
871
872 struct anv_state_pool dynamic_state_pool;
873 struct anv_state_pool instruction_state_pool;
874 struct anv_state_pool surface_state_pool;
875
876 struct anv_bo workaround_bo;
877 struct anv_bo trivial_batch_bo;
878
879 struct anv_pipeline_cache blorp_shader_cache;
880 struct blorp_context blorp;
881
882 struct anv_state border_colors;
883
884 struct anv_queue queue;
885
886 struct anv_scratch_pool scratch_pool;
887
888 uint32_t default_mocs;
889
890 pthread_mutex_t mutex;
891 pthread_cond_t queue_submit;
892 bool lost;
893 };
894
895 static void inline
896 anv_state_flush(struct anv_device *device, struct anv_state state)
897 {
898 if (device->info.has_llc)
899 return;
900
901 gen_flush_range(state.map, state.alloc_size);
902 }
903
904 void anv_device_init_blorp(struct anv_device *device);
905 void anv_device_finish_blorp(struct anv_device *device);
906
907 VkResult anv_device_execbuf(struct anv_device *device,
908 struct drm_i915_gem_execbuffer2 *execbuf,
909 struct anv_bo **execbuf_bos);
910 VkResult anv_device_query_status(struct anv_device *device);
911 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
912 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
913 int64_t timeout);
914
915 void* anv_gem_mmap(struct anv_device *device,
916 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
917 void anv_gem_munmap(void *p, uint64_t size);
918 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
919 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
920 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
921 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
922 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
923 int anv_gem_execbuffer(struct anv_device *device,
924 struct drm_i915_gem_execbuffer2 *execbuf);
925 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
926 uint32_t stride, uint32_t tiling);
927 int anv_gem_create_context(struct anv_device *device);
928 int anv_gem_destroy_context(struct anv_device *device, int context);
929 int anv_gem_get_context_param(int fd, int context, uint32_t param,
930 uint64_t *value);
931 int anv_gem_get_param(int fd, uint32_t param);
932 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
933 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
934 int anv_gem_get_aperture(int fd, uint64_t *size);
935 bool anv_gem_supports_48b_addresses(int fd);
936 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
937 uint32_t *active, uint32_t *pending);
938 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
939 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
940 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
941 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
942 uint32_t read_domains, uint32_t write_domain);
943 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
944 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
945 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
946 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
947 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
948 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
949 uint32_t handle);
950 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
951 uint32_t handle, int fd);
952 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
953 bool anv_gem_supports_syncobj_wait(int fd);
954 int anv_gem_syncobj_wait(struct anv_device *device,
955 uint32_t *handles, uint32_t num_handles,
956 int64_t abs_timeout_ns, bool wait_all);
957
958 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
959
960 struct anv_reloc_list {
961 uint32_t num_relocs;
962 uint32_t array_length;
963 struct drm_i915_gem_relocation_entry * relocs;
964 struct anv_bo ** reloc_bos;
965 };
966
967 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
968 const VkAllocationCallbacks *alloc);
969 void anv_reloc_list_finish(struct anv_reloc_list *list,
970 const VkAllocationCallbacks *alloc);
971
972 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
973 const VkAllocationCallbacks *alloc,
974 uint32_t offset, struct anv_bo *target_bo,
975 uint32_t delta);
976
977 struct anv_batch_bo {
978 /* Link in the anv_cmd_buffer.owned_batch_bos list */
979 struct list_head link;
980
981 struct anv_bo bo;
982
983 /* Bytes actually consumed in this batch BO */
984 uint32_t length;
985
986 struct anv_reloc_list relocs;
987 };
988
989 struct anv_batch {
990 const VkAllocationCallbacks * alloc;
991
992 void * start;
993 void * end;
994 void * next;
995
996 struct anv_reloc_list * relocs;
997
998 /* This callback is called (with the associated user data) in the event
999 * that the batch runs out of space.
1000 */
1001 VkResult (*extend_cb)(struct anv_batch *, void *);
1002 void * user_data;
1003
1004 /**
1005 * Current error status of the command buffer. Used to track inconsistent
1006 * or incomplete command buffer states that are the consequence of run-time
1007 * errors such as out of memory scenarios. We want to track this in the
1008 * batch because the command buffer object is not visible to some parts
1009 * of the driver.
1010 */
1011 VkResult status;
1012 };
1013
1014 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1015 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1016 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1017 void *location, struct anv_bo *bo, uint32_t offset);
1018 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1019 struct anv_batch *batch);
1020
1021 static inline VkResult
1022 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1023 {
1024 assert(error != VK_SUCCESS);
1025 if (batch->status == VK_SUCCESS)
1026 batch->status = error;
1027 return batch->status;
1028 }
1029
1030 static inline bool
1031 anv_batch_has_error(struct anv_batch *batch)
1032 {
1033 return batch->status != VK_SUCCESS;
1034 }
1035
1036 struct anv_address {
1037 struct anv_bo *bo;
1038 uint32_t offset;
1039 };
1040
1041 static inline uint64_t
1042 _anv_combine_address(struct anv_batch *batch, void *location,
1043 const struct anv_address address, uint32_t delta)
1044 {
1045 if (address.bo == NULL) {
1046 return address.offset + delta;
1047 } else {
1048 assert(batch->start <= location && location < batch->end);
1049
1050 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1051 }
1052 }
1053
1054 #define __gen_address_type struct anv_address
1055 #define __gen_user_data struct anv_batch
1056 #define __gen_combine_address _anv_combine_address
1057
1058 /* Wrapper macros needed to work around preprocessor argument issues. In
1059 * particular, arguments don't get pre-evaluated if they are concatenated.
1060 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1061 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1062 * We can work around this easily enough with these helpers.
1063 */
1064 #define __anv_cmd_length(cmd) cmd ## _length
1065 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1066 #define __anv_cmd_header(cmd) cmd ## _header
1067 #define __anv_cmd_pack(cmd) cmd ## _pack
1068 #define __anv_reg_num(reg) reg ## _num
1069
1070 #define anv_pack_struct(dst, struc, ...) do { \
1071 struct struc __template = { \
1072 __VA_ARGS__ \
1073 }; \
1074 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1075 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1076 } while (0)
1077
1078 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1079 void *__dst = anv_batch_emit_dwords(batch, n); \
1080 if (__dst) { \
1081 struct cmd __template = { \
1082 __anv_cmd_header(cmd), \
1083 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1084 __VA_ARGS__ \
1085 }; \
1086 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1087 } \
1088 __dst; \
1089 })
1090
1091 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1092 do { \
1093 uint32_t *dw; \
1094 \
1095 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1096 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1097 if (!dw) \
1098 break; \
1099 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1100 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1101 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1102 } while (0)
1103
1104 #define anv_batch_emit(batch, cmd, name) \
1105 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1106 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1107 __builtin_expect(_dst != NULL, 1); \
1108 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1109 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1110 _dst = NULL; \
1111 }))
1112
1113 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1114 .GraphicsDataTypeGFDT = 0, \
1115 .LLCCacheabilityControlLLCCC = 0, \
1116 .L3CacheabilityControlL3CC = 1, \
1117 }
1118
1119 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1120 .LLCeLLCCacheabilityControlLLCCC = 0, \
1121 .L3CacheabilityControlL3CC = 1, \
1122 }
1123
1124 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1125 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1126 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1127 .AgeforQUADLRU = 0 \
1128 }
1129
1130 /* Skylake: MOCS is now an index into an array of 62 different caching
1131 * configurations programmed by the kernel.
1132 */
1133
1134 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1135 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1136 .IndextoMOCSTables = 2 \
1137 }
1138
1139 #define GEN9_MOCS_PTE { \
1140 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1141 .IndextoMOCSTables = 1 \
1142 }
1143
1144 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1145 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1146 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1147 .IndextoMOCSTables = 2 \
1148 }
1149
1150 #define GEN10_MOCS_PTE { \
1151 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1152 .IndextoMOCSTables = 1 \
1153 }
1154
1155 struct anv_device_memory {
1156 struct anv_bo * bo;
1157 struct anv_memory_type * type;
1158 VkDeviceSize map_size;
1159 void * map;
1160 };
1161
1162 /**
1163 * Header for Vertex URB Entry (VUE)
1164 */
1165 struct anv_vue_header {
1166 uint32_t Reserved;
1167 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1168 uint32_t ViewportIndex;
1169 float PointWidth;
1170 };
1171
1172 struct anv_descriptor_set_binding_layout {
1173 #ifndef NDEBUG
1174 /* The type of the descriptors in this binding */
1175 VkDescriptorType type;
1176 #endif
1177
1178 /* Number of array elements in this binding */
1179 uint16_t array_size;
1180
1181 /* Index into the flattend descriptor set */
1182 uint16_t descriptor_index;
1183
1184 /* Index into the dynamic state array for a dynamic buffer */
1185 int16_t dynamic_offset_index;
1186
1187 /* Index into the descriptor set buffer views */
1188 int16_t buffer_index;
1189
1190 struct {
1191 /* Index into the binding table for the associated surface */
1192 int16_t surface_index;
1193
1194 /* Index into the sampler table for the associated sampler */
1195 int16_t sampler_index;
1196
1197 /* Index into the image table for the associated image */
1198 int16_t image_index;
1199 } stage[MESA_SHADER_STAGES];
1200
1201 /* Immutable samplers (or NULL if no immutable samplers) */
1202 struct anv_sampler **immutable_samplers;
1203 };
1204
1205 struct anv_descriptor_set_layout {
1206 /* Number of bindings in this descriptor set */
1207 uint16_t binding_count;
1208
1209 /* Total size of the descriptor set with room for all array entries */
1210 uint16_t size;
1211
1212 /* Shader stages affected by this descriptor set */
1213 uint16_t shader_stages;
1214
1215 /* Number of buffers in this descriptor set */
1216 uint16_t buffer_count;
1217
1218 /* Number of dynamic offsets used by this descriptor set */
1219 uint16_t dynamic_offset_count;
1220
1221 /* Bindings in this descriptor set */
1222 struct anv_descriptor_set_binding_layout binding[0];
1223 };
1224
1225 struct anv_descriptor {
1226 VkDescriptorType type;
1227
1228 union {
1229 struct {
1230 VkImageLayout layout;
1231 struct anv_image_view *image_view;
1232 struct anv_sampler *sampler;
1233 };
1234
1235 struct {
1236 struct anv_buffer *buffer;
1237 uint64_t offset;
1238 uint64_t range;
1239 };
1240
1241 struct anv_buffer_view *buffer_view;
1242 };
1243 };
1244
1245 struct anv_descriptor_set {
1246 const struct anv_descriptor_set_layout *layout;
1247 uint32_t size;
1248 uint32_t buffer_count;
1249 struct anv_buffer_view *buffer_views;
1250 struct anv_descriptor descriptors[0];
1251 };
1252
1253 struct anv_buffer_view {
1254 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1255 struct anv_bo *bo;
1256 uint32_t offset; /**< Offset into bo. */
1257 uint64_t range; /**< VkBufferViewCreateInfo::range */
1258
1259 struct anv_state surface_state;
1260 struct anv_state storage_surface_state;
1261 struct anv_state writeonly_storage_surface_state;
1262
1263 struct brw_image_param storage_image_param;
1264 };
1265
1266 struct anv_push_descriptor_set {
1267 struct anv_descriptor_set set;
1268
1269 /* Put this field right behind anv_descriptor_set so it fills up the
1270 * descriptors[0] field. */
1271 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1272 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1273 };
1274
1275 struct anv_descriptor_pool {
1276 uint32_t size;
1277 uint32_t next;
1278 uint32_t free_list;
1279
1280 struct anv_state_stream surface_state_stream;
1281 void *surface_state_free_list;
1282
1283 char data[0];
1284 };
1285
1286 enum anv_descriptor_template_entry_type {
1287 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1288 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1289 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1290 };
1291
1292 struct anv_descriptor_template_entry {
1293 /* The type of descriptor in this entry */
1294 VkDescriptorType type;
1295
1296 /* Binding in the descriptor set */
1297 uint32_t binding;
1298
1299 /* Offset at which to write into the descriptor set binding */
1300 uint32_t array_element;
1301
1302 /* Number of elements to write into the descriptor set binding */
1303 uint32_t array_count;
1304
1305 /* Offset into the user provided data */
1306 size_t offset;
1307
1308 /* Stride between elements into the user provided data */
1309 size_t stride;
1310 };
1311
1312 struct anv_descriptor_update_template {
1313 /* The descriptor set this template corresponds to. This value is only
1314 * valid if the template was created with the templateType
1315 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1316 */
1317 uint8_t set;
1318
1319 /* Number of entries in this template */
1320 uint32_t entry_count;
1321
1322 /* Entries of the template */
1323 struct anv_descriptor_template_entry entries[0];
1324 };
1325
1326 size_t
1327 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1328
1329 size_t
1330 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1331
1332 void
1333 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1334 const struct gen_device_info * const devinfo,
1335 const VkDescriptorImageInfo * const info,
1336 VkDescriptorType type,
1337 uint32_t binding,
1338 uint32_t element);
1339
1340 void
1341 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1342 VkDescriptorType type,
1343 struct anv_buffer_view *buffer_view,
1344 uint32_t binding,
1345 uint32_t element);
1346
1347 void
1348 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1349 struct anv_device *device,
1350 struct anv_state_stream *alloc_stream,
1351 VkDescriptorType type,
1352 struct anv_buffer *buffer,
1353 uint32_t binding,
1354 uint32_t element,
1355 VkDeviceSize offset,
1356 VkDeviceSize range);
1357
1358 void
1359 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1360 struct anv_device *device,
1361 struct anv_state_stream *alloc_stream,
1362 const struct anv_descriptor_update_template *template,
1363 const void *data);
1364
1365 VkResult
1366 anv_descriptor_set_create(struct anv_device *device,
1367 struct anv_descriptor_pool *pool,
1368 const struct anv_descriptor_set_layout *layout,
1369 struct anv_descriptor_set **out_set);
1370
1371 void
1372 anv_descriptor_set_destroy(struct anv_device *device,
1373 struct anv_descriptor_pool *pool,
1374 struct anv_descriptor_set *set);
1375
1376 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1377
1378 struct anv_pipeline_binding {
1379 /* The descriptor set this surface corresponds to. The special value of
1380 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1381 * to a color attachment and not a regular descriptor.
1382 */
1383 uint8_t set;
1384
1385 /* Binding in the descriptor set */
1386 uint32_t binding;
1387
1388 /* Index in the binding */
1389 uint32_t index;
1390
1391 /* Plane in the binding index */
1392 uint8_t plane;
1393
1394 /* Input attachment index (relative to the subpass) */
1395 uint8_t input_attachment_index;
1396
1397 /* For a storage image, whether it is write-only */
1398 bool write_only;
1399 };
1400
1401 struct anv_pipeline_layout {
1402 struct {
1403 struct anv_descriptor_set_layout *layout;
1404 uint32_t dynamic_offset_start;
1405 } set[MAX_SETS];
1406
1407 uint32_t num_sets;
1408
1409 struct {
1410 bool has_dynamic_offsets;
1411 } stage[MESA_SHADER_STAGES];
1412
1413 unsigned char sha1[20];
1414 };
1415
1416 struct anv_buffer {
1417 struct anv_device * device;
1418 VkDeviceSize size;
1419
1420 VkBufferUsageFlags usage;
1421
1422 /* Set when bound */
1423 struct anv_bo * bo;
1424 VkDeviceSize offset;
1425 };
1426
1427 static inline uint64_t
1428 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1429 {
1430 assert(offset <= buffer->size);
1431 if (range == VK_WHOLE_SIZE) {
1432 return buffer->size - offset;
1433 } else {
1434 assert(range <= buffer->size);
1435 return range;
1436 }
1437 }
1438
1439 enum anv_cmd_dirty_bits {
1440 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1441 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1442 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1443 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1444 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1445 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1446 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1447 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1448 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1449 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1450 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1451 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1452 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1453 };
1454 typedef uint32_t anv_cmd_dirty_mask_t;
1455
1456 enum anv_pipe_bits {
1457 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1458 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1459 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1460 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1461 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1462 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1463 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1464 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1465 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1466 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1467 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1468
1469 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1470 * a flush has happened but not a CS stall. The next time we do any sort
1471 * of invalidation we need to insert a CS stall at that time. Otherwise,
1472 * we would have to CS stall on every flush which could be bad.
1473 */
1474 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1475 };
1476
1477 #define ANV_PIPE_FLUSH_BITS ( \
1478 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1479 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1480 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1481
1482 #define ANV_PIPE_STALL_BITS ( \
1483 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1484 ANV_PIPE_DEPTH_STALL_BIT | \
1485 ANV_PIPE_CS_STALL_BIT)
1486
1487 #define ANV_PIPE_INVALIDATE_BITS ( \
1488 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1489 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1490 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1491 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1492 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1493 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1494
1495 static inline enum anv_pipe_bits
1496 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1497 {
1498 enum anv_pipe_bits pipe_bits = 0;
1499
1500 unsigned b;
1501 for_each_bit(b, flags) {
1502 switch ((VkAccessFlagBits)(1 << b)) {
1503 case VK_ACCESS_SHADER_WRITE_BIT:
1504 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1505 break;
1506 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1507 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1508 break;
1509 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1510 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1511 break;
1512 case VK_ACCESS_TRANSFER_WRITE_BIT:
1513 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1514 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1515 break;
1516 default:
1517 break; /* Nothing to do */
1518 }
1519 }
1520
1521 return pipe_bits;
1522 }
1523
1524 static inline enum anv_pipe_bits
1525 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1526 {
1527 enum anv_pipe_bits pipe_bits = 0;
1528
1529 unsigned b;
1530 for_each_bit(b, flags) {
1531 switch ((VkAccessFlagBits)(1 << b)) {
1532 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1533 case VK_ACCESS_INDEX_READ_BIT:
1534 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1535 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1536 break;
1537 case VK_ACCESS_UNIFORM_READ_BIT:
1538 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1539 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1540 break;
1541 case VK_ACCESS_SHADER_READ_BIT:
1542 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1543 case VK_ACCESS_TRANSFER_READ_BIT:
1544 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1545 break;
1546 default:
1547 break; /* Nothing to do */
1548 }
1549 }
1550
1551 return pipe_bits;
1552 }
1553
1554 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT ( \
1555 VK_IMAGE_ASPECT_COLOR_BIT | \
1556 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1557 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1558 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1559 #define VK_IMAGE_ASPECT_PLANES_BITS ( \
1560 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1561 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1562 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1563
1564 struct anv_vertex_binding {
1565 struct anv_buffer * buffer;
1566 VkDeviceSize offset;
1567 };
1568
1569 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1570 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1571
1572 struct anv_push_constants {
1573 /* Current allocated size of this push constants data structure.
1574 * Because a decent chunk of it may not be used (images on SKL, for
1575 * instance), we won't actually allocate the entire structure up-front.
1576 */
1577 uint32_t size;
1578
1579 /* Push constant data provided by the client through vkPushConstants */
1580 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1581
1582 /* Image data for image_load_store on pre-SKL */
1583 struct brw_image_param images[MAX_IMAGES];
1584 };
1585
1586 struct anv_dynamic_state {
1587 struct {
1588 uint32_t count;
1589 VkViewport viewports[MAX_VIEWPORTS];
1590 } viewport;
1591
1592 struct {
1593 uint32_t count;
1594 VkRect2D scissors[MAX_SCISSORS];
1595 } scissor;
1596
1597 float line_width;
1598
1599 struct {
1600 float bias;
1601 float clamp;
1602 float slope;
1603 } depth_bias;
1604
1605 float blend_constants[4];
1606
1607 struct {
1608 float min;
1609 float max;
1610 } depth_bounds;
1611
1612 struct {
1613 uint32_t front;
1614 uint32_t back;
1615 } stencil_compare_mask;
1616
1617 struct {
1618 uint32_t front;
1619 uint32_t back;
1620 } stencil_write_mask;
1621
1622 struct {
1623 uint32_t front;
1624 uint32_t back;
1625 } stencil_reference;
1626 };
1627
1628 extern const struct anv_dynamic_state default_dynamic_state;
1629
1630 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1631 const struct anv_dynamic_state *src,
1632 uint32_t copy_mask);
1633
1634 struct anv_surface_state {
1635 struct anv_state state;
1636 /** Address of the surface referred to by this state
1637 *
1638 * This address is relative to the start of the BO.
1639 */
1640 uint64_t address;
1641 /* Address of the aux surface, if any
1642 *
1643 * This field is 0 if and only if no aux surface exists.
1644 *
1645 * This address is relative to the start of the BO. On gen7, the bottom 12
1646 * bits of this address include extra aux information.
1647 */
1648 uint64_t aux_address;
1649 };
1650
1651 /**
1652 * Attachment state when recording a renderpass instance.
1653 *
1654 * The clear value is valid only if there exists a pending clear.
1655 */
1656 struct anv_attachment_state {
1657 enum isl_aux_usage aux_usage;
1658 enum isl_aux_usage input_aux_usage;
1659 struct anv_surface_state color;
1660 struct anv_surface_state input;
1661
1662 VkImageLayout current_layout;
1663 VkImageAspectFlags pending_clear_aspects;
1664 bool fast_clear;
1665 VkClearValue clear_value;
1666 bool clear_color_is_zero_one;
1667 bool clear_color_is_zero;
1668 };
1669
1670 /** State required while building cmd buffer */
1671 struct anv_cmd_state {
1672 /* PIPELINE_SELECT.PipelineSelection */
1673 uint32_t current_pipeline;
1674 const struct gen_l3_config * current_l3_config;
1675 uint32_t vb_dirty;
1676 anv_cmd_dirty_mask_t dirty;
1677 anv_cmd_dirty_mask_t compute_dirty;
1678 enum anv_pipe_bits pending_pipe_bits;
1679 uint32_t num_workgroups_offset;
1680 struct anv_bo *num_workgroups_bo;
1681 VkShaderStageFlags descriptors_dirty;
1682 VkShaderStageFlags push_constants_dirty;
1683 uint32_t scratch_size;
1684 struct anv_pipeline * pipeline;
1685 struct anv_pipeline * compute_pipeline;
1686 struct anv_framebuffer * framebuffer;
1687 struct anv_render_pass * pass;
1688 struct anv_subpass * subpass;
1689 VkRect2D render_area;
1690 uint32_t restart_index;
1691 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1692 struct anv_descriptor_set * descriptors[MAX_SETS];
1693 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1694 VkShaderStageFlags push_constant_stages;
1695 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1696 struct anv_state binding_tables[MESA_SHADER_STAGES];
1697 struct anv_state samplers[MESA_SHADER_STAGES];
1698 struct anv_dynamic_state dynamic;
1699 bool need_query_wa;
1700
1701 struct anv_push_descriptor_set * push_descriptors[MAX_SETS];
1702
1703 /**
1704 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1705 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1706 * and before invoking the secondary in ExecuteCommands.
1707 */
1708 bool pma_fix_enabled;
1709
1710 /**
1711 * Whether or not we know for certain that HiZ is enabled for the current
1712 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1713 * enabled or not, this will be false.
1714 */
1715 bool hiz_enabled;
1716
1717 /**
1718 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1719 * valid only when recording a render pass instance.
1720 */
1721 struct anv_attachment_state * attachments;
1722
1723 /**
1724 * Surface states for color render targets. These are stored in a single
1725 * flat array. For depth-stencil attachments, the surface state is simply
1726 * left blank.
1727 */
1728 struct anv_state render_pass_states;
1729
1730 /**
1731 * A null surface state of the right size to match the framebuffer. This
1732 * is one of the states in render_pass_states.
1733 */
1734 struct anv_state null_surface_state;
1735
1736 struct {
1737 struct anv_buffer * index_buffer;
1738 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1739 uint32_t index_offset;
1740 } gen7;
1741 };
1742
1743 struct anv_cmd_pool {
1744 VkAllocationCallbacks alloc;
1745 struct list_head cmd_buffers;
1746 };
1747
1748 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1749
1750 enum anv_cmd_buffer_exec_mode {
1751 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1752 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1753 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1754 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1755 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1756 };
1757
1758 struct anv_cmd_buffer {
1759 VK_LOADER_DATA _loader_data;
1760
1761 struct anv_device * device;
1762
1763 struct anv_cmd_pool * pool;
1764 struct list_head pool_link;
1765
1766 struct anv_batch batch;
1767
1768 /* Fields required for the actual chain of anv_batch_bo's.
1769 *
1770 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1771 */
1772 struct list_head batch_bos;
1773 enum anv_cmd_buffer_exec_mode exec_mode;
1774
1775 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1776 * referenced by this command buffer
1777 *
1778 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1779 */
1780 struct u_vector seen_bbos;
1781
1782 /* A vector of int32_t's for every block of binding tables.
1783 *
1784 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1785 */
1786 struct u_vector bt_block_states;
1787 uint32_t bt_next;
1788
1789 struct anv_reloc_list surface_relocs;
1790 /** Last seen surface state block pool center bo offset */
1791 uint32_t last_ss_pool_center;
1792
1793 /* Serial for tracking buffer completion */
1794 uint32_t serial;
1795
1796 /* Stream objects for storing temporary data */
1797 struct anv_state_stream surface_state_stream;
1798 struct anv_state_stream dynamic_state_stream;
1799
1800 VkCommandBufferUsageFlags usage_flags;
1801 VkCommandBufferLevel level;
1802
1803 struct anv_cmd_state state;
1804 };
1805
1806 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1807 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1808 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1809 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1810 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1811 struct anv_cmd_buffer *secondary);
1812 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1813 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1814 struct anv_cmd_buffer *cmd_buffer,
1815 const VkSemaphore *in_semaphores,
1816 uint32_t num_in_semaphores,
1817 const VkSemaphore *out_semaphores,
1818 uint32_t num_out_semaphores,
1819 VkFence fence);
1820
1821 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1822
1823 VkResult
1824 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1825 gl_shader_stage stage, uint32_t size);
1826 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1827 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1828 (offsetof(struct anv_push_constants, field) + \
1829 sizeof(cmd_buffer->state.push_constants[0]->field)))
1830
1831 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1832 const void *data, uint32_t size, uint32_t alignment);
1833 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1834 uint32_t *a, uint32_t *b,
1835 uint32_t dwords, uint32_t alignment);
1836
1837 struct anv_address
1838 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1839 struct anv_state
1840 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1841 uint32_t entries, uint32_t *state_offset);
1842 struct anv_state
1843 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1844 struct anv_state
1845 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1846 uint32_t size, uint32_t alignment);
1847
1848 VkResult
1849 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1850
1851 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1852 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1853 bool depth_clamp_enable);
1854 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1855
1856 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1857 struct anv_render_pass *pass,
1858 struct anv_framebuffer *framebuffer,
1859 const VkClearValue *clear_values);
1860
1861 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1862
1863 struct anv_state
1864 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1865 gl_shader_stage stage);
1866 struct anv_state
1867 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1868
1869 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1870 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1871
1872 const struct anv_image_view *
1873 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1874
1875 VkResult
1876 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1877 uint32_t num_entries,
1878 uint32_t *state_offset,
1879 struct anv_state *bt_state);
1880
1881 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1882
1883 enum anv_fence_type {
1884 ANV_FENCE_TYPE_NONE = 0,
1885 ANV_FENCE_TYPE_BO,
1886 ANV_FENCE_TYPE_SYNCOBJ,
1887 };
1888
1889 enum anv_bo_fence_state {
1890 /** Indicates that this is a new (or newly reset fence) */
1891 ANV_BO_FENCE_STATE_RESET,
1892
1893 /** Indicates that this fence has been submitted to the GPU but is still
1894 * (as far as we know) in use by the GPU.
1895 */
1896 ANV_BO_FENCE_STATE_SUBMITTED,
1897
1898 ANV_BO_FENCE_STATE_SIGNALED,
1899 };
1900
1901 struct anv_fence_impl {
1902 enum anv_fence_type type;
1903
1904 union {
1905 /** Fence implementation for BO fences
1906 *
1907 * These fences use a BO and a set of CPU-tracked state flags. The BO
1908 * is added to the object list of the last execbuf call in a QueueSubmit
1909 * and is marked EXEC_WRITE. The state flags track when the BO has been
1910 * submitted to the kernel. We need to do this because Vulkan lets you
1911 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1912 * will say it's idle in this case.
1913 */
1914 struct {
1915 struct anv_bo bo;
1916 enum anv_bo_fence_state state;
1917 } bo;
1918
1919 /** DRM syncobj handle for syncobj-based fences */
1920 uint32_t syncobj;
1921 };
1922 };
1923
1924 struct anv_fence {
1925 /* Permanent fence state. Every fence has some form of permanent state
1926 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
1927 * cross-process fences) or it could just be a dummy for use internally.
1928 */
1929 struct anv_fence_impl permanent;
1930
1931 /* Temporary fence state. A fence *may* have temporary state. That state
1932 * is added to the fence by an import operation and is reset back to
1933 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
1934 * state cannot be signaled because the fence must already be signaled
1935 * before the temporary state can be exported from the fence in the other
1936 * process and imported here.
1937 */
1938 struct anv_fence_impl temporary;
1939 };
1940
1941 struct anv_event {
1942 uint64_t semaphore;
1943 struct anv_state state;
1944 };
1945
1946 enum anv_semaphore_type {
1947 ANV_SEMAPHORE_TYPE_NONE = 0,
1948 ANV_SEMAPHORE_TYPE_DUMMY,
1949 ANV_SEMAPHORE_TYPE_BO,
1950 ANV_SEMAPHORE_TYPE_SYNC_FILE,
1951 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
1952 };
1953
1954 struct anv_semaphore_impl {
1955 enum anv_semaphore_type type;
1956
1957 union {
1958 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
1959 * This BO will be added to the object list on any execbuf2 calls for
1960 * which this semaphore is used as a wait or signal fence. When used as
1961 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
1962 */
1963 struct anv_bo *bo;
1964
1965 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
1966 * If the semaphore is in the unsignaled state due to either just being
1967 * created or because it has been used for a wait, fd will be -1.
1968 */
1969 int fd;
1970
1971 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
1972 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
1973 * import so we don't need to bother with a userspace cache.
1974 */
1975 uint32_t syncobj;
1976 };
1977 };
1978
1979 struct anv_semaphore {
1980 /* Permanent semaphore state. Every semaphore has some form of permanent
1981 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
1982 * (for cross-process semaphores0 or it could just be a dummy for use
1983 * internally.
1984 */
1985 struct anv_semaphore_impl permanent;
1986
1987 /* Temporary semaphore state. A semaphore *may* have temporary state.
1988 * That state is added to the semaphore by an import operation and is reset
1989 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
1990 * semaphore with temporary state cannot be signaled because the semaphore
1991 * must already be signaled before the temporary state can be exported from
1992 * the semaphore in the other process and imported here.
1993 */
1994 struct anv_semaphore_impl temporary;
1995 };
1996
1997 void anv_semaphore_reset_temporary(struct anv_device *device,
1998 struct anv_semaphore *semaphore);
1999
2000 struct anv_shader_module {
2001 unsigned char sha1[20];
2002 uint32_t size;
2003 char data[0];
2004 };
2005
2006 static inline gl_shader_stage
2007 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2008 {
2009 assert(__builtin_popcount(vk_stage) == 1);
2010 return ffs(vk_stage) - 1;
2011 }
2012
2013 static inline VkShaderStageFlagBits
2014 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2015 {
2016 return (1 << mesa_stage);
2017 }
2018
2019 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2020
2021 #define anv_foreach_stage(stage, stage_bits) \
2022 for (gl_shader_stage stage, \
2023 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2024 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2025 __tmp &= ~(1 << (stage)))
2026
2027 struct anv_pipeline_bind_map {
2028 uint32_t surface_count;
2029 uint32_t sampler_count;
2030 uint32_t image_count;
2031
2032 struct anv_pipeline_binding * surface_to_descriptor;
2033 struct anv_pipeline_binding * sampler_to_descriptor;
2034 };
2035
2036 struct anv_shader_bin_key {
2037 uint32_t size;
2038 uint8_t data[0];
2039 };
2040
2041 struct anv_shader_bin {
2042 uint32_t ref_cnt;
2043
2044 const struct anv_shader_bin_key *key;
2045
2046 struct anv_state kernel;
2047 uint32_t kernel_size;
2048
2049 const struct brw_stage_prog_data *prog_data;
2050 uint32_t prog_data_size;
2051
2052 struct anv_pipeline_bind_map bind_map;
2053 };
2054
2055 struct anv_shader_bin *
2056 anv_shader_bin_create(struct anv_device *device,
2057 const void *key, uint32_t key_size,
2058 const void *kernel, uint32_t kernel_size,
2059 const struct brw_stage_prog_data *prog_data,
2060 uint32_t prog_data_size, const void *prog_data_param,
2061 const struct anv_pipeline_bind_map *bind_map);
2062
2063 void
2064 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2065
2066 static inline void
2067 anv_shader_bin_ref(struct anv_shader_bin *shader)
2068 {
2069 assert(shader && shader->ref_cnt >= 1);
2070 p_atomic_inc(&shader->ref_cnt);
2071 }
2072
2073 static inline void
2074 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2075 {
2076 assert(shader && shader->ref_cnt >= 1);
2077 if (p_atomic_dec_zero(&shader->ref_cnt))
2078 anv_shader_bin_destroy(device, shader);
2079 }
2080
2081 struct anv_pipeline {
2082 struct anv_device * device;
2083 struct anv_batch batch;
2084 uint32_t batch_data[512];
2085 struct anv_reloc_list batch_relocs;
2086 uint32_t dynamic_state_mask;
2087 struct anv_dynamic_state dynamic_state;
2088
2089 struct anv_subpass * subpass;
2090 struct anv_pipeline_layout * layout;
2091
2092 bool needs_data_cache;
2093
2094 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2095
2096 struct {
2097 const struct gen_l3_config * l3_config;
2098 uint32_t total_size;
2099 } urb;
2100
2101 VkShaderStageFlags active_stages;
2102 struct anv_state blend_state;
2103
2104 uint32_t vb_used;
2105 uint32_t binding_stride[MAX_VBS];
2106 bool instancing_enable[MAX_VBS];
2107 bool primitive_restart;
2108 uint32_t topology;
2109
2110 uint32_t cs_right_mask;
2111
2112 bool writes_depth;
2113 bool depth_test_enable;
2114 bool writes_stencil;
2115 bool stencil_test_enable;
2116 bool depth_clamp_enable;
2117 bool sample_shading_enable;
2118 bool kill_pixel;
2119
2120 struct {
2121 uint32_t sf[7];
2122 uint32_t depth_stencil_state[3];
2123 } gen7;
2124
2125 struct {
2126 uint32_t sf[4];
2127 uint32_t raster[5];
2128 uint32_t wm_depth_stencil[3];
2129 } gen8;
2130
2131 struct {
2132 uint32_t wm_depth_stencil[4];
2133 } gen9;
2134
2135 uint32_t interface_descriptor_data[8];
2136 };
2137
2138 static inline bool
2139 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2140 gl_shader_stage stage)
2141 {
2142 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2143 }
2144
2145 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2146 static inline const struct brw_##prefix##_prog_data * \
2147 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2148 { \
2149 if (anv_pipeline_has_stage(pipeline, stage)) { \
2150 return (const struct brw_##prefix##_prog_data *) \
2151 pipeline->shaders[stage]->prog_data; \
2152 } else { \
2153 return NULL; \
2154 } \
2155 }
2156
2157 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2158 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2159 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2160 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2161 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2162 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2163
2164 static inline const struct brw_vue_prog_data *
2165 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2166 {
2167 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2168 return &get_gs_prog_data(pipeline)->base;
2169 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2170 return &get_tes_prog_data(pipeline)->base;
2171 else
2172 return &get_vs_prog_data(pipeline)->base;
2173 }
2174
2175 VkResult
2176 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2177 struct anv_pipeline_cache *cache,
2178 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2179 const VkAllocationCallbacks *alloc);
2180
2181 VkResult
2182 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2183 struct anv_pipeline_cache *cache,
2184 const VkComputePipelineCreateInfo *info,
2185 struct anv_shader_module *module,
2186 const char *entrypoint,
2187 const VkSpecializationInfo *spec_info);
2188
2189 struct anv_format_plane {
2190 enum isl_format isl_format:16;
2191 struct isl_swizzle swizzle;
2192
2193 /* Whether this plane contains chroma channels */
2194 bool has_chroma;
2195
2196 /* For downscaling of YUV planes */
2197 uint8_t denominator_scales[2];
2198
2199 /* How to map sampled ycbcr planes to a single 4 component element. */
2200 struct isl_swizzle ycbcr_swizzle;
2201 };
2202
2203
2204 struct anv_format {
2205 struct anv_format_plane planes[3];
2206 uint8_t n_planes;
2207 bool can_ycbcr;
2208 };
2209
2210 static inline uint32_t
2211 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2212 VkImageAspectFlags aspect_mask)
2213 {
2214 switch (aspect_mask) {
2215 case VK_IMAGE_ASPECT_COLOR_BIT:
2216 case VK_IMAGE_ASPECT_DEPTH_BIT:
2217 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
2218 return 0;
2219 case VK_IMAGE_ASPECT_STENCIL_BIT:
2220 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2221 return 0;
2222 /* Fall-through */
2223 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
2224 return 1;
2225 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
2226 return 2;
2227 default:
2228 /* Purposefully assert with depth/stencil aspects. */
2229 unreachable("invalid image aspect");
2230 }
2231 }
2232
2233 static inline uint32_t
2234 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2235 {
2236 uint32_t planes = 0;
2237
2238 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2239 VK_IMAGE_ASPECT_DEPTH_BIT |
2240 VK_IMAGE_ASPECT_STENCIL_BIT |
2241 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR))
2242 planes++;
2243 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT_KHR)
2244 planes++;
2245 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
2246 planes++;
2247
2248 return planes;
2249 }
2250
2251 static inline VkImageAspectFlags
2252 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2253 uint32_t plane)
2254 {
2255 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT) {
2256 if (_mesa_bitcount(image_aspects) > 1)
2257 return VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << plane;
2258 return VK_IMAGE_ASPECT_COLOR_BIT;
2259 }
2260 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2261 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2262 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2263 return VK_IMAGE_ASPECT_STENCIL_BIT;
2264 }
2265
2266 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2267 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2268
2269 const struct anv_format *
2270 anv_get_format(VkFormat format);
2271
2272 static inline uint32_t
2273 anv_get_format_planes(VkFormat vk_format)
2274 {
2275 const struct anv_format *format = anv_get_format(vk_format);
2276
2277 return format != NULL ? format->n_planes : 0;
2278 }
2279
2280 struct anv_format_plane
2281 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2282 VkImageAspectFlags aspect, VkImageTiling tiling);
2283
2284 static inline enum isl_format
2285 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2286 VkImageAspectFlags aspect, VkImageTiling tiling)
2287 {
2288 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2289 }
2290
2291 static inline struct isl_swizzle
2292 anv_swizzle_for_render(struct isl_swizzle swizzle)
2293 {
2294 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2295 * RGB as RGBA for texturing
2296 */
2297 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2298 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2299
2300 /* But it doesn't matter what we render to that channel */
2301 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2302
2303 return swizzle;
2304 }
2305
2306 void
2307 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2308
2309 /**
2310 * Subsurface of an anv_image.
2311 */
2312 struct anv_surface {
2313 /** Valid only if isl_surf::size > 0. */
2314 struct isl_surf isl;
2315
2316 /**
2317 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2318 */
2319 uint32_t offset;
2320 };
2321
2322 struct anv_image {
2323 VkImageType type;
2324 /* The original VkFormat provided by the client. This may not match any
2325 * of the actual surface formats.
2326 */
2327 VkFormat vk_format;
2328 const struct anv_format *format;
2329
2330 VkImageAspectFlags aspects;
2331 VkExtent3D extent;
2332 uint32_t levels;
2333 uint32_t array_size;
2334 uint32_t samples; /**< VkImageCreateInfo::samples */
2335 uint32_t n_planes;
2336 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2337 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2338
2339 VkDeviceSize size;
2340 uint32_t alignment;
2341
2342 /* Whether the image is made of several underlying buffer objects rather a
2343 * single one with different offsets.
2344 */
2345 bool disjoint;
2346
2347 /**
2348 * Image subsurfaces
2349 *
2350 * For each foo, anv_image::planes[x].surface is valid if and only if
2351 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2352 * to figure the number associated with a given aspect.
2353 *
2354 * The hardware requires that the depth buffer and stencil buffer be
2355 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2356 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2357 * allocate the depth and stencil buffers as separate surfaces in the same
2358 * bo.
2359 *
2360 * Memory layout :
2361 *
2362 * -----------------------
2363 * | surface0 | /|\
2364 * ----------------------- |
2365 * | shadow surface0 | |
2366 * ----------------------- | Plane 0
2367 * | aux surface0 | |
2368 * ----------------------- |
2369 * | fast clear colors0 | \|/
2370 * -----------------------
2371 * | surface1 | /|\
2372 * ----------------------- |
2373 * | shadow surface1 | |
2374 * ----------------------- | Plane 1
2375 * | aux surface1 | |
2376 * ----------------------- |
2377 * | fast clear colors1 | \|/
2378 * -----------------------
2379 * | ... |
2380 * | |
2381 * -----------------------
2382 */
2383 struct {
2384 /**
2385 * Offset of the entire plane (whenever the image is disjoint this is
2386 * set to 0).
2387 */
2388 uint32_t offset;
2389
2390 VkDeviceSize size;
2391 uint32_t alignment;
2392
2393 struct anv_surface surface;
2394
2395 /**
2396 * A surface which shadows the main surface and may have different
2397 * tiling. This is used for sampling using a tiling that isn't supported
2398 * for other operations.
2399 */
2400 struct anv_surface shadow_surface;
2401
2402 /**
2403 * For color images, this is the aux usage for this image when not used
2404 * as a color attachment.
2405 *
2406 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2407 * image has a HiZ buffer.
2408 */
2409 enum isl_aux_usage aux_usage;
2410
2411 struct anv_surface aux_surface;
2412
2413 /**
2414 * Offset of the fast clear state (used to compute the
2415 * fast_clear_state_offset of the following planes).
2416 */
2417 uint32_t fast_clear_state_offset;
2418
2419 /**
2420 * BO associated with this plane, set when bound.
2421 */
2422 struct anv_bo *bo;
2423 VkDeviceSize bo_offset;
2424
2425 /**
2426 * When destroying the image, also free the bo.
2427 * */
2428 bool bo_is_owned;
2429 } planes[3];
2430 };
2431
2432 /* Returns the number of auxiliary buffer levels attached to an image. */
2433 static inline uint8_t
2434 anv_image_aux_levels(const struct anv_image * const image,
2435 VkImageAspectFlagBits aspect)
2436 {
2437 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2438 return image->planes[plane].aux_surface.isl.size > 0 ?
2439 image->planes[plane].aux_surface.isl.levels : 0;
2440 }
2441
2442 /* Returns the number of auxiliary buffer layers attached to an image. */
2443 static inline uint32_t
2444 anv_image_aux_layers(const struct anv_image * const image,
2445 VkImageAspectFlagBits aspect,
2446 const uint8_t miplevel)
2447 {
2448 assert(image);
2449
2450 /* The miplevel must exist in the main buffer. */
2451 assert(miplevel < image->levels);
2452
2453 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2454 /* There are no layers with auxiliary data because the miplevel has no
2455 * auxiliary data.
2456 */
2457 return 0;
2458 } else {
2459 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2460 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2461 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2462 }
2463 }
2464
2465 static inline unsigned
2466 anv_fast_clear_state_entry_size(const struct anv_device *device)
2467 {
2468 assert(device);
2469 /* Entry contents:
2470 * +--------------------------------------------+
2471 * | clear value dword(s) | needs resolve dword |
2472 * +--------------------------------------------+
2473 */
2474
2475 /* Ensure that the needs resolve dword is in fact dword-aligned to enable
2476 * GPU memcpy operations.
2477 */
2478 assert(device->isl_dev.ss.clear_value_size % 4 == 0);
2479 return device->isl_dev.ss.clear_value_size + 4;
2480 }
2481
2482 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2483 static inline bool
2484 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2485 const struct anv_image *image)
2486 {
2487 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2488 return false;
2489
2490 if (devinfo->gen < 8)
2491 return false;
2492
2493 return image->samples == 1;
2494 }
2495
2496 void
2497 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
2498 const struct anv_image *image,
2499 enum blorp_hiz_op op);
2500 void
2501 anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
2502 const struct anv_state surface_state,
2503 const struct anv_image * const image,
2504 VkImageAspectFlagBits aspect,
2505 const uint8_t level, const uint32_t layer_count,
2506 const enum blorp_fast_clear_op op);
2507
2508 void
2509 anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
2510 const struct anv_image *image,
2511 VkImageAspectFlagBits aspect,
2512 const uint32_t base_level, const uint32_t level_count,
2513 const uint32_t base_layer, uint32_t layer_count);
2514
2515 void
2516 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2517 const struct anv_image *image,
2518 uint32_t base_level, uint32_t level_count,
2519 uint32_t base_layer, uint32_t layer_count);
2520
2521 enum isl_aux_usage
2522 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2523 const struct anv_image *image,
2524 const VkImageAspectFlagBits aspect,
2525 const VkImageLayout layout);
2526
2527 /* This is defined as a macro so that it works for both
2528 * VkImageSubresourceRange and VkImageSubresourceLayers
2529 */
2530 #define anv_get_layerCount(_image, _range) \
2531 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2532 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2533
2534 static inline uint32_t
2535 anv_get_levelCount(const struct anv_image *image,
2536 const VkImageSubresourceRange *range)
2537 {
2538 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2539 image->levels - range->baseMipLevel : range->levelCount;
2540 }
2541
2542 static inline VkImageAspectFlags
2543 anv_image_expand_aspects(const struct anv_image *image,
2544 VkImageAspectFlags aspects)
2545 {
2546 /* If the underlying image has color plane aspects and
2547 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2548 * the underlying image. */
2549 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS) != 0 &&
2550 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2551 return image->aspects;
2552
2553 return aspects;
2554 }
2555
2556 static inline bool
2557 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2558 VkImageAspectFlags aspects2)
2559 {
2560 if (aspects1 == aspects2)
2561 return true;
2562
2563 /* Only 1 color aspects are compatibles. */
2564 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT) != 0 &&
2565 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT) != 0 &&
2566 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2567 return true;
2568
2569 return false;
2570 }
2571
2572 struct anv_image_view {
2573 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2574
2575 VkImageAspectFlags aspect_mask;
2576 VkFormat vk_format;
2577 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2578
2579 unsigned n_planes;
2580 struct {
2581 uint32_t image_plane;
2582
2583 struct isl_view isl;
2584
2585 /**
2586 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2587 * image layout of SHADER_READ_ONLY_OPTIMAL or
2588 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2589 */
2590 struct anv_surface_state optimal_sampler_surface_state;
2591
2592 /**
2593 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2594 * image layout of GENERAL.
2595 */
2596 struct anv_surface_state general_sampler_surface_state;
2597
2598 /**
2599 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2600 * states for write-only and readable, using the real format for
2601 * write-only and the lowered format for readable.
2602 */
2603 struct anv_surface_state storage_surface_state;
2604 struct anv_surface_state writeonly_storage_surface_state;
2605
2606 struct brw_image_param storage_image_param;
2607 } planes[3];
2608 };
2609
2610 enum anv_image_view_state_flags {
2611 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2612 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2613 };
2614
2615 void anv_image_fill_surface_state(struct anv_device *device,
2616 const struct anv_image *image,
2617 VkImageAspectFlagBits aspect,
2618 const struct isl_view *view,
2619 isl_surf_usage_flags_t view_usage,
2620 enum isl_aux_usage aux_usage,
2621 const union isl_color_value *clear_color,
2622 enum anv_image_view_state_flags flags,
2623 struct anv_surface_state *state_inout,
2624 struct brw_image_param *image_param_out);
2625
2626 struct anv_image_create_info {
2627 const VkImageCreateInfo *vk_info;
2628
2629 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2630 isl_tiling_flags_t isl_tiling_flags;
2631
2632 uint32_t stride;
2633 };
2634
2635 VkResult anv_image_create(VkDevice _device,
2636 const struct anv_image_create_info *info,
2637 const VkAllocationCallbacks* alloc,
2638 VkImage *pImage);
2639
2640 const struct anv_surface *
2641 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2642 VkImageAspectFlags aspect_mask);
2643
2644 enum isl_format
2645 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2646
2647 static inline struct VkExtent3D
2648 anv_sanitize_image_extent(const VkImageType imageType,
2649 const struct VkExtent3D imageExtent)
2650 {
2651 switch (imageType) {
2652 case VK_IMAGE_TYPE_1D:
2653 return (VkExtent3D) { imageExtent.width, 1, 1 };
2654 case VK_IMAGE_TYPE_2D:
2655 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2656 case VK_IMAGE_TYPE_3D:
2657 return imageExtent;
2658 default:
2659 unreachable("invalid image type");
2660 }
2661 }
2662
2663 static inline struct VkOffset3D
2664 anv_sanitize_image_offset(const VkImageType imageType,
2665 const struct VkOffset3D imageOffset)
2666 {
2667 switch (imageType) {
2668 case VK_IMAGE_TYPE_1D:
2669 return (VkOffset3D) { imageOffset.x, 0, 0 };
2670 case VK_IMAGE_TYPE_2D:
2671 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2672 case VK_IMAGE_TYPE_3D:
2673 return imageOffset;
2674 default:
2675 unreachable("invalid image type");
2676 }
2677 }
2678
2679
2680 void anv_fill_buffer_surface_state(struct anv_device *device,
2681 struct anv_state state,
2682 enum isl_format format,
2683 uint32_t offset, uint32_t range,
2684 uint32_t stride);
2685
2686
2687 struct anv_ycbcr_conversion {
2688 const struct anv_format * format;
2689 VkSamplerYcbcrModelConversionKHR ycbcr_model;
2690 VkSamplerYcbcrRangeKHR ycbcr_range;
2691 VkComponentSwizzle mapping[4];
2692 VkChromaLocationKHR chroma_offsets[2];
2693 VkFilter chroma_filter;
2694 bool chroma_reconstruction;
2695 };
2696
2697 struct anv_sampler {
2698 uint32_t state[3][4];
2699 uint32_t n_planes;
2700 struct anv_ycbcr_conversion *conversion;
2701 };
2702
2703 struct anv_framebuffer {
2704 uint32_t width;
2705 uint32_t height;
2706 uint32_t layers;
2707
2708 uint32_t attachment_count;
2709 struct anv_image_view * attachments[0];
2710 };
2711
2712 struct anv_subpass {
2713 uint32_t attachment_count;
2714
2715 /**
2716 * A pointer to all attachment references used in this subpass.
2717 * Only valid if ::attachment_count > 0.
2718 */
2719 VkAttachmentReference * attachments;
2720 uint32_t input_count;
2721 VkAttachmentReference * input_attachments;
2722 uint32_t color_count;
2723 VkAttachmentReference * color_attachments;
2724 VkAttachmentReference * resolve_attachments;
2725
2726 VkAttachmentReference depth_stencil_attachment;
2727
2728 uint32_t view_mask;
2729
2730 /** Subpass has a depth/stencil self-dependency */
2731 bool has_ds_self_dep;
2732
2733 /** Subpass has at least one resolve attachment */
2734 bool has_resolve;
2735 };
2736
2737 static inline unsigned
2738 anv_subpass_view_count(const struct anv_subpass *subpass)
2739 {
2740 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2741 }
2742
2743 struct anv_render_pass_attachment {
2744 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2745 * its members individually.
2746 */
2747 VkFormat format;
2748 uint32_t samples;
2749 VkImageUsageFlags usage;
2750 VkAttachmentLoadOp load_op;
2751 VkAttachmentStoreOp store_op;
2752 VkAttachmentLoadOp stencil_load_op;
2753 VkImageLayout initial_layout;
2754 VkImageLayout final_layout;
2755 VkImageLayout first_subpass_layout;
2756
2757 /* The subpass id in which the attachment will be used last. */
2758 uint32_t last_subpass_idx;
2759 };
2760
2761 struct anv_render_pass {
2762 uint32_t attachment_count;
2763 uint32_t subpass_count;
2764 /* An array of subpass_count+1 flushes, one per subpass boundary */
2765 enum anv_pipe_bits * subpass_flushes;
2766 struct anv_render_pass_attachment * attachments;
2767 struct anv_subpass subpasses[0];
2768 };
2769
2770 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2771
2772 struct anv_query_pool {
2773 VkQueryType type;
2774 VkQueryPipelineStatisticFlags pipeline_statistics;
2775 /** Stride between slots, in bytes */
2776 uint32_t stride;
2777 /** Number of slots in this query pool */
2778 uint32_t slots;
2779 struct anv_bo bo;
2780 };
2781
2782 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2783 const char *name);
2784
2785 void anv_dump_image_to_ppm(struct anv_device *device,
2786 struct anv_image *image, unsigned miplevel,
2787 unsigned array_layer, VkImageAspectFlagBits aspect,
2788 const char *filename);
2789
2790 enum anv_dump_action {
2791 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2792 };
2793
2794 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2795 void anv_dump_finish(void);
2796
2797 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2798 struct anv_framebuffer *fb);
2799
2800 static inline uint32_t
2801 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2802 {
2803 /* This function must be called from within a subpass. */
2804 assert(cmd_state->pass && cmd_state->subpass);
2805
2806 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
2807
2808 /* The id of this subpass shouldn't exceed the number of subpasses in this
2809 * render pass minus 1.
2810 */
2811 assert(subpass_id < cmd_state->pass->subpass_count);
2812 return subpass_id;
2813 }
2814
2815 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
2816 \
2817 static inline struct __anv_type * \
2818 __anv_type ## _from_handle(__VkType _handle) \
2819 { \
2820 return (struct __anv_type *) _handle; \
2821 } \
2822 \
2823 static inline __VkType \
2824 __anv_type ## _to_handle(struct __anv_type *_obj) \
2825 { \
2826 return (__VkType) _obj; \
2827 }
2828
2829 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
2830 \
2831 static inline struct __anv_type * \
2832 __anv_type ## _from_handle(__VkType _handle) \
2833 { \
2834 return (struct __anv_type *)(uintptr_t) _handle; \
2835 } \
2836 \
2837 static inline __VkType \
2838 __anv_type ## _to_handle(struct __anv_type *_obj) \
2839 { \
2840 return (__VkType)(uintptr_t) _obj; \
2841 }
2842
2843 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
2844 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
2845
2846 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
2847 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
2848 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
2849 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
2850 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
2851
2852 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
2853 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
2854 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
2855 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
2856 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
2857 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
2858 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
2859 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
2860 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
2861 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
2862 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
2863 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
2864 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
2865 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
2866 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
2867 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
2868 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
2869 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
2870 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
2871 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
2872 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
2873 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_debug_report_callback, VkDebugReportCallbackEXT)
2874 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversionKHR)
2875
2876 /* Gen-specific function declarations */
2877 #ifdef genX
2878 # include "anv_genX.h"
2879 #else
2880 # define genX(x) gen7_##x
2881 # include "anv_genX.h"
2882 # undef genX
2883 # define genX(x) gen75_##x
2884 # include "anv_genX.h"
2885 # undef genX
2886 # define genX(x) gen8_##x
2887 # include "anv_genX.h"
2888 # undef genX
2889 # define genX(x) gen9_##x
2890 # include "anv_genX.h"
2891 # undef genX
2892 # define genX(x) gen10_##x
2893 # include "anv_genX.h"
2894 # undef genX
2895 #endif
2896
2897 #endif /* ANV_PRIVATE_H */