Move the intel vulkan driver to src/intel/vulkan
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #pragma once
25
26 #include <stdlib.h>
27 #include <stdio.h>
28 #include <stdbool.h>
29 #include <pthread.h>
30 #include <assert.h>
31 #include <stdint.h>
32 #include <i915_drm.h>
33
34 #ifdef HAVE_VALGRIND
35 #include <valgrind.h>
36 #include <memcheck.h>
37 #define VG(x) x
38 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
39 #else
40 #define VG(x)
41 #endif
42
43 #include "brw_device_info.h"
44 #include "util/macros.h"
45 #include "util/list.h"
46
47 /* Pre-declarations needed for WSI entrypoints */
48 struct wl_surface;
49 struct wl_display;
50 typedef struct xcb_connection_t xcb_connection_t;
51 typedef uint32_t xcb_visualid_t;
52 typedef uint32_t xcb_window_t;
53
54 #define VK_USE_PLATFORM_XCB_KHR
55 #define VK_USE_PLATFORM_WAYLAND_KHR
56
57 #define VK_PROTOTYPES
58 #include <vulkan/vulkan.h>
59 #include <vulkan/vulkan_intel.h>
60 #include <vulkan/vk_icd.h>
61
62 #include "anv_entrypoints.h"
63 #include "anv_gen_macros.h"
64 #include "brw_context.h"
65 #include "isl/isl.h"
66
67 #ifdef __cplusplus
68 extern "C" {
69 #endif
70
71 #define MAX_VBS 32
72 #define MAX_SETS 8
73 #define MAX_RTS 8
74 #define MAX_VIEWPORTS 16
75 #define MAX_SCISSORS 16
76 #define MAX_PUSH_CONSTANTS_SIZE 128
77 #define MAX_DYNAMIC_BUFFERS 16
78 #define MAX_IMAGES 8
79 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
80
81 #define anv_noreturn __attribute__((__noreturn__))
82 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
83
84 #define MIN(a, b) ((a) < (b) ? (a) : (b))
85 #define MAX(a, b) ((a) > (b) ? (a) : (b))
86
87 static inline uint32_t
88 align_u32(uint32_t v, uint32_t a)
89 {
90 assert(a != 0 && a == (a & -a));
91 return (v + a - 1) & ~(a - 1);
92 }
93
94 static inline uint64_t
95 align_u64(uint64_t v, uint64_t a)
96 {
97 assert(a != 0 && a == (a & -a));
98 return (v + a - 1) & ~(a - 1);
99 }
100
101 static inline int32_t
102 align_i32(int32_t v, int32_t a)
103 {
104 assert(a != 0 && a == (a & -a));
105 return (v + a - 1) & ~(a - 1);
106 }
107
108 /** Alignment must be a power of 2. */
109 static inline bool
110 anv_is_aligned(uintmax_t n, uintmax_t a)
111 {
112 assert(a == (a & -a));
113 return (n & (a - 1)) == 0;
114 }
115
116 static inline uint32_t
117 anv_minify(uint32_t n, uint32_t levels)
118 {
119 if (unlikely(n == 0))
120 return 0;
121 else
122 return MAX(n >> levels, 1);
123 }
124
125 static inline float
126 anv_clamp_f(float f, float min, float max)
127 {
128 assert(min < max);
129
130 if (f > max)
131 return max;
132 else if (f < min)
133 return min;
134 else
135 return f;
136 }
137
138 static inline bool
139 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
140 {
141 if (*inout_mask & clear_mask) {
142 *inout_mask &= ~clear_mask;
143 return true;
144 } else {
145 return false;
146 }
147 }
148
149 #define for_each_bit(b, dword) \
150 for (uint32_t __dword = (dword); \
151 (b) = __builtin_ffs(__dword) - 1, __dword; \
152 __dword &= ~(1 << (b)))
153
154 #define typed_memcpy(dest, src, count) ({ \
155 static_assert(sizeof(*src) == sizeof(*dest), ""); \
156 memcpy((dest), (src), (count) * sizeof(*(src))); \
157 })
158
159 #define zero(x) (memset(&(x), 0, sizeof(x)))
160
161 /* Define no kernel as 1, since that's an illegal offset for a kernel */
162 #define NO_KERNEL 1
163
164 struct anv_common {
165 VkStructureType sType;
166 const void* pNext;
167 };
168
169 /* Whenever we generate an error, pass it through this function. Useful for
170 * debugging, where we can break on it. Only call at error site, not when
171 * propagating errors. Might be useful to plug in a stack trace here.
172 */
173
174 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
175
176 #ifdef DEBUG
177 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
178 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
179 #else
180 #define vk_error(error) error
181 #define vk_errorf(error, format, ...) error
182 #endif
183
184 void __anv_finishme(const char *file, int line, const char *format, ...)
185 anv_printflike(3, 4);
186 void anv_loge(const char *format, ...) anv_printflike(1, 2);
187 void anv_loge_v(const char *format, va_list va);
188
189 /**
190 * Print a FINISHME message, including its source location.
191 */
192 #define anv_finishme(format, ...) \
193 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
194
195 /* A non-fatal assert. Useful for debugging. */
196 #ifdef DEBUG
197 #define anv_assert(x) ({ \
198 if (unlikely(!(x))) \
199 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
200 })
201 #else
202 #define anv_assert(x)
203 #endif
204
205 /**
206 * If a block of code is annotated with anv_validate, then the block runs only
207 * in debug builds.
208 */
209 #ifdef DEBUG
210 #define anv_validate if (1)
211 #else
212 #define anv_validate if (0)
213 #endif
214
215 void anv_abortf(const char *format, ...) anv_noreturn anv_printflike(1, 2);
216 void anv_abortfv(const char *format, va_list va) anv_noreturn;
217
218 #define stub_return(v) \
219 do { \
220 anv_finishme("stub %s", __func__); \
221 return (v); \
222 } while (0)
223
224 #define stub() \
225 do { \
226 anv_finishme("stub %s", __func__); \
227 return; \
228 } while (0)
229
230 /**
231 * A dynamically growable, circular buffer. Elements are added at head and
232 * removed from tail. head and tail are free-running uint32_t indices and we
233 * only compute the modulo with size when accessing the array. This way,
234 * number of bytes in the queue is always head - tail, even in case of
235 * wraparound.
236 */
237
238 struct anv_vector {
239 uint32_t head;
240 uint32_t tail;
241 uint32_t element_size;
242 uint32_t size;
243 void *data;
244 };
245
246 int anv_vector_init(struct anv_vector *queue, uint32_t element_size, uint32_t size);
247 void *anv_vector_add(struct anv_vector *queue);
248 void *anv_vector_remove(struct anv_vector *queue);
249
250 static inline int
251 anv_vector_length(struct anv_vector *queue)
252 {
253 return (queue->head - queue->tail) / queue->element_size;
254 }
255
256 static inline void *
257 anv_vector_head(struct anv_vector *vector)
258 {
259 assert(vector->tail < vector->head);
260 return (void *)((char *)vector->data +
261 ((vector->head - vector->element_size) &
262 (vector->size - 1)));
263 }
264
265 static inline void *
266 anv_vector_tail(struct anv_vector *vector)
267 {
268 return (void *)((char *)vector->data + (vector->tail & (vector->size - 1)));
269 }
270
271 static inline void
272 anv_vector_finish(struct anv_vector *queue)
273 {
274 free(queue->data);
275 }
276
277 #define anv_vector_foreach(elem, queue) \
278 static_assert(__builtin_types_compatible_p(__typeof__(queue), struct anv_vector *), ""); \
279 for (uint32_t __anv_vector_offset = (queue)->tail; \
280 elem = (queue)->data + (__anv_vector_offset & ((queue)->size - 1)), __anv_vector_offset < (queue)->head; \
281 __anv_vector_offset += (queue)->element_size)
282
283 struct anv_bo {
284 uint32_t gem_handle;
285
286 /* Index into the current validation list. This is used by the
287 * validation list building alrogithm to track which buffers are already
288 * in the validation list so that we can ensure uniqueness.
289 */
290 uint32_t index;
291
292 /* Last known offset. This value is provided by the kernel when we
293 * execbuf and is used as the presumed offset for the next bunch of
294 * relocations.
295 */
296 uint64_t offset;
297
298 uint64_t size;
299 void *map;
300
301 /* We need to set the WRITE flag on winsys bos so GEM will know we're
302 * writing to them and synchronize uses on other rings (eg if the display
303 * server uses the blitter ring).
304 */
305 bool is_winsys_bo;
306 };
307
308 /* Represents a lock-free linked list of "free" things. This is used by
309 * both the block pool and the state pools. Unfortunately, in order to
310 * solve the ABA problem, we can't use a single uint32_t head.
311 */
312 union anv_free_list {
313 struct {
314 int32_t offset;
315
316 /* A simple count that is incremented every time the head changes. */
317 uint32_t count;
318 };
319 uint64_t u64;
320 };
321
322 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
323
324 struct anv_block_state {
325 union {
326 struct {
327 uint32_t next;
328 uint32_t end;
329 };
330 uint64_t u64;
331 };
332 };
333
334 struct anv_block_pool {
335 struct anv_device *device;
336
337 struct anv_bo bo;
338
339 /* The offset from the start of the bo to the "center" of the block
340 * pool. Pointers to allocated blocks are given by
341 * bo.map + center_bo_offset + offsets.
342 */
343 uint32_t center_bo_offset;
344
345 /* Current memory map of the block pool. This pointer may or may not
346 * point to the actual beginning of the block pool memory. If
347 * anv_block_pool_alloc_back has ever been called, then this pointer
348 * will point to the "center" position of the buffer and all offsets
349 * (negative or positive) given out by the block pool alloc functions
350 * will be valid relative to this pointer.
351 *
352 * In particular, map == bo.map + center_offset
353 */
354 void *map;
355 int fd;
356
357 /**
358 * Array of mmaps and gem handles owned by the block pool, reclaimed when
359 * the block pool is destroyed.
360 */
361 struct anv_vector mmap_cleanups;
362
363 uint32_t block_size;
364
365 union anv_free_list free_list;
366 struct anv_block_state state;
367
368 union anv_free_list back_free_list;
369 struct anv_block_state back_state;
370 };
371
372 /* Block pools are backed by a fixed-size 2GB memfd */
373 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
374
375 /* The center of the block pool is also the middle of the memfd. This may
376 * change in the future if we decide differently for some reason.
377 */
378 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
379
380 static inline uint32_t
381 anv_block_pool_size(struct anv_block_pool *pool)
382 {
383 return pool->state.end + pool->back_state.end;
384 }
385
386 struct anv_state {
387 int32_t offset;
388 uint32_t alloc_size;
389 void *map;
390 };
391
392 struct anv_fixed_size_state_pool {
393 size_t state_size;
394 union anv_free_list free_list;
395 struct anv_block_state block;
396 };
397
398 #define ANV_MIN_STATE_SIZE_LOG2 6
399 #define ANV_MAX_STATE_SIZE_LOG2 10
400
401 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2)
402
403 struct anv_state_pool {
404 struct anv_block_pool *block_pool;
405 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
406 };
407
408 struct anv_state_stream_block;
409
410 struct anv_state_stream {
411 struct anv_block_pool *block_pool;
412
413 /* The current working block */
414 struct anv_state_stream_block *block;
415
416 /* Offset at which the current block starts */
417 uint32_t start;
418 /* Offset at which to allocate the next state */
419 uint32_t next;
420 /* Offset at which the current block ends */
421 uint32_t end;
422 };
423
424 #define CACHELINE_SIZE 64
425 #define CACHELINE_MASK 63
426
427 static inline void
428 anv_clflush_range(void *start, size_t size)
429 {
430 void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
431 void *end = start + size;
432
433 __builtin_ia32_mfence();
434 while (p < end) {
435 __builtin_ia32_clflush(p);
436 p += CACHELINE_SIZE;
437 }
438 }
439
440 static void inline
441 anv_state_clflush(struct anv_state state)
442 {
443 anv_clflush_range(state.map, state.alloc_size);
444 }
445
446 void anv_block_pool_init(struct anv_block_pool *pool,
447 struct anv_device *device, uint32_t block_size);
448 void anv_block_pool_finish(struct anv_block_pool *pool);
449 int32_t anv_block_pool_alloc(struct anv_block_pool *pool);
450 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool);
451 void anv_block_pool_free(struct anv_block_pool *pool, int32_t offset);
452 void anv_state_pool_init(struct anv_state_pool *pool,
453 struct anv_block_pool *block_pool);
454 void anv_state_pool_finish(struct anv_state_pool *pool);
455 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
456 size_t state_size, size_t alignment);
457 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
458 void anv_state_stream_init(struct anv_state_stream *stream,
459 struct anv_block_pool *block_pool);
460 void anv_state_stream_finish(struct anv_state_stream *stream);
461 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
462 uint32_t size, uint32_t alignment);
463
464 /**
465 * Implements a pool of re-usable BOs. The interface is identical to that
466 * of block_pool except that each block is its own BO.
467 */
468 struct anv_bo_pool {
469 struct anv_device *device;
470
471 uint32_t bo_size;
472
473 void *free_list;
474 };
475
476 void anv_bo_pool_init(struct anv_bo_pool *pool,
477 struct anv_device *device, uint32_t block_size);
478 void anv_bo_pool_finish(struct anv_bo_pool *pool);
479 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo);
480 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
481
482
483 void *anv_resolve_entrypoint(uint32_t index);
484
485 extern struct anv_dispatch_table dtable;
486
487 #define ANV_CALL(func) ({ \
488 if (dtable.func == NULL) { \
489 size_t idx = offsetof(struct anv_dispatch_table, func) / sizeof(void *); \
490 dtable.entrypoints[idx] = anv_resolve_entrypoint(idx); \
491 } \
492 dtable.func; \
493 })
494
495 static inline void *
496 anv_alloc(const VkAllocationCallbacks *alloc,
497 size_t size, size_t align,
498 VkSystemAllocationScope scope)
499 {
500 return alloc->pfnAllocation(alloc->pUserData, size, align, scope);
501 }
502
503 static inline void *
504 anv_realloc(const VkAllocationCallbacks *alloc,
505 void *ptr, size_t size, size_t align,
506 VkSystemAllocationScope scope)
507 {
508 return alloc->pfnReallocation(alloc->pUserData, ptr, size, align, scope);
509 }
510
511 static inline void
512 anv_free(const VkAllocationCallbacks *alloc, void *data)
513 {
514 alloc->pfnFree(alloc->pUserData, data);
515 }
516
517 static inline void *
518 anv_alloc2(const VkAllocationCallbacks *parent_alloc,
519 const VkAllocationCallbacks *alloc,
520 size_t size, size_t align,
521 VkSystemAllocationScope scope)
522 {
523 if (alloc)
524 return anv_alloc(alloc, size, align, scope);
525 else
526 return anv_alloc(parent_alloc, size, align, scope);
527 }
528
529 static inline void
530 anv_free2(const VkAllocationCallbacks *parent_alloc,
531 const VkAllocationCallbacks *alloc,
532 void *data)
533 {
534 if (alloc)
535 anv_free(alloc, data);
536 else
537 anv_free(parent_alloc, data);
538 }
539
540 struct anv_physical_device {
541 VK_LOADER_DATA _loader_data;
542
543 struct anv_instance * instance;
544 uint32_t chipset_id;
545 const char * path;
546 const char * name;
547 const struct brw_device_info * info;
548 uint64_t aperture_size;
549 struct brw_compiler * compiler;
550 struct isl_device isl_dev;
551 };
552
553 struct anv_wsi_interaface;
554
555 #define VK_ICD_WSI_PLATFORM_MAX 5
556
557 struct anv_instance {
558 VK_LOADER_DATA _loader_data;
559
560 VkAllocationCallbacks alloc;
561
562 uint32_t apiVersion;
563 int physicalDeviceCount;
564 struct anv_physical_device physicalDevice;
565
566 struct anv_wsi_interface * wsi[VK_ICD_WSI_PLATFORM_MAX];
567 };
568
569 VkResult anv_init_wsi(struct anv_instance *instance);
570 void anv_finish_wsi(struct anv_instance *instance);
571
572 struct anv_meta_state {
573 VkAllocationCallbacks alloc;
574
575 /**
576 * Use array element `i` for images with `2^i` samples.
577 */
578 struct {
579 /**
580 * Pipeline N is used to clear color attachment N of the current
581 * subpass.
582 *
583 * HACK: We use one pipeline per color attachment to work around the
584 * compiler's inability to dynamically set the render target index of
585 * the render target write message.
586 */
587 struct anv_pipeline *color_pipelines[MAX_RTS];
588
589 struct anv_pipeline *depth_only_pipeline;
590 struct anv_pipeline *stencil_only_pipeline;
591 struct anv_pipeline *depthstencil_pipeline;
592 } clear[1 + MAX_SAMPLES_LOG2];
593
594 struct {
595 VkRenderPass render_pass;
596
597 /** Pipeline that blits from a 1D image. */
598 VkPipeline pipeline_1d_src;
599
600 /** Pipeline that blits from a 2D image. */
601 VkPipeline pipeline_2d_src;
602
603 /** Pipeline that blits from a 3D image. */
604 VkPipeline pipeline_3d_src;
605
606 VkPipelineLayout pipeline_layout;
607 VkDescriptorSetLayout ds_layout;
608 } blit;
609
610 struct {
611 /** Pipeline [i] resolves an image with 2^(i+1) samples. */
612 VkPipeline pipelines[MAX_SAMPLES_LOG2];
613
614 VkRenderPass pass;
615 VkPipelineLayout pipeline_layout;
616 VkDescriptorSetLayout ds_layout;
617 } resolve;
618 };
619
620 struct anv_queue {
621 VK_LOADER_DATA _loader_data;
622
623 struct anv_device * device;
624
625 struct anv_state_pool * pool;
626 };
627
628 struct anv_pipeline_cache {
629 struct anv_device * device;
630 struct anv_state_stream program_stream;
631 pthread_mutex_t mutex;
632
633 uint32_t total_size;
634 uint32_t table_size;
635 uint32_t kernel_count;
636 uint32_t *table;
637 };
638
639 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
640 struct anv_device *device);
641 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
642 uint32_t anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
643 const unsigned char *sha1, void *prog_data);
644 uint32_t anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
645 const unsigned char *sha1,
646 const void *kernel,
647 size_t kernel_size,
648 const void *prog_data,
649 size_t prog_data_size);
650
651 struct anv_device {
652 VK_LOADER_DATA _loader_data;
653
654 VkAllocationCallbacks alloc;
655
656 struct anv_instance * instance;
657 uint32_t chipset_id;
658 struct brw_device_info info;
659 struct isl_device isl_dev;
660 int context_id;
661 int fd;
662
663 struct anv_bo_pool batch_bo_pool;
664
665 struct anv_block_pool dynamic_state_block_pool;
666 struct anv_state_pool dynamic_state_pool;
667
668 struct anv_block_pool instruction_block_pool;
669 struct anv_pipeline_cache default_pipeline_cache;
670
671 struct anv_block_pool surface_state_block_pool;
672 struct anv_state_pool surface_state_pool;
673
674 struct anv_bo workaround_bo;
675
676 struct anv_meta_state meta_state;
677
678 struct anv_state border_colors;
679
680 struct anv_queue queue;
681
682 struct anv_block_pool scratch_block_pool;
683
684 pthread_mutex_t mutex;
685 };
686
687 VkResult gen7_init_device_state(struct anv_device *device);
688 VkResult gen75_init_device_state(struct anv_device *device);
689 VkResult gen8_init_device_state(struct anv_device *device);
690 VkResult gen9_init_device_state(struct anv_device *device);
691
692 void anv_device_get_cache_uuid(void *uuid);
693
694
695 void* anv_gem_mmap(struct anv_device *device,
696 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
697 void anv_gem_munmap(void *p, uint64_t size);
698 uint32_t anv_gem_create(struct anv_device *device, size_t size);
699 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
700 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
701 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
702 int anv_gem_execbuffer(struct anv_device *device,
703 struct drm_i915_gem_execbuffer2 *execbuf);
704 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
705 uint32_t stride, uint32_t tiling);
706 int anv_gem_create_context(struct anv_device *device);
707 int anv_gem_destroy_context(struct anv_device *device, int context);
708 int anv_gem_get_param(int fd, uint32_t param);
709 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
710 int anv_gem_get_aperture(int fd, uint64_t *size);
711 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
712 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
713 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
714 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
715 uint32_t read_domains, uint32_t write_domain);
716
717 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
718
719 struct anv_reloc_list {
720 size_t num_relocs;
721 size_t array_length;
722 struct drm_i915_gem_relocation_entry * relocs;
723 struct anv_bo ** reloc_bos;
724 };
725
726 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
727 const VkAllocationCallbacks *alloc);
728 void anv_reloc_list_finish(struct anv_reloc_list *list,
729 const VkAllocationCallbacks *alloc);
730
731 uint64_t anv_reloc_list_add(struct anv_reloc_list *list,
732 const VkAllocationCallbacks *alloc,
733 uint32_t offset, struct anv_bo *target_bo,
734 uint32_t delta);
735
736 struct anv_batch_bo {
737 /* Link in the anv_cmd_buffer.owned_batch_bos list */
738 struct list_head link;
739
740 struct anv_bo bo;
741
742 /* Bytes actually consumed in this batch BO */
743 size_t length;
744
745 /* Last seen surface state block pool bo offset */
746 uint32_t last_ss_pool_bo_offset;
747
748 struct anv_reloc_list relocs;
749 };
750
751 struct anv_batch {
752 const VkAllocationCallbacks * alloc;
753
754 void * start;
755 void * end;
756 void * next;
757
758 struct anv_reloc_list * relocs;
759
760 /* This callback is called (with the associated user data) in the event
761 * that the batch runs out of space.
762 */
763 VkResult (*extend_cb)(struct anv_batch *, void *);
764 void * user_data;
765 };
766
767 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
768 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
769 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
770 void *location, struct anv_bo *bo, uint32_t offset);
771 VkResult anv_device_submit_simple_batch(struct anv_device *device,
772 struct anv_batch *batch);
773
774 struct anv_address {
775 struct anv_bo *bo;
776 uint32_t offset;
777 };
778
779 #define __gen_address_type struct anv_address
780 #define __gen_user_data struct anv_batch
781
782 static inline uint64_t
783 __gen_combine_address(struct anv_batch *batch, void *location,
784 const struct anv_address address, uint32_t delta)
785 {
786 if (address.bo == NULL) {
787 return address.offset + delta;
788 } else {
789 assert(batch->start <= location && location < batch->end);
790
791 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
792 }
793 }
794
795 /* Wrapper macros needed to work around preprocessor argument issues. In
796 * particular, arguments don't get pre-evaluated if they are concatenated.
797 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
798 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
799 * We can work around this easily enough with these helpers.
800 */
801 #define __anv_cmd_length(cmd) cmd ## _length
802 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
803 #define __anv_cmd_header(cmd) cmd ## _header
804 #define __anv_cmd_pack(cmd) cmd ## _pack
805
806 #define anv_batch_emit(batch, cmd, ...) do { \
807 void *__dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
808 struct cmd __template = { \
809 __anv_cmd_header(cmd), \
810 __VA_ARGS__ \
811 }; \
812 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
813 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__dst, __anv_cmd_length(cmd) * 4)); \
814 } while (0)
815
816 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
817 void *__dst = anv_batch_emit_dwords(batch, n); \
818 struct cmd __template = { \
819 __anv_cmd_header(cmd), \
820 .DWordLength = n - __anv_cmd_length_bias(cmd), \
821 __VA_ARGS__ \
822 }; \
823 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
824 __dst; \
825 })
826
827 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
828 do { \
829 uint32_t *dw; \
830 \
831 static_assert(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1), "mismatch merge"); \
832 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
833 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
834 dw[i] = (dwords0)[i] | (dwords1)[i]; \
835 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
836 } while (0)
837
838 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
839 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
840 struct anv_state __state = \
841 anv_state_pool_alloc((pool), __size, align); \
842 struct cmd __template = { \
843 __VA_ARGS__ \
844 }; \
845 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
846 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
847 if (!(pool)->block_pool->device->info.has_llc) \
848 anv_state_clflush(__state); \
849 __state; \
850 })
851
852 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
853 .GraphicsDataTypeGFDT = 0, \
854 .LLCCacheabilityControlLLCCC = 0, \
855 .L3CacheabilityControlL3CC = 1, \
856 }
857
858 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
859 .LLCeLLCCacheabilityControlLLCCC = 0, \
860 .L3CacheabilityControlL3CC = 1, \
861 }
862
863 #define GEN8_MOCS { \
864 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
865 .TargetCache = L3DefertoPATforLLCeLLCselection, \
866 .AgeforQUADLRU = 0 \
867 }
868
869 /* Skylake: MOCS is now an index into an array of 62 different caching
870 * configurations programmed by the kernel.
871 */
872
873 #define GEN9_MOCS { \
874 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
875 .IndextoMOCSTables = 2 \
876 }
877
878 #define GEN9_MOCS_PTE { \
879 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
880 .IndextoMOCSTables = 1 \
881 }
882
883 struct anv_device_memory {
884 struct anv_bo bo;
885 uint32_t type_index;
886 VkDeviceSize map_size;
887 void * map;
888 };
889
890 /**
891 * Header for Vertex URB Entry (VUE)
892 */
893 struct anv_vue_header {
894 uint32_t Reserved;
895 uint32_t RTAIndex; /* RenderTargetArrayIndex */
896 uint32_t ViewportIndex;
897 float PointWidth;
898 };
899
900 struct anv_descriptor_set_binding_layout {
901 /* Number of array elements in this binding */
902 uint16_t array_size;
903
904 /* Index into the flattend descriptor set */
905 uint16_t descriptor_index;
906
907 /* Index into the dynamic state array for a dynamic buffer */
908 int16_t dynamic_offset_index;
909
910 /* Index into the descriptor set buffer views */
911 int16_t buffer_index;
912
913 struct {
914 /* Index into the binding table for the associated surface */
915 int16_t surface_index;
916
917 /* Index into the sampler table for the associated sampler */
918 int16_t sampler_index;
919
920 /* Index into the image table for the associated image */
921 int16_t image_index;
922 } stage[MESA_SHADER_STAGES];
923
924 /* Immutable samplers (or NULL if no immutable samplers) */
925 struct anv_sampler **immutable_samplers;
926 };
927
928 struct anv_descriptor_set_layout {
929 /* Number of bindings in this descriptor set */
930 uint16_t binding_count;
931
932 /* Total size of the descriptor set with room for all array entries */
933 uint16_t size;
934
935 /* Shader stages affected by this descriptor set */
936 uint16_t shader_stages;
937
938 /* Number of buffers in this descriptor set */
939 uint16_t buffer_count;
940
941 /* Number of dynamic offsets used by this descriptor set */
942 uint16_t dynamic_offset_count;
943
944 /* Bindings in this descriptor set */
945 struct anv_descriptor_set_binding_layout binding[0];
946 };
947
948 struct anv_descriptor {
949 VkDescriptorType type;
950
951 union {
952 struct {
953 struct anv_image_view *image_view;
954 struct anv_sampler *sampler;
955 };
956
957 struct anv_buffer_view *buffer_view;
958 };
959 };
960
961 struct anv_descriptor_set {
962 const struct anv_descriptor_set_layout *layout;
963 uint32_t buffer_count;
964 struct anv_buffer_view *buffer_views;
965 struct anv_descriptor descriptors[0];
966 };
967
968 VkResult
969 anv_descriptor_set_create(struct anv_device *device,
970 const struct anv_descriptor_set_layout *layout,
971 struct anv_descriptor_set **out_set);
972
973 void
974 anv_descriptor_set_destroy(struct anv_device *device,
975 struct anv_descriptor_set *set);
976
977 struct anv_pipeline_binding {
978 /* The descriptor set this surface corresponds to */
979 uint16_t set;
980
981 /* Offset into the descriptor set */
982 uint16_t offset;
983 };
984
985 struct anv_pipeline_layout {
986 struct {
987 struct anv_descriptor_set_layout *layout;
988 uint32_t dynamic_offset_start;
989 } set[MAX_SETS];
990
991 uint32_t num_sets;
992
993 struct {
994 bool has_dynamic_offsets;
995 } stage[MESA_SHADER_STAGES];
996 };
997
998 struct anv_buffer {
999 struct anv_device * device;
1000 VkDeviceSize size;
1001
1002 VkBufferUsageFlags usage;
1003
1004 /* Set when bound */
1005 struct anv_bo * bo;
1006 VkDeviceSize offset;
1007 };
1008
1009 enum anv_cmd_dirty_bits {
1010 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1011 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1012 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1013 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1014 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1015 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1016 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1017 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1018 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1019 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1020 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1021 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1022 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1023 };
1024 typedef uint32_t anv_cmd_dirty_mask_t;
1025
1026 struct anv_vertex_binding {
1027 struct anv_buffer * buffer;
1028 VkDeviceSize offset;
1029 };
1030
1031 struct anv_push_constants {
1032 /* Current allocated size of this push constants data structure.
1033 * Because a decent chunk of it may not be used (images on SKL, for
1034 * instance), we won't actually allocate the entire structure up-front.
1035 */
1036 uint32_t size;
1037
1038 /* Push constant data provided by the client through vkPushConstants */
1039 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1040
1041 /* Our hardware only provides zero-based vertex and instance id so, in
1042 * order to satisfy the vulkan requirements, we may have to push one or
1043 * both of these into the shader.
1044 */
1045 uint32_t base_vertex;
1046 uint32_t base_instance;
1047
1048 /* Offsets and ranges for dynamically bound buffers */
1049 struct {
1050 uint32_t offset;
1051 uint32_t range;
1052 } dynamic[MAX_DYNAMIC_BUFFERS];
1053
1054 /* Image data for image_load_store on pre-SKL */
1055 struct brw_image_param images[MAX_IMAGES];
1056 };
1057
1058 struct anv_dynamic_state {
1059 struct {
1060 uint32_t count;
1061 VkViewport viewports[MAX_VIEWPORTS];
1062 } viewport;
1063
1064 struct {
1065 uint32_t count;
1066 VkRect2D scissors[MAX_SCISSORS];
1067 } scissor;
1068
1069 float line_width;
1070
1071 struct {
1072 float bias;
1073 float clamp;
1074 float slope;
1075 } depth_bias;
1076
1077 float blend_constants[4];
1078
1079 struct {
1080 float min;
1081 float max;
1082 } depth_bounds;
1083
1084 struct {
1085 uint32_t front;
1086 uint32_t back;
1087 } stencil_compare_mask;
1088
1089 struct {
1090 uint32_t front;
1091 uint32_t back;
1092 } stencil_write_mask;
1093
1094 struct {
1095 uint32_t front;
1096 uint32_t back;
1097 } stencil_reference;
1098 };
1099
1100 extern const struct anv_dynamic_state default_dynamic_state;
1101
1102 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1103 const struct anv_dynamic_state *src,
1104 uint32_t copy_mask);
1105
1106 /**
1107 * Attachment state when recording a renderpass instance.
1108 *
1109 * The clear value is valid only if there exists a pending clear.
1110 */
1111 struct anv_attachment_state {
1112 VkImageAspectFlags pending_clear_aspects;
1113 VkClearValue clear_value;
1114 };
1115
1116 /** State required while building cmd buffer */
1117 struct anv_cmd_state {
1118 /* PIPELINE_SELECT.PipelineSelection */
1119 uint32_t current_pipeline;
1120 uint32_t current_l3_config;
1121 uint32_t vb_dirty;
1122 anv_cmd_dirty_mask_t dirty;
1123 anv_cmd_dirty_mask_t compute_dirty;
1124 uint32_t num_workgroups_offset;
1125 struct anv_bo *num_workgroups_bo;
1126 VkShaderStageFlags descriptors_dirty;
1127 VkShaderStageFlags push_constants_dirty;
1128 uint32_t scratch_size;
1129 struct anv_pipeline * pipeline;
1130 struct anv_pipeline * compute_pipeline;
1131 struct anv_framebuffer * framebuffer;
1132 struct anv_render_pass * pass;
1133 struct anv_subpass * subpass;
1134 uint32_t restart_index;
1135 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1136 struct anv_descriptor_set * descriptors[MAX_SETS];
1137 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1138 struct anv_state binding_tables[MESA_SHADER_STAGES];
1139 struct anv_state samplers[MESA_SHADER_STAGES];
1140 struct anv_dynamic_state dynamic;
1141 bool need_query_wa;
1142
1143 /**
1144 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1145 * valid only when recording a render pass instance.
1146 */
1147 struct anv_attachment_state * attachments;
1148
1149 struct {
1150 struct anv_buffer * index_buffer;
1151 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1152 uint32_t index_offset;
1153 } gen7;
1154 };
1155
1156 struct anv_cmd_pool {
1157 VkAllocationCallbacks alloc;
1158 struct list_head cmd_buffers;
1159 };
1160
1161 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1162
1163 enum anv_cmd_buffer_exec_mode {
1164 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1165 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1166 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1167 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1168 };
1169
1170 struct anv_cmd_buffer {
1171 VK_LOADER_DATA _loader_data;
1172
1173 struct anv_device * device;
1174
1175 struct anv_cmd_pool * pool;
1176 struct list_head pool_link;
1177
1178 struct anv_batch batch;
1179
1180 /* Fields required for the actual chain of anv_batch_bo's.
1181 *
1182 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1183 */
1184 struct list_head batch_bos;
1185 enum anv_cmd_buffer_exec_mode exec_mode;
1186
1187 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1188 * referenced by this command buffer
1189 *
1190 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1191 */
1192 struct anv_vector seen_bbos;
1193
1194 /* A vector of int32_t's for every block of binding tables.
1195 *
1196 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1197 */
1198 struct anv_vector bt_blocks;
1199 uint32_t bt_next;
1200 struct anv_reloc_list surface_relocs;
1201
1202 /* Information needed for execbuf
1203 *
1204 * These fields are generated by anv_cmd_buffer_prepare_execbuf().
1205 */
1206 struct {
1207 struct drm_i915_gem_execbuffer2 execbuf;
1208
1209 struct drm_i915_gem_exec_object2 * objects;
1210 uint32_t bo_count;
1211 struct anv_bo ** bos;
1212
1213 /* Allocated length of the 'objects' and 'bos' arrays */
1214 uint32_t array_length;
1215
1216 bool need_reloc;
1217 } execbuf2;
1218
1219 /* Serial for tracking buffer completion */
1220 uint32_t serial;
1221
1222 /* Stream objects for storing temporary data */
1223 struct anv_state_stream surface_state_stream;
1224 struct anv_state_stream dynamic_state_stream;
1225
1226 VkCommandBufferUsageFlags usage_flags;
1227 VkCommandBufferLevel level;
1228
1229 struct anv_cmd_state state;
1230 };
1231
1232 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1233 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1234 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1235 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1236 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1237 struct anv_cmd_buffer *secondary);
1238 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1239
1240 VkResult anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
1241 unsigned stage, struct anv_state *bt_state);
1242 VkResult anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
1243 unsigned stage, struct anv_state *state);
1244 uint32_t gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer);
1245 void gen7_cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
1246 uint32_t stages);
1247
1248 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1249 const void *data, uint32_t size, uint32_t alignment);
1250 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1251 uint32_t *a, uint32_t *b,
1252 uint32_t dwords, uint32_t alignment);
1253
1254 struct anv_address
1255 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1256 struct anv_state
1257 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1258 uint32_t entries, uint32_t *state_offset);
1259 struct anv_state
1260 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1261 struct anv_state
1262 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1263 uint32_t size, uint32_t alignment);
1264
1265 VkResult
1266 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1267
1268 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1269 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1270
1271 void gen7_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1272 void gen75_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1273 void gen8_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1274 void gen9_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1275
1276 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1277
1278 void anv_cmd_state_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1279 const VkRenderPassBeginInfo *info);
1280
1281 void gen7_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
1282 struct anv_subpass *subpass);
1283 void gen75_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
1284 struct anv_subpass *subpass);
1285 void gen8_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
1286 struct anv_subpass *subpass);
1287 void gen9_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
1288 struct anv_subpass *subpass);
1289 void anv_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
1290 struct anv_subpass *subpass);
1291
1292 void gen7_flush_pipeline_select_3d(struct anv_cmd_buffer *cmd_buffer);
1293 void gen75_flush_pipeline_select_3d(struct anv_cmd_buffer *cmd_buffer);
1294 void gen8_flush_pipeline_select_3d(struct anv_cmd_buffer *cmd_buffer);
1295 void gen9_flush_pipeline_select_3d(struct anv_cmd_buffer *cmd_buffer);
1296
1297 void gen7_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer);
1298 void gen75_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer);
1299 void gen8_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer);
1300 void gen9_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer);
1301
1302 void gen7_cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer);
1303 void gen75_cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer);
1304 void gen8_cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer);
1305 void gen9_cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer);
1306
1307 struct anv_state
1308 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1309 gl_shader_stage stage);
1310 struct anv_state
1311 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1312
1313 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1314 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1315
1316 const struct anv_image_view *
1317 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1318
1319 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1320
1321 struct anv_fence {
1322 struct anv_bo bo;
1323 struct drm_i915_gem_execbuffer2 execbuf;
1324 struct drm_i915_gem_exec_object2 exec2_objects[1];
1325 bool ready;
1326 };
1327
1328 struct anv_event {
1329 uint64_t semaphore;
1330 struct anv_state state;
1331 };
1332
1333 struct nir_shader;
1334
1335 struct anv_shader_module {
1336 struct nir_shader * nir;
1337
1338 unsigned char sha1[20];
1339 uint32_t size;
1340 char data[0];
1341 };
1342
1343 void anv_hash_shader(unsigned char *hash, const void *key, size_t key_size,
1344 struct anv_shader_module *module,
1345 const char *entrypoint,
1346 const VkSpecializationInfo *spec_info);
1347
1348 static inline gl_shader_stage
1349 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1350 {
1351 assert(__builtin_popcount(vk_stage) == 1);
1352 return ffs(vk_stage) - 1;
1353 }
1354
1355 static inline VkShaderStageFlagBits
1356 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1357 {
1358 return (1 << mesa_stage);
1359 }
1360
1361 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1362
1363 #define anv_foreach_stage(stage, stage_bits) \
1364 for (gl_shader_stage stage, \
1365 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1366 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1367 __tmp &= ~(1 << (stage)))
1368
1369 struct anv_pipeline_bind_map {
1370 uint32_t surface_count;
1371 uint32_t sampler_count;
1372 uint32_t image_count;
1373
1374 struct anv_pipeline_binding * surface_to_descriptor;
1375 struct anv_pipeline_binding * sampler_to_descriptor;
1376 };
1377
1378 struct anv_pipeline {
1379 struct anv_device * device;
1380 struct anv_batch batch;
1381 uint32_t batch_data[512];
1382 struct anv_reloc_list batch_relocs;
1383 uint32_t dynamic_state_mask;
1384 struct anv_dynamic_state dynamic_state;
1385
1386 struct anv_pipeline_layout * layout;
1387 struct anv_pipeline_bind_map bindings[MESA_SHADER_STAGES];
1388
1389 bool use_repclear;
1390
1391 struct brw_vs_prog_data vs_prog_data;
1392 struct brw_wm_prog_data wm_prog_data;
1393 struct brw_gs_prog_data gs_prog_data;
1394 struct brw_cs_prog_data cs_prog_data;
1395 bool writes_point_size;
1396 struct brw_stage_prog_data * prog_data[MESA_SHADER_STAGES];
1397 uint32_t scratch_start[MESA_SHADER_STAGES];
1398 uint32_t total_scratch;
1399 struct {
1400 uint32_t vs_start;
1401 uint32_t vs_size;
1402 uint32_t nr_vs_entries;
1403 uint32_t gs_start;
1404 uint32_t gs_size;
1405 uint32_t nr_gs_entries;
1406 } urb;
1407
1408 VkShaderStageFlags active_stages;
1409 struct anv_state blend_state;
1410 uint32_t vs_simd8;
1411 uint32_t vs_vec4;
1412 uint32_t ps_simd8;
1413 uint32_t ps_simd16;
1414 uint32_t ps_ksp0;
1415 uint32_t ps_ksp2;
1416 uint32_t ps_grf_start0;
1417 uint32_t ps_grf_start2;
1418 uint32_t gs_kernel;
1419 uint32_t cs_simd;
1420
1421 uint32_t vb_used;
1422 uint32_t binding_stride[MAX_VBS];
1423 bool instancing_enable[MAX_VBS];
1424 bool primitive_restart;
1425 uint32_t topology;
1426
1427 uint32_t cs_thread_width_max;
1428 uint32_t cs_right_mask;
1429
1430 struct {
1431 uint32_t sf[7];
1432 uint32_t depth_stencil_state[3];
1433 } gen7;
1434
1435 struct {
1436 uint32_t sf[4];
1437 uint32_t raster[5];
1438 uint32_t wm_depth_stencil[3];
1439 } gen8;
1440
1441 struct {
1442 uint32_t wm_depth_stencil[4];
1443 } gen9;
1444 };
1445
1446 struct anv_graphics_pipeline_create_info {
1447 /**
1448 * If non-negative, overrides the color attachment count of the pipeline's
1449 * subpass.
1450 */
1451 int8_t color_attachment_count;
1452
1453 bool use_repclear;
1454 bool disable_viewport;
1455 bool disable_scissor;
1456 bool disable_vs;
1457 bool use_rectlist;
1458 };
1459
1460 VkResult
1461 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
1462 struct anv_pipeline_cache *cache,
1463 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1464 const struct anv_graphics_pipeline_create_info *extra,
1465 const VkAllocationCallbacks *alloc);
1466
1467 VkResult
1468 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1469 struct anv_pipeline_cache *cache,
1470 const VkComputePipelineCreateInfo *info,
1471 struct anv_shader_module *module,
1472 const char *entrypoint,
1473 const VkSpecializationInfo *spec_info);
1474
1475 VkResult
1476 anv_graphics_pipeline_create(VkDevice device,
1477 VkPipelineCache cache,
1478 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1479 const struct anv_graphics_pipeline_create_info *extra,
1480 const VkAllocationCallbacks *alloc,
1481 VkPipeline *pPipeline);
1482
1483 VkResult
1484 gen7_graphics_pipeline_create(VkDevice _device,
1485 struct anv_pipeline_cache *cache,
1486 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1487 const struct anv_graphics_pipeline_create_info *extra,
1488 const VkAllocationCallbacks *alloc,
1489 VkPipeline *pPipeline);
1490
1491 VkResult
1492 gen75_graphics_pipeline_create(VkDevice _device,
1493 struct anv_pipeline_cache *cache,
1494 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1495 const struct anv_graphics_pipeline_create_info *extra,
1496 const VkAllocationCallbacks *alloc,
1497 VkPipeline *pPipeline);
1498
1499 VkResult
1500 gen8_graphics_pipeline_create(VkDevice _device,
1501 struct anv_pipeline_cache *cache,
1502 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1503 const struct anv_graphics_pipeline_create_info *extra,
1504 const VkAllocationCallbacks *alloc,
1505 VkPipeline *pPipeline);
1506 VkResult
1507 gen9_graphics_pipeline_create(VkDevice _device,
1508 struct anv_pipeline_cache *cache,
1509 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1510 const struct anv_graphics_pipeline_create_info *extra,
1511 const VkAllocationCallbacks *alloc,
1512 VkPipeline *pPipeline);
1513 VkResult
1514 gen7_compute_pipeline_create(VkDevice _device,
1515 struct anv_pipeline_cache *cache,
1516 const VkComputePipelineCreateInfo *pCreateInfo,
1517 const VkAllocationCallbacks *alloc,
1518 VkPipeline *pPipeline);
1519 VkResult
1520 gen75_compute_pipeline_create(VkDevice _device,
1521 struct anv_pipeline_cache *cache,
1522 const VkComputePipelineCreateInfo *pCreateInfo,
1523 const VkAllocationCallbacks *alloc,
1524 VkPipeline *pPipeline);
1525
1526 VkResult
1527 gen8_compute_pipeline_create(VkDevice _device,
1528 struct anv_pipeline_cache *cache,
1529 const VkComputePipelineCreateInfo *pCreateInfo,
1530 const VkAllocationCallbacks *alloc,
1531 VkPipeline *pPipeline);
1532 VkResult
1533 gen9_compute_pipeline_create(VkDevice _device,
1534 struct anv_pipeline_cache *cache,
1535 const VkComputePipelineCreateInfo *pCreateInfo,
1536 const VkAllocationCallbacks *alloc,
1537 VkPipeline *pPipeline);
1538
1539 struct anv_format_swizzle {
1540 unsigned r:2;
1541 unsigned g:2;
1542 unsigned b:2;
1543 unsigned a:2;
1544 };
1545
1546 struct anv_format {
1547 const VkFormat vk_format;
1548 const char *name;
1549 enum isl_format isl_format; /**< RENDER_SURFACE_STATE.SurfaceFormat */
1550 const struct isl_format_layout *isl_layout;
1551 struct anv_format_swizzle swizzle;
1552 bool has_depth;
1553 bool has_stencil;
1554 };
1555
1556 const struct anv_format *
1557 anv_format_for_vk_format(VkFormat format);
1558
1559 enum isl_format
1560 anv_get_isl_format(VkFormat format, VkImageAspectFlags aspect,
1561 VkImageTiling tiling, struct anv_format_swizzle *swizzle);
1562
1563 static inline bool
1564 anv_format_is_color(const struct anv_format *format)
1565 {
1566 return !format->has_depth && !format->has_stencil;
1567 }
1568
1569 static inline bool
1570 anv_format_is_depth_or_stencil(const struct anv_format *format)
1571 {
1572 return format->has_depth || format->has_stencil;
1573 }
1574
1575 /**
1576 * Subsurface of an anv_image.
1577 */
1578 struct anv_surface {
1579 struct isl_surf isl;
1580
1581 /**
1582 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1583 */
1584 uint32_t offset;
1585 };
1586
1587 struct anv_image {
1588 VkImageType type;
1589 /* The original VkFormat provided by the client. This may not match any
1590 * of the actual surface formats.
1591 */
1592 VkFormat vk_format;
1593 const struct anv_format *format;
1594 VkExtent3D extent;
1595 uint32_t levels;
1596 uint32_t array_size;
1597 uint32_t samples; /**< VkImageCreateInfo::samples */
1598 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1599 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1600
1601 VkDeviceSize size;
1602 uint32_t alignment;
1603
1604 /* Set when bound */
1605 struct anv_bo *bo;
1606 VkDeviceSize offset;
1607
1608 /**
1609 * Image subsurfaces
1610 *
1611 * For each foo, anv_image::foo_surface is valid if and only if
1612 * anv_image::format has a foo aspect.
1613 *
1614 * The hardware requires that the depth buffer and stencil buffer be
1615 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1616 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1617 * allocate the depth and stencil buffers as separate surfaces in the same
1618 * bo.
1619 */
1620 union {
1621 struct anv_surface color_surface;
1622
1623 struct {
1624 struct anv_surface depth_surface;
1625 struct anv_surface stencil_surface;
1626 };
1627 };
1628 };
1629
1630 struct anv_image_view {
1631 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
1632 struct anv_bo *bo;
1633 uint32_t offset; /**< Offset into bo. */
1634
1635 VkImageAspectFlags aspect_mask;
1636 VkFormat vk_format;
1637 VkComponentMapping swizzle;
1638 enum isl_format format;
1639 uint32_t base_layer;
1640 uint32_t base_mip;
1641 VkExtent3D level_0_extent; /**< Extent of ::image's level 0 adjusted for ::vk_format. */
1642 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1643
1644 /** RENDER_SURFACE_STATE when using image as a color render target. */
1645 struct anv_state color_rt_surface_state;
1646
1647 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1648 struct anv_state sampler_surface_state;
1649
1650 /** RENDER_SURFACE_STATE when using image as a storage image. */
1651 struct anv_state storage_surface_state;
1652 };
1653
1654 struct anv_image_create_info {
1655 const VkImageCreateInfo *vk_info;
1656 isl_tiling_flags_t isl_tiling_flags;
1657 uint32_t stride;
1658 };
1659
1660 VkResult anv_image_create(VkDevice _device,
1661 const struct anv_image_create_info *info,
1662 const VkAllocationCallbacks* alloc,
1663 VkImage *pImage);
1664
1665 struct anv_surface *
1666 anv_image_get_surface_for_aspect_mask(struct anv_image *image,
1667 VkImageAspectFlags aspect_mask);
1668
1669 void anv_image_view_init(struct anv_image_view *view,
1670 struct anv_device *device,
1671 const VkImageViewCreateInfo* pCreateInfo,
1672 struct anv_cmd_buffer *cmd_buffer,
1673 uint32_t offset);
1674
1675 void
1676 anv_fill_image_surface_state(struct anv_device *device, struct anv_state state,
1677 struct anv_image_view *iview,
1678 const VkImageViewCreateInfo *pCreateInfo,
1679 VkImageUsageFlagBits usage);
1680 void
1681 gen7_fill_image_surface_state(struct anv_device *device, void *state_map,
1682 struct anv_image_view *iview,
1683 const VkImageViewCreateInfo *pCreateInfo,
1684 VkImageUsageFlagBits usage);
1685 void
1686 gen75_fill_image_surface_state(struct anv_device *device, void *state_map,
1687 struct anv_image_view *iview,
1688 const VkImageViewCreateInfo *pCreateInfo,
1689 VkImageUsageFlagBits usage);
1690 void
1691 gen8_fill_image_surface_state(struct anv_device *device, void *state_map,
1692 struct anv_image_view *iview,
1693 const VkImageViewCreateInfo *pCreateInfo,
1694 VkImageUsageFlagBits usage);
1695 void
1696 gen9_fill_image_surface_state(struct anv_device *device, void *state_map,
1697 struct anv_image_view *iview,
1698 const VkImageViewCreateInfo *pCreateInfo,
1699 VkImageUsageFlagBits usage);
1700
1701 struct anv_buffer_view {
1702 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1703 struct anv_bo *bo;
1704 uint32_t offset; /**< Offset into bo. */
1705 uint64_t range; /**< VkBufferViewCreateInfo::range */
1706
1707 struct anv_state surface_state;
1708 struct anv_state storage_surface_state;
1709 };
1710
1711 const struct anv_format *
1712 anv_format_for_descriptor_type(VkDescriptorType type);
1713
1714 void anv_fill_buffer_surface_state(struct anv_device *device,
1715 struct anv_state state,
1716 enum isl_format format,
1717 uint32_t offset, uint32_t range,
1718 uint32_t stride);
1719
1720 void gen7_fill_buffer_surface_state(void *state, enum isl_format format,
1721 uint32_t offset, uint32_t range,
1722 uint32_t stride);
1723 void gen75_fill_buffer_surface_state(void *state, enum isl_format format,
1724 uint32_t offset, uint32_t range,
1725 uint32_t stride);
1726 void gen8_fill_buffer_surface_state(void *state, enum isl_format format,
1727 uint32_t offset, uint32_t range,
1728 uint32_t stride);
1729 void gen9_fill_buffer_surface_state(void *state, enum isl_format format,
1730 uint32_t offset, uint32_t range,
1731 uint32_t stride);
1732
1733 void anv_image_view_fill_image_param(struct anv_device *device,
1734 struct anv_image_view *view,
1735 struct brw_image_param *param);
1736 void anv_buffer_view_fill_image_param(struct anv_device *device,
1737 struct anv_buffer_view *view,
1738 struct brw_image_param *param);
1739
1740 struct anv_sampler {
1741 uint32_t state[4];
1742 };
1743
1744 struct anv_framebuffer {
1745 uint32_t width;
1746 uint32_t height;
1747 uint32_t layers;
1748
1749 uint32_t attachment_count;
1750 struct anv_image_view * attachments[0];
1751 };
1752
1753 struct anv_subpass {
1754 uint32_t input_count;
1755 uint32_t * input_attachments;
1756 uint32_t color_count;
1757 uint32_t * color_attachments;
1758 uint32_t * resolve_attachments;
1759 uint32_t depth_stencil_attachment;
1760
1761 /** Subpass has at least one resolve attachment */
1762 bool has_resolve;
1763 };
1764
1765 struct anv_render_pass_attachment {
1766 const struct anv_format *format;
1767 uint32_t samples;
1768 VkAttachmentLoadOp load_op;
1769 VkAttachmentLoadOp stencil_load_op;
1770 };
1771
1772 struct anv_render_pass {
1773 uint32_t attachment_count;
1774 uint32_t subpass_count;
1775 uint32_t * subpass_attachments;
1776 struct anv_render_pass_attachment * attachments;
1777 struct anv_subpass subpasses[0];
1778 };
1779
1780 extern struct anv_render_pass anv_meta_dummy_renderpass;
1781
1782 struct anv_query_pool_slot {
1783 uint64_t begin;
1784 uint64_t end;
1785 uint64_t available;
1786 };
1787
1788 struct anv_query_pool {
1789 VkQueryType type;
1790 uint32_t slots;
1791 struct anv_bo bo;
1792 };
1793
1794 VkResult anv_device_init_meta(struct anv_device *device);
1795 void anv_device_finish_meta(struct anv_device *device);
1796
1797 void *anv_lookup_entrypoint(const char *name);
1798
1799 void anv_dump_image_to_ppm(struct anv_device *device,
1800 struct anv_image *image, unsigned miplevel,
1801 unsigned array_layer, const char *filename);
1802
1803 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1804 \
1805 static inline struct __anv_type * \
1806 __anv_type ## _from_handle(__VkType _handle) \
1807 { \
1808 return (struct __anv_type *) _handle; \
1809 } \
1810 \
1811 static inline __VkType \
1812 __anv_type ## _to_handle(struct __anv_type *_obj) \
1813 { \
1814 return (__VkType) _obj; \
1815 }
1816
1817 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1818 \
1819 static inline struct __anv_type * \
1820 __anv_type ## _from_handle(__VkType _handle) \
1821 { \
1822 return (struct __anv_type *)(uintptr_t) _handle; \
1823 } \
1824 \
1825 static inline __VkType \
1826 __anv_type ## _to_handle(struct __anv_type *_obj) \
1827 { \
1828 return (__VkType)(uintptr_t) _obj; \
1829 }
1830
1831 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1832 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1833
1834 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
1835 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
1836 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
1837 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
1838 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
1839
1840 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
1841 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
1842 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
1843 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
1844 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
1845 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
1846 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
1847 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
1848 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
1849 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
1850 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
1851 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
1852 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
1853 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
1854 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
1855 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
1856 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
1857 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
1858
1859 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1860 \
1861 static inline const __VkType * \
1862 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1863 { \
1864 return (const __VkType *) __anv_obj; \
1865 }
1866
1867 #define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1868 const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name)
1869
1870 ANV_DEFINE_STRUCT_CASTS(anv_common, VkMemoryBarrier)
1871 ANV_DEFINE_STRUCT_CASTS(anv_common, VkBufferMemoryBarrier)
1872 ANV_DEFINE_STRUCT_CASTS(anv_common, VkImageMemoryBarrier)
1873
1874 #ifdef __cplusplus
1875 }
1876 #endif