2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/macros.h"
53 #include "util/hash_table.h"
54 #include "util/list.h"
56 #include "util/sparse_array.h"
57 #include "util/u_atomic.h"
58 #include "util/u_vector.h"
59 #include "util/u_math.h"
61 #include "util/xmlconfig.h"
63 #include "vk_debug_report.h"
65 /* Pre-declarations needed for WSI entrypoints */
68 typedef struct xcb_connection_t xcb_connection_t
;
69 typedef uint32_t xcb_visualid_t
;
70 typedef uint32_t xcb_window_t
;
73 struct anv_buffer_view
;
74 struct anv_image_view
;
77 struct gen_aux_map_context
;
79 struct gen_perf_config
;
81 #include <vulkan/vulkan.h>
82 #include <vulkan/vulkan_intel.h>
83 #include <vulkan/vk_icd.h>
85 #include "anv_android.h"
86 #include "anv_entrypoints.h"
87 #include "anv_extensions.h"
90 #include "dev/gen_debug.h"
91 #include "common/intel_log.h"
92 #include "wsi_common.h"
94 /* anv Virtual Memory Layout
95 * =========================
97 * When the anv driver is determining the virtual graphics addresses of memory
98 * objects itself using the softpin mechanism, the following memory ranges
101 * Three special considerations to notice:
103 * (1) the dynamic state pool is located within the same 4 GiB as the low
104 * heap. This is to work around a VF cache issue described in a comment in
105 * anv_physical_device_init_heaps.
107 * (2) the binding table pool is located at lower addresses than the surface
108 * state pool, within a 4 GiB range. This allows surface state base addresses
109 * to cover both binding tables (16 bit offsets) and surface states (32 bit
112 * (3) the last 4 GiB of the address space is withheld from the high
113 * heap. Various hardware units will read past the end of an object for
114 * various reasons. This healthy margin prevents reads from wrapping around
117 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
118 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
119 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
120 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
121 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
122 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
123 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
124 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
125 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
126 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
127 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
129 #define LOW_HEAP_SIZE \
130 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
131 #define DYNAMIC_STATE_POOL_SIZE \
132 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
133 #define BINDING_TABLE_POOL_SIZE \
134 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
135 #define SURFACE_STATE_POOL_SIZE \
136 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
137 #define INSTRUCTION_STATE_POOL_SIZE \
138 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
140 /* Allowing different clear colors requires us to perform a depth resolve at
141 * the end of certain render passes. This is because while slow clears store
142 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
143 * See the PRMs for examples describing when additional resolves would be
144 * necessary. To enable fast clears without requiring extra resolves, we set
145 * the clear value to a globally-defined one. We could allow different values
146 * if the user doesn't expect coherent data during or after a render passes
147 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
148 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
149 * 1.0f seems to be the only value used. The only application that doesn't set
150 * this value does so through the usage of an seemingly uninitialized clear
153 #define ANV_HZ_FC_VAL 1.0f
156 #define MAX_XFB_BUFFERS 4
157 #define MAX_XFB_STREAMS 4
160 #define MAX_VIEWPORTS 16
161 #define MAX_SCISSORS 16
162 #define MAX_PUSH_CONSTANTS_SIZE 128
163 #define MAX_DYNAMIC_BUFFERS 16
164 #define MAX_IMAGES 64
165 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
166 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
167 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
169 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
171 * "The surface state model is used when a Binding Table Index (specified
172 * in the message descriptor) of less than 240 is specified. In this model,
173 * the Binding Table Index is used to index into the binding table, and the
174 * binding table entry contains a pointer to the SURFACE_STATE."
176 * Binding table values above 240 are used for various things in the hardware
177 * such as stateless, stateless with incoherent cache, SLM, and bindless.
179 #define MAX_BINDING_TABLE_SIZE 240
181 /* The kernel relocation API has a limitation of a 32-bit delta value
182 * applied to the address before it is written which, in spite of it being
183 * unsigned, is treated as signed . Because of the way that this maps to
184 * the Vulkan API, we cannot handle an offset into a buffer that does not
185 * fit into a signed 32 bits. The only mechanism we have for dealing with
186 * this at the moment is to limit all VkDeviceMemory objects to a maximum
187 * of 2GB each. The Vulkan spec allows us to do this:
189 * "Some platforms may have a limit on the maximum size of a single
190 * allocation. For example, certain systems may fail to create
191 * allocations with a size greater than or equal to 4GB. Such a limit is
192 * implementation-dependent, and if such a failure occurs then the error
193 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
195 * We don't use vk_error here because it's not an error so much as an
196 * indication to the application that the allocation is too large.
198 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
200 #define ANV_SVGS_VB_INDEX MAX_VBS
201 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
203 /* We reserve this MI ALU register for the purpose of handling predication.
204 * Other code which uses the MI ALU should leave it alone.
206 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
208 /* For gen12 we set the streamout buffers using 4 separate commands
209 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
210 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
211 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
212 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
213 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
214 * 3DSTATE_SO_BUFFER_INDEX_0.
216 #define SO_BUFFER_INDEX_0_CMD 0x60
217 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
219 static inline uint32_t
220 align_down_npot_u32(uint32_t v
, uint32_t a
)
225 static inline uint32_t
226 align_u32(uint32_t v
, uint32_t a
)
228 assert(a
!= 0 && a
== (a
& -a
));
229 return (v
+ a
- 1) & ~(a
- 1);
232 static inline uint64_t
233 align_u64(uint64_t v
, uint64_t a
)
235 assert(a
!= 0 && a
== (a
& -a
));
236 return (v
+ a
- 1) & ~(a
- 1);
239 static inline int32_t
240 align_i32(int32_t v
, int32_t a
)
242 assert(a
!= 0 && a
== (a
& -a
));
243 return (v
+ a
- 1) & ~(a
- 1);
246 /** Alignment must be a power of 2. */
248 anv_is_aligned(uintmax_t n
, uintmax_t a
)
250 assert(a
== (a
& -a
));
251 return (n
& (a
- 1)) == 0;
254 static inline uint32_t
255 anv_minify(uint32_t n
, uint32_t levels
)
257 if (unlikely(n
== 0))
260 return MAX2(n
>> levels
, 1);
264 anv_clamp_f(float f
, float min
, float max
)
277 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
279 if (*inout_mask
& clear_mask
) {
280 *inout_mask
&= ~clear_mask
;
287 static inline union isl_color_value
288 vk_to_isl_color(VkClearColorValue color
)
290 return (union isl_color_value
) {
300 #define for_each_bit(b, dword) \
301 for (uint32_t __dword = (dword); \
302 (b) = __builtin_ffs(__dword) - 1, __dword; \
303 __dword &= ~(1 << (b)))
305 #define typed_memcpy(dest, src, count) ({ \
306 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
307 memcpy((dest), (src), (count) * sizeof(*(src))); \
310 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
311 * to be added here in order to utilize mapping in debug/error/perf macros.
313 #define REPORT_OBJECT_TYPE(o) \
314 __builtin_choose_expr ( \
315 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
316 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
317 __builtin_choose_expr ( \
318 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
319 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
320 __builtin_choose_expr ( \
321 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
322 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
323 __builtin_choose_expr ( \
324 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
325 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
326 __builtin_choose_expr ( \
327 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
328 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
329 __builtin_choose_expr ( \
330 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
331 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
332 __builtin_choose_expr ( \
333 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
334 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
335 __builtin_choose_expr ( \
336 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
337 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
338 __builtin_choose_expr ( \
339 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
340 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), void*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
407 /* The void expression results in a compile-time error \
408 when assigning the result to something. */ \
409 (void)0)))))))))))))))))))))))))))))))
411 /* Whenever we generate an error, pass it through this function. Useful for
412 * debugging, where we can break on it. Only call at error site, not when
413 * propagating errors. Might be useful to plug in a stack trace here.
416 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
417 VkDebugReportObjectTypeEXT type
, VkResult error
,
418 const char *file
, int line
, const char *format
,
421 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
422 VkDebugReportObjectTypeEXT type
, VkResult error
,
423 const char *file
, int line
, const char *format
, ...)
424 anv_printflike(7, 8);
427 #define vk_error(error) __vk_errorf(NULL, NULL,\
428 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
429 error, __FILE__, __LINE__, NULL)
430 #define vk_errorv(instance, obj, error, format, args)\
431 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
432 __FILE__, __LINE__, format, args)
433 #define vk_errorf(instance, obj, error, format, ...)\
434 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
435 __FILE__, __LINE__, format, ## __VA_ARGS__)
437 #define vk_error(error) error
438 #define vk_errorf(instance, obj, error, format, ...) error
442 * Warn on ignored extension structs.
444 * The Vulkan spec requires us to ignore unsupported or unknown structs in
445 * a pNext chain. In debug mode, emitting warnings for ignored structs may
446 * help us discover structs that we should not have ignored.
449 * From the Vulkan 1.0.38 spec:
451 * Any component of the implementation (the loader, any enabled layers,
452 * and drivers) must skip over, without processing (other than reading the
453 * sType and pNext members) any chained structures with sType values not
454 * defined by extensions supported by that component.
456 #define anv_debug_ignored_stype(sType) \
457 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
459 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
460 VkDebugReportObjectTypeEXT type
, const char *file
,
461 int line
, const char *format
, ...)
462 anv_printflike(6, 7);
463 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
464 void anv_loge_v(const char *format
, va_list va
);
467 * Print a FINISHME message, including its source location.
469 #define anv_finishme(format, ...) \
471 static bool reported = false; \
473 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
480 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
482 #define anv_perf_warn(instance, obj, format, ...) \
484 static bool reported = false; \
485 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
486 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
487 format, ##__VA_ARGS__); \
492 /* A non-fatal assert. Useful for debugging. */
494 #define anv_assert(x) ({ \
495 if (unlikely(!(x))) \
496 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
499 #define anv_assert(x)
502 /* A multi-pointer allocator
504 * When copying data structures from the user (such as a render pass), it's
505 * common to need to allocate data for a bunch of different things. Instead
506 * of doing several allocations and having to handle all of the error checking
507 * that entails, it can be easier to do a single allocation. This struct
508 * helps facilitate that. The intended usage looks like this:
511 * anv_multialloc_add(&ma, &main_ptr, 1);
512 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
513 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
515 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
516 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
518 struct anv_multialloc
{
526 #define ANV_MULTIALLOC_INIT \
527 ((struct anv_multialloc) { 0, })
529 #define ANV_MULTIALLOC(_name) \
530 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
532 __attribute__((always_inline
))
534 _anv_multialloc_add(struct anv_multialloc
*ma
,
535 void **ptr
, size_t size
, size_t align
)
537 size_t offset
= align_u64(ma
->size
, align
);
538 ma
->size
= offset
+ size
;
539 ma
->align
= MAX2(ma
->align
, align
);
541 /* Store the offset in the pointer. */
542 *ptr
= (void *)(uintptr_t)offset
;
544 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
545 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
548 #define anv_multialloc_add_size(_ma, _ptr, _size) \
549 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
551 #define anv_multialloc_add(_ma, _ptr, _count) \
552 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
554 __attribute__((always_inline
))
556 anv_multialloc_alloc(struct anv_multialloc
*ma
,
557 const VkAllocationCallbacks
*alloc
,
558 VkSystemAllocationScope scope
)
560 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
564 /* Fill out each of the pointers with their final value.
566 * for (uint32_t i = 0; i < ma->ptr_count; i++)
567 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
569 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
570 * constant, GCC is incapable of figuring this out and unrolling the loop
571 * so we have to give it a little help.
573 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
574 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
575 if ((_i) < ma->ptr_count) \
576 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
577 _ANV_MULTIALLOC_UPDATE_POINTER(0);
578 _ANV_MULTIALLOC_UPDATE_POINTER(1);
579 _ANV_MULTIALLOC_UPDATE_POINTER(2);
580 _ANV_MULTIALLOC_UPDATE_POINTER(3);
581 _ANV_MULTIALLOC_UPDATE_POINTER(4);
582 _ANV_MULTIALLOC_UPDATE_POINTER(5);
583 _ANV_MULTIALLOC_UPDATE_POINTER(6);
584 _ANV_MULTIALLOC_UPDATE_POINTER(7);
585 #undef _ANV_MULTIALLOC_UPDATE_POINTER
590 __attribute__((always_inline
))
592 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
593 const VkAllocationCallbacks
*parent_alloc
,
594 const VkAllocationCallbacks
*alloc
,
595 VkSystemAllocationScope scope
)
597 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
600 /* Extra ANV-defined BO flags which won't be passed to the kernel */
601 #define ANV_BO_EXTERNAL (1ull << 31)
602 #define ANV_BO_FLAG_MASK (1ull << 31)
609 /* Index into the current validation list. This is used by the
610 * validation list building alrogithm to track which buffers are already
611 * in the validation list so that we can ensure uniqueness.
615 /* Last known offset. This value is provided by the kernel when we
616 * execbuf and is used as the presumed offset for the next bunch of
624 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
629 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
631 bo
->gem_handle
= gem_handle
;
640 /* Represents a lock-free linked list of "free" things. This is used by
641 * both the block pool and the state pools. Unfortunately, in order to
642 * solve the ABA problem, we can't use a single uint32_t head.
644 union anv_free_list
{
648 /* A simple count that is incremented every time the head changes. */
651 /* Make sure it's aligned to 64 bits. This will make atomic operations
652 * faster on 32 bit platforms.
654 uint64_t u64
__attribute__ ((aligned (8)));
657 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
659 struct anv_block_state
{
665 /* Make sure it's aligned to 64 bits. This will make atomic operations
666 * faster on 32 bit platforms.
668 uint64_t u64
__attribute__ ((aligned (8)));
672 #define anv_block_pool_foreach_bo(bo, pool) \
673 for (struct anv_bo *bo = (pool)->bos; bo != &(pool)->bos[(pool)->nbos]; bo++)
675 #define ANV_MAX_BLOCK_POOL_BOS 20
677 struct anv_block_pool
{
678 struct anv_device
*device
;
682 struct anv_bo bos
[ANV_MAX_BLOCK_POOL_BOS
];
688 /* The address where the start of the pool is pinned. The various bos that
689 * are created as the pool grows will have addresses in the range
690 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
692 uint64_t start_address
;
694 /* The offset from the start of the bo to the "center" of the block
695 * pool. Pointers to allocated blocks are given by
696 * bo.map + center_bo_offset + offsets.
698 uint32_t center_bo_offset
;
700 /* Current memory map of the block pool. This pointer may or may not
701 * point to the actual beginning of the block pool memory. If
702 * anv_block_pool_alloc_back has ever been called, then this pointer
703 * will point to the "center" position of the buffer and all offsets
704 * (negative or positive) given out by the block pool alloc functions
705 * will be valid relative to this pointer.
707 * In particular, map == bo.map + center_offset
709 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
710 * since it will handle the softpin case as well, where this points to NULL.
716 * Array of mmaps and gem handles owned by the block pool, reclaimed when
717 * the block pool is destroyed.
719 struct u_vector mmap_cleanups
;
721 struct anv_block_state state
;
723 struct anv_block_state back_state
;
726 /* Block pools are backed by a fixed-size 1GB memfd */
727 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
729 /* The center of the block pool is also the middle of the memfd. This may
730 * change in the future if we decide differently for some reason.
732 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
734 static inline uint32_t
735 anv_block_pool_size(struct anv_block_pool
*pool
)
737 return pool
->state
.end
+ pool
->back_state
.end
;
747 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
749 struct anv_fixed_size_state_pool
{
750 union anv_free_list free_list
;
751 struct anv_block_state block
;
754 #define ANV_MIN_STATE_SIZE_LOG2 6
755 #define ANV_MAX_STATE_SIZE_LOG2 21
757 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
759 struct anv_free_entry
{
761 struct anv_state state
;
764 struct anv_state_table
{
765 struct anv_device
*device
;
767 struct anv_free_entry
*map
;
769 struct anv_block_state state
;
770 struct u_vector cleanups
;
773 struct anv_state_pool
{
774 struct anv_block_pool block_pool
;
776 struct anv_state_table table
;
778 /* The size of blocks which will be allocated from the block pool */
781 /** Free list for "back" allocations */
782 union anv_free_list back_alloc_free_list
;
784 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
787 struct anv_state_stream_block
;
789 struct anv_state_stream
{
790 struct anv_state_pool
*state_pool
;
792 /* The size of blocks to allocate from the state pool */
795 /* Current block we're allocating from */
796 struct anv_state block
;
798 /* Offset into the current block at which to allocate the next state */
801 /* List of all blocks allocated from this pool */
802 struct anv_state_stream_block
*block_list
;
805 /* The block_pool functions exported for testing only. The block pool should
806 * only be used via a state pool (see below).
808 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
809 struct anv_device
*device
,
810 uint64_t start_address
,
811 uint32_t initial_size
,
813 void anv_block_pool_finish(struct anv_block_pool
*pool
);
814 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
815 uint32_t block_size
, uint32_t *padding
);
816 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
817 uint32_t block_size
);
818 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
820 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
821 struct anv_device
*device
,
822 uint64_t start_address
,
825 void anv_state_pool_finish(struct anv_state_pool
*pool
);
826 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
827 uint32_t state_size
, uint32_t alignment
);
828 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
829 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
830 void anv_state_stream_init(struct anv_state_stream
*stream
,
831 struct anv_state_pool
*state_pool
,
832 uint32_t block_size
);
833 void anv_state_stream_finish(struct anv_state_stream
*stream
);
834 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
835 uint32_t size
, uint32_t alignment
);
837 VkResult
anv_state_table_init(struct anv_state_table
*table
,
838 struct anv_device
*device
,
839 uint32_t initial_entries
);
840 void anv_state_table_finish(struct anv_state_table
*table
);
841 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
843 void anv_free_list_push(union anv_free_list
*list
,
844 struct anv_state_table
*table
,
845 uint32_t idx
, uint32_t count
);
846 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
847 struct anv_state_table
*table
);
850 static inline struct anv_state
*
851 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
853 return &table
->map
[idx
].state
;
856 * Implements a pool of re-usable BOs. The interface is identical to that
857 * of block_pool except that each block is its own BO.
860 struct anv_device
*device
;
867 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
869 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
870 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
872 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
874 struct anv_scratch_bo
{
879 struct anv_scratch_pool
{
880 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
881 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
884 void anv_scratch_pool_init(struct anv_device
*device
,
885 struct anv_scratch_pool
*pool
);
886 void anv_scratch_pool_finish(struct anv_device
*device
,
887 struct anv_scratch_pool
*pool
);
888 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
889 struct anv_scratch_pool
*pool
,
890 gl_shader_stage stage
,
891 unsigned per_thread_scratch
);
893 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
894 struct anv_bo_cache
{
895 struct util_sparse_array bo_map
;
896 pthread_mutex_t mutex
;
899 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
900 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
901 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
902 struct anv_bo_cache
*cache
,
903 uint64_t size
, uint64_t bo_flags
,
905 VkResult
anv_bo_cache_import_host_ptr(struct anv_device
*device
,
906 struct anv_bo_cache
*cache
,
907 void *host_ptr
, uint32_t size
,
908 uint64_t bo_flags
, struct anv_bo
**bo_out
);
909 VkResult
anv_bo_cache_import(struct anv_device
*device
,
910 struct anv_bo_cache
*cache
,
911 int fd
, uint64_t bo_flags
,
913 VkResult
anv_bo_cache_export(struct anv_device
*device
,
914 struct anv_bo_cache
*cache
,
915 struct anv_bo
*bo_in
, int *fd_out
);
916 void anv_bo_cache_release(struct anv_device
*device
,
917 struct anv_bo_cache
*cache
,
920 struct anv_memory_type
{
921 /* Standard bits passed on to the client */
922 VkMemoryPropertyFlags propertyFlags
;
925 /* Driver-internal book-keeping */
926 VkBufferUsageFlags valid_buffer_usage
;
929 struct anv_memory_heap
{
930 /* Standard bits passed on to the client */
932 VkMemoryHeapFlags flags
;
934 /* Driver-internal book-keeping */
937 bool supports_48bit_addresses
;
941 struct anv_physical_device
{
942 VK_LOADER_DATA _loader_data
;
944 struct anv_instance
* instance
;
955 struct gen_device_info info
;
956 /** Amount of "GPU memory" we want to advertise
958 * Clearly, this value is bogus since Intel is a UMA architecture. On
959 * gen7 platforms, we are limited by GTT size unless we want to implement
960 * fine-grained tracking and GTT splitting. On Broadwell and above we are
961 * practically unlimited. However, we will never report more than 3/4 of
962 * the total system ram to try and avoid running out of RAM.
964 bool supports_48bit_addresses
;
965 struct brw_compiler
* compiler
;
966 struct isl_device isl_dev
;
967 struct gen_perf_config
* perf
;
968 int cmd_parser_version
;
970 bool has_exec_capture
;
973 bool has_syncobj_wait
;
974 bool has_context_priority
;
976 bool has_context_isolation
;
977 bool has_mem_available
;
978 bool always_use_bindless
;
980 /** True if we can access buffers using A64 messages */
981 bool has_a64_buffer_access
;
982 /** True if we can use bindless access for images */
983 bool has_bindless_images
;
984 /** True if we can use bindless access for samplers */
985 bool has_bindless_samplers
;
987 struct anv_device_extension_table supported_extensions
;
988 struct anv_physical_device_dispatch_table dispatch
;
991 uint32_t subslice_total
;
995 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
997 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1000 uint8_t driver_build_sha1
[20];
1001 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1002 uint8_t driver_uuid
[VK_UUID_SIZE
];
1003 uint8_t device_uuid
[VK_UUID_SIZE
];
1005 struct disk_cache
* disk_cache
;
1007 struct wsi_device wsi_device
;
1012 struct anv_app_info
{
1013 const char* app_name
;
1014 uint32_t app_version
;
1015 const char* engine_name
;
1016 uint32_t engine_version
;
1017 uint32_t api_version
;
1020 struct anv_instance
{
1021 VK_LOADER_DATA _loader_data
;
1023 VkAllocationCallbacks alloc
;
1025 struct anv_app_info app_info
;
1027 struct anv_instance_extension_table enabled_extensions
;
1028 struct anv_instance_dispatch_table dispatch
;
1029 struct anv_device_dispatch_table device_dispatch
;
1031 int physicalDeviceCount
;
1032 struct anv_physical_device physicalDevice
;
1034 bool pipeline_cache_enabled
;
1036 struct vk_debug_report_instance debug_report_callbacks
;
1038 struct driOptionCache dri_options
;
1039 struct driOptionCache available_dri_options
;
1042 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1043 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1045 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1046 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1050 VK_LOADER_DATA _loader_data
;
1052 struct anv_device
* device
;
1054 VkDeviceQueueCreateFlags flags
;
1057 struct anv_pipeline_cache
{
1058 struct anv_device
* device
;
1059 pthread_mutex_t mutex
;
1061 struct hash_table
* nir_cache
;
1063 struct hash_table
* cache
;
1066 struct nir_xfb_info
;
1067 struct anv_pipeline_bind_map
;
1069 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1070 struct anv_device
*device
,
1071 bool cache_enabled
);
1072 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1074 struct anv_shader_bin
*
1075 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1076 const void *key
, uint32_t key_size
);
1077 struct anv_shader_bin
*
1078 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1079 const void *key_data
, uint32_t key_size
,
1080 const void *kernel_data
, uint32_t kernel_size
,
1081 const void *constant_data
,
1082 uint32_t constant_data_size
,
1083 const struct brw_stage_prog_data
*prog_data
,
1084 uint32_t prog_data_size
,
1085 const struct brw_compile_stats
*stats
,
1087 const struct nir_xfb_info
*xfb_info
,
1088 const struct anv_pipeline_bind_map
*bind_map
);
1090 struct anv_shader_bin
*
1091 anv_device_search_for_kernel(struct anv_device
*device
,
1092 struct anv_pipeline_cache
*cache
,
1093 const void *key_data
, uint32_t key_size
,
1094 bool *user_cache_bit
);
1096 struct anv_shader_bin
*
1097 anv_device_upload_kernel(struct anv_device
*device
,
1098 struct anv_pipeline_cache
*cache
,
1099 const void *key_data
, uint32_t key_size
,
1100 const void *kernel_data
, uint32_t kernel_size
,
1101 const void *constant_data
,
1102 uint32_t constant_data_size
,
1103 const struct brw_stage_prog_data
*prog_data
,
1104 uint32_t prog_data_size
,
1105 const struct brw_compile_stats
*stats
,
1107 const struct nir_xfb_info
*xfb_info
,
1108 const struct anv_pipeline_bind_map
*bind_map
);
1111 struct nir_shader_compiler_options
;
1114 anv_device_search_for_nir(struct anv_device
*device
,
1115 struct anv_pipeline_cache
*cache
,
1116 const struct nir_shader_compiler_options
*nir_options
,
1117 unsigned char sha1_key
[20],
1121 anv_device_upload_nir(struct anv_device
*device
,
1122 struct anv_pipeline_cache
*cache
,
1123 const struct nir_shader
*nir
,
1124 unsigned char sha1_key
[20]);
1127 VK_LOADER_DATA _loader_data
;
1129 VkAllocationCallbacks alloc
;
1131 struct anv_instance
* instance
;
1132 uint32_t chipset_id
;
1134 struct gen_device_info info
;
1135 struct isl_device isl_dev
;
1138 bool can_chain_batches
;
1139 bool robust_buffer_access
;
1140 struct anv_device_extension_table enabled_extensions
;
1141 struct anv_device_dispatch_table dispatch
;
1143 pthread_mutex_t vma_mutex
;
1144 struct util_vma_heap vma_lo
;
1145 struct util_vma_heap vma_hi
;
1146 uint64_t vma_lo_available
;
1147 uint64_t vma_hi_available
;
1149 /** List of all anv_device_memory objects */
1150 struct list_head memory_objects
;
1152 struct anv_bo_pool batch_bo_pool
;
1154 struct anv_bo_cache bo_cache
;
1156 struct anv_state_pool dynamic_state_pool
;
1157 struct anv_state_pool instruction_state_pool
;
1158 struct anv_state_pool binding_table_pool
;
1159 struct anv_state_pool surface_state_pool
;
1161 struct anv_bo workaround_bo
;
1162 struct anv_bo trivial_batch_bo
;
1163 struct anv_bo hiz_clear_bo
;
1165 struct anv_pipeline_cache default_pipeline_cache
;
1166 struct blorp_context blorp
;
1168 struct anv_state border_colors
;
1170 struct anv_state slice_hash
;
1172 struct anv_queue queue
;
1174 struct anv_scratch_pool scratch_pool
;
1176 uint32_t default_mocs
;
1177 uint32_t external_mocs
;
1179 pthread_mutex_t mutex
;
1180 pthread_cond_t queue_submit
;
1183 struct gen_batch_decode_ctx decoder_ctx
;
1185 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1186 * the cmd_buffer's list.
1188 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1190 int perf_fd
; /* -1 if no opened */
1191 uint64_t perf_metric
; /* 0 if unset */
1193 struct gen_aux_map_context
*aux_map_ctx
;
1196 static inline struct anv_state_pool
*
1197 anv_binding_table_pool(struct anv_device
*device
)
1199 if (device
->instance
->physicalDevice
.use_softpin
)
1200 return &device
->binding_table_pool
;
1202 return &device
->surface_state_pool
;
1205 static inline struct anv_state
1206 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1207 if (device
->instance
->physicalDevice
.use_softpin
)
1208 return anv_state_pool_alloc(&device
->binding_table_pool
,
1209 device
->binding_table_pool
.block_size
, 0);
1211 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1215 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1216 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1219 static inline uint32_t
1220 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1222 if (bo
->flags
& ANV_BO_EXTERNAL
)
1223 return device
->external_mocs
;
1225 return device
->default_mocs
;
1228 void anv_device_init_blorp(struct anv_device
*device
);
1229 void anv_device_finish_blorp(struct anv_device
*device
);
1231 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1232 const char *file
, int line
,
1233 const char *msg
, ...)
1234 anv_printflike(4, 5);
1235 #define anv_device_set_lost(dev, ...) \
1236 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1239 anv_device_is_lost(struct anv_device
*device
)
1241 return unlikely(device
->_lost
);
1244 VkResult
anv_device_execbuf(struct anv_device
*device
,
1245 struct drm_i915_gem_execbuffer2
*execbuf
,
1246 struct anv_bo
**execbuf_bos
);
1247 VkResult
anv_device_query_status(struct anv_device
*device
);
1248 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1249 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1252 void* anv_gem_mmap(struct anv_device
*device
,
1253 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1254 void anv_gem_munmap(void *p
, uint64_t size
);
1255 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1256 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1257 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1258 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1259 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1260 int anv_gem_execbuffer(struct anv_device
*device
,
1261 struct drm_i915_gem_execbuffer2
*execbuf
);
1262 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1263 uint32_t stride
, uint32_t tiling
);
1264 int anv_gem_create_context(struct anv_device
*device
);
1265 bool anv_gem_has_context_priority(int fd
);
1266 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1267 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1269 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1271 int anv_gem_get_param(int fd
, uint32_t param
);
1272 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1273 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1274 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1275 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1276 uint32_t *active
, uint32_t *pending
);
1277 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1278 int anv_gem_reg_read(struct anv_device
*device
,
1279 uint32_t offset
, uint64_t *result
);
1280 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1281 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1282 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1283 uint32_t read_domains
, uint32_t write_domain
);
1284 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1285 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1286 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1287 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1288 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1289 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1291 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1292 uint32_t handle
, int fd
);
1293 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1294 bool anv_gem_supports_syncobj_wait(int fd
);
1295 int anv_gem_syncobj_wait(struct anv_device
*device
,
1296 uint32_t *handles
, uint32_t num_handles
,
1297 int64_t abs_timeout_ns
, bool wait_all
);
1299 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1300 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1302 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1304 struct anv_reloc_list
{
1305 uint32_t num_relocs
;
1306 uint32_t array_length
;
1307 struct drm_i915_gem_relocation_entry
* relocs
;
1308 struct anv_bo
** reloc_bos
;
1312 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1313 const VkAllocationCallbacks
*alloc
);
1314 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1315 const VkAllocationCallbacks
*alloc
);
1317 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1318 const VkAllocationCallbacks
*alloc
,
1319 uint32_t offset
, struct anv_bo
*target_bo
,
1320 uint32_t delta
, uint64_t *address_u64_out
);
1322 struct anv_batch_bo
{
1323 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1324 struct list_head link
;
1328 /* Bytes actually consumed in this batch BO */
1331 struct anv_reloc_list relocs
;
1335 const VkAllocationCallbacks
* alloc
;
1341 struct anv_reloc_list
* relocs
;
1343 /* This callback is called (with the associated user data) in the event
1344 * that the batch runs out of space.
1346 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1350 * Current error status of the command buffer. Used to track inconsistent
1351 * or incomplete command buffer states that are the consequence of run-time
1352 * errors such as out of memory scenarios. We want to track this in the
1353 * batch because the command buffer object is not visible to some parts
1359 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1360 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1361 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1362 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1363 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1364 struct anv_batch
*batch
);
1366 static inline VkResult
1367 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1369 assert(error
!= VK_SUCCESS
);
1370 if (batch
->status
== VK_SUCCESS
)
1371 batch
->status
= error
;
1372 return batch
->status
;
1376 anv_batch_has_error(struct anv_batch
*batch
)
1378 return batch
->status
!= VK_SUCCESS
;
1381 struct anv_address
{
1386 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1389 anv_address_is_null(struct anv_address addr
)
1391 return addr
.bo
== NULL
&& addr
.offset
== 0;
1394 static inline uint64_t
1395 anv_address_physical(struct anv_address addr
)
1397 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1398 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1400 return gen_canonical_address(addr
.offset
);
1403 static inline struct anv_address
1404 anv_address_add(struct anv_address addr
, uint64_t offset
)
1406 addr
.offset
+= offset
;
1411 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1413 unsigned reloc_size
= 0;
1414 if (device
->info
.gen
>= 8) {
1415 reloc_size
= sizeof(uint64_t);
1416 *(uint64_t *)p
= gen_canonical_address(v
);
1418 reloc_size
= sizeof(uint32_t);
1422 if (flush
&& !device
->info
.has_llc
)
1423 gen_flush_range(p
, reloc_size
);
1426 static inline uint64_t
1427 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1428 const struct anv_address address
, uint32_t delta
)
1430 if (address
.bo
== NULL
) {
1431 return address
.offset
+ delta
;
1433 assert(batch
->start
<= location
&& location
< batch
->end
);
1435 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1439 #define __gen_address_type struct anv_address
1440 #define __gen_user_data struct anv_batch
1441 #define __gen_combine_address _anv_combine_address
1443 /* Wrapper macros needed to work around preprocessor argument issues. In
1444 * particular, arguments don't get pre-evaluated if they are concatenated.
1445 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1446 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1447 * We can work around this easily enough with these helpers.
1449 #define __anv_cmd_length(cmd) cmd ## _length
1450 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1451 #define __anv_cmd_header(cmd) cmd ## _header
1452 #define __anv_cmd_pack(cmd) cmd ## _pack
1453 #define __anv_reg_num(reg) reg ## _num
1455 #define anv_pack_struct(dst, struc, ...) do { \
1456 struct struc __template = { \
1459 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1460 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1463 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1464 void *__dst = anv_batch_emit_dwords(batch, n); \
1466 struct cmd __template = { \
1467 __anv_cmd_header(cmd), \
1468 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1471 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1476 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1480 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1481 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1484 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1485 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1486 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1489 #define anv_batch_emit(batch, cmd, name) \
1490 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1491 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1492 __builtin_expect(_dst != NULL, 1); \
1493 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1494 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1498 /* MEMORY_OBJECT_CONTROL_STATE:
1499 * .GraphicsDataTypeGFDT = 0,
1500 * .LLCCacheabilityControlLLCCC = 0,
1501 * .L3CacheabilityControlL3CC = 1,
1505 /* MEMORY_OBJECT_CONTROL_STATE:
1506 * .LLCeLLCCacheabilityControlLLCCC = 0,
1507 * .L3CacheabilityControlL3CC = 1,
1509 #define GEN75_MOCS 1
1511 /* MEMORY_OBJECT_CONTROL_STATE:
1512 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
1513 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1514 * .AgeforQUADLRU = 0
1516 #define GEN8_MOCS 0x78
1518 /* MEMORY_OBJECT_CONTROL_STATE:
1519 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
1520 * .TargetCache = L3DefertoPATforLLCeLLCselection,
1521 * .AgeforQUADLRU = 0
1523 #define GEN8_EXTERNAL_MOCS 0x18
1525 /* Skylake: MOCS is now an index into an array of 62 different caching
1526 * configurations programmed by the kernel.
1529 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1530 #define GEN9_MOCS (2 << 1)
1532 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
1533 #define GEN9_EXTERNAL_MOCS (1 << 1)
1535 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1536 #define GEN10_MOCS GEN9_MOCS
1537 #define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1539 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1540 #define GEN11_MOCS GEN9_MOCS
1541 #define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS
1543 /* TigerLake MOCS */
1544 #define GEN12_MOCS GEN9_MOCS
1545 /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
1546 #define GEN12_EXTERNAL_MOCS (3 << 1)
1548 struct anv_device_memory
{
1549 struct list_head link
;
1552 struct anv_memory_type
* type
;
1553 VkDeviceSize map_size
;
1556 /* If set, we are holding reference to AHardwareBuffer
1557 * which we must release when memory is freed.
1559 struct AHardwareBuffer
* ahw
;
1561 /* If set, this memory comes from a host pointer. */
1566 * Header for Vertex URB Entry (VUE)
1568 struct anv_vue_header
{
1570 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1571 uint32_t ViewportIndex
;
1575 /** Struct representing a sampled image descriptor
1577 * This descriptor layout is used for sampled images, bare sampler, and
1578 * combined image/sampler descriptors.
1580 struct anv_sampled_image_descriptor
{
1581 /** Bindless image handle
1583 * This is expected to already be shifted such that the 20-bit
1584 * SURFACE_STATE table index is in the top 20 bits.
1588 /** Bindless sampler handle
1590 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1591 * to the dynamic state base address.
1596 struct anv_texture_swizzle_descriptor
{
1599 * See also nir_intrinsic_channel_select_intel
1603 /** Unused padding to ensure the struct is a multiple of 64 bits */
1607 /** Struct representing a storage image descriptor */
1608 struct anv_storage_image_descriptor
{
1609 /** Bindless image handles
1611 * These are expected to already be shifted such that the 20-bit
1612 * SURFACE_STATE table index is in the top 20 bits.
1614 uint32_t read_write
;
1615 uint32_t write_only
;
1618 /** Struct representing a address/range descriptor
1620 * The fields of this struct correspond directly to the data layout of
1621 * nir_address_format_64bit_bounded_global addresses. The last field is the
1622 * offset in the NIR address so it must be zero so that when you load the
1623 * descriptor you get a pointer to the start of the range.
1625 struct anv_address_range_descriptor
{
1631 enum anv_descriptor_data
{
1632 /** The descriptor contains a BTI reference to a surface state */
1633 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1634 /** The descriptor contains a BTI reference to a sampler state */
1635 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1636 /** The descriptor contains an actual buffer view */
1637 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1638 /** The descriptor contains auxiliary image layout data */
1639 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1640 /** The descriptor contains auxiliary image layout data */
1641 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1642 /** anv_address_range_descriptor with a buffer address and range */
1643 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1644 /** Bindless surface handle */
1645 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1646 /** Storage image handles */
1647 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1648 /** Storage image handles */
1649 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1652 struct anv_descriptor_set_binding_layout
{
1654 /* The type of the descriptors in this binding */
1655 VkDescriptorType type
;
1658 /* Flags provided when this binding was created */
1659 VkDescriptorBindingFlagsEXT flags
;
1661 /* Bitfield representing the type of data this descriptor contains */
1662 enum anv_descriptor_data data
;
1664 /* Maximum number of YCbCr texture/sampler planes */
1665 uint8_t max_plane_count
;
1667 /* Number of array elements in this binding (or size in bytes for inline
1670 uint16_t array_size
;
1672 /* Index into the flattend descriptor set */
1673 uint16_t descriptor_index
;
1675 /* Index into the dynamic state array for a dynamic buffer */
1676 int16_t dynamic_offset_index
;
1678 /* Index into the descriptor set buffer views */
1679 int16_t buffer_view_index
;
1681 /* Offset into the descriptor buffer where this descriptor lives */
1682 uint32_t descriptor_offset
;
1684 /* Immutable samplers (or NULL if no immutable samplers) */
1685 struct anv_sampler
**immutable_samplers
;
1688 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1690 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1691 VkDescriptorType type
);
1693 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1694 const struct anv_descriptor_set_binding_layout
*binding
,
1697 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1698 const struct anv_descriptor_set_binding_layout
*binding
,
1701 struct anv_descriptor_set_layout
{
1702 /* Descriptor set layouts can be destroyed at almost any time */
1705 /* Number of bindings in this descriptor set */
1706 uint16_t binding_count
;
1708 /* Total size of the descriptor set with room for all array entries */
1711 /* Shader stages affected by this descriptor set */
1712 uint16_t shader_stages
;
1714 /* Number of buffer views in this descriptor set */
1715 uint16_t buffer_view_count
;
1717 /* Number of dynamic offsets used by this descriptor set */
1718 uint16_t dynamic_offset_count
;
1720 /* Size of the descriptor buffer for this descriptor set */
1721 uint32_t descriptor_buffer_size
;
1723 /* Bindings in this descriptor set */
1724 struct anv_descriptor_set_binding_layout binding
[0];
1728 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1730 assert(layout
&& layout
->ref_cnt
>= 1);
1731 p_atomic_inc(&layout
->ref_cnt
);
1735 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1736 struct anv_descriptor_set_layout
*layout
)
1738 assert(layout
&& layout
->ref_cnt
>= 1);
1739 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1740 vk_free(&device
->alloc
, layout
);
1743 struct anv_descriptor
{
1744 VkDescriptorType type
;
1748 VkImageLayout layout
;
1749 struct anv_image_view
*image_view
;
1750 struct anv_sampler
*sampler
;
1754 struct anv_buffer
*buffer
;
1759 struct anv_buffer_view
*buffer_view
;
1763 struct anv_descriptor_set
{
1764 struct anv_descriptor_pool
*pool
;
1765 struct anv_descriptor_set_layout
*layout
;
1768 /* State relative to anv_descriptor_pool::bo */
1769 struct anv_state desc_mem
;
1770 /* Surface state for the descriptor buffer */
1771 struct anv_state desc_surface_state
;
1773 uint32_t buffer_view_count
;
1774 struct anv_buffer_view
*buffer_views
;
1776 /* Link to descriptor pool's desc_sets list . */
1777 struct list_head pool_link
;
1779 struct anv_descriptor descriptors
[0];
1782 struct anv_buffer_view
{
1783 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1784 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1786 struct anv_address address
;
1788 struct anv_state surface_state
;
1789 struct anv_state storage_surface_state
;
1790 struct anv_state writeonly_storage_surface_state
;
1792 struct brw_image_param storage_image_param
;
1795 struct anv_push_descriptor_set
{
1796 struct anv_descriptor_set set
;
1798 /* Put this field right behind anv_descriptor_set so it fills up the
1799 * descriptors[0] field. */
1800 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1802 /** True if the descriptor set buffer has been referenced by a draw or
1805 bool set_used_on_gpu
;
1807 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1810 struct anv_descriptor_pool
{
1816 struct util_vma_heap bo_heap
;
1818 struct anv_state_stream surface_state_stream
;
1819 void *surface_state_free_list
;
1821 struct list_head desc_sets
;
1826 enum anv_descriptor_template_entry_type
{
1827 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1828 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1829 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1832 struct anv_descriptor_template_entry
{
1833 /* The type of descriptor in this entry */
1834 VkDescriptorType type
;
1836 /* Binding in the descriptor set */
1839 /* Offset at which to write into the descriptor set binding */
1840 uint32_t array_element
;
1842 /* Number of elements to write into the descriptor set binding */
1843 uint32_t array_count
;
1845 /* Offset into the user provided data */
1848 /* Stride between elements into the user provided data */
1852 struct anv_descriptor_update_template
{
1853 VkPipelineBindPoint bind_point
;
1855 /* The descriptor set this template corresponds to. This value is only
1856 * valid if the template was created with the templateType
1857 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1861 /* Number of entries in this template */
1862 uint32_t entry_count
;
1864 /* Entries of the template */
1865 struct anv_descriptor_template_entry entries
[0];
1869 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1872 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1873 struct anv_descriptor_set
*set
,
1874 const VkDescriptorImageInfo
* const info
,
1875 VkDescriptorType type
,
1880 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1881 struct anv_descriptor_set
*set
,
1882 VkDescriptorType type
,
1883 struct anv_buffer_view
*buffer_view
,
1888 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1889 struct anv_descriptor_set
*set
,
1890 struct anv_state_stream
*alloc_stream
,
1891 VkDescriptorType type
,
1892 struct anv_buffer
*buffer
,
1895 VkDeviceSize offset
,
1896 VkDeviceSize range
);
1898 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1899 struct anv_descriptor_set
*set
,
1906 anv_descriptor_set_write_template(struct anv_device
*device
,
1907 struct anv_descriptor_set
*set
,
1908 struct anv_state_stream
*alloc_stream
,
1909 const struct anv_descriptor_update_template
*template,
1913 anv_descriptor_set_create(struct anv_device
*device
,
1914 struct anv_descriptor_pool
*pool
,
1915 struct anv_descriptor_set_layout
*layout
,
1916 struct anv_descriptor_set
**out_set
);
1919 anv_descriptor_set_destroy(struct anv_device
*device
,
1920 struct anv_descriptor_pool
*pool
,
1921 struct anv_descriptor_set
*set
);
1923 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
1924 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
1925 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
1926 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1928 struct anv_pipeline_binding
{
1929 /* The descriptor set this surface corresponds to. The special value of
1930 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1931 * to a color attachment and not a regular descriptor.
1935 /* Binding in the descriptor set */
1938 /* Index in the binding */
1941 /* Plane in the binding index */
1944 /* Input attachment index (relative to the subpass) */
1945 uint8_t input_attachment_index
;
1947 /* For a storage image, whether it is write-only */
1951 struct anv_pipeline_layout
{
1953 struct anv_descriptor_set_layout
*layout
;
1954 uint32_t dynamic_offset_start
;
1959 unsigned char sha1
[20];
1963 struct anv_device
* device
;
1966 VkBufferUsageFlags usage
;
1968 /* Set when bound */
1969 struct anv_address address
;
1972 static inline uint64_t
1973 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1975 assert(offset
<= buffer
->size
);
1976 if (range
== VK_WHOLE_SIZE
) {
1977 return buffer
->size
- offset
;
1979 assert(range
+ offset
>= range
);
1980 assert(range
+ offset
<= buffer
->size
);
1985 enum anv_cmd_dirty_bits
{
1986 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1987 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1988 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1989 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1990 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1991 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1992 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1993 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1994 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1995 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1996 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1997 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1998 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
1999 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2001 typedef uint32_t anv_cmd_dirty_mask_t
;
2003 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2004 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2005 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2006 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2007 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2008 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2009 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2010 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2011 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2012 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2013 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2015 static inline enum anv_cmd_dirty_bits
2016 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2019 case VK_DYNAMIC_STATE_VIEWPORT
:
2020 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2021 case VK_DYNAMIC_STATE_SCISSOR
:
2022 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2023 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2024 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2025 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2026 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2027 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2028 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2029 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2030 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2031 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2032 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2033 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2034 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2035 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2036 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2037 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2038 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2040 assert(!"Unsupported dynamic state");
2046 enum anv_pipe_bits
{
2047 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2048 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2049 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2050 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2051 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2052 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2053 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2054 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2055 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2056 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2057 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2058 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2060 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2061 * a flush has happened but not a CS stall. The next time we do any sort
2062 * of invalidation we need to insert a CS stall at that time. Otherwise,
2063 * we would have to CS stall on every flush which could be bad.
2065 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2067 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2068 * target operations related to transfer commands with VkBuffer as
2069 * destination are ongoing. Some operations like copies on the command
2070 * streamer might need to be aware of this to trigger the appropriate stall
2071 * before they can proceed with the copy.
2073 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2076 #define ANV_PIPE_FLUSH_BITS ( \
2077 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2078 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2079 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2080 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2082 #define ANV_PIPE_STALL_BITS ( \
2083 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2084 ANV_PIPE_DEPTH_STALL_BIT | \
2085 ANV_PIPE_CS_STALL_BIT)
2087 #define ANV_PIPE_INVALIDATE_BITS ( \
2088 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2089 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2090 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2091 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2092 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2093 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2095 static inline enum anv_pipe_bits
2096 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2098 enum anv_pipe_bits pipe_bits
= 0;
2101 for_each_bit(b
, flags
) {
2102 switch ((VkAccessFlagBits
)(1 << b
)) {
2103 case VK_ACCESS_SHADER_WRITE_BIT
:
2104 /* We're transitioning a buffer that was previously used as write
2105 * destination through the data port. To make its content available
2106 * to future operations, flush the data cache.
2108 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2110 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2111 /* We're transitioning a buffer that was previously used as render
2112 * target. To make its content available to future operations, flush
2113 * the render target cache.
2115 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2117 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2118 /* We're transitioning a buffer that was previously used as depth
2119 * buffer. To make its content available to future operations, flush
2122 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2124 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2125 /* We're transitioning a buffer that was previously used as a
2126 * transfer write destination. Generic write operations include color
2127 * & depth operations as well as buffer operations like :
2128 * - vkCmdClearColorImage()
2129 * - vkCmdClearDepthStencilImage()
2130 * - vkCmdBlitImage()
2131 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2133 * Most of these operations are implemented using Blorp which writes
2134 * through the render target, so flush that cache to make it visible
2135 * to future operations. And for depth related operations we also
2136 * need to flush the depth cache.
2138 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2139 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2141 case VK_ACCESS_MEMORY_WRITE_BIT
:
2142 /* We're transitioning a buffer for generic write operations. Flush
2145 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2148 break; /* Nothing to do */
2155 static inline enum anv_pipe_bits
2156 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2158 enum anv_pipe_bits pipe_bits
= 0;
2161 for_each_bit(b
, flags
) {
2162 switch ((VkAccessFlagBits
)(1 << b
)) {
2163 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2164 /* Indirect draw commands take a buffer as input that we're going to
2165 * read from the command streamer to load some of the HW registers
2166 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2167 * command streamer stall so that all the cache flushes have
2168 * completed before the command streamer loads from memory.
2170 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2171 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2172 * through a vertex buffer, so invalidate that cache.
2174 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2175 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2176 * UBO from the buffer, so we need to invalidate constant cache.
2178 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2180 case VK_ACCESS_INDEX_READ_BIT
:
2181 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2182 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2183 * commands, so we invalidate the VF cache to make sure there is no
2184 * stale data when we start rendering.
2186 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2188 case VK_ACCESS_UNIFORM_READ_BIT
:
2189 /* We transitioning a buffer to be used as uniform data. Because
2190 * uniform is accessed through the data port & sampler, we need to
2191 * invalidate the texture cache (sampler) & constant cache (data
2192 * port) to avoid stale data.
2194 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2195 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2197 case VK_ACCESS_SHADER_READ_BIT
:
2198 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2199 case VK_ACCESS_TRANSFER_READ_BIT
:
2200 /* Transitioning a buffer to be read through the sampler, so
2201 * invalidate the texture cache, we don't want any stale data.
2203 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2205 case VK_ACCESS_MEMORY_READ_BIT
:
2206 /* Transitioning a buffer for generic read, invalidate all the
2209 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2211 case VK_ACCESS_MEMORY_WRITE_BIT
:
2212 /* Generic write, make sure all previously written things land in
2215 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2217 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2218 /* Transitioning a buffer for conditional rendering. We'll load the
2219 * content of this buffer into HW registers using the command
2220 * streamer, so we need to stall the command streamer to make sure
2221 * any in-flight flush operations have completed.
2223 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2226 break; /* Nothing to do */
2233 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2234 VK_IMAGE_ASPECT_COLOR_BIT | \
2235 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2236 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2237 VK_IMAGE_ASPECT_PLANE_2_BIT)
2238 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2239 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2240 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2241 VK_IMAGE_ASPECT_PLANE_2_BIT)
2243 struct anv_vertex_binding
{
2244 struct anv_buffer
* buffer
;
2245 VkDeviceSize offset
;
2248 struct anv_xfb_binding
{
2249 struct anv_buffer
* buffer
;
2250 VkDeviceSize offset
;
2254 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
2255 #define ANV_PARAM_IS_PUSH(param) ((uint32_t)(param) >> 16 == 1)
2256 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
2258 #define ANV_PARAM_DYN_OFFSET(offset) ((2 << 16) | (uint32_t)(offset))
2259 #define ANV_PARAM_IS_DYN_OFFSET(param) ((uint32_t)(param) >> 16 == 2)
2260 #define ANV_PARAM_DYN_OFFSET_IDX(param) ((param) & 0xffff)
2262 struct anv_push_constants
{
2263 /* Push constant data provided by the client through vkPushConstants */
2264 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2266 /* Used for vkCmdDispatchBase */
2267 uint32_t base_work_group_id
[3];
2270 struct anv_dynamic_state
{
2273 VkViewport viewports
[MAX_VIEWPORTS
];
2278 VkRect2D scissors
[MAX_SCISSORS
];
2289 float blend_constants
[4];
2299 } stencil_compare_mask
;
2304 } stencil_write_mask
;
2309 } stencil_reference
;
2317 extern const struct anv_dynamic_state default_dynamic_state
;
2319 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2320 const struct anv_dynamic_state
*src
,
2321 uint32_t copy_mask
);
2323 struct anv_surface_state
{
2324 struct anv_state state
;
2325 /** Address of the surface referred to by this state
2327 * This address is relative to the start of the BO.
2329 struct anv_address address
;
2330 /* Address of the aux surface, if any
2332 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2334 * With the exception of gen8, the bottom 12 bits of this address' offset
2335 * include extra aux information.
2337 struct anv_address aux_address
;
2338 /* Address of the clear color, if any
2340 * This address is relative to the start of the BO.
2342 struct anv_address clear_address
;
2346 * Attachment state when recording a renderpass instance.
2348 * The clear value is valid only if there exists a pending clear.
2350 struct anv_attachment_state
{
2351 enum isl_aux_usage aux_usage
;
2352 enum isl_aux_usage input_aux_usage
;
2353 struct anv_surface_state color
;
2354 struct anv_surface_state input
;
2356 VkImageLayout current_layout
;
2357 VkImageAspectFlags pending_clear_aspects
;
2358 VkImageAspectFlags pending_load_aspects
;
2360 VkClearValue clear_value
;
2361 bool clear_color_is_zero_one
;
2362 bool clear_color_is_zero
;
2364 /* When multiview is active, attachments with a renderpass clear
2365 * operation have their respective layers cleared on the first
2366 * subpass that uses them, and only in that subpass. We keep track
2367 * of this using a bitfield to indicate which layers of an attachment
2368 * have not been cleared yet when multiview is active.
2370 uint32_t pending_clear_views
;
2371 struct anv_image_view
* image_view
;
2374 /** State tracking for particular pipeline bind point
2376 * This struct is the base struct for anv_cmd_graphics_state and
2377 * anv_cmd_compute_state. These are used to track state which is bound to a
2378 * particular type of pipeline. Generic state that applies per-stage such as
2379 * binding table offsets and push constants is tracked generically with a
2380 * per-stage array in anv_cmd_state.
2382 struct anv_cmd_pipeline_state
{
2383 struct anv_pipeline
*pipeline
;
2384 struct anv_pipeline_layout
*layout
;
2386 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2387 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2389 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2392 /** State tracking for graphics pipeline
2394 * This has anv_cmd_pipeline_state as a base struct to track things which get
2395 * bound to a graphics pipeline. Along with general pipeline bind point state
2396 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2397 * state which is graphics-specific.
2399 struct anv_cmd_graphics_state
{
2400 struct anv_cmd_pipeline_state base
;
2402 anv_cmd_dirty_mask_t dirty
;
2405 struct anv_dynamic_state dynamic
;
2408 struct anv_buffer
*index_buffer
;
2409 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2410 uint32_t index_offset
;
2414 /** State tracking for compute pipeline
2416 * This has anv_cmd_pipeline_state as a base struct to track things which get
2417 * bound to a compute pipeline. Along with general pipeline bind point state
2418 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2419 * state which is compute-specific.
2421 struct anv_cmd_compute_state
{
2422 struct anv_cmd_pipeline_state base
;
2424 bool pipeline_dirty
;
2426 struct anv_address num_workgroups
;
2429 /** State required while building cmd buffer */
2430 struct anv_cmd_state
{
2431 /* PIPELINE_SELECT.PipelineSelection */
2432 uint32_t current_pipeline
;
2433 const struct gen_l3_config
* current_l3_config
;
2434 uint32_t last_aux_map_state
;
2436 struct anv_cmd_graphics_state gfx
;
2437 struct anv_cmd_compute_state compute
;
2439 enum anv_pipe_bits pending_pipe_bits
;
2440 VkShaderStageFlags descriptors_dirty
;
2441 VkShaderStageFlags push_constants_dirty
;
2443 struct anv_framebuffer
* framebuffer
;
2444 struct anv_render_pass
* pass
;
2445 struct anv_subpass
* subpass
;
2446 VkRect2D render_area
;
2447 uint32_t restart_index
;
2448 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2450 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2451 VkShaderStageFlags push_constant_stages
;
2452 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2453 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2454 struct anv_state samplers
[MESA_SHADER_STAGES
];
2457 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2458 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2459 * and before invoking the secondary in ExecuteCommands.
2461 bool pma_fix_enabled
;
2464 * Whether or not we know for certain that HiZ is enabled for the current
2465 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2466 * enabled or not, this will be false.
2470 bool conditional_render_enabled
;
2473 * Last rendering scale argument provided to
2474 * genX(cmd_buffer_emit_hashing_mode)().
2476 unsigned current_hash_scale
;
2479 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2480 * valid only when recording a render pass instance.
2482 struct anv_attachment_state
* attachments
;
2485 * Surface states for color render targets. These are stored in a single
2486 * flat array. For depth-stencil attachments, the surface state is simply
2489 struct anv_state render_pass_states
;
2492 * A null surface state of the right size to match the framebuffer. This
2493 * is one of the states in render_pass_states.
2495 struct anv_state null_surface_state
;
2498 struct anv_cmd_pool
{
2499 VkAllocationCallbacks alloc
;
2500 struct list_head cmd_buffers
;
2503 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2505 enum anv_cmd_buffer_exec_mode
{
2506 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2507 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2508 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2509 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2510 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2513 struct anv_cmd_buffer
{
2514 VK_LOADER_DATA _loader_data
;
2516 struct anv_device
* device
;
2518 struct anv_cmd_pool
* pool
;
2519 struct list_head pool_link
;
2521 struct anv_batch batch
;
2523 /* Fields required for the actual chain of anv_batch_bo's.
2525 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2527 struct list_head batch_bos
;
2528 enum anv_cmd_buffer_exec_mode exec_mode
;
2530 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2531 * referenced by this command buffer
2533 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2535 struct u_vector seen_bbos
;
2537 /* A vector of int32_t's for every block of binding tables.
2539 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2541 struct u_vector bt_block_states
;
2544 struct anv_reloc_list surface_relocs
;
2545 /** Last seen surface state block pool center bo offset */
2546 uint32_t last_ss_pool_center
;
2548 /* Serial for tracking buffer completion */
2551 /* Stream objects for storing temporary data */
2552 struct anv_state_stream surface_state_stream
;
2553 struct anv_state_stream dynamic_state_stream
;
2555 VkCommandBufferUsageFlags usage_flags
;
2556 VkCommandBufferLevel level
;
2558 struct anv_cmd_state state
;
2560 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2561 uint64_t intel_perf_marker
;
2564 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2565 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2566 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2567 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2568 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2569 struct anv_cmd_buffer
*secondary
);
2570 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2571 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2572 struct anv_cmd_buffer
*cmd_buffer
,
2573 const VkSemaphore
*in_semaphores
,
2574 uint32_t num_in_semaphores
,
2575 const VkSemaphore
*out_semaphores
,
2576 uint32_t num_out_semaphores
,
2579 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2581 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2582 const void *data
, uint32_t size
, uint32_t alignment
);
2583 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2584 uint32_t *a
, uint32_t *b
,
2585 uint32_t dwords
, uint32_t alignment
);
2588 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2590 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2591 uint32_t entries
, uint32_t *state_offset
);
2593 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2595 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2596 uint32_t size
, uint32_t alignment
);
2599 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2601 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2602 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2603 bool depth_clamp_enable
);
2604 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2606 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2607 struct anv_render_pass
*pass
,
2608 struct anv_framebuffer
*framebuffer
,
2609 const VkClearValue
*clear_values
);
2611 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2614 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2615 gl_shader_stage stage
);
2617 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2619 const struct anv_image_view
*
2620 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2623 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2624 uint32_t num_entries
,
2625 uint32_t *state_offset
,
2626 struct anv_state
*bt_state
);
2628 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2630 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2632 enum anv_fence_type
{
2633 ANV_FENCE_TYPE_NONE
= 0,
2635 ANV_FENCE_TYPE_SYNCOBJ
,
2639 enum anv_bo_fence_state
{
2640 /** Indicates that this is a new (or newly reset fence) */
2641 ANV_BO_FENCE_STATE_RESET
,
2643 /** Indicates that this fence has been submitted to the GPU but is still
2644 * (as far as we know) in use by the GPU.
2646 ANV_BO_FENCE_STATE_SUBMITTED
,
2648 ANV_BO_FENCE_STATE_SIGNALED
,
2651 struct anv_fence_impl
{
2652 enum anv_fence_type type
;
2655 /** Fence implementation for BO fences
2657 * These fences use a BO and a set of CPU-tracked state flags. The BO
2658 * is added to the object list of the last execbuf call in a QueueSubmit
2659 * and is marked EXEC_WRITE. The state flags track when the BO has been
2660 * submitted to the kernel. We need to do this because Vulkan lets you
2661 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2662 * will say it's idle in this case.
2666 enum anv_bo_fence_state state
;
2669 /** DRM syncobj handle for syncobj-based fences */
2673 struct wsi_fence
*fence_wsi
;
2678 /* Permanent fence state. Every fence has some form of permanent state
2679 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2680 * cross-process fences) or it could just be a dummy for use internally.
2682 struct anv_fence_impl permanent
;
2684 /* Temporary fence state. A fence *may* have temporary state. That state
2685 * is added to the fence by an import operation and is reset back to
2686 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2687 * state cannot be signaled because the fence must already be signaled
2688 * before the temporary state can be exported from the fence in the other
2689 * process and imported here.
2691 struct anv_fence_impl temporary
;
2696 struct anv_state state
;
2699 enum anv_semaphore_type
{
2700 ANV_SEMAPHORE_TYPE_NONE
= 0,
2701 ANV_SEMAPHORE_TYPE_DUMMY
,
2702 ANV_SEMAPHORE_TYPE_BO
,
2703 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2704 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2707 struct anv_semaphore_impl
{
2708 enum anv_semaphore_type type
;
2711 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2712 * This BO will be added to the object list on any execbuf2 calls for
2713 * which this semaphore is used as a wait or signal fence. When used as
2714 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2718 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2719 * If the semaphore is in the unsignaled state due to either just being
2720 * created or because it has been used for a wait, fd will be -1.
2724 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2725 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2726 * import so we don't need to bother with a userspace cache.
2732 struct anv_semaphore
{
2733 /* Permanent semaphore state. Every semaphore has some form of permanent
2734 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2735 * (for cross-process semaphores0 or it could just be a dummy for use
2738 struct anv_semaphore_impl permanent
;
2740 /* Temporary semaphore state. A semaphore *may* have temporary state.
2741 * That state is added to the semaphore by an import operation and is reset
2742 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2743 * semaphore with temporary state cannot be signaled because the semaphore
2744 * must already be signaled before the temporary state can be exported from
2745 * the semaphore in the other process and imported here.
2747 struct anv_semaphore_impl temporary
;
2750 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2751 struct anv_semaphore
*semaphore
);
2753 struct anv_shader_module
{
2754 unsigned char sha1
[20];
2759 static inline gl_shader_stage
2760 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2762 assert(__builtin_popcount(vk_stage
) == 1);
2763 return ffs(vk_stage
) - 1;
2766 static inline VkShaderStageFlagBits
2767 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2769 return (1 << mesa_stage
);
2772 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2774 #define anv_foreach_stage(stage, stage_bits) \
2775 for (gl_shader_stage stage, \
2776 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2777 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2778 __tmp &= ~(1 << (stage)))
2780 struct anv_pipeline_bind_map
{
2781 uint32_t surface_count
;
2782 uint32_t sampler_count
;
2784 struct anv_pipeline_binding
* surface_to_descriptor
;
2785 struct anv_pipeline_binding
* sampler_to_descriptor
;
2788 struct anv_shader_bin_key
{
2793 struct anv_shader_bin
{
2796 const struct anv_shader_bin_key
*key
;
2798 struct anv_state kernel
;
2799 uint32_t kernel_size
;
2801 struct anv_state constant_data
;
2802 uint32_t constant_data_size
;
2804 const struct brw_stage_prog_data
*prog_data
;
2805 uint32_t prog_data_size
;
2807 struct brw_compile_stats stats
[3];
2810 struct nir_xfb_info
*xfb_info
;
2812 struct anv_pipeline_bind_map bind_map
;
2815 struct anv_shader_bin
*
2816 anv_shader_bin_create(struct anv_device
*device
,
2817 const void *key
, uint32_t key_size
,
2818 const void *kernel
, uint32_t kernel_size
,
2819 const void *constant_data
, uint32_t constant_data_size
,
2820 const struct brw_stage_prog_data
*prog_data
,
2821 uint32_t prog_data_size
, const void *prog_data_param
,
2822 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
2823 const struct nir_xfb_info
*xfb_info
,
2824 const struct anv_pipeline_bind_map
*bind_map
);
2827 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2830 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2832 assert(shader
&& shader
->ref_cnt
>= 1);
2833 p_atomic_inc(&shader
->ref_cnt
);
2837 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2839 assert(shader
&& shader
->ref_cnt
>= 1);
2840 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2841 anv_shader_bin_destroy(device
, shader
);
2844 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
2845 #define MAX_PIPELINE_EXECUTABLES 7
2847 struct anv_pipeline_executable
{
2848 gl_shader_stage stage
;
2850 struct brw_compile_stats stats
;
2856 struct anv_pipeline
{
2857 struct anv_device
* device
;
2858 struct anv_batch batch
;
2859 uint32_t batch_data
[512];
2860 struct anv_reloc_list batch_relocs
;
2861 anv_cmd_dirty_mask_t dynamic_state_mask
;
2862 struct anv_dynamic_state dynamic_state
;
2866 VkPipelineCreateFlags flags
;
2867 struct anv_subpass
* subpass
;
2869 bool needs_data_cache
;
2871 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2873 uint32_t num_executables
;
2874 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
2877 const struct gen_l3_config
* l3_config
;
2878 uint32_t total_size
;
2881 VkShaderStageFlags active_stages
;
2882 struct anv_state blend_state
;
2885 struct anv_pipeline_vertex_binding
{
2888 uint32_t instance_divisor
;
2893 bool primitive_restart
;
2896 uint32_t cs_right_mask
;
2899 bool depth_test_enable
;
2900 bool writes_stencil
;
2901 bool stencil_test_enable
;
2902 bool depth_clamp_enable
;
2903 bool depth_clip_enable
;
2904 bool sample_shading_enable
;
2906 bool depth_bounds_test_enable
;
2910 uint32_t depth_stencil_state
[3];
2916 uint32_t wm_depth_stencil
[3];
2920 uint32_t wm_depth_stencil
[4];
2923 uint32_t interface_descriptor_data
[8];
2927 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2928 gl_shader_stage stage
)
2930 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2933 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2934 static inline const struct brw_##prefix##_prog_data * \
2935 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2937 if (anv_pipeline_has_stage(pipeline, stage)) { \
2938 return (const struct brw_##prefix##_prog_data *) \
2939 pipeline->shaders[stage]->prog_data; \
2945 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2946 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2947 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2948 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2949 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2950 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2952 static inline const struct brw_vue_prog_data
*
2953 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2955 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2956 return &get_gs_prog_data(pipeline
)->base
;
2957 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2958 return &get_tes_prog_data(pipeline
)->base
;
2960 return &get_vs_prog_data(pipeline
)->base
;
2964 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2965 struct anv_pipeline_cache
*cache
,
2966 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2967 const VkAllocationCallbacks
*alloc
);
2970 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2971 struct anv_pipeline_cache
*cache
,
2972 const VkComputePipelineCreateInfo
*info
,
2973 const struct anv_shader_module
*module
,
2974 const char *entrypoint
,
2975 const VkSpecializationInfo
*spec_info
);
2977 struct anv_format_plane
{
2978 enum isl_format isl_format
:16;
2979 struct isl_swizzle swizzle
;
2981 /* Whether this plane contains chroma channels */
2984 /* For downscaling of YUV planes */
2985 uint8_t denominator_scales
[2];
2987 /* How to map sampled ycbcr planes to a single 4 component element. */
2988 struct isl_swizzle ycbcr_swizzle
;
2990 /* What aspect is associated to this plane */
2991 VkImageAspectFlags aspect
;
2996 struct anv_format_plane planes
[3];
3002 static inline uint32_t
3003 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3004 VkImageAspectFlags aspect_mask
)
3006 switch (aspect_mask
) {
3007 case VK_IMAGE_ASPECT_COLOR_BIT
:
3008 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3009 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3011 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3012 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3015 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3017 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3020 /* Purposefully assert with depth/stencil aspects. */
3021 unreachable("invalid image aspect");
3025 static inline VkImageAspectFlags
3026 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3029 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3030 if (util_bitcount(image_aspects
) > 1)
3031 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3032 return VK_IMAGE_ASPECT_COLOR_BIT
;
3034 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3035 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3036 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3037 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3040 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3041 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3043 const struct anv_format
*
3044 anv_get_format(VkFormat format
);
3046 static inline uint32_t
3047 anv_get_format_planes(VkFormat vk_format
)
3049 const struct anv_format
*format
= anv_get_format(vk_format
);
3051 return format
!= NULL
? format
->n_planes
: 0;
3054 struct anv_format_plane
3055 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3056 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3058 static inline enum isl_format
3059 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3060 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3062 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3065 static inline struct isl_swizzle
3066 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3068 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3069 * RGB as RGBA for texturing
3071 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3072 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3074 /* But it doesn't matter what we render to that channel */
3075 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3081 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3084 * Subsurface of an anv_image.
3086 struct anv_surface
{
3087 /** Valid only if isl_surf::size_B > 0. */
3088 struct isl_surf isl
;
3091 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3097 VkImageType type
; /**< VkImageCreateInfo::imageType */
3098 /* The original VkFormat provided by the client. This may not match any
3099 * of the actual surface formats.
3102 const struct anv_format
*format
;
3104 VkImageAspectFlags aspects
;
3107 uint32_t array_size
;
3108 uint32_t samples
; /**< VkImageCreateInfo::samples */
3110 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3111 VkImageUsageFlags stencil_usage
;
3112 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3113 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3115 /** True if this is needs to be bound to an appropriately tiled BO.
3117 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3118 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3119 * we require a dedicated allocation so that we can know to allocate a
3122 bool needs_set_tiling
;
3125 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3126 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3128 uint64_t drm_format_mod
;
3133 /* Whether the image is made of several underlying buffer objects rather a
3134 * single one with different offsets.
3138 /* All the formats that can be used when creating views of this image
3139 * are CCS_E compatible.
3141 bool ccs_e_compatible
;
3143 /* Image was created with external format. */
3144 bool external_format
;
3149 * For each foo, anv_image::planes[x].surface is valid if and only if
3150 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3151 * to figure the number associated with a given aspect.
3153 * The hardware requires that the depth buffer and stencil buffer be
3154 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3155 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3156 * allocate the depth and stencil buffers as separate surfaces in the same
3161 * -----------------------
3163 * ----------------------- |
3164 * | shadow surface0 | |
3165 * ----------------------- | Plane 0
3166 * | aux surface0 | |
3167 * ----------------------- |
3168 * | fast clear colors0 | \|/
3169 * -----------------------
3171 * ----------------------- |
3172 * | shadow surface1 | |
3173 * ----------------------- | Plane 1
3174 * | aux surface1 | |
3175 * ----------------------- |
3176 * | fast clear colors1 | \|/
3177 * -----------------------
3180 * -----------------------
3184 * Offset of the entire plane (whenever the image is disjoint this is
3192 struct anv_surface surface
;
3195 * A surface which shadows the main surface and may have different
3196 * tiling. This is used for sampling using a tiling that isn't supported
3197 * for other operations.
3199 struct anv_surface shadow_surface
;
3202 * For color images, this is the aux usage for this image when not used
3203 * as a color attachment.
3205 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3206 * image has a HiZ buffer.
3208 enum isl_aux_usage aux_usage
;
3210 struct anv_surface aux_surface
;
3213 * Offset of the fast clear state (used to compute the
3214 * fast_clear_state_offset of the following planes).
3216 uint32_t fast_clear_state_offset
;
3219 * BO associated with this plane, set when bound.
3221 struct anv_address address
;
3224 * Address of the main surface used to fill the aux map table. This is
3225 * used at destruction of the image since the Vulkan spec does not
3226 * guarantee that the address.bo field we still be valid at destruction.
3228 uint64_t aux_map_surface_address
;
3231 * When destroying the image, also free the bo.
3237 /* The ordering of this enum is important */
3238 enum anv_fast_clear_type
{
3239 /** Image does not have/support any fast-clear blocks */
3240 ANV_FAST_CLEAR_NONE
= 0,
3241 /** Image has/supports fast-clear but only to the default value */
3242 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3243 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3244 ANV_FAST_CLEAR_ANY
= 2,
3247 /* Returns the number of auxiliary buffer levels attached to an image. */
3248 static inline uint8_t
3249 anv_image_aux_levels(const struct anv_image
* const image
,
3250 VkImageAspectFlagBits aspect
)
3252 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3254 /* The Gen12 CCS aux surface is represented with only one level. */
3255 const uint8_t aux_logical_levels
=
3256 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3257 image
->planes
[plane
].surface
.isl
.levels
:
3258 image
->planes
[plane
].aux_surface
.isl
.levels
;
3260 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3261 aux_logical_levels
: 0;
3264 /* Returns the number of auxiliary buffer layers attached to an image. */
3265 static inline uint32_t
3266 anv_image_aux_layers(const struct anv_image
* const image
,
3267 VkImageAspectFlagBits aspect
,
3268 const uint8_t miplevel
)
3272 /* The miplevel must exist in the main buffer. */
3273 assert(miplevel
< image
->levels
);
3275 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3276 /* There are no layers with auxiliary data because the miplevel has no
3281 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3283 /* The Gen12 CCS aux surface is represented with only one layer. */
3284 const struct isl_extent4d
*aux_logical_level0_px
=
3285 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3286 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3287 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3289 return MAX2(aux_logical_level0_px
->array_len
,
3290 aux_logical_level0_px
->depth
>> miplevel
);
3294 static inline struct anv_address
3295 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3296 const struct anv_image
*image
,
3297 VkImageAspectFlagBits aspect
)
3299 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3301 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3302 return anv_address_add(image
->planes
[plane
].address
,
3303 image
->planes
[plane
].fast_clear_state_offset
);
3306 static inline struct anv_address
3307 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3308 const struct anv_image
*image
,
3309 VkImageAspectFlagBits aspect
)
3311 struct anv_address addr
=
3312 anv_image_get_clear_color_addr(device
, image
, aspect
);
3314 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3315 device
->isl_dev
.ss
.clear_color_state_size
:
3316 device
->isl_dev
.ss
.clear_value_size
;
3317 return anv_address_add(addr
, clear_color_state_size
);
3320 static inline struct anv_address
3321 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3322 const struct anv_image
*image
,
3323 VkImageAspectFlagBits aspect
,
3324 uint32_t level
, uint32_t array_layer
)
3326 assert(level
< anv_image_aux_levels(image
, aspect
));
3327 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3328 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3329 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3331 struct anv_address addr
=
3332 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3333 addr
.offset
+= 4; /* Go past the fast clear type */
3335 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3336 for (uint32_t l
= 0; l
< level
; l
++)
3337 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3339 addr
.offset
+= level
* image
->array_size
* 4;
3341 addr
.offset
+= array_layer
* 4;
3343 assert(addr
.offset
<
3344 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3348 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3350 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3351 const struct anv_image
*image
)
3353 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3356 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3357 * struct. There's documentation which suggests that this feature actually
3358 * reduces performance on BDW, but it has only been observed to help so
3359 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3360 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3362 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3365 return image
->samples
== 1;
3369 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3370 const struct anv_image
*image
,
3373 return device
->info
.has_aux_map
&&
3374 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3378 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3379 const struct anv_image
*image
,
3380 VkImageAspectFlagBits aspect
,
3381 enum isl_aux_usage aux_usage
,
3383 uint32_t base_layer
,
3384 uint32_t layer_count
);
3387 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3388 const struct anv_image
*image
,
3389 VkImageAspectFlagBits aspect
,
3390 enum isl_aux_usage aux_usage
,
3391 enum isl_format format
, struct isl_swizzle swizzle
,
3392 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3393 VkRect2D area
, union isl_color_value clear_color
);
3395 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3396 const struct anv_image
*image
,
3397 VkImageAspectFlags aspects
,
3398 enum isl_aux_usage depth_aux_usage
,
3400 uint32_t base_layer
, uint32_t layer_count
,
3402 float depth_value
, uint8_t stencil_value
);
3404 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3405 const struct anv_image
*src_image
,
3406 enum isl_aux_usage src_aux_usage
,
3407 uint32_t src_level
, uint32_t src_base_layer
,
3408 const struct anv_image
*dst_image
,
3409 enum isl_aux_usage dst_aux_usage
,
3410 uint32_t dst_level
, uint32_t dst_base_layer
,
3411 VkImageAspectFlagBits aspect
,
3412 uint32_t src_x
, uint32_t src_y
,
3413 uint32_t dst_x
, uint32_t dst_y
,
3414 uint32_t width
, uint32_t height
,
3415 uint32_t layer_count
,
3416 enum blorp_filter filter
);
3418 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3419 const struct anv_image
*image
,
3420 VkImageAspectFlagBits aspect
, uint32_t level
,
3421 uint32_t base_layer
, uint32_t layer_count
,
3422 enum isl_aux_op hiz_op
);
3424 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3425 const struct anv_image
*image
,
3426 VkImageAspectFlags aspects
,
3428 uint32_t base_layer
, uint32_t layer_count
,
3429 VkRect2D area
, uint8_t stencil_value
);
3431 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3432 const struct anv_image
*image
,
3433 enum isl_format format
,
3434 VkImageAspectFlagBits aspect
,
3435 uint32_t base_layer
, uint32_t layer_count
,
3436 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3439 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3440 const struct anv_image
*image
,
3441 enum isl_format format
,
3442 VkImageAspectFlagBits aspect
, uint32_t level
,
3443 uint32_t base_layer
, uint32_t layer_count
,
3444 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3448 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3449 const struct anv_image
*image
,
3450 VkImageAspectFlagBits aspect
,
3451 uint32_t base_level
, uint32_t level_count
,
3452 uint32_t base_layer
, uint32_t layer_count
);
3455 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3456 const struct anv_image
*image
,
3457 const VkImageAspectFlagBits aspect
,
3458 const VkImageLayout layout
);
3460 enum anv_fast_clear_type
3461 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3462 const struct anv_image
* const image
,
3463 const VkImageAspectFlagBits aspect
,
3464 const VkImageLayout layout
);
3466 /* This is defined as a macro so that it works for both
3467 * VkImageSubresourceRange and VkImageSubresourceLayers
3469 #define anv_get_layerCount(_image, _range) \
3470 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3471 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3473 static inline uint32_t
3474 anv_get_levelCount(const struct anv_image
*image
,
3475 const VkImageSubresourceRange
*range
)
3477 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3478 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3481 static inline VkImageAspectFlags
3482 anv_image_expand_aspects(const struct anv_image
*image
,
3483 VkImageAspectFlags aspects
)
3485 /* If the underlying image has color plane aspects and
3486 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3487 * the underlying image. */
3488 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3489 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3490 return image
->aspects
;
3496 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3497 VkImageAspectFlags aspects2
)
3499 if (aspects1
== aspects2
)
3502 /* Only 1 color aspects are compatibles. */
3503 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3504 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3505 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3511 struct anv_image_view
{
3512 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3514 VkImageAspectFlags aspect_mask
;
3516 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3520 uint32_t image_plane
;
3522 struct isl_view isl
;
3525 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3526 * image layout of SHADER_READ_ONLY_OPTIMAL or
3527 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3529 struct anv_surface_state optimal_sampler_surface_state
;
3532 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3533 * image layout of GENERAL.
3535 struct anv_surface_state general_sampler_surface_state
;
3538 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3539 * states for write-only and readable, using the real format for
3540 * write-only and the lowered format for readable.
3542 struct anv_surface_state storage_surface_state
;
3543 struct anv_surface_state writeonly_storage_surface_state
;
3545 struct brw_image_param storage_image_param
;
3549 enum anv_image_view_state_flags
{
3550 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3551 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3554 void anv_image_fill_surface_state(struct anv_device
*device
,
3555 const struct anv_image
*image
,
3556 VkImageAspectFlagBits aspect
,
3557 const struct isl_view
*view
,
3558 isl_surf_usage_flags_t view_usage
,
3559 enum isl_aux_usage aux_usage
,
3560 const union isl_color_value
*clear_color
,
3561 enum anv_image_view_state_flags flags
,
3562 struct anv_surface_state
*state_inout
,
3563 struct brw_image_param
*image_param_out
);
3565 struct anv_image_create_info
{
3566 const VkImageCreateInfo
*vk_info
;
3568 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3569 isl_tiling_flags_t isl_tiling_flags
;
3571 /** These flags will be added to any derived from VkImageCreateInfo. */
3572 isl_surf_usage_flags_t isl_extra_usage_flags
;
3575 bool external_format
;
3578 VkResult
anv_image_create(VkDevice _device
,
3579 const struct anv_image_create_info
*info
,
3580 const VkAllocationCallbacks
* alloc
,
3583 const struct anv_surface
*
3584 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3585 VkImageAspectFlags aspect_mask
);
3588 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3590 static inline struct VkExtent3D
3591 anv_sanitize_image_extent(const VkImageType imageType
,
3592 const struct VkExtent3D imageExtent
)
3594 switch (imageType
) {
3595 case VK_IMAGE_TYPE_1D
:
3596 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3597 case VK_IMAGE_TYPE_2D
:
3598 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3599 case VK_IMAGE_TYPE_3D
:
3602 unreachable("invalid image type");
3606 static inline struct VkOffset3D
3607 anv_sanitize_image_offset(const VkImageType imageType
,
3608 const struct VkOffset3D imageOffset
)
3610 switch (imageType
) {
3611 case VK_IMAGE_TYPE_1D
:
3612 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3613 case VK_IMAGE_TYPE_2D
:
3614 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3615 case VK_IMAGE_TYPE_3D
:
3618 unreachable("invalid image type");
3622 VkFormatFeatureFlags
3623 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3625 const struct anv_format
*anv_format
,
3626 VkImageTiling vk_tiling
);
3628 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3629 struct anv_state state
,
3630 enum isl_format format
,
3631 struct anv_address address
,
3632 uint32_t range
, uint32_t stride
);
3635 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3636 const struct anv_attachment_state
*att_state
,
3637 const struct anv_image_view
*iview
)
3639 const struct isl_format_layout
*view_fmtl
=
3640 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3642 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3643 if (view_fmtl->channels.c.bits) \
3644 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3646 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3647 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3648 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3649 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3651 #undef COPY_CLEAR_COLOR_CHANNEL
3655 struct anv_ycbcr_conversion
{
3656 const struct anv_format
* format
;
3657 VkSamplerYcbcrModelConversion ycbcr_model
;
3658 VkSamplerYcbcrRange ycbcr_range
;
3659 VkComponentSwizzle mapping
[4];
3660 VkChromaLocation chroma_offsets
[2];
3661 VkFilter chroma_filter
;
3662 bool chroma_reconstruction
;
3665 struct anv_sampler
{
3666 uint32_t state
[3][4];
3668 struct anv_ycbcr_conversion
*conversion
;
3670 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3671 * and with a 32-byte stride for use as bindless samplers.
3673 struct anv_state bindless_state
;
3676 struct anv_framebuffer
{
3681 uint32_t attachment_count
;
3682 struct anv_image_view
* attachments
[0];
3685 struct anv_subpass_attachment
{
3686 VkImageUsageFlagBits usage
;
3687 uint32_t attachment
;
3688 VkImageLayout layout
;
3691 struct anv_subpass
{
3692 uint32_t attachment_count
;
3695 * A pointer to all attachment references used in this subpass.
3696 * Only valid if ::attachment_count > 0.
3698 struct anv_subpass_attachment
* attachments
;
3699 uint32_t input_count
;
3700 struct anv_subpass_attachment
* input_attachments
;
3701 uint32_t color_count
;
3702 struct anv_subpass_attachment
* color_attachments
;
3703 struct anv_subpass_attachment
* resolve_attachments
;
3705 struct anv_subpass_attachment
* depth_stencil_attachment
;
3706 struct anv_subpass_attachment
* ds_resolve_attachment
;
3707 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3708 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3712 /** Subpass has a depth/stencil self-dependency */
3713 bool has_ds_self_dep
;
3715 /** Subpass has at least one color resolve attachment */
3716 bool has_color_resolve
;
3719 static inline unsigned
3720 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3722 return MAX2(1, util_bitcount(subpass
->view_mask
));
3725 struct anv_render_pass_attachment
{
3726 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3727 * its members individually.
3731 VkImageUsageFlags usage
;
3732 VkAttachmentLoadOp load_op
;
3733 VkAttachmentStoreOp store_op
;
3734 VkAttachmentLoadOp stencil_load_op
;
3735 VkImageLayout initial_layout
;
3736 VkImageLayout final_layout
;
3737 VkImageLayout first_subpass_layout
;
3739 /* The subpass id in which the attachment will be used last. */
3740 uint32_t last_subpass_idx
;
3743 struct anv_render_pass
{
3744 uint32_t attachment_count
;
3745 uint32_t subpass_count
;
3746 /* An array of subpass_count+1 flushes, one per subpass boundary */
3747 enum anv_pipe_bits
* subpass_flushes
;
3748 struct anv_render_pass_attachment
* attachments
;
3749 struct anv_subpass subpasses
[0];
3752 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3754 struct anv_query_pool
{
3756 VkQueryPipelineStatisticFlags pipeline_statistics
;
3757 /** Stride between slots, in bytes */
3759 /** Number of slots in this query pool */
3764 int anv_get_instance_entrypoint_index(const char *name
);
3765 int anv_get_device_entrypoint_index(const char *name
);
3766 int anv_get_physical_device_entrypoint_index(const char *name
);
3768 const char *anv_get_instance_entry_name(int index
);
3769 const char *anv_get_physical_device_entry_name(int index
);
3770 const char *anv_get_device_entry_name(int index
);
3773 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3774 const struct anv_instance_extension_table
*instance
);
3776 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3777 const struct anv_instance_extension_table
*instance
);
3779 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3780 const struct anv_instance_extension_table
*instance
,
3781 const struct anv_device_extension_table
*device
);
3783 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3786 void anv_dump_image_to_ppm(struct anv_device
*device
,
3787 struct anv_image
*image
, unsigned miplevel
,
3788 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3789 const char *filename
);
3791 enum anv_dump_action
{
3792 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3795 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3796 void anv_dump_finish(void);
3798 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
3800 static inline uint32_t
3801 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3803 /* This function must be called from within a subpass. */
3804 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3806 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3808 /* The id of this subpass shouldn't exceed the number of subpasses in this
3809 * render pass minus 1.
3811 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3815 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
3816 void anv_device_perf_init(struct anv_device
*device
);
3818 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3820 static inline struct __anv_type * \
3821 __anv_type ## _from_handle(__VkType _handle) \
3823 return (struct __anv_type *) _handle; \
3826 static inline __VkType \
3827 __anv_type ## _to_handle(struct __anv_type *_obj) \
3829 return (__VkType) _obj; \
3832 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3834 static inline struct __anv_type * \
3835 __anv_type ## _from_handle(__VkType _handle) \
3837 return (struct __anv_type *)(uintptr_t) _handle; \
3840 static inline __VkType \
3841 __anv_type ## _to_handle(struct __anv_type *_obj) \
3843 return (__VkType)(uintptr_t) _obj; \
3846 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3847 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3849 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3850 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3851 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3852 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3853 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3855 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3856 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3857 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3858 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3859 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3860 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3861 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
3862 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3863 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3864 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3865 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3866 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3867 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3868 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3869 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3870 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3871 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3872 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3873 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3874 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3875 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3876 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3877 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3879 /* Gen-specific function declarations */
3881 # include "anv_genX.h"
3883 # define genX(x) gen7_##x
3884 # include "anv_genX.h"
3886 # define genX(x) gen75_##x
3887 # include "anv_genX.h"
3889 # define genX(x) gen8_##x
3890 # include "anv_genX.h"
3892 # define genX(x) gen9_##x
3893 # include "anv_genX.h"
3895 # define genX(x) gen10_##x
3896 # include "anv_genX.h"
3898 # define genX(x) gen11_##x
3899 # include "anv_genX.h"
3901 # define genX(x) gen12_##x
3902 # include "anv_genX.h"
3906 #endif /* ANV_PRIVATE_H */