2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_clflush.h"
45 #include "common/gen_gem.h"
46 #include "dev/gen_device_info.h"
47 #include "blorp/blorp.h"
48 #include "compiler/brw_compiler.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/u_atomic.h"
52 #include "util/u_vector.h"
55 #include "vk_debug_report.h"
57 /* Pre-declarations needed for WSI entrypoints */
60 typedef struct xcb_connection_t xcb_connection_t
;
61 typedef uint32_t xcb_visualid_t
;
62 typedef uint32_t xcb_window_t
;
65 struct anv_buffer_view
;
66 struct anv_image_view
;
71 #include <vulkan/vulkan.h>
72 #include <vulkan/vulkan_intel.h>
73 #include <vulkan/vk_icd.h>
74 #include <vulkan/vk_android_native_buffer.h>
76 #include "anv_entrypoints.h"
77 #include "anv_extensions.h"
80 #include "common/gen_debug.h"
81 #include "common/intel_log.h"
82 #include "wsi_common.h"
84 /* anv Virtual Memory Layout
85 * =========================
87 * When the anv driver is determining the virtual graphics addresses of memory
88 * objects itself using the softpin mechanism, the following memory ranges
91 * Three special considerations to notice:
93 * (1) the dynamic state pool is located within the same 4 GiB as the low
94 * heap. This is to work around a VF cache issue described in a comment in
95 * anv_physical_device_init_heaps.
97 * (2) the binding table pool is located at lower addresses than the surface
98 * state pool, within a 4 GiB range. This allows surface state base addresses
99 * to cover both binding tables (16 bit offsets) and surface states (32 bit
102 * (3) the last 4 GiB of the address space is withheld from the high
103 * heap. Various hardware units will read past the end of an object for
104 * various reasons. This healthy margin prevents reads from wrapping around
107 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
108 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
109 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
110 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
111 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
112 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
113 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
114 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
115 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
116 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
117 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
118 #define HIGH_HEAP_MAX_ADDRESS 0xfffeffffffffULL
120 #define LOW_HEAP_SIZE \
121 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
122 #define HIGH_HEAP_SIZE \
123 (HIGH_HEAP_MAX_ADDRESS - HIGH_HEAP_MIN_ADDRESS + 1)
124 #define DYNAMIC_STATE_POOL_SIZE \
125 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
126 #define BINDING_TABLE_POOL_SIZE \
127 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
128 #define SURFACE_STATE_POOL_SIZE \
129 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
130 #define INSTRUCTION_STATE_POOL_SIZE \
131 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
133 /* Allowing different clear colors requires us to perform a depth resolve at
134 * the end of certain render passes. This is because while slow clears store
135 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
136 * See the PRMs for examples describing when additional resolves would be
137 * necessary. To enable fast clears without requiring extra resolves, we set
138 * the clear value to a globally-defined one. We could allow different values
139 * if the user doesn't expect coherent data during or after a render passes
140 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
141 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
142 * 1.0f seems to be the only value used. The only application that doesn't set
143 * this value does so through the usage of an seemingly uninitialized clear
146 #define ANV_HZ_FC_VAL 1.0f
151 #define MAX_VIEWPORTS 16
152 #define MAX_SCISSORS 16
153 #define MAX_PUSH_CONSTANTS_SIZE 128
154 #define MAX_DYNAMIC_BUFFERS 16
156 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
158 /* The kernel relocation API has a limitation of a 32-bit delta value
159 * applied to the address before it is written which, in spite of it being
160 * unsigned, is treated as signed . Because of the way that this maps to
161 * the Vulkan API, we cannot handle an offset into a buffer that does not
162 * fit into a signed 32 bits. The only mechanism we have for dealing with
163 * this at the moment is to limit all VkDeviceMemory objects to a maximum
164 * of 2GB each. The Vulkan spec allows us to do this:
166 * "Some platforms may have a limit on the maximum size of a single
167 * allocation. For example, certain systems may fail to create
168 * allocations with a size greater than or equal to 4GB. Such a limit is
169 * implementation-dependent, and if such a failure occurs then the error
170 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
172 * We don't use vk_error here because it's not an error so much as an
173 * indication to the application that the allocation is too large.
175 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
177 #define ANV_SVGS_VB_INDEX MAX_VBS
178 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
180 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
182 static inline uint32_t
183 align_down_npot_u32(uint32_t v
, uint32_t a
)
188 static inline uint32_t
189 align_u32(uint32_t v
, uint32_t a
)
191 assert(a
!= 0 && a
== (a
& -a
));
192 return (v
+ a
- 1) & ~(a
- 1);
195 static inline uint64_t
196 align_u64(uint64_t v
, uint64_t a
)
198 assert(a
!= 0 && a
== (a
& -a
));
199 return (v
+ a
- 1) & ~(a
- 1);
202 static inline int32_t
203 align_i32(int32_t v
, int32_t a
)
205 assert(a
!= 0 && a
== (a
& -a
));
206 return (v
+ a
- 1) & ~(a
- 1);
209 /** Alignment must be a power of 2. */
211 anv_is_aligned(uintmax_t n
, uintmax_t a
)
213 assert(a
== (a
& -a
));
214 return (n
& (a
- 1)) == 0;
217 static inline uint32_t
218 anv_minify(uint32_t n
, uint32_t levels
)
220 if (unlikely(n
== 0))
223 return MAX2(n
>> levels
, 1);
227 anv_clamp_f(float f
, float min
, float max
)
240 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
242 if (*inout_mask
& clear_mask
) {
243 *inout_mask
&= ~clear_mask
;
250 static inline union isl_color_value
251 vk_to_isl_color(VkClearColorValue color
)
253 return (union isl_color_value
) {
263 #define for_each_bit(b, dword) \
264 for (uint32_t __dword = (dword); \
265 (b) = __builtin_ffs(__dword) - 1, __dword; \
266 __dword &= ~(1 << (b)))
268 #define typed_memcpy(dest, src, count) ({ \
269 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
270 memcpy((dest), (src), (count) * sizeof(*(src))); \
273 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
274 * to be added here in order to utilize mapping in debug/error/perf macros.
276 #define REPORT_OBJECT_TYPE(o) \
277 __builtin_choose_expr ( \
278 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
279 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
280 __builtin_choose_expr ( \
281 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
282 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
283 __builtin_choose_expr ( \
284 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
285 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
286 __builtin_choose_expr ( \
287 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
288 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
289 __builtin_choose_expr ( \
290 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
291 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
292 __builtin_choose_expr ( \
293 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
294 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
295 __builtin_choose_expr ( \
296 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
297 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
298 __builtin_choose_expr ( \
299 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
300 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
301 __builtin_choose_expr ( \
302 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
303 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
304 __builtin_choose_expr ( \
305 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
306 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
307 __builtin_choose_expr ( \
308 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
309 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
310 __builtin_choose_expr ( \
311 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
312 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
313 __builtin_choose_expr ( \
314 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
315 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
316 __builtin_choose_expr ( \
317 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
318 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
319 __builtin_choose_expr ( \
320 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
321 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
322 __builtin_choose_expr ( \
323 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
324 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
325 __builtin_choose_expr ( \
326 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
327 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
328 __builtin_choose_expr ( \
329 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
330 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
331 __builtin_choose_expr ( \
332 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
333 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
334 __builtin_choose_expr ( \
335 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
336 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
337 __builtin_choose_expr ( \
338 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
339 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
340 __builtin_choose_expr ( \
341 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
342 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
343 __builtin_choose_expr ( \
344 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
345 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
346 __builtin_choose_expr ( \
347 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
348 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
349 __builtin_choose_expr ( \
350 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
351 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
352 __builtin_choose_expr ( \
353 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
354 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
355 __builtin_choose_expr ( \
356 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
357 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
358 __builtin_choose_expr ( \
359 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
360 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
361 __builtin_choose_expr ( \
362 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
363 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
364 __builtin_choose_expr ( \
365 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
366 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
367 __builtin_choose_expr ( \
368 __builtin_types_compatible_p (__typeof (o), void*), \
369 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
370 /* The void expression results in a compile-time error \
371 when assigning the result to something. */ \
372 (void)0)))))))))))))))))))))))))))))))
374 /* Whenever we generate an error, pass it through this function. Useful for
375 * debugging, where we can break on it. Only call at error site, not when
376 * propagating errors. Might be useful to plug in a stack trace here.
379 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
380 VkDebugReportObjectTypeEXT type
, VkResult error
,
381 const char *file
, int line
, const char *format
, ...);
384 #define vk_error(error) __vk_errorf(NULL, NULL,\
385 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
386 error, __FILE__, __LINE__, NULL)
387 #define vk_errorf(instance, obj, error, format, ...)\
388 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
389 __FILE__, __LINE__, format, ## __VA_ARGS__)
391 #define vk_error(error) error
392 #define vk_errorf(instance, obj, error, format, ...) error
396 * Warn on ignored extension structs.
398 * The Vulkan spec requires us to ignore unsupported or unknown structs in
399 * a pNext chain. In debug mode, emitting warnings for ignored structs may
400 * help us discover structs that we should not have ignored.
403 * From the Vulkan 1.0.38 spec:
405 * Any component of the implementation (the loader, any enabled layers,
406 * and drivers) must skip over, without processing (other than reading the
407 * sType and pNext members) any chained structures with sType values not
408 * defined by extensions supported by that component.
410 #define anv_debug_ignored_stype(sType) \
411 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
413 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
414 VkDebugReportObjectTypeEXT type
, const char *file
,
415 int line
, const char *format
, ...)
416 anv_printflike(6, 7);
417 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
418 void anv_loge_v(const char *format
, va_list va
);
421 * Print a FINISHME message, including its source location.
423 #define anv_finishme(format, ...) \
425 static bool reported = false; \
427 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
434 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
436 #define anv_perf_warn(instance, obj, format, ...) \
438 static bool reported = false; \
439 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
440 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
441 format, ##__VA_ARGS__); \
446 /* A non-fatal assert. Useful for debugging. */
448 #define anv_assert(x) ({ \
449 if (unlikely(!(x))) \
450 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
453 #define anv_assert(x)
456 /* A multi-pointer allocator
458 * When copying data structures from the user (such as a render pass), it's
459 * common to need to allocate data for a bunch of different things. Instead
460 * of doing several allocations and having to handle all of the error checking
461 * that entails, it can be easier to do a single allocation. This struct
462 * helps facilitate that. The intended usage looks like this:
465 * anv_multialloc_add(&ma, &main_ptr, 1);
466 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
467 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
469 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
470 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
472 struct anv_multialloc
{
480 #define ANV_MULTIALLOC_INIT \
481 ((struct anv_multialloc) { 0, })
483 #define ANV_MULTIALLOC(_name) \
484 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
486 __attribute__((always_inline
))
488 _anv_multialloc_add(struct anv_multialloc
*ma
,
489 void **ptr
, size_t size
, size_t align
)
491 size_t offset
= align_u64(ma
->size
, align
);
492 ma
->size
= offset
+ size
;
493 ma
->align
= MAX2(ma
->align
, align
);
495 /* Store the offset in the pointer. */
496 *ptr
= (void *)(uintptr_t)offset
;
498 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
499 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
502 #define anv_multialloc_add_size(_ma, _ptr, _size) \
503 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
505 #define anv_multialloc_add(_ma, _ptr, _count) \
506 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
508 __attribute__((always_inline
))
510 anv_multialloc_alloc(struct anv_multialloc
*ma
,
511 const VkAllocationCallbacks
*alloc
,
512 VkSystemAllocationScope scope
)
514 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
518 /* Fill out each of the pointers with their final value.
520 * for (uint32_t i = 0; i < ma->ptr_count; i++)
521 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
523 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
524 * constant, GCC is incapable of figuring this out and unrolling the loop
525 * so we have to give it a little help.
527 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
528 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
529 if ((_i) < ma->ptr_count) \
530 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
531 _ANV_MULTIALLOC_UPDATE_POINTER(0);
532 _ANV_MULTIALLOC_UPDATE_POINTER(1);
533 _ANV_MULTIALLOC_UPDATE_POINTER(2);
534 _ANV_MULTIALLOC_UPDATE_POINTER(3);
535 _ANV_MULTIALLOC_UPDATE_POINTER(4);
536 _ANV_MULTIALLOC_UPDATE_POINTER(5);
537 _ANV_MULTIALLOC_UPDATE_POINTER(6);
538 _ANV_MULTIALLOC_UPDATE_POINTER(7);
539 #undef _ANV_MULTIALLOC_UPDATE_POINTER
544 __attribute__((always_inline
))
546 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
547 const VkAllocationCallbacks
*parent_alloc
,
548 const VkAllocationCallbacks
*alloc
,
549 VkSystemAllocationScope scope
)
551 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
557 /* Index into the current validation list. This is used by the
558 * validation list building alrogithm to track which buffers are already
559 * in the validation list so that we can ensure uniqueness.
563 /* Last known offset. This value is provided by the kernel when we
564 * execbuf and is used as the presumed offset for the next bunch of
572 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
577 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
579 bo
->gem_handle
= gem_handle
;
587 /* Represents a lock-free linked list of "free" things. This is used by
588 * both the block pool and the state pools. Unfortunately, in order to
589 * solve the ABA problem, we can't use a single uint32_t head.
591 union anv_free_list
{
595 /* A simple count that is incremented every time the head changes. */
601 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
603 struct anv_block_state
{
613 struct anv_block_pool
{
614 struct anv_device
*device
;
620 /* The address where the start of the pool is pinned. The various bos that
621 * are created as the pool grows will have addresses in the range
622 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
624 uint64_t start_address
;
626 /* The offset from the start of the bo to the "center" of the block
627 * pool. Pointers to allocated blocks are given by
628 * bo.map + center_bo_offset + offsets.
630 uint32_t center_bo_offset
;
632 /* Current memory map of the block pool. This pointer may or may not
633 * point to the actual beginning of the block pool memory. If
634 * anv_block_pool_alloc_back has ever been called, then this pointer
635 * will point to the "center" position of the buffer and all offsets
636 * (negative or positive) given out by the block pool alloc functions
637 * will be valid relative to this pointer.
639 * In particular, map == bo.map + center_offset
645 * Array of mmaps and gem handles owned by the block pool, reclaimed when
646 * the block pool is destroyed.
648 struct u_vector mmap_cleanups
;
650 struct anv_block_state state
;
652 struct anv_block_state back_state
;
655 /* Block pools are backed by a fixed-size 1GB memfd */
656 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
658 /* The center of the block pool is also the middle of the memfd. This may
659 * change in the future if we decide differently for some reason.
661 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
663 static inline uint32_t
664 anv_block_pool_size(struct anv_block_pool
*pool
)
666 return pool
->state
.end
+ pool
->back_state
.end
;
675 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
677 struct anv_fixed_size_state_pool
{
678 union anv_free_list free_list
;
679 struct anv_block_state block
;
682 #define ANV_MIN_STATE_SIZE_LOG2 6
683 #define ANV_MAX_STATE_SIZE_LOG2 20
685 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
687 struct anv_state_pool
{
688 struct anv_block_pool block_pool
;
690 /* The size of blocks which will be allocated from the block pool */
693 /** Free list for "back" allocations */
694 union anv_free_list back_alloc_free_list
;
696 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
699 struct anv_state_stream_block
;
701 struct anv_state_stream
{
702 struct anv_state_pool
*state_pool
;
704 /* The size of blocks to allocate from the state pool */
707 /* Current block we're allocating from */
708 struct anv_state block
;
710 /* Offset into the current block at which to allocate the next state */
713 /* List of all blocks allocated from this pool */
714 struct anv_state_stream_block
*block_list
;
717 /* The block_pool functions exported for testing only. The block pool should
718 * only be used via a state pool (see below).
720 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
721 struct anv_device
*device
,
722 uint64_t start_address
,
723 uint32_t initial_size
,
725 void anv_block_pool_finish(struct anv_block_pool
*pool
);
726 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
727 uint32_t block_size
);
728 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
729 uint32_t block_size
);
731 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
732 struct anv_device
*device
,
733 uint64_t start_address
,
736 void anv_state_pool_finish(struct anv_state_pool
*pool
);
737 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
738 uint32_t state_size
, uint32_t alignment
);
739 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
740 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
741 void anv_state_stream_init(struct anv_state_stream
*stream
,
742 struct anv_state_pool
*state_pool
,
743 uint32_t block_size
);
744 void anv_state_stream_finish(struct anv_state_stream
*stream
);
745 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
746 uint32_t size
, uint32_t alignment
);
749 * Implements a pool of re-usable BOs. The interface is identical to that
750 * of block_pool except that each block is its own BO.
753 struct anv_device
*device
;
760 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
762 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
763 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
765 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
767 struct anv_scratch_bo
{
772 struct anv_scratch_pool
{
773 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
774 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
777 void anv_scratch_pool_init(struct anv_device
*device
,
778 struct anv_scratch_pool
*pool
);
779 void anv_scratch_pool_finish(struct anv_device
*device
,
780 struct anv_scratch_pool
*pool
);
781 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
782 struct anv_scratch_pool
*pool
,
783 gl_shader_stage stage
,
784 unsigned per_thread_scratch
);
786 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
787 struct anv_bo_cache
{
788 struct hash_table
*bo_map
;
789 pthread_mutex_t mutex
;
792 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
793 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
794 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
795 struct anv_bo_cache
*cache
,
796 uint64_t size
, struct anv_bo
**bo
);
797 VkResult
anv_bo_cache_import(struct anv_device
*device
,
798 struct anv_bo_cache
*cache
,
799 int fd
, struct anv_bo
**bo
);
800 VkResult
anv_bo_cache_export(struct anv_device
*device
,
801 struct anv_bo_cache
*cache
,
802 struct anv_bo
*bo_in
, int *fd_out
);
803 void anv_bo_cache_release(struct anv_device
*device
,
804 struct anv_bo_cache
*cache
,
807 struct anv_memory_type
{
808 /* Standard bits passed on to the client */
809 VkMemoryPropertyFlags propertyFlags
;
812 /* Driver-internal book-keeping */
813 VkBufferUsageFlags valid_buffer_usage
;
816 struct anv_memory_heap
{
817 /* Standard bits passed on to the client */
819 VkMemoryHeapFlags flags
;
821 /* Driver-internal book-keeping */
822 bool supports_48bit_addresses
;
825 struct anv_physical_device
{
826 VK_LOADER_DATA _loader_data
;
828 struct anv_instance
* instance
;
833 struct gen_device_info info
;
834 /** Amount of "GPU memory" we want to advertise
836 * Clearly, this value is bogus since Intel is a UMA architecture. On
837 * gen7 platforms, we are limited by GTT size unless we want to implement
838 * fine-grained tracking and GTT splitting. On Broadwell and above we are
839 * practically unlimited. However, we will never report more than 3/4 of
840 * the total system ram to try and avoid running out of RAM.
842 bool supports_48bit_addresses
;
843 struct brw_compiler
* compiler
;
844 struct isl_device isl_dev
;
845 int cmd_parser_version
;
847 bool has_exec_capture
;
850 bool has_syncobj_wait
;
851 bool has_context_priority
;
854 struct anv_device_extension_table supported_extensions
;
857 uint32_t subslice_total
;
861 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
863 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
866 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
867 uint8_t driver_uuid
[VK_UUID_SIZE
];
868 uint8_t device_uuid
[VK_UUID_SIZE
];
870 struct wsi_device wsi_device
;
874 struct anv_instance
{
875 VK_LOADER_DATA _loader_data
;
877 VkAllocationCallbacks alloc
;
880 struct anv_instance_extension_table enabled_extensions
;
881 struct anv_dispatch_table dispatch
;
883 int physicalDeviceCount
;
884 struct anv_physical_device physicalDevice
;
886 struct vk_debug_report_instance debug_report_callbacks
;
889 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
890 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
892 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
893 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
897 VK_LOADER_DATA _loader_data
;
899 struct anv_device
* device
;
901 VkDeviceQueueCreateFlags flags
;
904 struct anv_pipeline_cache
{
905 struct anv_device
* device
;
906 pthread_mutex_t mutex
;
908 struct hash_table
* cache
;
911 struct anv_pipeline_bind_map
;
913 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
914 struct anv_device
*device
,
916 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
918 struct anv_shader_bin
*
919 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
920 const void *key
, uint32_t key_size
);
921 struct anv_shader_bin
*
922 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
923 const void *key_data
, uint32_t key_size
,
924 const void *kernel_data
, uint32_t kernel_size
,
925 const struct brw_stage_prog_data
*prog_data
,
926 uint32_t prog_data_size
,
927 const struct anv_pipeline_bind_map
*bind_map
);
930 VK_LOADER_DATA _loader_data
;
932 VkAllocationCallbacks alloc
;
934 struct anv_instance
* instance
;
937 struct gen_device_info info
;
938 struct isl_device isl_dev
;
941 bool can_chain_batches
;
942 bool robust_buffer_access
;
943 struct anv_device_extension_table enabled_extensions
;
944 struct anv_dispatch_table dispatch
;
946 pthread_mutex_t vma_mutex
;
947 struct util_vma_heap vma_lo
;
948 struct util_vma_heap vma_hi
;
949 uint64_t vma_lo_available
;
950 uint64_t vma_hi_available
;
952 struct anv_bo_pool batch_bo_pool
;
954 struct anv_bo_cache bo_cache
;
956 struct anv_state_pool dynamic_state_pool
;
957 struct anv_state_pool instruction_state_pool
;
958 struct anv_state_pool binding_table_pool
;
959 struct anv_state_pool surface_state_pool
;
961 struct anv_bo workaround_bo
;
962 struct anv_bo trivial_batch_bo
;
963 struct anv_bo hiz_clear_bo
;
965 struct anv_pipeline_cache blorp_shader_cache
;
966 struct blorp_context blorp
;
968 struct anv_state border_colors
;
970 struct anv_queue queue
;
972 struct anv_scratch_pool scratch_pool
;
974 uint32_t default_mocs
;
976 pthread_mutex_t mutex
;
977 pthread_cond_t queue_submit
;
981 static inline struct anv_state_pool
*
982 anv_binding_table_pool(struct anv_device
*device
)
984 if (device
->instance
->physicalDevice
.use_softpin
)
985 return &device
->binding_table_pool
;
987 return &device
->surface_state_pool
;
990 static inline struct anv_state
991 anv_binding_table_pool_alloc(struct anv_device
*device
) {
992 if (device
->instance
->physicalDevice
.use_softpin
)
993 return anv_state_pool_alloc(&device
->binding_table_pool
,
994 device
->binding_table_pool
.block_size
, 0);
996 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1000 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1001 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1005 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
1007 if (device
->info
.has_llc
)
1010 gen_flush_range(state
.map
, state
.alloc_size
);
1013 void anv_device_init_blorp(struct anv_device
*device
);
1014 void anv_device_finish_blorp(struct anv_device
*device
);
1016 VkResult
anv_device_execbuf(struct anv_device
*device
,
1017 struct drm_i915_gem_execbuffer2
*execbuf
,
1018 struct anv_bo
**execbuf_bos
);
1019 VkResult
anv_device_query_status(struct anv_device
*device
);
1020 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1021 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1024 void* anv_gem_mmap(struct anv_device
*device
,
1025 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1026 void anv_gem_munmap(void *p
, uint64_t size
);
1027 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1028 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1029 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1030 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1031 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1032 int anv_gem_execbuffer(struct anv_device
*device
,
1033 struct drm_i915_gem_execbuffer2
*execbuf
);
1034 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1035 uint32_t stride
, uint32_t tiling
);
1036 int anv_gem_create_context(struct anv_device
*device
);
1037 bool anv_gem_has_context_priority(int fd
);
1038 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1039 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1041 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1043 int anv_gem_get_param(int fd
, uint32_t param
);
1044 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1045 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1046 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1047 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1048 uint32_t *active
, uint32_t *pending
);
1049 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1050 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1051 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1052 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1053 uint32_t read_domains
, uint32_t write_domain
);
1054 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1055 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1056 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1057 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1058 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1059 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1061 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1062 uint32_t handle
, int fd
);
1063 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1064 bool anv_gem_supports_syncobj_wait(int fd
);
1065 int anv_gem_syncobj_wait(struct anv_device
*device
,
1066 uint32_t *handles
, uint32_t num_handles
,
1067 int64_t abs_timeout_ns
, bool wait_all
);
1069 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1070 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1072 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1074 struct anv_reloc_list
{
1075 uint32_t num_relocs
;
1076 uint32_t array_length
;
1077 struct drm_i915_gem_relocation_entry
* relocs
;
1078 struct anv_bo
** reloc_bos
;
1081 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1082 const VkAllocationCallbacks
*alloc
);
1083 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1084 const VkAllocationCallbacks
*alloc
);
1086 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1087 const VkAllocationCallbacks
*alloc
,
1088 uint32_t offset
, struct anv_bo
*target_bo
,
1091 struct anv_batch_bo
{
1092 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1093 struct list_head link
;
1097 /* Bytes actually consumed in this batch BO */
1100 struct anv_reloc_list relocs
;
1104 const VkAllocationCallbacks
* alloc
;
1110 struct anv_reloc_list
* relocs
;
1112 /* This callback is called (with the associated user data) in the event
1113 * that the batch runs out of space.
1115 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1119 * Current error status of the command buffer. Used to track inconsistent
1120 * or incomplete command buffer states that are the consequence of run-time
1121 * errors such as out of memory scenarios. We want to track this in the
1122 * batch because the command buffer object is not visible to some parts
1128 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1129 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1130 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1131 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1132 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1133 struct anv_batch
*batch
);
1135 static inline VkResult
1136 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1138 assert(error
!= VK_SUCCESS
);
1139 if (batch
->status
== VK_SUCCESS
)
1140 batch
->status
= error
;
1141 return batch
->status
;
1145 anv_batch_has_error(struct anv_batch
*batch
)
1147 return batch
->status
!= VK_SUCCESS
;
1150 struct anv_address
{
1155 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1158 anv_address_is_null(struct anv_address addr
)
1160 return addr
.bo
== NULL
&& addr
.offset
== 0;
1163 static inline uint64_t
1164 anv_address_physical(struct anv_address addr
)
1166 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1167 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1169 return gen_canonical_address(addr
.offset
);
1172 static inline struct anv_address
1173 anv_address_add(struct anv_address addr
, uint64_t offset
)
1175 addr
.offset
+= offset
;
1180 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1182 unsigned reloc_size
= 0;
1183 if (device
->info
.gen
>= 8) {
1184 reloc_size
= sizeof(uint64_t);
1185 *(uint64_t *)p
= gen_canonical_address(v
);
1187 reloc_size
= sizeof(uint32_t);
1191 if (flush
&& !device
->info
.has_llc
)
1192 gen_flush_range(p
, reloc_size
);
1195 static inline uint64_t
1196 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1197 const struct anv_address address
, uint32_t delta
)
1199 if (address
.bo
== NULL
) {
1200 return address
.offset
+ delta
;
1202 assert(batch
->start
<= location
&& location
< batch
->end
);
1204 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1208 #define __gen_address_type struct anv_address
1209 #define __gen_user_data struct anv_batch
1210 #define __gen_combine_address _anv_combine_address
1212 /* Wrapper macros needed to work around preprocessor argument issues. In
1213 * particular, arguments don't get pre-evaluated if they are concatenated.
1214 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1215 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1216 * We can work around this easily enough with these helpers.
1218 #define __anv_cmd_length(cmd) cmd ## _length
1219 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1220 #define __anv_cmd_header(cmd) cmd ## _header
1221 #define __anv_cmd_pack(cmd) cmd ## _pack
1222 #define __anv_reg_num(reg) reg ## _num
1224 #define anv_pack_struct(dst, struc, ...) do { \
1225 struct struc __template = { \
1228 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1229 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1232 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1233 void *__dst = anv_batch_emit_dwords(batch, n); \
1235 struct cmd __template = { \
1236 __anv_cmd_header(cmd), \
1237 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1240 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1245 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1249 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1250 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1253 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1254 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1255 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1258 #define anv_batch_emit(batch, cmd, name) \
1259 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1260 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1261 __builtin_expect(_dst != NULL, 1); \
1262 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1263 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1267 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1268 .GraphicsDataTypeGFDT = 0, \
1269 .LLCCacheabilityControlLLCCC = 0, \
1270 .L3CacheabilityControlL3CC = 1, \
1273 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1274 .LLCeLLCCacheabilityControlLLCCC = 0, \
1275 .L3CacheabilityControlL3CC = 1, \
1278 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1279 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1280 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1281 .AgeforQUADLRU = 0 \
1284 /* Skylake: MOCS is now an index into an array of 62 different caching
1285 * configurations programmed by the kernel.
1288 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1289 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1290 .IndextoMOCSTables = 2 \
1293 #define GEN9_MOCS_PTE { \
1294 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1295 .IndextoMOCSTables = 1 \
1298 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1299 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1300 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1301 .IndextoMOCSTables = 2 \
1304 #define GEN10_MOCS_PTE { \
1305 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1306 .IndextoMOCSTables = 1 \
1309 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1310 #define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1311 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1312 .IndextoMOCSTables = 2 \
1315 #define GEN11_MOCS_PTE { \
1316 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1317 .IndextoMOCSTables = 1 \
1320 struct anv_device_memory
{
1322 struct anv_memory_type
* type
;
1323 VkDeviceSize map_size
;
1328 * Header for Vertex URB Entry (VUE)
1330 struct anv_vue_header
{
1332 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1333 uint32_t ViewportIndex
;
1337 struct anv_descriptor_set_binding_layout
{
1339 /* The type of the descriptors in this binding */
1340 VkDescriptorType type
;
1343 /* Number of array elements in this binding */
1344 uint16_t array_size
;
1346 /* Index into the flattend descriptor set */
1347 uint16_t descriptor_index
;
1349 /* Index into the dynamic state array for a dynamic buffer */
1350 int16_t dynamic_offset_index
;
1352 /* Index into the descriptor set buffer views */
1353 int16_t buffer_index
;
1356 /* Index into the binding table for the associated surface */
1357 int16_t surface_index
;
1359 /* Index into the sampler table for the associated sampler */
1360 int16_t sampler_index
;
1362 /* Index into the image table for the associated image */
1363 int16_t image_index
;
1364 } stage
[MESA_SHADER_STAGES
];
1366 /* Immutable samplers (or NULL if no immutable samplers) */
1367 struct anv_sampler
**immutable_samplers
;
1370 struct anv_descriptor_set_layout
{
1371 /* Descriptor set layouts can be destroyed at almost any time */
1374 /* Number of bindings in this descriptor set */
1375 uint16_t binding_count
;
1377 /* Total size of the descriptor set with room for all array entries */
1380 /* Shader stages affected by this descriptor set */
1381 uint16_t shader_stages
;
1383 /* Number of buffers in this descriptor set */
1384 uint16_t buffer_count
;
1386 /* Number of dynamic offsets used by this descriptor set */
1387 uint16_t dynamic_offset_count
;
1389 /* Bindings in this descriptor set */
1390 struct anv_descriptor_set_binding_layout binding
[0];
1394 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1396 assert(layout
&& layout
->ref_cnt
>= 1);
1397 p_atomic_inc(&layout
->ref_cnt
);
1401 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1402 struct anv_descriptor_set_layout
*layout
)
1404 assert(layout
&& layout
->ref_cnt
>= 1);
1405 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1406 vk_free(&device
->alloc
, layout
);
1409 struct anv_descriptor
{
1410 VkDescriptorType type
;
1414 VkImageLayout layout
;
1415 struct anv_image_view
*image_view
;
1416 struct anv_sampler
*sampler
;
1420 struct anv_buffer
*buffer
;
1425 struct anv_buffer_view
*buffer_view
;
1429 struct anv_descriptor_set
{
1430 struct anv_descriptor_set_layout
*layout
;
1432 uint32_t buffer_count
;
1433 struct anv_buffer_view
*buffer_views
;
1434 struct anv_descriptor descriptors
[0];
1437 struct anv_buffer_view
{
1438 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1439 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1441 struct anv_address address
;
1443 struct anv_state surface_state
;
1444 struct anv_state storage_surface_state
;
1445 struct anv_state writeonly_storage_surface_state
;
1447 struct brw_image_param storage_image_param
;
1450 struct anv_push_descriptor_set
{
1451 struct anv_descriptor_set set
;
1453 /* Put this field right behind anv_descriptor_set so it fills up the
1454 * descriptors[0] field. */
1455 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1456 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1459 struct anv_descriptor_pool
{
1464 struct anv_state_stream surface_state_stream
;
1465 void *surface_state_free_list
;
1470 enum anv_descriptor_template_entry_type
{
1471 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1472 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1473 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1476 struct anv_descriptor_template_entry
{
1477 /* The type of descriptor in this entry */
1478 VkDescriptorType type
;
1480 /* Binding in the descriptor set */
1483 /* Offset at which to write into the descriptor set binding */
1484 uint32_t array_element
;
1486 /* Number of elements to write into the descriptor set binding */
1487 uint32_t array_count
;
1489 /* Offset into the user provided data */
1492 /* Stride between elements into the user provided data */
1496 struct anv_descriptor_update_template
{
1497 VkPipelineBindPoint bind_point
;
1499 /* The descriptor set this template corresponds to. This value is only
1500 * valid if the template was created with the templateType
1501 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1505 /* Number of entries in this template */
1506 uint32_t entry_count
;
1508 /* Entries of the template */
1509 struct anv_descriptor_template_entry entries
[0];
1513 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout
*binding
);
1516 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1519 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1520 const struct gen_device_info
* const devinfo
,
1521 const VkDescriptorImageInfo
* const info
,
1522 VkDescriptorType type
,
1527 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1528 VkDescriptorType type
,
1529 struct anv_buffer_view
*buffer_view
,
1534 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1535 struct anv_device
*device
,
1536 struct anv_state_stream
*alloc_stream
,
1537 VkDescriptorType type
,
1538 struct anv_buffer
*buffer
,
1541 VkDeviceSize offset
,
1542 VkDeviceSize range
);
1545 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1546 struct anv_device
*device
,
1547 struct anv_state_stream
*alloc_stream
,
1548 const struct anv_descriptor_update_template
*template,
1552 anv_descriptor_set_create(struct anv_device
*device
,
1553 struct anv_descriptor_pool
*pool
,
1554 struct anv_descriptor_set_layout
*layout
,
1555 struct anv_descriptor_set
**out_set
);
1558 anv_descriptor_set_destroy(struct anv_device
*device
,
1559 struct anv_descriptor_pool
*pool
,
1560 struct anv_descriptor_set
*set
);
1562 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1564 struct anv_pipeline_binding
{
1565 /* The descriptor set this surface corresponds to. The special value of
1566 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1567 * to a color attachment and not a regular descriptor.
1571 /* Binding in the descriptor set */
1574 /* Index in the binding */
1577 /* Plane in the binding index */
1580 /* Input attachment index (relative to the subpass) */
1581 uint8_t input_attachment_index
;
1583 /* For a storage image, whether it is write-only */
1587 struct anv_pipeline_layout
{
1589 struct anv_descriptor_set_layout
*layout
;
1590 uint32_t dynamic_offset_start
;
1596 bool has_dynamic_offsets
;
1597 } stage
[MESA_SHADER_STAGES
];
1599 unsigned char sha1
[20];
1603 struct anv_device
* device
;
1606 VkBufferUsageFlags usage
;
1608 /* Set when bound */
1609 struct anv_address address
;
1612 static inline uint64_t
1613 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1615 assert(offset
<= buffer
->size
);
1616 if (range
== VK_WHOLE_SIZE
) {
1617 return buffer
->size
- offset
;
1619 assert(range
<= buffer
->size
);
1624 enum anv_cmd_dirty_bits
{
1625 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1626 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1627 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1628 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1629 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1630 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1631 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1632 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1633 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1634 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1635 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1636 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1637 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1639 typedef uint32_t anv_cmd_dirty_mask_t
;
1641 enum anv_pipe_bits
{
1642 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1643 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1644 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1645 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1646 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1647 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1648 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1649 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1650 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1651 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1652 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1654 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1655 * a flush has happened but not a CS stall. The next time we do any sort
1656 * of invalidation we need to insert a CS stall at that time. Otherwise,
1657 * we would have to CS stall on every flush which could be bad.
1659 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1662 #define ANV_PIPE_FLUSH_BITS ( \
1663 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1664 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1665 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1667 #define ANV_PIPE_STALL_BITS ( \
1668 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1669 ANV_PIPE_DEPTH_STALL_BIT | \
1670 ANV_PIPE_CS_STALL_BIT)
1672 #define ANV_PIPE_INVALIDATE_BITS ( \
1673 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1674 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1675 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1676 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1677 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1678 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1680 static inline enum anv_pipe_bits
1681 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1683 enum anv_pipe_bits pipe_bits
= 0;
1686 for_each_bit(b
, flags
) {
1687 switch ((VkAccessFlagBits
)(1 << b
)) {
1688 case VK_ACCESS_SHADER_WRITE_BIT
:
1689 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1691 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1692 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1694 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1695 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1697 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1698 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1699 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1702 break; /* Nothing to do */
1709 static inline enum anv_pipe_bits
1710 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1712 enum anv_pipe_bits pipe_bits
= 0;
1715 for_each_bit(b
, flags
) {
1716 switch ((VkAccessFlagBits
)(1 << b
)) {
1717 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1718 case VK_ACCESS_INDEX_READ_BIT
:
1719 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1720 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1722 case VK_ACCESS_UNIFORM_READ_BIT
:
1723 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1724 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1726 case VK_ACCESS_SHADER_READ_BIT
:
1727 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1728 case VK_ACCESS_TRANSFER_READ_BIT
:
1729 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1732 break; /* Nothing to do */
1739 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1740 VK_IMAGE_ASPECT_COLOR_BIT | \
1741 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1742 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1743 VK_IMAGE_ASPECT_PLANE_2_BIT)
1744 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1745 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1746 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1747 VK_IMAGE_ASPECT_PLANE_2_BIT)
1749 struct anv_vertex_binding
{
1750 struct anv_buffer
* buffer
;
1751 VkDeviceSize offset
;
1754 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1755 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1757 struct anv_push_constants
{
1758 /* Current allocated size of this push constants data structure.
1759 * Because a decent chunk of it may not be used (images on SKL, for
1760 * instance), we won't actually allocate the entire structure up-front.
1764 /* Push constant data provided by the client through vkPushConstants */
1765 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1767 /* Used for vkCmdDispatchBase */
1768 uint32_t base_work_group_id
[3];
1770 /* Image data for image_load_store on pre-SKL */
1771 struct brw_image_param images
[MAX_IMAGES
];
1774 struct anv_dynamic_state
{
1777 VkViewport viewports
[MAX_VIEWPORTS
];
1782 VkRect2D scissors
[MAX_SCISSORS
];
1793 float blend_constants
[4];
1803 } stencil_compare_mask
;
1808 } stencil_write_mask
;
1813 } stencil_reference
;
1816 extern const struct anv_dynamic_state default_dynamic_state
;
1818 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1819 const struct anv_dynamic_state
*src
,
1820 uint32_t copy_mask
);
1822 struct anv_surface_state
{
1823 struct anv_state state
;
1824 /** Address of the surface referred to by this state
1826 * This address is relative to the start of the BO.
1828 struct anv_address address
;
1829 /* Address of the aux surface, if any
1831 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
1833 * With the exception of gen8, the bottom 12 bits of this address' offset
1834 * include extra aux information.
1836 struct anv_address aux_address
;
1837 /* Address of the clear color, if any
1839 * This address is relative to the start of the BO.
1841 struct anv_address clear_address
;
1845 * Attachment state when recording a renderpass instance.
1847 * The clear value is valid only if there exists a pending clear.
1849 struct anv_attachment_state
{
1850 enum isl_aux_usage aux_usage
;
1851 enum isl_aux_usage input_aux_usage
;
1852 struct anv_surface_state color
;
1853 struct anv_surface_state input
;
1855 VkImageLayout current_layout
;
1856 VkImageAspectFlags pending_clear_aspects
;
1857 VkImageAspectFlags pending_load_aspects
;
1859 VkClearValue clear_value
;
1860 bool clear_color_is_zero_one
;
1861 bool clear_color_is_zero
;
1863 /* When multiview is active, attachments with a renderpass clear
1864 * operation have their respective layers cleared on the first
1865 * subpass that uses them, and only in that subpass. We keep track
1866 * of this using a bitfield to indicate which layers of an attachment
1867 * have not been cleared yet when multiview is active.
1869 uint32_t pending_clear_views
;
1872 /** State tracking for particular pipeline bind point
1874 * This struct is the base struct for anv_cmd_graphics_state and
1875 * anv_cmd_compute_state. These are used to track state which is bound to a
1876 * particular type of pipeline. Generic state that applies per-stage such as
1877 * binding table offsets and push constants is tracked generically with a
1878 * per-stage array in anv_cmd_state.
1880 struct anv_cmd_pipeline_state
{
1881 struct anv_pipeline
*pipeline
;
1882 struct anv_pipeline_layout
*layout
;
1884 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
1885 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
1887 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
1890 /** State tracking for graphics pipeline
1892 * This has anv_cmd_pipeline_state as a base struct to track things which get
1893 * bound to a graphics pipeline. Along with general pipeline bind point state
1894 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1895 * state which is graphics-specific.
1897 struct anv_cmd_graphics_state
{
1898 struct anv_cmd_pipeline_state base
;
1900 anv_cmd_dirty_mask_t dirty
;
1903 struct anv_dynamic_state dynamic
;
1906 struct anv_buffer
*index_buffer
;
1907 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1908 uint32_t index_offset
;
1912 /** State tracking for compute pipeline
1914 * This has anv_cmd_pipeline_state as a base struct to track things which get
1915 * bound to a compute pipeline. Along with general pipeline bind point state
1916 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1917 * state which is compute-specific.
1919 struct anv_cmd_compute_state
{
1920 struct anv_cmd_pipeline_state base
;
1922 bool pipeline_dirty
;
1924 struct anv_address num_workgroups
;
1927 /** State required while building cmd buffer */
1928 struct anv_cmd_state
{
1929 /* PIPELINE_SELECT.PipelineSelection */
1930 uint32_t current_pipeline
;
1931 const struct gen_l3_config
* current_l3_config
;
1933 struct anv_cmd_graphics_state gfx
;
1934 struct anv_cmd_compute_state compute
;
1936 enum anv_pipe_bits pending_pipe_bits
;
1937 VkShaderStageFlags descriptors_dirty
;
1938 VkShaderStageFlags push_constants_dirty
;
1940 struct anv_framebuffer
* framebuffer
;
1941 struct anv_render_pass
* pass
;
1942 struct anv_subpass
* subpass
;
1943 VkRect2D render_area
;
1944 uint32_t restart_index
;
1945 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1946 VkShaderStageFlags push_constant_stages
;
1947 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1948 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1949 struct anv_state samplers
[MESA_SHADER_STAGES
];
1952 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1953 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1954 * and before invoking the secondary in ExecuteCommands.
1956 bool pma_fix_enabled
;
1959 * Whether or not we know for certain that HiZ is enabled for the current
1960 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1961 * enabled or not, this will be false.
1966 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1967 * valid only when recording a render pass instance.
1969 struct anv_attachment_state
* attachments
;
1972 * Surface states for color render targets. These are stored in a single
1973 * flat array. For depth-stencil attachments, the surface state is simply
1976 struct anv_state render_pass_states
;
1979 * A null surface state of the right size to match the framebuffer. This
1980 * is one of the states in render_pass_states.
1982 struct anv_state null_surface_state
;
1985 struct anv_cmd_pool
{
1986 VkAllocationCallbacks alloc
;
1987 struct list_head cmd_buffers
;
1990 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1992 enum anv_cmd_buffer_exec_mode
{
1993 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1994 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1995 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1996 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1997 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2000 struct anv_cmd_buffer
{
2001 VK_LOADER_DATA _loader_data
;
2003 struct anv_device
* device
;
2005 struct anv_cmd_pool
* pool
;
2006 struct list_head pool_link
;
2008 struct anv_batch batch
;
2010 /* Fields required for the actual chain of anv_batch_bo's.
2012 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2014 struct list_head batch_bos
;
2015 enum anv_cmd_buffer_exec_mode exec_mode
;
2017 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2018 * referenced by this command buffer
2020 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2022 struct u_vector seen_bbos
;
2024 /* A vector of int32_t's for every block of binding tables.
2026 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2028 struct u_vector bt_block_states
;
2031 struct anv_reloc_list surface_relocs
;
2032 /** Last seen surface state block pool center bo offset */
2033 uint32_t last_ss_pool_center
;
2035 /* Serial for tracking buffer completion */
2038 /* Stream objects for storing temporary data */
2039 struct anv_state_stream surface_state_stream
;
2040 struct anv_state_stream dynamic_state_stream
;
2042 VkCommandBufferUsageFlags usage_flags
;
2043 VkCommandBufferLevel level
;
2045 struct anv_cmd_state state
;
2048 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2049 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2050 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2051 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2052 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2053 struct anv_cmd_buffer
*secondary
);
2054 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2055 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2056 struct anv_cmd_buffer
*cmd_buffer
,
2057 const VkSemaphore
*in_semaphores
,
2058 uint32_t num_in_semaphores
,
2059 const VkSemaphore
*out_semaphores
,
2060 uint32_t num_out_semaphores
,
2063 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2066 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
2067 gl_shader_stage stage
, uint32_t size
);
2068 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
2069 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
2070 (offsetof(struct anv_push_constants, field) + \
2071 sizeof(cmd_buffer->state.push_constants[0]->field)))
2073 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2074 const void *data
, uint32_t size
, uint32_t alignment
);
2075 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2076 uint32_t *a
, uint32_t *b
,
2077 uint32_t dwords
, uint32_t alignment
);
2080 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2082 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2083 uint32_t entries
, uint32_t *state_offset
);
2085 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2087 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2088 uint32_t size
, uint32_t alignment
);
2091 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2093 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2094 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2095 bool depth_clamp_enable
);
2096 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2098 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2099 struct anv_render_pass
*pass
,
2100 struct anv_framebuffer
*framebuffer
,
2101 const VkClearValue
*clear_values
);
2103 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2106 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2107 gl_shader_stage stage
);
2109 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2111 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
2113 const struct anv_image_view
*
2114 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2117 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2118 uint32_t num_entries
,
2119 uint32_t *state_offset
,
2120 struct anv_state
*bt_state
);
2122 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2124 enum anv_fence_type
{
2125 ANV_FENCE_TYPE_NONE
= 0,
2127 ANV_FENCE_TYPE_SYNCOBJ
,
2130 enum anv_bo_fence_state
{
2131 /** Indicates that this is a new (or newly reset fence) */
2132 ANV_BO_FENCE_STATE_RESET
,
2134 /** Indicates that this fence has been submitted to the GPU but is still
2135 * (as far as we know) in use by the GPU.
2137 ANV_BO_FENCE_STATE_SUBMITTED
,
2139 ANV_BO_FENCE_STATE_SIGNALED
,
2142 struct anv_fence_impl
{
2143 enum anv_fence_type type
;
2146 /** Fence implementation for BO fences
2148 * These fences use a BO and a set of CPU-tracked state flags. The BO
2149 * is added to the object list of the last execbuf call in a QueueSubmit
2150 * and is marked EXEC_WRITE. The state flags track when the BO has been
2151 * submitted to the kernel. We need to do this because Vulkan lets you
2152 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2153 * will say it's idle in this case.
2157 enum anv_bo_fence_state state
;
2160 /** DRM syncobj handle for syncobj-based fences */
2166 /* Permanent fence state. Every fence has some form of permanent state
2167 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2168 * cross-process fences) or it could just be a dummy for use internally.
2170 struct anv_fence_impl permanent
;
2172 /* Temporary fence state. A fence *may* have temporary state. That state
2173 * is added to the fence by an import operation and is reset back to
2174 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2175 * state cannot be signaled because the fence must already be signaled
2176 * before the temporary state can be exported from the fence in the other
2177 * process and imported here.
2179 struct anv_fence_impl temporary
;
2184 struct anv_state state
;
2187 enum anv_semaphore_type
{
2188 ANV_SEMAPHORE_TYPE_NONE
= 0,
2189 ANV_SEMAPHORE_TYPE_DUMMY
,
2190 ANV_SEMAPHORE_TYPE_BO
,
2191 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2192 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2195 struct anv_semaphore_impl
{
2196 enum anv_semaphore_type type
;
2199 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2200 * This BO will be added to the object list on any execbuf2 calls for
2201 * which this semaphore is used as a wait or signal fence. When used as
2202 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2206 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2207 * If the semaphore is in the unsignaled state due to either just being
2208 * created or because it has been used for a wait, fd will be -1.
2212 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2213 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2214 * import so we don't need to bother with a userspace cache.
2220 struct anv_semaphore
{
2221 /* Permanent semaphore state. Every semaphore has some form of permanent
2222 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2223 * (for cross-process semaphores0 or it could just be a dummy for use
2226 struct anv_semaphore_impl permanent
;
2228 /* Temporary semaphore state. A semaphore *may* have temporary state.
2229 * That state is added to the semaphore by an import operation and is reset
2230 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2231 * semaphore with temporary state cannot be signaled because the semaphore
2232 * must already be signaled before the temporary state can be exported from
2233 * the semaphore in the other process and imported here.
2235 struct anv_semaphore_impl temporary
;
2238 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2239 struct anv_semaphore
*semaphore
);
2241 struct anv_shader_module
{
2242 unsigned char sha1
[20];
2247 static inline gl_shader_stage
2248 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2250 assert(__builtin_popcount(vk_stage
) == 1);
2251 return ffs(vk_stage
) - 1;
2254 static inline VkShaderStageFlagBits
2255 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2257 return (1 << mesa_stage
);
2260 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2262 #define anv_foreach_stage(stage, stage_bits) \
2263 for (gl_shader_stage stage, \
2264 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2265 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2266 __tmp &= ~(1 << (stage)))
2268 struct anv_pipeline_bind_map
{
2269 uint32_t surface_count
;
2270 uint32_t sampler_count
;
2271 uint32_t image_count
;
2273 struct anv_pipeline_binding
* surface_to_descriptor
;
2274 struct anv_pipeline_binding
* sampler_to_descriptor
;
2277 struct anv_shader_bin_key
{
2282 struct anv_shader_bin
{
2285 const struct anv_shader_bin_key
*key
;
2287 struct anv_state kernel
;
2288 uint32_t kernel_size
;
2290 const struct brw_stage_prog_data
*prog_data
;
2291 uint32_t prog_data_size
;
2293 struct anv_pipeline_bind_map bind_map
;
2296 struct anv_shader_bin
*
2297 anv_shader_bin_create(struct anv_device
*device
,
2298 const void *key
, uint32_t key_size
,
2299 const void *kernel
, uint32_t kernel_size
,
2300 const struct brw_stage_prog_data
*prog_data
,
2301 uint32_t prog_data_size
, const void *prog_data_param
,
2302 const struct anv_pipeline_bind_map
*bind_map
);
2305 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2308 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2310 assert(shader
&& shader
->ref_cnt
>= 1);
2311 p_atomic_inc(&shader
->ref_cnt
);
2315 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2317 assert(shader
&& shader
->ref_cnt
>= 1);
2318 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2319 anv_shader_bin_destroy(device
, shader
);
2322 struct anv_pipeline
{
2323 struct anv_device
* device
;
2324 struct anv_batch batch
;
2325 uint32_t batch_data
[512];
2326 struct anv_reloc_list batch_relocs
;
2327 uint32_t dynamic_state_mask
;
2328 struct anv_dynamic_state dynamic_state
;
2330 struct anv_subpass
* subpass
;
2332 bool needs_data_cache
;
2334 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2337 const struct gen_l3_config
* l3_config
;
2338 uint32_t total_size
;
2341 VkShaderStageFlags active_stages
;
2342 struct anv_state blend_state
;
2345 uint32_t binding_stride
[MAX_VBS
];
2346 bool instancing_enable
[MAX_VBS
];
2347 bool primitive_restart
;
2350 uint32_t cs_right_mask
;
2353 bool depth_test_enable
;
2354 bool writes_stencil
;
2355 bool stencil_test_enable
;
2356 bool depth_clamp_enable
;
2357 bool sample_shading_enable
;
2362 uint32_t depth_stencil_state
[3];
2368 uint32_t wm_depth_stencil
[3];
2372 uint32_t wm_depth_stencil
[4];
2375 uint32_t interface_descriptor_data
[8];
2379 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2380 gl_shader_stage stage
)
2382 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2385 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2386 static inline const struct brw_##prefix##_prog_data * \
2387 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2389 if (anv_pipeline_has_stage(pipeline, stage)) { \
2390 return (const struct brw_##prefix##_prog_data *) \
2391 pipeline->shaders[stage]->prog_data; \
2397 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2398 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2399 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2400 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2401 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2402 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2404 static inline const struct brw_vue_prog_data
*
2405 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2407 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2408 return &get_gs_prog_data(pipeline
)->base
;
2409 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2410 return &get_tes_prog_data(pipeline
)->base
;
2412 return &get_vs_prog_data(pipeline
)->base
;
2416 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2417 struct anv_pipeline_cache
*cache
,
2418 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2419 const VkAllocationCallbacks
*alloc
);
2422 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2423 struct anv_pipeline_cache
*cache
,
2424 const VkComputePipelineCreateInfo
*info
,
2425 struct anv_shader_module
*module
,
2426 const char *entrypoint
,
2427 const VkSpecializationInfo
*spec_info
);
2429 struct anv_format_plane
{
2430 enum isl_format isl_format
:16;
2431 struct isl_swizzle swizzle
;
2433 /* Whether this plane contains chroma channels */
2436 /* For downscaling of YUV planes */
2437 uint8_t denominator_scales
[2];
2439 /* How to map sampled ycbcr planes to a single 4 component element. */
2440 struct isl_swizzle ycbcr_swizzle
;
2445 struct anv_format_plane planes
[3];
2450 static inline uint32_t
2451 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2452 VkImageAspectFlags aspect_mask
)
2454 switch (aspect_mask
) {
2455 case VK_IMAGE_ASPECT_COLOR_BIT
:
2456 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2457 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2459 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2460 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2463 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2465 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2468 /* Purposefully assert with depth/stencil aspects. */
2469 unreachable("invalid image aspect");
2473 static inline uint32_t
2474 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask
)
2476 uint32_t planes
= 0;
2478 if (aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
|
2479 VK_IMAGE_ASPECT_DEPTH_BIT
|
2480 VK_IMAGE_ASPECT_STENCIL_BIT
|
2481 VK_IMAGE_ASPECT_PLANE_0_BIT
))
2483 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_1_BIT
)
2485 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_2_BIT
)
2488 if ((aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) != 0 &&
2489 (aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) != 0)
2495 static inline VkImageAspectFlags
2496 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
2499 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2500 if (_mesa_bitcount(image_aspects
) > 1)
2501 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
2502 return VK_IMAGE_ASPECT_COLOR_BIT
;
2504 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
2505 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
2506 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
2507 return VK_IMAGE_ASPECT_STENCIL_BIT
;
2510 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2511 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2513 const struct anv_format
*
2514 anv_get_format(VkFormat format
);
2516 static inline uint32_t
2517 anv_get_format_planes(VkFormat vk_format
)
2519 const struct anv_format
*format
= anv_get_format(vk_format
);
2521 return format
!= NULL
? format
->n_planes
: 0;
2524 struct anv_format_plane
2525 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2526 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
2528 static inline enum isl_format
2529 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2530 VkImageAspectFlags aspect
, VkImageTiling tiling
)
2532 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
2535 static inline struct isl_swizzle
2536 anv_swizzle_for_render(struct isl_swizzle swizzle
)
2538 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2539 * RGB as RGBA for texturing
2541 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
2542 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
2544 /* But it doesn't matter what we render to that channel */
2545 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
2551 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
2554 * Subsurface of an anv_image.
2556 struct anv_surface
{
2557 /** Valid only if isl_surf::size > 0. */
2558 struct isl_surf isl
;
2561 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2568 /* The original VkFormat provided by the client. This may not match any
2569 * of the actual surface formats.
2572 const struct anv_format
*format
;
2574 VkImageAspectFlags aspects
;
2577 uint32_t array_size
;
2578 uint32_t samples
; /**< VkImageCreateInfo::samples */
2580 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2581 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2583 /** True if this is needs to be bound to an appropriately tiled BO.
2585 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2586 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2587 * we require a dedicated allocation so that we can know to allocate a
2590 bool needs_set_tiling
;
2593 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2594 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2596 uint64_t drm_format_mod
;
2601 /* Whether the image is made of several underlying buffer objects rather a
2602 * single one with different offsets.
2609 * For each foo, anv_image::planes[x].surface is valid if and only if
2610 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2611 * to figure the number associated with a given aspect.
2613 * The hardware requires that the depth buffer and stencil buffer be
2614 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2615 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2616 * allocate the depth and stencil buffers as separate surfaces in the same
2621 * -----------------------
2623 * ----------------------- |
2624 * | shadow surface0 | |
2625 * ----------------------- | Plane 0
2626 * | aux surface0 | |
2627 * ----------------------- |
2628 * | fast clear colors0 | \|/
2629 * -----------------------
2631 * ----------------------- |
2632 * | shadow surface1 | |
2633 * ----------------------- | Plane 1
2634 * | aux surface1 | |
2635 * ----------------------- |
2636 * | fast clear colors1 | \|/
2637 * -----------------------
2640 * -----------------------
2644 * Offset of the entire plane (whenever the image is disjoint this is
2652 struct anv_surface surface
;
2655 * A surface which shadows the main surface and may have different
2656 * tiling. This is used for sampling using a tiling that isn't supported
2657 * for other operations.
2659 struct anv_surface shadow_surface
;
2662 * For color images, this is the aux usage for this image when not used
2663 * as a color attachment.
2665 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2666 * image has a HiZ buffer.
2668 enum isl_aux_usage aux_usage
;
2670 struct anv_surface aux_surface
;
2673 * Offset of the fast clear state (used to compute the
2674 * fast_clear_state_offset of the following planes).
2676 uint32_t fast_clear_state_offset
;
2679 * BO associated with this plane, set when bound.
2681 struct anv_address address
;
2684 * When destroying the image, also free the bo.
2690 /* The ordering of this enum is important */
2691 enum anv_fast_clear_type
{
2692 /** Image does not have/support any fast-clear blocks */
2693 ANV_FAST_CLEAR_NONE
= 0,
2694 /** Image has/supports fast-clear but only to the default value */
2695 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
2696 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2697 ANV_FAST_CLEAR_ANY
= 2,
2700 /* Returns the number of auxiliary buffer levels attached to an image. */
2701 static inline uint8_t
2702 anv_image_aux_levels(const struct anv_image
* const image
,
2703 VkImageAspectFlagBits aspect
)
2705 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2706 return image
->planes
[plane
].aux_surface
.isl
.size
> 0 ?
2707 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
2710 /* Returns the number of auxiliary buffer layers attached to an image. */
2711 static inline uint32_t
2712 anv_image_aux_layers(const struct anv_image
* const image
,
2713 VkImageAspectFlagBits aspect
,
2714 const uint8_t miplevel
)
2718 /* The miplevel must exist in the main buffer. */
2719 assert(miplevel
< image
->levels
);
2721 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
2722 /* There are no layers with auxiliary data because the miplevel has no
2727 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2728 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
2729 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
2733 static inline struct anv_address
2734 anv_image_get_clear_color_addr(const struct anv_device
*device
,
2735 const struct anv_image
*image
,
2736 VkImageAspectFlagBits aspect
)
2738 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
2740 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2741 return anv_address_add(image
->planes
[plane
].address
,
2742 image
->planes
[plane
].fast_clear_state_offset
);
2745 static inline struct anv_address
2746 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
2747 const struct anv_image
*image
,
2748 VkImageAspectFlagBits aspect
)
2750 struct anv_address addr
=
2751 anv_image_get_clear_color_addr(device
, image
, aspect
);
2753 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
2754 device
->isl_dev
.ss
.clear_color_state_size
:
2755 device
->isl_dev
.ss
.clear_value_size
;
2756 addr
.offset
+= clear_color_state_size
;
2760 static inline struct anv_address
2761 anv_image_get_compression_state_addr(const struct anv_device
*device
,
2762 const struct anv_image
*image
,
2763 VkImageAspectFlagBits aspect
,
2764 uint32_t level
, uint32_t array_layer
)
2766 assert(level
< anv_image_aux_levels(image
, aspect
));
2767 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
2768 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2769 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
2771 struct anv_address addr
=
2772 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
2773 addr
.offset
+= 4; /* Go past the fast clear type */
2775 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2776 for (uint32_t l
= 0; l
< level
; l
++)
2777 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
2779 addr
.offset
+= level
* image
->array_size
* 4;
2781 addr
.offset
+= array_layer
* 4;
2786 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2788 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
2789 const struct anv_image
*image
)
2791 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
2794 if (devinfo
->gen
< 8)
2797 return image
->samples
== 1;
2801 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
2802 const struct anv_image
*image
,
2803 VkImageAspectFlagBits aspect
,
2804 enum isl_aux_usage aux_usage
,
2806 uint32_t base_layer
,
2807 uint32_t layer_count
);
2810 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
2811 const struct anv_image
*image
,
2812 VkImageAspectFlagBits aspect
,
2813 enum isl_aux_usage aux_usage
,
2814 enum isl_format format
, struct isl_swizzle swizzle
,
2815 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
2816 VkRect2D area
, union isl_color_value clear_color
);
2818 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
2819 const struct anv_image
*image
,
2820 VkImageAspectFlags aspects
,
2821 enum isl_aux_usage depth_aux_usage
,
2823 uint32_t base_layer
, uint32_t layer_count
,
2825 float depth_value
, uint8_t stencil_value
);
2827 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
2828 const struct anv_image
*image
,
2829 VkImageAspectFlagBits aspect
, uint32_t level
,
2830 uint32_t base_layer
, uint32_t layer_count
,
2831 enum isl_aux_op hiz_op
);
2833 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
2834 const struct anv_image
*image
,
2835 VkImageAspectFlags aspects
,
2837 uint32_t base_layer
, uint32_t layer_count
,
2838 VkRect2D area
, uint8_t stencil_value
);
2840 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
2841 const struct anv_image
*image
,
2842 VkImageAspectFlagBits aspect
,
2843 uint32_t base_layer
, uint32_t layer_count
,
2844 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
2847 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
2848 const struct anv_image
*image
,
2849 VkImageAspectFlagBits aspect
, uint32_t level
,
2850 uint32_t base_layer
, uint32_t layer_count
,
2851 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
2855 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
2856 const struct anv_image
*image
,
2857 uint32_t base_level
, uint32_t level_count
,
2858 uint32_t base_layer
, uint32_t layer_count
);
2861 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
2862 const struct anv_image
*image
,
2863 const VkImageAspectFlagBits aspect
,
2864 const VkImageLayout layout
);
2866 enum anv_fast_clear_type
2867 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
2868 const struct anv_image
* const image
,
2869 const VkImageAspectFlagBits aspect
,
2870 const VkImageLayout layout
);
2872 /* This is defined as a macro so that it works for both
2873 * VkImageSubresourceRange and VkImageSubresourceLayers
2875 #define anv_get_layerCount(_image, _range) \
2876 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2877 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2879 static inline uint32_t
2880 anv_get_levelCount(const struct anv_image
*image
,
2881 const VkImageSubresourceRange
*range
)
2883 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
2884 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
2887 static inline VkImageAspectFlags
2888 anv_image_expand_aspects(const struct anv_image
*image
,
2889 VkImageAspectFlags aspects
)
2891 /* If the underlying image has color plane aspects and
2892 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2893 * the underlying image. */
2894 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
2895 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
2896 return image
->aspects
;
2902 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
2903 VkImageAspectFlags aspects2
)
2905 if (aspects1
== aspects2
)
2908 /* Only 1 color aspects are compatibles. */
2909 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
2910 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
2911 _mesa_bitcount(aspects1
) == _mesa_bitcount(aspects2
))
2917 struct anv_image_view
{
2918 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
2920 VkImageAspectFlags aspect_mask
;
2922 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2926 uint32_t image_plane
;
2928 struct isl_view isl
;
2931 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2932 * image layout of SHADER_READ_ONLY_OPTIMAL or
2933 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2935 struct anv_surface_state optimal_sampler_surface_state
;
2938 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2939 * image layout of GENERAL.
2941 struct anv_surface_state general_sampler_surface_state
;
2944 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2945 * states for write-only and readable, using the real format for
2946 * write-only and the lowered format for readable.
2948 struct anv_surface_state storage_surface_state
;
2949 struct anv_surface_state writeonly_storage_surface_state
;
2951 struct brw_image_param storage_image_param
;
2955 enum anv_image_view_state_flags
{
2956 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
2957 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
2960 void anv_image_fill_surface_state(struct anv_device
*device
,
2961 const struct anv_image
*image
,
2962 VkImageAspectFlagBits aspect
,
2963 const struct isl_view
*view
,
2964 isl_surf_usage_flags_t view_usage
,
2965 enum isl_aux_usage aux_usage
,
2966 const union isl_color_value
*clear_color
,
2967 enum anv_image_view_state_flags flags
,
2968 struct anv_surface_state
*state_inout
,
2969 struct brw_image_param
*image_param_out
);
2971 struct anv_image_create_info
{
2972 const VkImageCreateInfo
*vk_info
;
2974 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2975 isl_tiling_flags_t isl_tiling_flags
;
2977 /** These flags will be added to any derived from VkImageCreateInfo. */
2978 isl_surf_usage_flags_t isl_extra_usage_flags
;
2983 VkResult
anv_image_create(VkDevice _device
,
2984 const struct anv_image_create_info
*info
,
2985 const VkAllocationCallbacks
* alloc
,
2989 VkResult
anv_image_from_gralloc(VkDevice device_h
,
2990 const VkImageCreateInfo
*base_info
,
2991 const VkNativeBufferANDROID
*gralloc_info
,
2992 const VkAllocationCallbacks
*alloc
,
2996 const struct anv_surface
*
2997 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
2998 VkImageAspectFlags aspect_mask
);
3001 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3003 static inline struct VkExtent3D
3004 anv_sanitize_image_extent(const VkImageType imageType
,
3005 const struct VkExtent3D imageExtent
)
3007 switch (imageType
) {
3008 case VK_IMAGE_TYPE_1D
:
3009 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3010 case VK_IMAGE_TYPE_2D
:
3011 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3012 case VK_IMAGE_TYPE_3D
:
3015 unreachable("invalid image type");
3019 static inline struct VkOffset3D
3020 anv_sanitize_image_offset(const VkImageType imageType
,
3021 const struct VkOffset3D imageOffset
)
3023 switch (imageType
) {
3024 case VK_IMAGE_TYPE_1D
:
3025 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3026 case VK_IMAGE_TYPE_2D
:
3027 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3028 case VK_IMAGE_TYPE_3D
:
3031 unreachable("invalid image type");
3036 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3037 struct anv_state state
,
3038 enum isl_format format
,
3039 struct anv_address address
,
3040 uint32_t range
, uint32_t stride
);
3043 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3044 const struct anv_attachment_state
*att_state
,
3045 const struct anv_image_view
*iview
)
3047 const struct isl_format_layout
*view_fmtl
=
3048 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3050 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3051 if (view_fmtl->channels.c.bits) \
3052 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3054 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3055 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3056 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3057 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3059 #undef COPY_CLEAR_COLOR_CHANNEL
3063 struct anv_ycbcr_conversion
{
3064 const struct anv_format
* format
;
3065 VkSamplerYcbcrModelConversion ycbcr_model
;
3066 VkSamplerYcbcrRange ycbcr_range
;
3067 VkComponentSwizzle mapping
[4];
3068 VkChromaLocation chroma_offsets
[2];
3069 VkFilter chroma_filter
;
3070 bool chroma_reconstruction
;
3073 struct anv_sampler
{
3074 uint32_t state
[3][4];
3076 struct anv_ycbcr_conversion
*conversion
;
3079 struct anv_framebuffer
{
3084 uint32_t attachment_count
;
3085 struct anv_image_view
* attachments
[0];
3088 struct anv_subpass_attachment
{
3089 VkImageUsageFlagBits usage
;
3090 uint32_t attachment
;
3091 VkImageLayout layout
;
3094 struct anv_subpass
{
3095 uint32_t attachment_count
;
3098 * A pointer to all attachment references used in this subpass.
3099 * Only valid if ::attachment_count > 0.
3101 struct anv_subpass_attachment
* attachments
;
3102 uint32_t input_count
;
3103 struct anv_subpass_attachment
* input_attachments
;
3104 uint32_t color_count
;
3105 struct anv_subpass_attachment
* color_attachments
;
3106 struct anv_subpass_attachment
* resolve_attachments
;
3108 struct anv_subpass_attachment depth_stencil_attachment
;
3112 /** Subpass has a depth/stencil self-dependency */
3113 bool has_ds_self_dep
;
3115 /** Subpass has at least one resolve attachment */
3119 static inline unsigned
3120 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3122 return MAX2(1, _mesa_bitcount(subpass
->view_mask
));
3125 struct anv_render_pass_attachment
{
3126 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3127 * its members individually.
3131 VkImageUsageFlags usage
;
3132 VkAttachmentLoadOp load_op
;
3133 VkAttachmentStoreOp store_op
;
3134 VkAttachmentLoadOp stencil_load_op
;
3135 VkImageLayout initial_layout
;
3136 VkImageLayout final_layout
;
3137 VkImageLayout first_subpass_layout
;
3139 /* The subpass id in which the attachment will be used last. */
3140 uint32_t last_subpass_idx
;
3143 struct anv_render_pass
{
3144 uint32_t attachment_count
;
3145 uint32_t subpass_count
;
3146 /* An array of subpass_count+1 flushes, one per subpass boundary */
3147 enum anv_pipe_bits
* subpass_flushes
;
3148 struct anv_render_pass_attachment
* attachments
;
3149 struct anv_subpass subpasses
[0];
3152 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3154 struct anv_query_pool
{
3156 VkQueryPipelineStatisticFlags pipeline_statistics
;
3157 /** Stride between slots, in bytes */
3159 /** Number of slots in this query pool */
3164 int anv_get_entrypoint_index(const char *name
);
3167 anv_entrypoint_is_enabled(int index
, uint32_t core_version
,
3168 const struct anv_instance_extension_table
*instance
,
3169 const struct anv_device_extension_table
*device
);
3171 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3174 void anv_dump_image_to_ppm(struct anv_device
*device
,
3175 struct anv_image
*image
, unsigned miplevel
,
3176 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3177 const char *filename
);
3179 enum anv_dump_action
{
3180 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3183 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3184 void anv_dump_finish(void);
3186 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
3187 struct anv_framebuffer
*fb
);
3189 static inline uint32_t
3190 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3192 /* This function must be called from within a subpass. */
3193 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3195 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3197 /* The id of this subpass shouldn't exceed the number of subpasses in this
3198 * render pass minus 1.
3200 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3204 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3206 static inline struct __anv_type * \
3207 __anv_type ## _from_handle(__VkType _handle) \
3209 return (struct __anv_type *) _handle; \
3212 static inline __VkType \
3213 __anv_type ## _to_handle(struct __anv_type *_obj) \
3215 return (__VkType) _obj; \
3218 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3220 static inline struct __anv_type * \
3221 __anv_type ## _from_handle(__VkType _handle) \
3223 return (struct __anv_type *)(uintptr_t) _handle; \
3226 static inline __VkType \
3227 __anv_type ## _to_handle(struct __anv_type *_obj) \
3229 return (__VkType)(uintptr_t) _obj; \
3232 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3233 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3235 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3236 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3237 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3238 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3239 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3241 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3242 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3243 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3244 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3245 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3246 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3247 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
3248 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3249 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3250 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3251 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3252 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3253 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3254 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3255 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3256 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3257 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3258 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3259 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3260 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3261 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3262 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3263 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3265 /* Gen-specific function declarations */
3267 # include "anv_genX.h"
3269 # define genX(x) gen7_##x
3270 # include "anv_genX.h"
3272 # define genX(x) gen75_##x
3273 # include "anv_genX.h"
3275 # define genX(x) gen8_##x
3276 # include "anv_genX.h"
3278 # define genX(x) gen9_##x
3279 # include "anv_genX.h"
3281 # define genX(x) gen10_##x
3282 # include "anv_genX.h"
3284 # define genX(x) gen11_##x
3285 # include "anv_genX.h"
3289 #endif /* ANV_PRIVATE_H */