2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
44 #include "common/gen_clflush.h"
45 #include "common/gen_gem.h"
46 #include "dev/gen_device_info.h"
47 #include "blorp/blorp.h"
48 #include "compiler/brw_compiler.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/u_atomic.h"
52 #include "util/u_vector.h"
55 #include "vk_debug_report.h"
57 /* Pre-declarations needed for WSI entrypoints */
60 typedef struct xcb_connection_t xcb_connection_t
;
61 typedef uint32_t xcb_visualid_t
;
62 typedef uint32_t xcb_window_t
;
65 struct anv_buffer_view
;
66 struct anv_image_view
;
71 #include <vulkan/vulkan.h>
72 #include <vulkan/vulkan_intel.h>
73 #include <vulkan/vk_icd.h>
74 #include <vulkan/vk_android_native_buffer.h>
76 #include "anv_entrypoints.h"
77 #include "anv_extensions.h"
80 #include "common/gen_debug.h"
81 #include "common/intel_log.h"
82 #include "wsi_common.h"
84 /* anv Virtual Memory Layout
85 * =========================
87 * When the anv driver is determining the virtual graphics addresses of memory
88 * objects itself using the softpin mechanism, the following memory ranges
91 * Three special considerations to notice:
93 * (1) the dynamic state pool is located within the same 4 GiB as the low
94 * heap. This is to work around a VF cache issue described in a comment in
95 * anv_physical_device_init_heaps.
97 * (2) the binding table pool is located at lower addresses than the surface
98 * state pool, within a 4 GiB range. This allows surface state base addresses
99 * to cover both binding tables (16 bit offsets) and surface states (32 bit
102 * (3) the last 4 GiB of the address space is withheld from the high
103 * heap. Various hardware units will read past the end of an object for
104 * various reasons. This healthy margin prevents reads from wrapping around
107 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
108 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
109 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
110 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
111 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
112 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
113 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
114 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
115 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
116 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
117 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
118 #define HIGH_HEAP_MAX_ADDRESS 0xfffeffffffffULL
120 #define LOW_HEAP_SIZE \
121 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
122 #define HIGH_HEAP_SIZE \
123 (HIGH_HEAP_MAX_ADDRESS - HIGH_HEAP_MIN_ADDRESS + 1)
124 #define DYNAMIC_STATE_POOL_SIZE \
125 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
126 #define BINDING_TABLE_POOL_SIZE \
127 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
128 #define SURFACE_STATE_POOL_SIZE \
129 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
130 #define INSTRUCTION_STATE_POOL_SIZE \
131 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
133 /* Allowing different clear colors requires us to perform a depth resolve at
134 * the end of certain render passes. This is because while slow clears store
135 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
136 * See the PRMs for examples describing when additional resolves would be
137 * necessary. To enable fast clears without requiring extra resolves, we set
138 * the clear value to a globally-defined one. We could allow different values
139 * if the user doesn't expect coherent data during or after a render passes
140 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
141 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
142 * 1.0f seems to be the only value used. The only application that doesn't set
143 * this value does so through the usage of an seemingly uninitialized clear
146 #define ANV_HZ_FC_VAL 1.0f
151 #define MAX_VIEWPORTS 16
152 #define MAX_SCISSORS 16
153 #define MAX_PUSH_CONSTANTS_SIZE 128
154 #define MAX_DYNAMIC_BUFFERS 16
156 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
158 /* The kernel relocation API has a limitation of a 32-bit delta value
159 * applied to the address before it is written which, in spite of it being
160 * unsigned, is treated as signed . Because of the way that this maps to
161 * the Vulkan API, we cannot handle an offset into a buffer that does not
162 * fit into a signed 32 bits. The only mechanism we have for dealing with
163 * this at the moment is to limit all VkDeviceMemory objects to a maximum
164 * of 2GB each. The Vulkan spec allows us to do this:
166 * "Some platforms may have a limit on the maximum size of a single
167 * allocation. For example, certain systems may fail to create
168 * allocations with a size greater than or equal to 4GB. Such a limit is
169 * implementation-dependent, and if such a failure occurs then the error
170 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
172 * We don't use vk_error here because it's not an error so much as an
173 * indication to the application that the allocation is too large.
175 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
177 #define ANV_SVGS_VB_INDEX MAX_VBS
178 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
180 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
182 static inline uint32_t
183 align_down_npot_u32(uint32_t v
, uint32_t a
)
188 static inline uint32_t
189 align_u32(uint32_t v
, uint32_t a
)
191 assert(a
!= 0 && a
== (a
& -a
));
192 return (v
+ a
- 1) & ~(a
- 1);
195 static inline uint64_t
196 align_u64(uint64_t v
, uint64_t a
)
198 assert(a
!= 0 && a
== (a
& -a
));
199 return (v
+ a
- 1) & ~(a
- 1);
202 static inline int32_t
203 align_i32(int32_t v
, int32_t a
)
205 assert(a
!= 0 && a
== (a
& -a
));
206 return (v
+ a
- 1) & ~(a
- 1);
209 /** Alignment must be a power of 2. */
211 anv_is_aligned(uintmax_t n
, uintmax_t a
)
213 assert(a
== (a
& -a
));
214 return (n
& (a
- 1)) == 0;
217 static inline uint32_t
218 anv_minify(uint32_t n
, uint32_t levels
)
220 if (unlikely(n
== 0))
223 return MAX2(n
>> levels
, 1);
227 anv_clamp_f(float f
, float min
, float max
)
240 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
242 if (*inout_mask
& clear_mask
) {
243 *inout_mask
&= ~clear_mask
;
250 static inline union isl_color_value
251 vk_to_isl_color(VkClearColorValue color
)
253 return (union isl_color_value
) {
263 #define for_each_bit(b, dword) \
264 for (uint32_t __dword = (dword); \
265 (b) = __builtin_ffs(__dword) - 1, __dword; \
266 __dword &= ~(1 << (b)))
268 #define typed_memcpy(dest, src, count) ({ \
269 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
270 memcpy((dest), (src), (count) * sizeof(*(src))); \
273 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
274 * to be added here in order to utilize mapping in debug/error/perf macros.
276 #define REPORT_OBJECT_TYPE(o) \
277 __builtin_choose_expr ( \
278 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
279 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
280 __builtin_choose_expr ( \
281 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
282 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
283 __builtin_choose_expr ( \
284 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
285 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
286 __builtin_choose_expr ( \
287 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
288 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
289 __builtin_choose_expr ( \
290 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
291 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
292 __builtin_choose_expr ( \
293 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
294 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
295 __builtin_choose_expr ( \
296 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
297 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
298 __builtin_choose_expr ( \
299 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
300 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
301 __builtin_choose_expr ( \
302 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
303 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
304 __builtin_choose_expr ( \
305 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
306 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
307 __builtin_choose_expr ( \
308 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
309 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
310 __builtin_choose_expr ( \
311 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
312 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
313 __builtin_choose_expr ( \
314 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
315 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
316 __builtin_choose_expr ( \
317 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
318 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
319 __builtin_choose_expr ( \
320 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
321 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
322 __builtin_choose_expr ( \
323 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
324 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
325 __builtin_choose_expr ( \
326 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
327 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
328 __builtin_choose_expr ( \
329 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
330 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
331 __builtin_choose_expr ( \
332 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
333 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
334 __builtin_choose_expr ( \
335 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
336 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
337 __builtin_choose_expr ( \
338 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
339 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
340 __builtin_choose_expr ( \
341 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
342 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
343 __builtin_choose_expr ( \
344 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
345 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
346 __builtin_choose_expr ( \
347 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
348 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
349 __builtin_choose_expr ( \
350 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
351 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
352 __builtin_choose_expr ( \
353 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
354 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
355 __builtin_choose_expr ( \
356 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
357 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
358 __builtin_choose_expr ( \
359 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
360 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
361 __builtin_choose_expr ( \
362 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
363 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
364 __builtin_choose_expr ( \
365 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
366 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
367 __builtin_choose_expr ( \
368 __builtin_types_compatible_p (__typeof (o), void*), \
369 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
370 /* The void expression results in a compile-time error \
371 when assigning the result to something. */ \
372 (void)0)))))))))))))))))))))))))))))))
374 /* Whenever we generate an error, pass it through this function. Useful for
375 * debugging, where we can break on it. Only call at error site, not when
376 * propagating errors. Might be useful to plug in a stack trace here.
379 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
380 VkDebugReportObjectTypeEXT type
, VkResult error
,
381 const char *file
, int line
, const char *format
, ...);
384 #define vk_error(error) __vk_errorf(NULL, NULL,\
385 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
386 error, __FILE__, __LINE__, NULL)
387 #define vk_errorf(instance, obj, error, format, ...)\
388 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
389 __FILE__, __LINE__, format, ## __VA_ARGS__)
391 #define vk_error(error) error
392 #define vk_errorf(instance, obj, error, format, ...) error
396 * Warn on ignored extension structs.
398 * The Vulkan spec requires us to ignore unsupported or unknown structs in
399 * a pNext chain. In debug mode, emitting warnings for ignored structs may
400 * help us discover structs that we should not have ignored.
403 * From the Vulkan 1.0.38 spec:
405 * Any component of the implementation (the loader, any enabled layers,
406 * and drivers) must skip over, without processing (other than reading the
407 * sType and pNext members) any chained structures with sType values not
408 * defined by extensions supported by that component.
410 #define anv_debug_ignored_stype(sType) \
411 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
413 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
414 VkDebugReportObjectTypeEXT type
, const char *file
,
415 int line
, const char *format
, ...)
416 anv_printflike(6, 7);
417 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
418 void anv_loge_v(const char *format
, va_list va
);
421 * Print a FINISHME message, including its source location.
423 #define anv_finishme(format, ...) \
425 static bool reported = false; \
427 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
434 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
436 #define anv_perf_warn(instance, obj, format, ...) \
438 static bool reported = false; \
439 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
440 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
441 format, ##__VA_ARGS__); \
446 /* A non-fatal assert. Useful for debugging. */
448 #define anv_assert(x) ({ \
449 if (unlikely(!(x))) \
450 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
453 #define anv_assert(x)
456 /* A multi-pointer allocator
458 * When copying data structures from the user (such as a render pass), it's
459 * common to need to allocate data for a bunch of different things. Instead
460 * of doing several allocations and having to handle all of the error checking
461 * that entails, it can be easier to do a single allocation. This struct
462 * helps facilitate that. The intended usage looks like this:
465 * anv_multialloc_add(&ma, &main_ptr, 1);
466 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
467 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
469 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
470 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
472 struct anv_multialloc
{
480 #define ANV_MULTIALLOC_INIT \
481 ((struct anv_multialloc) { 0, })
483 #define ANV_MULTIALLOC(_name) \
484 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
486 __attribute__((always_inline
))
488 _anv_multialloc_add(struct anv_multialloc
*ma
,
489 void **ptr
, size_t size
, size_t align
)
491 size_t offset
= align_u64(ma
->size
, align
);
492 ma
->size
= offset
+ size
;
493 ma
->align
= MAX2(ma
->align
, align
);
495 /* Store the offset in the pointer. */
496 *ptr
= (void *)(uintptr_t)offset
;
498 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
499 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
502 #define anv_multialloc_add_size(_ma, _ptr, _size) \
503 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
505 #define anv_multialloc_add(_ma, _ptr, _count) \
506 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
508 __attribute__((always_inline
))
510 anv_multialloc_alloc(struct anv_multialloc
*ma
,
511 const VkAllocationCallbacks
*alloc
,
512 VkSystemAllocationScope scope
)
514 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
518 /* Fill out each of the pointers with their final value.
520 * for (uint32_t i = 0; i < ma->ptr_count; i++)
521 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
523 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
524 * constant, GCC is incapable of figuring this out and unrolling the loop
525 * so we have to give it a little help.
527 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
528 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
529 if ((_i) < ma->ptr_count) \
530 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
531 _ANV_MULTIALLOC_UPDATE_POINTER(0);
532 _ANV_MULTIALLOC_UPDATE_POINTER(1);
533 _ANV_MULTIALLOC_UPDATE_POINTER(2);
534 _ANV_MULTIALLOC_UPDATE_POINTER(3);
535 _ANV_MULTIALLOC_UPDATE_POINTER(4);
536 _ANV_MULTIALLOC_UPDATE_POINTER(5);
537 _ANV_MULTIALLOC_UPDATE_POINTER(6);
538 _ANV_MULTIALLOC_UPDATE_POINTER(7);
539 #undef _ANV_MULTIALLOC_UPDATE_POINTER
544 __attribute__((always_inline
))
546 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
547 const VkAllocationCallbacks
*parent_alloc
,
548 const VkAllocationCallbacks
*alloc
,
549 VkSystemAllocationScope scope
)
551 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
557 /* Index into the current validation list. This is used by the
558 * validation list building alrogithm to track which buffers are already
559 * in the validation list so that we can ensure uniqueness.
563 /* Last known offset. This value is provided by the kernel when we
564 * execbuf and is used as the presumed offset for the next bunch of
572 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
577 anv_bo_init(struct anv_bo
*bo
, uint32_t gem_handle
, uint64_t size
)
579 bo
->gem_handle
= gem_handle
;
587 /* Represents a lock-free linked list of "free" things. This is used by
588 * both the block pool and the state pools. Unfortunately, in order to
589 * solve the ABA problem, we can't use a single uint32_t head.
591 union anv_free_list
{
595 /* A simple count that is incremented every time the head changes. */
601 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
603 struct anv_block_state
{
613 struct anv_block_pool
{
614 struct anv_device
*device
;
620 /* The offset from the start of the bo to the "center" of the block
621 * pool. Pointers to allocated blocks are given by
622 * bo.map + center_bo_offset + offsets.
624 uint32_t center_bo_offset
;
626 /* Current memory map of the block pool. This pointer may or may not
627 * point to the actual beginning of the block pool memory. If
628 * anv_block_pool_alloc_back has ever been called, then this pointer
629 * will point to the "center" position of the buffer and all offsets
630 * (negative or positive) given out by the block pool alloc functions
631 * will be valid relative to this pointer.
633 * In particular, map == bo.map + center_offset
639 * Array of mmaps and gem handles owned by the block pool, reclaimed when
640 * the block pool is destroyed.
642 struct u_vector mmap_cleanups
;
644 struct anv_block_state state
;
646 struct anv_block_state back_state
;
649 /* Block pools are backed by a fixed-size 1GB memfd */
650 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
652 /* The center of the block pool is also the middle of the memfd. This may
653 * change in the future if we decide differently for some reason.
655 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
657 static inline uint32_t
658 anv_block_pool_size(struct anv_block_pool
*pool
)
660 return pool
->state
.end
+ pool
->back_state
.end
;
669 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
671 struct anv_fixed_size_state_pool
{
672 union anv_free_list free_list
;
673 struct anv_block_state block
;
676 #define ANV_MIN_STATE_SIZE_LOG2 6
677 #define ANV_MAX_STATE_SIZE_LOG2 20
679 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
681 struct anv_state_pool
{
682 struct anv_block_pool block_pool
;
684 /* The size of blocks which will be allocated from the block pool */
687 /** Free list for "back" allocations */
688 union anv_free_list back_alloc_free_list
;
690 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
693 struct anv_state_stream_block
;
695 struct anv_state_stream
{
696 struct anv_state_pool
*state_pool
;
698 /* The size of blocks to allocate from the state pool */
701 /* Current block we're allocating from */
702 struct anv_state block
;
704 /* Offset into the current block at which to allocate the next state */
707 /* List of all blocks allocated from this pool */
708 struct anv_state_stream_block
*block_list
;
711 /* The block_pool functions exported for testing only. The block pool should
712 * only be used via a state pool (see below).
714 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
715 struct anv_device
*device
,
716 uint32_t initial_size
,
718 void anv_block_pool_finish(struct anv_block_pool
*pool
);
719 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
720 uint32_t block_size
);
721 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
722 uint32_t block_size
);
724 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
725 struct anv_device
*device
,
728 void anv_state_pool_finish(struct anv_state_pool
*pool
);
729 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
730 uint32_t state_size
, uint32_t alignment
);
731 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
732 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
733 void anv_state_stream_init(struct anv_state_stream
*stream
,
734 struct anv_state_pool
*state_pool
,
735 uint32_t block_size
);
736 void anv_state_stream_finish(struct anv_state_stream
*stream
);
737 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
738 uint32_t size
, uint32_t alignment
);
741 * Implements a pool of re-usable BOs. The interface is identical to that
742 * of block_pool except that each block is its own BO.
745 struct anv_device
*device
;
752 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
,
754 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
755 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, struct anv_bo
*bo
,
757 void anv_bo_pool_free(struct anv_bo_pool
*pool
, const struct anv_bo
*bo
);
759 struct anv_scratch_bo
{
764 struct anv_scratch_pool
{
765 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
766 struct anv_scratch_bo bos
[16][MESA_SHADER_STAGES
];
769 void anv_scratch_pool_init(struct anv_device
*device
,
770 struct anv_scratch_pool
*pool
);
771 void anv_scratch_pool_finish(struct anv_device
*device
,
772 struct anv_scratch_pool
*pool
);
773 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
774 struct anv_scratch_pool
*pool
,
775 gl_shader_stage stage
,
776 unsigned per_thread_scratch
);
778 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
779 struct anv_bo_cache
{
780 struct hash_table
*bo_map
;
781 pthread_mutex_t mutex
;
784 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
785 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
786 VkResult
anv_bo_cache_alloc(struct anv_device
*device
,
787 struct anv_bo_cache
*cache
,
788 uint64_t size
, struct anv_bo
**bo
);
789 VkResult
anv_bo_cache_import(struct anv_device
*device
,
790 struct anv_bo_cache
*cache
,
791 int fd
, struct anv_bo
**bo
);
792 VkResult
anv_bo_cache_export(struct anv_device
*device
,
793 struct anv_bo_cache
*cache
,
794 struct anv_bo
*bo_in
, int *fd_out
);
795 void anv_bo_cache_release(struct anv_device
*device
,
796 struct anv_bo_cache
*cache
,
799 struct anv_memory_type
{
800 /* Standard bits passed on to the client */
801 VkMemoryPropertyFlags propertyFlags
;
804 /* Driver-internal book-keeping */
805 VkBufferUsageFlags valid_buffer_usage
;
808 struct anv_memory_heap
{
809 /* Standard bits passed on to the client */
811 VkMemoryHeapFlags flags
;
813 /* Driver-internal book-keeping */
814 bool supports_48bit_addresses
;
817 struct anv_physical_device
{
818 VK_LOADER_DATA _loader_data
;
820 struct anv_instance
* instance
;
825 struct gen_device_info info
;
826 /** Amount of "GPU memory" we want to advertise
828 * Clearly, this value is bogus since Intel is a UMA architecture. On
829 * gen7 platforms, we are limited by GTT size unless we want to implement
830 * fine-grained tracking and GTT splitting. On Broadwell and above we are
831 * practically unlimited. However, we will never report more than 3/4 of
832 * the total system ram to try and avoid running out of RAM.
834 bool supports_48bit_addresses
;
835 struct brw_compiler
* compiler
;
836 struct isl_device isl_dev
;
837 int cmd_parser_version
;
839 bool has_exec_capture
;
842 bool has_syncobj_wait
;
843 bool has_context_priority
;
846 struct anv_device_extension_table supported_extensions
;
849 uint32_t subslice_total
;
853 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
855 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
858 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
859 uint8_t driver_uuid
[VK_UUID_SIZE
];
860 uint8_t device_uuid
[VK_UUID_SIZE
];
862 struct wsi_device wsi_device
;
866 struct anv_instance
{
867 VK_LOADER_DATA _loader_data
;
869 VkAllocationCallbacks alloc
;
872 struct anv_instance_extension_table enabled_extensions
;
873 struct anv_dispatch_table dispatch
;
875 int physicalDeviceCount
;
876 struct anv_physical_device physicalDevice
;
878 struct vk_debug_report_instance debug_report_callbacks
;
881 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
882 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
884 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
885 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
889 VK_LOADER_DATA _loader_data
;
891 struct anv_device
* device
;
893 VkDeviceQueueCreateFlags flags
;
896 struct anv_pipeline_cache
{
897 struct anv_device
* device
;
898 pthread_mutex_t mutex
;
900 struct hash_table
* cache
;
903 struct anv_pipeline_bind_map
;
905 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
906 struct anv_device
*device
,
908 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
910 struct anv_shader_bin
*
911 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
912 const void *key
, uint32_t key_size
);
913 struct anv_shader_bin
*
914 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
915 const void *key_data
, uint32_t key_size
,
916 const void *kernel_data
, uint32_t kernel_size
,
917 const struct brw_stage_prog_data
*prog_data
,
918 uint32_t prog_data_size
,
919 const struct anv_pipeline_bind_map
*bind_map
);
922 VK_LOADER_DATA _loader_data
;
924 VkAllocationCallbacks alloc
;
926 struct anv_instance
* instance
;
929 struct gen_device_info info
;
930 struct isl_device isl_dev
;
933 bool can_chain_batches
;
934 bool robust_buffer_access
;
935 struct anv_device_extension_table enabled_extensions
;
936 struct anv_dispatch_table dispatch
;
938 pthread_mutex_t vma_mutex
;
939 struct util_vma_heap vma_lo
;
940 struct util_vma_heap vma_hi
;
941 uint64_t vma_lo_available
;
942 uint64_t vma_hi_available
;
944 struct anv_bo_pool batch_bo_pool
;
946 struct anv_bo_cache bo_cache
;
948 struct anv_state_pool dynamic_state_pool
;
949 struct anv_state_pool instruction_state_pool
;
950 struct anv_state_pool surface_state_pool
;
952 struct anv_bo workaround_bo
;
953 struct anv_bo trivial_batch_bo
;
954 struct anv_bo hiz_clear_bo
;
956 struct anv_pipeline_cache blorp_shader_cache
;
957 struct blorp_context blorp
;
959 struct anv_state border_colors
;
961 struct anv_queue queue
;
963 struct anv_scratch_pool scratch_pool
;
965 uint32_t default_mocs
;
967 pthread_mutex_t mutex
;
968 pthread_cond_t queue_submit
;
973 anv_state_flush(struct anv_device
*device
, struct anv_state state
)
975 if (device
->info
.has_llc
)
978 gen_flush_range(state
.map
, state
.alloc_size
);
981 void anv_device_init_blorp(struct anv_device
*device
);
982 void anv_device_finish_blorp(struct anv_device
*device
);
984 VkResult
anv_device_execbuf(struct anv_device
*device
,
985 struct drm_i915_gem_execbuffer2
*execbuf
,
986 struct anv_bo
**execbuf_bos
);
987 VkResult
anv_device_query_status(struct anv_device
*device
);
988 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
989 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
992 void* anv_gem_mmap(struct anv_device
*device
,
993 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
994 void anv_gem_munmap(void *p
, uint64_t size
);
995 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
996 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
997 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
998 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
999 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1000 int anv_gem_execbuffer(struct anv_device
*device
,
1001 struct drm_i915_gem_execbuffer2
*execbuf
);
1002 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1003 uint32_t stride
, uint32_t tiling
);
1004 int anv_gem_create_context(struct anv_device
*device
);
1005 bool anv_gem_has_context_priority(int fd
);
1006 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1007 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1009 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1011 int anv_gem_get_param(int fd
, uint32_t param
);
1012 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1013 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1014 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1015 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1016 uint32_t *active
, uint32_t *pending
);
1017 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1018 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1019 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1020 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1021 uint32_t read_domains
, uint32_t write_domain
);
1022 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1023 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1024 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1025 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1026 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1027 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1029 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1030 uint32_t handle
, int fd
);
1031 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1032 bool anv_gem_supports_syncobj_wait(int fd
);
1033 int anv_gem_syncobj_wait(struct anv_device
*device
,
1034 uint32_t *handles
, uint32_t num_handles
,
1035 int64_t abs_timeout_ns
, bool wait_all
);
1037 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1038 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1040 VkResult
anv_bo_init_new(struct anv_bo
*bo
, struct anv_device
*device
, uint64_t size
);
1042 struct anv_reloc_list
{
1043 uint32_t num_relocs
;
1044 uint32_t array_length
;
1045 struct drm_i915_gem_relocation_entry
* relocs
;
1046 struct anv_bo
** reloc_bos
;
1049 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1050 const VkAllocationCallbacks
*alloc
);
1051 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1052 const VkAllocationCallbacks
*alloc
);
1054 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1055 const VkAllocationCallbacks
*alloc
,
1056 uint32_t offset
, struct anv_bo
*target_bo
,
1059 struct anv_batch_bo
{
1060 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1061 struct list_head link
;
1065 /* Bytes actually consumed in this batch BO */
1068 struct anv_reloc_list relocs
;
1072 const VkAllocationCallbacks
* alloc
;
1078 struct anv_reloc_list
* relocs
;
1080 /* This callback is called (with the associated user data) in the event
1081 * that the batch runs out of space.
1083 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1087 * Current error status of the command buffer. Used to track inconsistent
1088 * or incomplete command buffer states that are the consequence of run-time
1089 * errors such as out of memory scenarios. We want to track this in the
1090 * batch because the command buffer object is not visible to some parts
1096 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1097 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1098 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1099 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1100 VkResult
anv_device_submit_simple_batch(struct anv_device
*device
,
1101 struct anv_batch
*batch
);
1103 static inline VkResult
1104 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1106 assert(error
!= VK_SUCCESS
);
1107 if (batch
->status
== VK_SUCCESS
)
1108 batch
->status
= error
;
1109 return batch
->status
;
1113 anv_batch_has_error(struct anv_batch
*batch
)
1115 return batch
->status
!= VK_SUCCESS
;
1118 struct anv_address
{
1123 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1126 anv_address_is_null(struct anv_address addr
)
1128 return addr
.bo
== NULL
&& addr
.offset
== 0;
1131 static inline uint64_t
1132 anv_address_physical(struct anv_address addr
)
1134 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1135 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1137 return gen_canonical_address(addr
.offset
);
1140 static inline struct anv_address
1141 anv_address_add(struct anv_address addr
, uint64_t offset
)
1143 addr
.offset
+= offset
;
1147 static inline uint64_t
1148 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1149 const struct anv_address address
, uint32_t delta
)
1151 if (address
.bo
== NULL
) {
1152 return address
.offset
+ delta
;
1154 assert(batch
->start
<= location
&& location
< batch
->end
);
1156 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1160 #define __gen_address_type struct anv_address
1161 #define __gen_user_data struct anv_batch
1162 #define __gen_combine_address _anv_combine_address
1164 /* Wrapper macros needed to work around preprocessor argument issues. In
1165 * particular, arguments don't get pre-evaluated if they are concatenated.
1166 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1167 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1168 * We can work around this easily enough with these helpers.
1170 #define __anv_cmd_length(cmd) cmd ## _length
1171 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1172 #define __anv_cmd_header(cmd) cmd ## _header
1173 #define __anv_cmd_pack(cmd) cmd ## _pack
1174 #define __anv_reg_num(reg) reg ## _num
1176 #define anv_pack_struct(dst, struc, ...) do { \
1177 struct struc __template = { \
1180 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1181 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1184 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1185 void *__dst = anv_batch_emit_dwords(batch, n); \
1187 struct cmd __template = { \
1188 __anv_cmd_header(cmd), \
1189 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1192 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1197 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1201 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1202 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1205 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1206 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1207 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1210 #define anv_batch_emit(batch, cmd, name) \
1211 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1212 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1213 __builtin_expect(_dst != NULL, 1); \
1214 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1215 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1219 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1220 .GraphicsDataTypeGFDT = 0, \
1221 .LLCCacheabilityControlLLCCC = 0, \
1222 .L3CacheabilityControlL3CC = 1, \
1225 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1226 .LLCeLLCCacheabilityControlLLCCC = 0, \
1227 .L3CacheabilityControlL3CC = 1, \
1230 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1231 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1232 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1233 .AgeforQUADLRU = 0 \
1236 /* Skylake: MOCS is now an index into an array of 62 different caching
1237 * configurations programmed by the kernel.
1240 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1241 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1242 .IndextoMOCSTables = 2 \
1245 #define GEN9_MOCS_PTE { \
1246 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1247 .IndextoMOCSTables = 1 \
1250 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1251 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1252 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1253 .IndextoMOCSTables = 2 \
1256 #define GEN10_MOCS_PTE { \
1257 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1258 .IndextoMOCSTables = 1 \
1261 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1262 #define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1263 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1264 .IndextoMOCSTables = 2 \
1267 #define GEN11_MOCS_PTE { \
1268 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1269 .IndextoMOCSTables = 1 \
1272 struct anv_device_memory
{
1274 struct anv_memory_type
* type
;
1275 VkDeviceSize map_size
;
1280 * Header for Vertex URB Entry (VUE)
1282 struct anv_vue_header
{
1284 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1285 uint32_t ViewportIndex
;
1289 struct anv_descriptor_set_binding_layout
{
1291 /* The type of the descriptors in this binding */
1292 VkDescriptorType type
;
1295 /* Number of array elements in this binding */
1296 uint16_t array_size
;
1298 /* Index into the flattend descriptor set */
1299 uint16_t descriptor_index
;
1301 /* Index into the dynamic state array for a dynamic buffer */
1302 int16_t dynamic_offset_index
;
1304 /* Index into the descriptor set buffer views */
1305 int16_t buffer_index
;
1308 /* Index into the binding table for the associated surface */
1309 int16_t surface_index
;
1311 /* Index into the sampler table for the associated sampler */
1312 int16_t sampler_index
;
1314 /* Index into the image table for the associated image */
1315 int16_t image_index
;
1316 } stage
[MESA_SHADER_STAGES
];
1318 /* Immutable samplers (or NULL if no immutable samplers) */
1319 struct anv_sampler
**immutable_samplers
;
1322 struct anv_descriptor_set_layout
{
1323 /* Descriptor set layouts can be destroyed at almost any time */
1326 /* Number of bindings in this descriptor set */
1327 uint16_t binding_count
;
1329 /* Total size of the descriptor set with room for all array entries */
1332 /* Shader stages affected by this descriptor set */
1333 uint16_t shader_stages
;
1335 /* Number of buffers in this descriptor set */
1336 uint16_t buffer_count
;
1338 /* Number of dynamic offsets used by this descriptor set */
1339 uint16_t dynamic_offset_count
;
1341 /* Bindings in this descriptor set */
1342 struct anv_descriptor_set_binding_layout binding
[0];
1346 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1348 assert(layout
&& layout
->ref_cnt
>= 1);
1349 p_atomic_inc(&layout
->ref_cnt
);
1353 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1354 struct anv_descriptor_set_layout
*layout
)
1356 assert(layout
&& layout
->ref_cnt
>= 1);
1357 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1358 vk_free(&device
->alloc
, layout
);
1361 struct anv_descriptor
{
1362 VkDescriptorType type
;
1366 VkImageLayout layout
;
1367 struct anv_image_view
*image_view
;
1368 struct anv_sampler
*sampler
;
1372 struct anv_buffer
*buffer
;
1377 struct anv_buffer_view
*buffer_view
;
1381 struct anv_descriptor_set
{
1382 struct anv_descriptor_set_layout
*layout
;
1384 uint32_t buffer_count
;
1385 struct anv_buffer_view
*buffer_views
;
1386 struct anv_descriptor descriptors
[0];
1389 struct anv_buffer_view
{
1390 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1391 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1393 struct anv_address address
;
1395 struct anv_state surface_state
;
1396 struct anv_state storage_surface_state
;
1397 struct anv_state writeonly_storage_surface_state
;
1399 struct brw_image_param storage_image_param
;
1402 struct anv_push_descriptor_set
{
1403 struct anv_descriptor_set set
;
1405 /* Put this field right behind anv_descriptor_set so it fills up the
1406 * descriptors[0] field. */
1407 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1408 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1411 struct anv_descriptor_pool
{
1416 struct anv_state_stream surface_state_stream
;
1417 void *surface_state_free_list
;
1422 enum anv_descriptor_template_entry_type
{
1423 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1424 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1425 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1428 struct anv_descriptor_template_entry
{
1429 /* The type of descriptor in this entry */
1430 VkDescriptorType type
;
1432 /* Binding in the descriptor set */
1435 /* Offset at which to write into the descriptor set binding */
1436 uint32_t array_element
;
1438 /* Number of elements to write into the descriptor set binding */
1439 uint32_t array_count
;
1441 /* Offset into the user provided data */
1444 /* Stride between elements into the user provided data */
1448 struct anv_descriptor_update_template
{
1449 VkPipelineBindPoint bind_point
;
1451 /* The descriptor set this template corresponds to. This value is only
1452 * valid if the template was created with the templateType
1453 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1457 /* Number of entries in this template */
1458 uint32_t entry_count
;
1460 /* Entries of the template */
1461 struct anv_descriptor_template_entry entries
[0];
1465 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout
*binding
);
1468 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1471 anv_descriptor_set_write_image_view(struct anv_descriptor_set
*set
,
1472 const struct gen_device_info
* const devinfo
,
1473 const VkDescriptorImageInfo
* const info
,
1474 VkDescriptorType type
,
1479 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set
*set
,
1480 VkDescriptorType type
,
1481 struct anv_buffer_view
*buffer_view
,
1486 anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set
,
1487 struct anv_device
*device
,
1488 struct anv_state_stream
*alloc_stream
,
1489 VkDescriptorType type
,
1490 struct anv_buffer
*buffer
,
1493 VkDeviceSize offset
,
1494 VkDeviceSize range
);
1497 anv_descriptor_set_write_template(struct anv_descriptor_set
*set
,
1498 struct anv_device
*device
,
1499 struct anv_state_stream
*alloc_stream
,
1500 const struct anv_descriptor_update_template
*template,
1504 anv_descriptor_set_create(struct anv_device
*device
,
1505 struct anv_descriptor_pool
*pool
,
1506 struct anv_descriptor_set_layout
*layout
,
1507 struct anv_descriptor_set
**out_set
);
1510 anv_descriptor_set_destroy(struct anv_device
*device
,
1511 struct anv_descriptor_pool
*pool
,
1512 struct anv_descriptor_set
*set
);
1514 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1516 struct anv_pipeline_binding
{
1517 /* The descriptor set this surface corresponds to. The special value of
1518 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1519 * to a color attachment and not a regular descriptor.
1523 /* Binding in the descriptor set */
1526 /* Index in the binding */
1529 /* Plane in the binding index */
1532 /* Input attachment index (relative to the subpass) */
1533 uint8_t input_attachment_index
;
1535 /* For a storage image, whether it is write-only */
1539 struct anv_pipeline_layout
{
1541 struct anv_descriptor_set_layout
*layout
;
1542 uint32_t dynamic_offset_start
;
1548 bool has_dynamic_offsets
;
1549 } stage
[MESA_SHADER_STAGES
];
1551 unsigned char sha1
[20];
1555 struct anv_device
* device
;
1558 VkBufferUsageFlags usage
;
1560 /* Set when bound */
1561 struct anv_address address
;
1564 static inline uint64_t
1565 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
1567 assert(offset
<= buffer
->size
);
1568 if (range
== VK_WHOLE_SIZE
) {
1569 return buffer
->size
- offset
;
1571 assert(range
<= buffer
->size
);
1576 enum anv_cmd_dirty_bits
{
1577 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1578 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1579 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1580 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1581 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1582 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1583 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1584 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1585 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1586 ANV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
1587 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
1588 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
1589 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
1591 typedef uint32_t anv_cmd_dirty_mask_t
;
1593 enum anv_pipe_bits
{
1594 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
1595 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
1596 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
1597 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
1598 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
1599 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
1600 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
1601 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
1602 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
1603 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
1604 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
1606 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1607 * a flush has happened but not a CS stall. The next time we do any sort
1608 * of invalidation we need to insert a CS stall at that time. Otherwise,
1609 * we would have to CS stall on every flush which could be bad.
1611 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
1614 #define ANV_PIPE_FLUSH_BITS ( \
1615 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1616 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1617 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1619 #define ANV_PIPE_STALL_BITS ( \
1620 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1621 ANV_PIPE_DEPTH_STALL_BIT | \
1622 ANV_PIPE_CS_STALL_BIT)
1624 #define ANV_PIPE_INVALIDATE_BITS ( \
1625 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1626 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1627 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1628 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1629 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1630 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1632 static inline enum anv_pipe_bits
1633 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
1635 enum anv_pipe_bits pipe_bits
= 0;
1638 for_each_bit(b
, flags
) {
1639 switch ((VkAccessFlagBits
)(1 << b
)) {
1640 case VK_ACCESS_SHADER_WRITE_BIT
:
1641 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1643 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
1644 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1646 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
1647 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1649 case VK_ACCESS_TRANSFER_WRITE_BIT
:
1650 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1651 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1654 break; /* Nothing to do */
1661 static inline enum anv_pipe_bits
1662 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
1664 enum anv_pipe_bits pipe_bits
= 0;
1667 for_each_bit(b
, flags
) {
1668 switch ((VkAccessFlagBits
)(1 << b
)) {
1669 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1670 case VK_ACCESS_INDEX_READ_BIT
:
1671 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1672 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1674 case VK_ACCESS_UNIFORM_READ_BIT
:
1675 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1676 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1678 case VK_ACCESS_SHADER_READ_BIT
:
1679 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1680 case VK_ACCESS_TRANSFER_READ_BIT
:
1681 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1684 break; /* Nothing to do */
1691 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1692 VK_IMAGE_ASPECT_COLOR_BIT | \
1693 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1694 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1695 VK_IMAGE_ASPECT_PLANE_2_BIT)
1696 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1697 VK_IMAGE_ASPECT_PLANE_0_BIT | \
1698 VK_IMAGE_ASPECT_PLANE_1_BIT | \
1699 VK_IMAGE_ASPECT_PLANE_2_BIT)
1701 struct anv_vertex_binding
{
1702 struct anv_buffer
* buffer
;
1703 VkDeviceSize offset
;
1706 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1707 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1709 struct anv_push_constants
{
1710 /* Current allocated size of this push constants data structure.
1711 * Because a decent chunk of it may not be used (images on SKL, for
1712 * instance), we won't actually allocate the entire structure up-front.
1716 /* Push constant data provided by the client through vkPushConstants */
1717 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
1719 /* Used for vkCmdDispatchBase */
1720 uint32_t base_work_group_id
[3];
1722 /* Image data for image_load_store on pre-SKL */
1723 struct brw_image_param images
[MAX_IMAGES
];
1726 struct anv_dynamic_state
{
1729 VkViewport viewports
[MAX_VIEWPORTS
];
1734 VkRect2D scissors
[MAX_SCISSORS
];
1745 float blend_constants
[4];
1755 } stencil_compare_mask
;
1760 } stencil_write_mask
;
1765 } stencil_reference
;
1768 extern const struct anv_dynamic_state default_dynamic_state
;
1770 void anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
1771 const struct anv_dynamic_state
*src
,
1772 uint32_t copy_mask
);
1774 struct anv_surface_state
{
1775 struct anv_state state
;
1776 /** Address of the surface referred to by this state
1778 * This address is relative to the start of the BO.
1780 struct anv_address address
;
1781 /* Address of the aux surface, if any
1783 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
1785 * With the exception of gen8, the bottom 12 bits of this address' offset
1786 * include extra aux information.
1788 struct anv_address aux_address
;
1789 /* Address of the clear color, if any
1791 * This address is relative to the start of the BO.
1793 struct anv_address clear_address
;
1797 * Attachment state when recording a renderpass instance.
1799 * The clear value is valid only if there exists a pending clear.
1801 struct anv_attachment_state
{
1802 enum isl_aux_usage aux_usage
;
1803 enum isl_aux_usage input_aux_usage
;
1804 struct anv_surface_state color
;
1805 struct anv_surface_state input
;
1807 VkImageLayout current_layout
;
1808 VkImageAspectFlags pending_clear_aspects
;
1809 VkImageAspectFlags pending_load_aspects
;
1811 VkClearValue clear_value
;
1812 bool clear_color_is_zero_one
;
1813 bool clear_color_is_zero
;
1815 /* When multiview is active, attachments with a renderpass clear
1816 * operation have their respective layers cleared on the first
1817 * subpass that uses them, and only in that subpass. We keep track
1818 * of this using a bitfield to indicate which layers of an attachment
1819 * have not been cleared yet when multiview is active.
1821 uint32_t pending_clear_views
;
1824 /** State tracking for particular pipeline bind point
1826 * This struct is the base struct for anv_cmd_graphics_state and
1827 * anv_cmd_compute_state. These are used to track state which is bound to a
1828 * particular type of pipeline. Generic state that applies per-stage such as
1829 * binding table offsets and push constants is tracked generically with a
1830 * per-stage array in anv_cmd_state.
1832 struct anv_cmd_pipeline_state
{
1833 struct anv_pipeline
*pipeline
;
1834 struct anv_pipeline_layout
*layout
;
1836 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
1837 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
1839 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
1842 /** State tracking for graphics pipeline
1844 * This has anv_cmd_pipeline_state as a base struct to track things which get
1845 * bound to a graphics pipeline. Along with general pipeline bind point state
1846 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1847 * state which is graphics-specific.
1849 struct anv_cmd_graphics_state
{
1850 struct anv_cmd_pipeline_state base
;
1852 anv_cmd_dirty_mask_t dirty
;
1855 struct anv_dynamic_state dynamic
;
1858 struct anv_buffer
*index_buffer
;
1859 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1860 uint32_t index_offset
;
1864 /** State tracking for compute pipeline
1866 * This has anv_cmd_pipeline_state as a base struct to track things which get
1867 * bound to a compute pipeline. Along with general pipeline bind point state
1868 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1869 * state which is compute-specific.
1871 struct anv_cmd_compute_state
{
1872 struct anv_cmd_pipeline_state base
;
1874 bool pipeline_dirty
;
1876 struct anv_address num_workgroups
;
1879 /** State required while building cmd buffer */
1880 struct anv_cmd_state
{
1881 /* PIPELINE_SELECT.PipelineSelection */
1882 uint32_t current_pipeline
;
1883 const struct gen_l3_config
* current_l3_config
;
1885 struct anv_cmd_graphics_state gfx
;
1886 struct anv_cmd_compute_state compute
;
1888 enum anv_pipe_bits pending_pipe_bits
;
1889 VkShaderStageFlags descriptors_dirty
;
1890 VkShaderStageFlags push_constants_dirty
;
1892 struct anv_framebuffer
* framebuffer
;
1893 struct anv_render_pass
* pass
;
1894 struct anv_subpass
* subpass
;
1895 VkRect2D render_area
;
1896 uint32_t restart_index
;
1897 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
1898 VkShaderStageFlags push_constant_stages
;
1899 struct anv_push_constants
* push_constants
[MESA_SHADER_STAGES
];
1900 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
1901 struct anv_state samplers
[MESA_SHADER_STAGES
];
1904 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1905 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1906 * and before invoking the secondary in ExecuteCommands.
1908 bool pma_fix_enabled
;
1911 * Whether or not we know for certain that HiZ is enabled for the current
1912 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1913 * enabled or not, this will be false.
1918 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1919 * valid only when recording a render pass instance.
1921 struct anv_attachment_state
* attachments
;
1924 * Surface states for color render targets. These are stored in a single
1925 * flat array. For depth-stencil attachments, the surface state is simply
1928 struct anv_state render_pass_states
;
1931 * A null surface state of the right size to match the framebuffer. This
1932 * is one of the states in render_pass_states.
1934 struct anv_state null_surface_state
;
1937 struct anv_cmd_pool
{
1938 VkAllocationCallbacks alloc
;
1939 struct list_head cmd_buffers
;
1942 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1944 enum anv_cmd_buffer_exec_mode
{
1945 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
1946 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
1947 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
1948 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
1949 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
1952 struct anv_cmd_buffer
{
1953 VK_LOADER_DATA _loader_data
;
1955 struct anv_device
* device
;
1957 struct anv_cmd_pool
* pool
;
1958 struct list_head pool_link
;
1960 struct anv_batch batch
;
1962 /* Fields required for the actual chain of anv_batch_bo's.
1964 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1966 struct list_head batch_bos
;
1967 enum anv_cmd_buffer_exec_mode exec_mode
;
1969 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1970 * referenced by this command buffer
1972 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1974 struct u_vector seen_bbos
;
1976 /* A vector of int32_t's for every block of binding tables.
1978 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1980 struct u_vector bt_block_states
;
1983 struct anv_reloc_list surface_relocs
;
1984 /** Last seen surface state block pool center bo offset */
1985 uint32_t last_ss_pool_center
;
1987 /* Serial for tracking buffer completion */
1990 /* Stream objects for storing temporary data */
1991 struct anv_state_stream surface_state_stream
;
1992 struct anv_state_stream dynamic_state_stream
;
1994 VkCommandBufferUsageFlags usage_flags
;
1995 VkCommandBufferLevel level
;
1997 struct anv_cmd_state state
;
2000 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2001 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2002 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2003 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2004 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2005 struct anv_cmd_buffer
*secondary
);
2006 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2007 VkResult
anv_cmd_buffer_execbuf(struct anv_device
*device
,
2008 struct anv_cmd_buffer
*cmd_buffer
,
2009 const VkSemaphore
*in_semaphores
,
2010 uint32_t num_in_semaphores
,
2011 const VkSemaphore
*out_semaphores
,
2012 uint32_t num_out_semaphores
,
2015 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2018 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
2019 gl_shader_stage stage
, uint32_t size
);
2020 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
2021 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
2022 (offsetof(struct anv_push_constants, field) + \
2023 sizeof(cmd_buffer->state.push_constants[0]->field)))
2025 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2026 const void *data
, uint32_t size
, uint32_t alignment
);
2027 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2028 uint32_t *a
, uint32_t *b
,
2029 uint32_t dwords
, uint32_t alignment
);
2032 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2034 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2035 uint32_t entries
, uint32_t *state_offset
);
2037 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2039 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2040 uint32_t size
, uint32_t alignment
);
2043 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2045 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2046 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2047 bool depth_clamp_enable
);
2048 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2050 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2051 struct anv_render_pass
*pass
,
2052 struct anv_framebuffer
*framebuffer
,
2053 const VkClearValue
*clear_values
);
2055 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2058 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2059 gl_shader_stage stage
);
2061 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2063 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
);
2065 const struct anv_image_view
*
2066 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2069 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2070 uint32_t num_entries
,
2071 uint32_t *state_offset
,
2072 struct anv_state
*bt_state
);
2074 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2076 enum anv_fence_type
{
2077 ANV_FENCE_TYPE_NONE
= 0,
2079 ANV_FENCE_TYPE_SYNCOBJ
,
2082 enum anv_bo_fence_state
{
2083 /** Indicates that this is a new (or newly reset fence) */
2084 ANV_BO_FENCE_STATE_RESET
,
2086 /** Indicates that this fence has been submitted to the GPU but is still
2087 * (as far as we know) in use by the GPU.
2089 ANV_BO_FENCE_STATE_SUBMITTED
,
2091 ANV_BO_FENCE_STATE_SIGNALED
,
2094 struct anv_fence_impl
{
2095 enum anv_fence_type type
;
2098 /** Fence implementation for BO fences
2100 * These fences use a BO and a set of CPU-tracked state flags. The BO
2101 * is added to the object list of the last execbuf call in a QueueSubmit
2102 * and is marked EXEC_WRITE. The state flags track when the BO has been
2103 * submitted to the kernel. We need to do this because Vulkan lets you
2104 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2105 * will say it's idle in this case.
2109 enum anv_bo_fence_state state
;
2112 /** DRM syncobj handle for syncobj-based fences */
2118 /* Permanent fence state. Every fence has some form of permanent state
2119 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2120 * cross-process fences) or it could just be a dummy for use internally.
2122 struct anv_fence_impl permanent
;
2124 /* Temporary fence state. A fence *may* have temporary state. That state
2125 * is added to the fence by an import operation and is reset back to
2126 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2127 * state cannot be signaled because the fence must already be signaled
2128 * before the temporary state can be exported from the fence in the other
2129 * process and imported here.
2131 struct anv_fence_impl temporary
;
2136 struct anv_state state
;
2139 enum anv_semaphore_type
{
2140 ANV_SEMAPHORE_TYPE_NONE
= 0,
2141 ANV_SEMAPHORE_TYPE_DUMMY
,
2142 ANV_SEMAPHORE_TYPE_BO
,
2143 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2144 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2147 struct anv_semaphore_impl
{
2148 enum anv_semaphore_type type
;
2151 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2152 * This BO will be added to the object list on any execbuf2 calls for
2153 * which this semaphore is used as a wait or signal fence. When used as
2154 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2158 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2159 * If the semaphore is in the unsignaled state due to either just being
2160 * created or because it has been used for a wait, fd will be -1.
2164 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2165 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2166 * import so we don't need to bother with a userspace cache.
2172 struct anv_semaphore
{
2173 /* Permanent semaphore state. Every semaphore has some form of permanent
2174 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2175 * (for cross-process semaphores0 or it could just be a dummy for use
2178 struct anv_semaphore_impl permanent
;
2180 /* Temporary semaphore state. A semaphore *may* have temporary state.
2181 * That state is added to the semaphore by an import operation and is reset
2182 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2183 * semaphore with temporary state cannot be signaled because the semaphore
2184 * must already be signaled before the temporary state can be exported from
2185 * the semaphore in the other process and imported here.
2187 struct anv_semaphore_impl temporary
;
2190 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2191 struct anv_semaphore
*semaphore
);
2193 struct anv_shader_module
{
2194 unsigned char sha1
[20];
2199 static inline gl_shader_stage
2200 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2202 assert(__builtin_popcount(vk_stage
) == 1);
2203 return ffs(vk_stage
) - 1;
2206 static inline VkShaderStageFlagBits
2207 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2209 return (1 << mesa_stage
);
2212 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2214 #define anv_foreach_stage(stage, stage_bits) \
2215 for (gl_shader_stage stage, \
2216 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2217 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2218 __tmp &= ~(1 << (stage)))
2220 struct anv_pipeline_bind_map
{
2221 uint32_t surface_count
;
2222 uint32_t sampler_count
;
2223 uint32_t image_count
;
2225 struct anv_pipeline_binding
* surface_to_descriptor
;
2226 struct anv_pipeline_binding
* sampler_to_descriptor
;
2229 struct anv_shader_bin_key
{
2234 struct anv_shader_bin
{
2237 const struct anv_shader_bin_key
*key
;
2239 struct anv_state kernel
;
2240 uint32_t kernel_size
;
2242 const struct brw_stage_prog_data
*prog_data
;
2243 uint32_t prog_data_size
;
2245 struct anv_pipeline_bind_map bind_map
;
2248 struct anv_shader_bin
*
2249 anv_shader_bin_create(struct anv_device
*device
,
2250 const void *key
, uint32_t key_size
,
2251 const void *kernel
, uint32_t kernel_size
,
2252 const struct brw_stage_prog_data
*prog_data
,
2253 uint32_t prog_data_size
, const void *prog_data_param
,
2254 const struct anv_pipeline_bind_map
*bind_map
);
2257 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
2260 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
2262 assert(shader
&& shader
->ref_cnt
>= 1);
2263 p_atomic_inc(&shader
->ref_cnt
);
2267 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
2269 assert(shader
&& shader
->ref_cnt
>= 1);
2270 if (p_atomic_dec_zero(&shader
->ref_cnt
))
2271 anv_shader_bin_destroy(device
, shader
);
2274 struct anv_pipeline
{
2275 struct anv_device
* device
;
2276 struct anv_batch batch
;
2277 uint32_t batch_data
[512];
2278 struct anv_reloc_list batch_relocs
;
2279 uint32_t dynamic_state_mask
;
2280 struct anv_dynamic_state dynamic_state
;
2282 struct anv_subpass
* subpass
;
2284 bool needs_data_cache
;
2286 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
2289 const struct gen_l3_config
* l3_config
;
2290 uint32_t total_size
;
2293 VkShaderStageFlags active_stages
;
2294 struct anv_state blend_state
;
2297 uint32_t binding_stride
[MAX_VBS
];
2298 bool instancing_enable
[MAX_VBS
];
2299 bool primitive_restart
;
2302 uint32_t cs_right_mask
;
2305 bool depth_test_enable
;
2306 bool writes_stencil
;
2307 bool stencil_test_enable
;
2308 bool depth_clamp_enable
;
2309 bool sample_shading_enable
;
2314 uint32_t depth_stencil_state
[3];
2320 uint32_t wm_depth_stencil
[3];
2324 uint32_t wm_depth_stencil
[4];
2327 uint32_t interface_descriptor_data
[8];
2331 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
2332 gl_shader_stage stage
)
2334 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
2337 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2338 static inline const struct brw_##prefix##_prog_data * \
2339 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2341 if (anv_pipeline_has_stage(pipeline, stage)) { \
2342 return (const struct brw_##prefix##_prog_data *) \
2343 pipeline->shaders[stage]->prog_data; \
2349 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
2350 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
2351 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
2352 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
2353 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
2354 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
2356 static inline const struct brw_vue_prog_data
*
2357 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
2359 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
2360 return &get_gs_prog_data(pipeline
)->base
;
2361 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2362 return &get_tes_prog_data(pipeline
)->base
;
2364 return &get_vs_prog_data(pipeline
)->base
;
2368 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
2369 struct anv_pipeline_cache
*cache
,
2370 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2371 const VkAllocationCallbacks
*alloc
);
2374 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
2375 struct anv_pipeline_cache
*cache
,
2376 const VkComputePipelineCreateInfo
*info
,
2377 struct anv_shader_module
*module
,
2378 const char *entrypoint
,
2379 const VkSpecializationInfo
*spec_info
);
2381 struct anv_format_plane
{
2382 enum isl_format isl_format
:16;
2383 struct isl_swizzle swizzle
;
2385 /* Whether this plane contains chroma channels */
2388 /* For downscaling of YUV planes */
2389 uint8_t denominator_scales
[2];
2391 /* How to map sampled ycbcr planes to a single 4 component element. */
2392 struct isl_swizzle ycbcr_swizzle
;
2397 struct anv_format_plane planes
[3];
2402 static inline uint32_t
2403 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
2404 VkImageAspectFlags aspect_mask
)
2406 switch (aspect_mask
) {
2407 case VK_IMAGE_ASPECT_COLOR_BIT
:
2408 case VK_IMAGE_ASPECT_DEPTH_BIT
:
2409 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
2411 case VK_IMAGE_ASPECT_STENCIL_BIT
:
2412 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
2415 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
2417 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
2420 /* Purposefully assert with depth/stencil aspects. */
2421 unreachable("invalid image aspect");
2425 static inline uint32_t
2426 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask
)
2428 uint32_t planes
= 0;
2430 if (aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
|
2431 VK_IMAGE_ASPECT_DEPTH_BIT
|
2432 VK_IMAGE_ASPECT_STENCIL_BIT
|
2433 VK_IMAGE_ASPECT_PLANE_0_BIT
))
2435 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_1_BIT
)
2437 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_2_BIT
)
2440 if ((aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) != 0 &&
2441 (aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) != 0)
2447 static inline VkImageAspectFlags
2448 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
2451 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2452 if (_mesa_bitcount(image_aspects
) > 1)
2453 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
2454 return VK_IMAGE_ASPECT_COLOR_BIT
;
2456 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
2457 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
2458 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
2459 return VK_IMAGE_ASPECT_STENCIL_BIT
;
2462 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2463 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2465 const struct anv_format
*
2466 anv_get_format(VkFormat format
);
2468 static inline uint32_t
2469 anv_get_format_planes(VkFormat vk_format
)
2471 const struct anv_format
*format
= anv_get_format(vk_format
);
2473 return format
!= NULL
? format
->n_planes
: 0;
2476 struct anv_format_plane
2477 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2478 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
2480 static inline enum isl_format
2481 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
2482 VkImageAspectFlags aspect
, VkImageTiling tiling
)
2484 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
2487 static inline struct isl_swizzle
2488 anv_swizzle_for_render(struct isl_swizzle swizzle
)
2490 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2491 * RGB as RGBA for texturing
2493 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
2494 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
2496 /* But it doesn't matter what we render to that channel */
2497 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
2503 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
2506 * Subsurface of an anv_image.
2508 struct anv_surface
{
2509 /** Valid only if isl_surf::size > 0. */
2510 struct isl_surf isl
;
2513 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2520 /* The original VkFormat provided by the client. This may not match any
2521 * of the actual surface formats.
2524 const struct anv_format
*format
;
2526 VkImageAspectFlags aspects
;
2529 uint32_t array_size
;
2530 uint32_t samples
; /**< VkImageCreateInfo::samples */
2532 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
2533 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
2535 /** True if this is needs to be bound to an appropriately tiled BO.
2537 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2538 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2539 * we require a dedicated allocation so that we can know to allocate a
2542 bool needs_set_tiling
;
2545 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2546 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2548 uint64_t drm_format_mod
;
2553 /* Whether the image is made of several underlying buffer objects rather a
2554 * single one with different offsets.
2561 * For each foo, anv_image::planes[x].surface is valid if and only if
2562 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2563 * to figure the number associated with a given aspect.
2565 * The hardware requires that the depth buffer and stencil buffer be
2566 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2567 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2568 * allocate the depth and stencil buffers as separate surfaces in the same
2573 * -----------------------
2575 * ----------------------- |
2576 * | shadow surface0 | |
2577 * ----------------------- | Plane 0
2578 * | aux surface0 | |
2579 * ----------------------- |
2580 * | fast clear colors0 | \|/
2581 * -----------------------
2583 * ----------------------- |
2584 * | shadow surface1 | |
2585 * ----------------------- | Plane 1
2586 * | aux surface1 | |
2587 * ----------------------- |
2588 * | fast clear colors1 | \|/
2589 * -----------------------
2592 * -----------------------
2596 * Offset of the entire plane (whenever the image is disjoint this is
2604 struct anv_surface surface
;
2607 * A surface which shadows the main surface and may have different
2608 * tiling. This is used for sampling using a tiling that isn't supported
2609 * for other operations.
2611 struct anv_surface shadow_surface
;
2614 * For color images, this is the aux usage for this image when not used
2615 * as a color attachment.
2617 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2618 * image has a HiZ buffer.
2620 enum isl_aux_usage aux_usage
;
2622 struct anv_surface aux_surface
;
2625 * Offset of the fast clear state (used to compute the
2626 * fast_clear_state_offset of the following planes).
2628 uint32_t fast_clear_state_offset
;
2631 * BO associated with this plane, set when bound.
2634 VkDeviceSize bo_offset
;
2637 * When destroying the image, also free the bo.
2643 /* The ordering of this enum is important */
2644 enum anv_fast_clear_type
{
2645 /** Image does not have/support any fast-clear blocks */
2646 ANV_FAST_CLEAR_NONE
= 0,
2647 /** Image has/supports fast-clear but only to the default value */
2648 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
2649 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2650 ANV_FAST_CLEAR_ANY
= 2,
2653 /* Returns the number of auxiliary buffer levels attached to an image. */
2654 static inline uint8_t
2655 anv_image_aux_levels(const struct anv_image
* const image
,
2656 VkImageAspectFlagBits aspect
)
2658 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2659 return image
->planes
[plane
].aux_surface
.isl
.size
> 0 ?
2660 image
->planes
[plane
].aux_surface
.isl
.levels
: 0;
2663 /* Returns the number of auxiliary buffer layers attached to an image. */
2664 static inline uint32_t
2665 anv_image_aux_layers(const struct anv_image
* const image
,
2666 VkImageAspectFlagBits aspect
,
2667 const uint8_t miplevel
)
2671 /* The miplevel must exist in the main buffer. */
2672 assert(miplevel
< image
->levels
);
2674 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
2675 /* There are no layers with auxiliary data because the miplevel has no
2680 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2681 return MAX2(image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.array_len
,
2682 image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
.depth
>> miplevel
);
2686 static inline struct anv_address
2687 anv_image_get_clear_color_addr(const struct anv_device
*device
,
2688 const struct anv_image
*image
,
2689 VkImageAspectFlagBits aspect
)
2691 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
2693 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2694 return (struct anv_address
) {
2695 .bo
= image
->planes
[plane
].bo
,
2696 .offset
= image
->planes
[plane
].bo_offset
+
2697 image
->planes
[plane
].fast_clear_state_offset
,
2701 static inline struct anv_address
2702 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
2703 const struct anv_image
*image
,
2704 VkImageAspectFlagBits aspect
)
2706 struct anv_address addr
=
2707 anv_image_get_clear_color_addr(device
, image
, aspect
);
2709 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
2710 device
->isl_dev
.ss
.clear_color_state_size
:
2711 device
->isl_dev
.ss
.clear_value_size
;
2712 addr
.offset
+= clear_color_state_size
;
2716 static inline struct anv_address
2717 anv_image_get_compression_state_addr(const struct anv_device
*device
,
2718 const struct anv_image
*image
,
2719 VkImageAspectFlagBits aspect
,
2720 uint32_t level
, uint32_t array_layer
)
2722 assert(level
< anv_image_aux_levels(image
, aspect
));
2723 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
2724 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
2725 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
2727 struct anv_address addr
=
2728 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
2729 addr
.offset
+= 4; /* Go past the fast clear type */
2731 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2732 for (uint32_t l
= 0; l
< level
; l
++)
2733 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
2735 addr
.offset
+= level
* image
->array_size
* 4;
2737 addr
.offset
+= array_layer
* 4;
2742 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2744 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
2745 const struct anv_image
*image
)
2747 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
2750 if (devinfo
->gen
< 8)
2753 return image
->samples
== 1;
2757 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
2758 const struct anv_image
*image
,
2759 VkImageAspectFlagBits aspect
,
2760 enum isl_aux_usage aux_usage
,
2762 uint32_t base_layer
,
2763 uint32_t layer_count
);
2766 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
2767 const struct anv_image
*image
,
2768 VkImageAspectFlagBits aspect
,
2769 enum isl_aux_usage aux_usage
,
2770 enum isl_format format
, struct isl_swizzle swizzle
,
2771 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
2772 VkRect2D area
, union isl_color_value clear_color
);
2774 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
2775 const struct anv_image
*image
,
2776 VkImageAspectFlags aspects
,
2777 enum isl_aux_usage depth_aux_usage
,
2779 uint32_t base_layer
, uint32_t layer_count
,
2781 float depth_value
, uint8_t stencil_value
);
2783 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
2784 const struct anv_image
*image
,
2785 VkImageAspectFlagBits aspect
, uint32_t level
,
2786 uint32_t base_layer
, uint32_t layer_count
,
2787 enum isl_aux_op hiz_op
);
2789 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
2790 const struct anv_image
*image
,
2791 VkImageAspectFlags aspects
,
2793 uint32_t base_layer
, uint32_t layer_count
,
2794 VkRect2D area
, uint8_t stencil_value
);
2796 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
2797 const struct anv_image
*image
,
2798 VkImageAspectFlagBits aspect
,
2799 uint32_t base_layer
, uint32_t layer_count
,
2800 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
2803 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
2804 const struct anv_image
*image
,
2805 VkImageAspectFlagBits aspect
, uint32_t level
,
2806 uint32_t base_layer
, uint32_t layer_count
,
2807 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
2811 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
2812 const struct anv_image
*image
,
2813 uint32_t base_level
, uint32_t level_count
,
2814 uint32_t base_layer
, uint32_t layer_count
);
2817 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
2818 const struct anv_image
*image
,
2819 const VkImageAspectFlagBits aspect
,
2820 const VkImageLayout layout
);
2822 enum anv_fast_clear_type
2823 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
2824 const struct anv_image
* const image
,
2825 const VkImageAspectFlagBits aspect
,
2826 const VkImageLayout layout
);
2828 /* This is defined as a macro so that it works for both
2829 * VkImageSubresourceRange and VkImageSubresourceLayers
2831 #define anv_get_layerCount(_image, _range) \
2832 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2833 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2835 static inline uint32_t
2836 anv_get_levelCount(const struct anv_image
*image
,
2837 const VkImageSubresourceRange
*range
)
2839 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
2840 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
2843 static inline VkImageAspectFlags
2844 anv_image_expand_aspects(const struct anv_image
*image
,
2845 VkImageAspectFlags aspects
)
2847 /* If the underlying image has color plane aspects and
2848 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2849 * the underlying image. */
2850 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
2851 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
2852 return image
->aspects
;
2858 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
2859 VkImageAspectFlags aspects2
)
2861 if (aspects1
== aspects2
)
2864 /* Only 1 color aspects are compatibles. */
2865 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
2866 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
2867 _mesa_bitcount(aspects1
) == _mesa_bitcount(aspects2
))
2873 struct anv_image_view
{
2874 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
2876 VkImageAspectFlags aspect_mask
;
2878 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2882 uint32_t image_plane
;
2884 struct isl_view isl
;
2887 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2888 * image layout of SHADER_READ_ONLY_OPTIMAL or
2889 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2891 struct anv_surface_state optimal_sampler_surface_state
;
2894 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2895 * image layout of GENERAL.
2897 struct anv_surface_state general_sampler_surface_state
;
2900 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2901 * states for write-only and readable, using the real format for
2902 * write-only and the lowered format for readable.
2904 struct anv_surface_state storage_surface_state
;
2905 struct anv_surface_state writeonly_storage_surface_state
;
2907 struct brw_image_param storage_image_param
;
2911 enum anv_image_view_state_flags
{
2912 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
2913 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
2916 void anv_image_fill_surface_state(struct anv_device
*device
,
2917 const struct anv_image
*image
,
2918 VkImageAspectFlagBits aspect
,
2919 const struct isl_view
*view
,
2920 isl_surf_usage_flags_t view_usage
,
2921 enum isl_aux_usage aux_usage
,
2922 const union isl_color_value
*clear_color
,
2923 enum anv_image_view_state_flags flags
,
2924 struct anv_surface_state
*state_inout
,
2925 struct brw_image_param
*image_param_out
);
2927 struct anv_image_create_info
{
2928 const VkImageCreateInfo
*vk_info
;
2930 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2931 isl_tiling_flags_t isl_tiling_flags
;
2933 /** These flags will be added to any derived from VkImageCreateInfo. */
2934 isl_surf_usage_flags_t isl_extra_usage_flags
;
2939 VkResult
anv_image_create(VkDevice _device
,
2940 const struct anv_image_create_info
*info
,
2941 const VkAllocationCallbacks
* alloc
,
2945 VkResult
anv_image_from_gralloc(VkDevice device_h
,
2946 const VkImageCreateInfo
*base_info
,
2947 const VkNativeBufferANDROID
*gralloc_info
,
2948 const VkAllocationCallbacks
*alloc
,
2952 const struct anv_surface
*
2953 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
2954 VkImageAspectFlags aspect_mask
);
2957 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
2959 static inline struct VkExtent3D
2960 anv_sanitize_image_extent(const VkImageType imageType
,
2961 const struct VkExtent3D imageExtent
)
2963 switch (imageType
) {
2964 case VK_IMAGE_TYPE_1D
:
2965 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2966 case VK_IMAGE_TYPE_2D
:
2967 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2968 case VK_IMAGE_TYPE_3D
:
2971 unreachable("invalid image type");
2975 static inline struct VkOffset3D
2976 anv_sanitize_image_offset(const VkImageType imageType
,
2977 const struct VkOffset3D imageOffset
)
2979 switch (imageType
) {
2980 case VK_IMAGE_TYPE_1D
:
2981 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2982 case VK_IMAGE_TYPE_2D
:
2983 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2984 case VK_IMAGE_TYPE_3D
:
2987 unreachable("invalid image type");
2992 void anv_fill_buffer_surface_state(struct anv_device
*device
,
2993 struct anv_state state
,
2994 enum isl_format format
,
2995 struct anv_address address
,
2996 uint32_t range
, uint32_t stride
);
2999 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3000 const struct anv_attachment_state
*att_state
,
3001 const struct anv_image_view
*iview
)
3003 const struct isl_format_layout
*view_fmtl
=
3004 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3006 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3007 if (view_fmtl->channels.c.bits) \
3008 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3010 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3011 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3012 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3013 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3015 #undef COPY_CLEAR_COLOR_CHANNEL
3019 struct anv_ycbcr_conversion
{
3020 const struct anv_format
* format
;
3021 VkSamplerYcbcrModelConversion ycbcr_model
;
3022 VkSamplerYcbcrRange ycbcr_range
;
3023 VkComponentSwizzle mapping
[4];
3024 VkChromaLocation chroma_offsets
[2];
3025 VkFilter chroma_filter
;
3026 bool chroma_reconstruction
;
3029 struct anv_sampler
{
3030 uint32_t state
[3][4];
3032 struct anv_ycbcr_conversion
*conversion
;
3035 struct anv_framebuffer
{
3040 uint32_t attachment_count
;
3041 struct anv_image_view
* attachments
[0];
3044 struct anv_subpass_attachment
{
3045 VkImageUsageFlagBits usage
;
3046 uint32_t attachment
;
3047 VkImageLayout layout
;
3050 struct anv_subpass
{
3051 uint32_t attachment_count
;
3054 * A pointer to all attachment references used in this subpass.
3055 * Only valid if ::attachment_count > 0.
3057 struct anv_subpass_attachment
* attachments
;
3058 uint32_t input_count
;
3059 struct anv_subpass_attachment
* input_attachments
;
3060 uint32_t color_count
;
3061 struct anv_subpass_attachment
* color_attachments
;
3062 struct anv_subpass_attachment
* resolve_attachments
;
3064 struct anv_subpass_attachment depth_stencil_attachment
;
3068 /** Subpass has a depth/stencil self-dependency */
3069 bool has_ds_self_dep
;
3071 /** Subpass has at least one resolve attachment */
3075 static inline unsigned
3076 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3078 return MAX2(1, _mesa_bitcount(subpass
->view_mask
));
3081 struct anv_render_pass_attachment
{
3082 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3083 * its members individually.
3087 VkImageUsageFlags usage
;
3088 VkAttachmentLoadOp load_op
;
3089 VkAttachmentStoreOp store_op
;
3090 VkAttachmentLoadOp stencil_load_op
;
3091 VkImageLayout initial_layout
;
3092 VkImageLayout final_layout
;
3093 VkImageLayout first_subpass_layout
;
3095 /* The subpass id in which the attachment will be used last. */
3096 uint32_t last_subpass_idx
;
3099 struct anv_render_pass
{
3100 uint32_t attachment_count
;
3101 uint32_t subpass_count
;
3102 /* An array of subpass_count+1 flushes, one per subpass boundary */
3103 enum anv_pipe_bits
* subpass_flushes
;
3104 struct anv_render_pass_attachment
* attachments
;
3105 struct anv_subpass subpasses
[0];
3108 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3110 struct anv_query_pool
{
3112 VkQueryPipelineStatisticFlags pipeline_statistics
;
3113 /** Stride between slots, in bytes */
3115 /** Number of slots in this query pool */
3120 int anv_get_entrypoint_index(const char *name
);
3123 anv_entrypoint_is_enabled(int index
, uint32_t core_version
,
3124 const struct anv_instance_extension_table
*instance
,
3125 const struct anv_device_extension_table
*device
);
3127 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3130 void anv_dump_image_to_ppm(struct anv_device
*device
,
3131 struct anv_image
*image
, unsigned miplevel
,
3132 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3133 const char *filename
);
3135 enum anv_dump_action
{
3136 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
3139 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
3140 void anv_dump_finish(void);
3142 void anv_dump_add_framebuffer(struct anv_cmd_buffer
*cmd_buffer
,
3143 struct anv_framebuffer
*fb
);
3145 static inline uint32_t
3146 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
3148 /* This function must be called from within a subpass. */
3149 assert(cmd_state
->pass
&& cmd_state
->subpass
);
3151 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
3153 /* The id of this subpass shouldn't exceed the number of subpasses in this
3154 * render pass minus 1.
3156 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
3160 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3162 static inline struct __anv_type * \
3163 __anv_type ## _from_handle(__VkType _handle) \
3165 return (struct __anv_type *) _handle; \
3168 static inline __VkType \
3169 __anv_type ## _to_handle(struct __anv_type *_obj) \
3171 return (__VkType) _obj; \
3174 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3176 static inline struct __anv_type * \
3177 __anv_type ## _from_handle(__VkType _handle) \
3179 return (struct __anv_type *)(uintptr_t) _handle; \
3182 static inline __VkType \
3183 __anv_type ## _to_handle(struct __anv_type *_obj) \
3185 return (__VkType)(uintptr_t) _obj; \
3188 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3189 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3191 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
3192 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
3193 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
3194 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
3195 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
3197 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
3198 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
3199 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
3200 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
3201 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
3202 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
3203 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
3204 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
3205 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
3206 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
3207 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
3208 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
3209 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
3210 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
3211 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
3212 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
3213 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
3214 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
3215 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
3216 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
3217 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
3218 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
3219 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
3221 /* Gen-specific function declarations */
3223 # include "anv_genX.h"
3225 # define genX(x) gen7_##x
3226 # include "anv_genX.h"
3228 # define genX(x) gen75_##x
3229 # include "anv_genX.h"
3231 # define genX(x) gen8_##x
3232 # include "anv_genX.h"
3234 # define genX(x) gen9_##x
3235 # include "anv_genX.h"
3237 # define genX(x) gen10_##x
3238 # include "anv_genX.h"
3240 # define genX(x) gen11_##x
3241 # include "anv_genX.h"
3245 #endif /* ANV_PRIVATE_H */