src/intel/vulkan/gen7_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31 #include "vk_format_info.h"
  32
  33 #include "genxml/gen_macros.h"
  34 #include "genxml/genX_pack.h"
  35
  36 #if GEN_GEN == 7 && !GEN_IS_HASWELL
  37 static int64_t
  38 clamp_int64(int64_t x, int64_t min, int64_t max)
  39 {
  40    if (x < min)
  41       return min;
  42    else if (x < max)
  43       return x;
  44    else
  45       return max;
  46 }
  47
  48 void
  49 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
  50 {
  51    struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
  52    uint32_t count = cmd_buffer->state.gfx.dynamic.scissor.count;
  53    const VkRect2D *scissors = cmd_buffer->state.gfx.dynamic.scissor.scissors;
  54    struct anv_state scissor_state =
  55       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  56
  57    for (uint32_t i = 0; i < count; i++) {
  58       const VkRect2D *s = &scissors[i];
  59
  60       /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
  61        * ymax < ymin for empty clips.  In case clip x, y, width height are all
  62        * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
  63        * what we want. Just special case empty clips and produce a canonical
  64        * empty clip. */
  65       static const struct GEN7_SCISSOR_RECT empty_scissor = {
  66          .ScissorRectangleYMin = 1,
  67          .ScissorRectangleXMin = 1,
  68          .ScissorRectangleYMax = 0,
  69          .ScissorRectangleXMax = 0
  70       };
  71
  72       const int max = 0xffff;
  73
  74       uint32_t y_min = s->offset.y;
  75       uint32_t x_min = s->offset.x;
  76       uint32_t y_max = s->offset.y + s->extent.height - 1;
  77       uint32_t x_max = s->offset.x + s->extent.width - 1;
  78
  79       /* Do this math using int64_t so overflow gets clamped correctly. */
  80       if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
  81          y_min = clamp_int64((uint64_t) y_min,
  82                              cmd_buffer->state.render_area.offset.y, max);
  83          x_min = clamp_int64((uint64_t) x_min,
  84                              cmd_buffer->state.render_area.offset.x, max);
  85          y_max = clamp_int64((uint64_t) y_max, 0,
  86                              cmd_buffer->state.render_area.offset.y +
  87                              cmd_buffer->state.render_area.extent.height - 1);
  88          x_max = clamp_int64((uint64_t) x_max, 0,
  89                              cmd_buffer->state.render_area.offset.x +
  90                              cmd_buffer->state.render_area.extent.width - 1);
  91       } else if (fb) {
  92          y_min = clamp_int64((uint64_t) y_min, 0, max);
  93          x_min = clamp_int64((uint64_t) x_min, 0, max);
  94          y_max = clamp_int64((uint64_t) y_max, 0, fb->height - 1);
  95          x_max = clamp_int64((uint64_t) x_max, 0, fb->width - 1);
  96       }
  97
  98       struct GEN7_SCISSOR_RECT scissor = {
  99          .ScissorRectangleYMin = y_min,
 100          .ScissorRectangleXMin = x_min,
 101          .ScissorRectangleYMax = y_max,
 102          .ScissorRectangleXMax = x_max
 103       };
 104
 105       if (s->extent.width <= 0 || s->extent.height <= 0) {
 106          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
 107                                 &empty_scissor);
 108       } else {
 109          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
 110       }
 111    }
 112
 113    anv_batch_emit(&cmd_buffer->batch,
 114                   GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
 115       ssp.ScissorRectPointer = scissor_state.offset;
 116    }
 117 }
 118 #endif
 119
 120 static const uint32_t vk_to_gen_index_type[] = {
 121    [VK_INDEX_TYPE_UINT16]                       = INDEX_WORD,
 122    [VK_INDEX_TYPE_UINT32]                       = INDEX_DWORD,
 123 };
 124
 125 static const uint32_t restart_index_for_type[] = {
 126    [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 127    [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 128 };
 129
 130 void genX(CmdBindIndexBuffer)(
 131     VkCommandBuffer                             commandBuffer,
 132     VkBuffer                                    _buffer,
 133     VkDeviceSize                                offset,
 134     VkIndexType                                 indexType)
 135 {
 136    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 137    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 138
 139    cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 140    if (GEN_IS_HASWELL)
 141       cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 142    cmd_buffer->state.gfx.gen7.index_buffer = buffer;
 143    cmd_buffer->state.gfx.gen7.index_type = vk_to_gen_index_type[indexType];
 144    cmd_buffer->state.gfx.gen7.index_offset = offset;
 145 }
 146
 147 static uint32_t
 148 get_depth_format(struct anv_cmd_buffer *cmd_buffer)
 149 {
 150    const struct anv_render_pass *pass = cmd_buffer->state.pass;
 151    const struct anv_subpass *subpass = cmd_buffer->state.subpass;
 152
 153    if (!subpass->depth_stencil_attachment)
 154       return D16_UNORM;
 155
 156    struct anv_render_pass_attachment *att =
 157       &pass->attachments[subpass->depth_stencil_attachment->attachment];
 158
 159    switch (att->format) {
 160    case VK_FORMAT_D16_UNORM:
 161    case VK_FORMAT_D16_UNORM_S8_UINT:
 162       return D16_UNORM;
 163
 164    case VK_FORMAT_X8_D24_UNORM_PACK32:
 165    case VK_FORMAT_D24_UNORM_S8_UINT:
 166       return D24_UNORM_X8_UINT;
 167
 168    case VK_FORMAT_D32_SFLOAT:
 169    case VK_FORMAT_D32_SFLOAT_S8_UINT:
 170       return D32_FLOAT;
 171
 172    default:
 173       return D16_UNORM;
 174    }
 175 }
 176
 177 void
 178 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 179 {
 180    struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
 181    struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
 182
 183    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 184                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 185                                       ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
 186                                       ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
 187       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 188       struct GENX(3DSTATE_SF) sf = {
 189          GENX(3DSTATE_SF_header),
 190          .DepthBufferSurfaceFormat = get_depth_format(cmd_buffer),
 191          .LineWidth = d->line_width,
 192          .GlobalDepthOffsetConstant = d->depth_bias.bias,
 193          .GlobalDepthOffsetScale = d->depth_bias.slope,
 194          .GlobalDepthOffsetClamp = d->depth_bias.clamp
 195       };
 196       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 197
 198       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
 199    }
 200
 201    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 202                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 203       struct anv_state cc_state =
 204          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 205                                             GENX(COLOR_CALC_STATE_length) * 4,
 206                                             64);
 207       struct GENX(COLOR_CALC_STATE) cc = {
 208          .BlendConstantColorRed = d->blend_constants[0],
 209          .BlendConstantColorGreen = d->blend_constants[1],
 210          .BlendConstantColorBlue = d->blend_constants[2],
 211          .BlendConstantColorAlpha = d->blend_constants[3],
 212          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 213          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 214       };
 215       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 216
 217       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 218          ccp.ColorCalcStatePointer = cc_state.offset;
 219       }
 220    }
 221
 222    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 223                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 224                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 225                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 226       uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
 227
 228       struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
 229          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 230          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 231
 232          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 233          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 234
 235          .StencilBufferWriteEnable =
 236             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 237             pipeline->writes_stencil,
 238       };
 239       GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
 240
 241       struct anv_state ds_state =
 242          anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
 243                                       pipeline->gen7.depth_stencil_state,
 244                                       GENX(DEPTH_STENCIL_STATE_length), 64);
 245
 246       anv_batch_emit(&cmd_buffer->batch,
 247                      GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
 248          dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
 249       }
 250    }
 251
 252    if (cmd_buffer->state.gfx.gen7.index_buffer &&
 253        cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 254                                       ANV_CMD_DIRTY_INDEX_BUFFER)) {
 255       struct anv_buffer *buffer = cmd_buffer->state.gfx.gen7.index_buffer;
 256       uint32_t offset = cmd_buffer->state.gfx.gen7.index_offset;
 257
 258 #if GEN_IS_HASWELL
 259       anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
 260          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 261          vf.CutIndex                   = cmd_buffer->state.restart_index;
 262       }
 263 #endif
 264
 265       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 266 #if !GEN_IS_HASWELL
 267          ib.CutIndexEnable             = pipeline->primitive_restart;
 268 #endif
 269          ib.IndexFormat                = cmd_buffer->state.gfx.gen7.index_type;
 270          ib.MOCS                       = anv_mocs_for_bo(cmd_buffer->device,
 271                                                          buffer->address.bo);
 272
 273          ib.BufferStartingAddress      = anv_address_add(buffer->address,
 274                                                          offset);
 275          ib.BufferEndingAddress        = anv_address_add(buffer->address,
 276                                                          buffer->size);
 277       }
 278    }
 279
 280    cmd_buffer->state.gfx.dirty = 0;
 281 }
 282
 283 void
 284 genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer,
 285                                 bool enable)
 286 {
 287    /* The NP PMA fix doesn't exist on gen7 */
 288 }