2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
31 #include "vk_format_info.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
36 #if GEN_GEN == 7 && !GEN_IS_HASWELL
38 clamp_int64(int64_t x
, int64_t min
, int64_t max
)
49 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
)
51 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
52 uint32_t count
= cmd_buffer
->state
.gfx
.dynamic
.scissor
.count
;
53 const VkRect2D
*scissors
= cmd_buffer
->state
.gfx
.dynamic
.scissor
.scissors
;
54 struct anv_state scissor_state
=
55 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 8, 32);
57 for (uint32_t i
= 0; i
< count
; i
++) {
58 const VkRect2D
*s
= &scissors
[i
];
60 /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
61 * ymax < ymin for empty clips. In case clip x, y, width height are all
62 * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
63 * what we want. Just special case empty clips and produce a canonical
65 static const struct GEN7_SCISSOR_RECT empty_scissor
= {
66 .ScissorRectangleYMin
= 1,
67 .ScissorRectangleXMin
= 1,
68 .ScissorRectangleYMax
= 0,
69 .ScissorRectangleXMax
= 0
72 const int max
= 0xffff;
74 uint32_t y_min
= s
->offset
.y
;
75 uint32_t x_min
= s
->offset
.x
;
76 uint32_t y_max
= s
->offset
.y
+ s
->extent
.height
- 1;
77 uint32_t x_max
= s
->offset
.x
+ s
->extent
.width
- 1;
79 /* Do this math using int64_t so overflow gets clamped correctly. */
80 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
81 y_min
= clamp_int64((uint64_t) y_min
,
82 cmd_buffer
->state
.render_area
.offset
.y
, max
);
83 x_min
= clamp_int64((uint64_t) x_min
,
84 cmd_buffer
->state
.render_area
.offset
.x
, max
);
85 y_max
= clamp_int64((uint64_t) y_max
, 0,
86 cmd_buffer
->state
.render_area
.offset
.y
+
87 cmd_buffer
->state
.render_area
.extent
.height
- 1);
88 x_max
= clamp_int64((uint64_t) x_max
, 0,
89 cmd_buffer
->state
.render_area
.offset
.x
+
90 cmd_buffer
->state
.render_area
.extent
.width
- 1);
92 y_min
= clamp_int64((uint64_t) y_min
, 0, max
);
93 x_min
= clamp_int64((uint64_t) x_min
, 0, max
);
94 y_max
= clamp_int64((uint64_t) y_max
, 0, fb
->height
- 1);
95 x_max
= clamp_int64((uint64_t) x_max
, 0, fb
->width
- 1);
98 struct GEN7_SCISSOR_RECT scissor
= {
99 .ScissorRectangleYMin
= y_min
,
100 .ScissorRectangleXMin
= x_min
,
101 .ScissorRectangleYMax
= y_max
,
102 .ScissorRectangleXMax
= x_max
105 if (s
->extent
.width
<= 0 || s
->extent
.height
<= 0) {
106 GEN7_SCISSOR_RECT_pack(NULL
, scissor_state
.map
+ i
* 8,
109 GEN7_SCISSOR_RECT_pack(NULL
, scissor_state
.map
+ i
* 8, &scissor
);
113 anv_batch_emit(&cmd_buffer
->batch
,
114 GEN7_3DSTATE_SCISSOR_STATE_POINTERS
, ssp
) {
115 ssp
.ScissorRectPointer
= scissor_state
.offset
;
120 static uint32_t vk_to_gen_index_type(VkIndexType type
)
123 case VK_INDEX_TYPE_UINT8_EXT
:
125 case VK_INDEX_TYPE_UINT16
:
127 case VK_INDEX_TYPE_UINT32
:
130 unreachable("invalid index type");
134 static uint32_t restart_index_for_type(VkIndexType type
)
137 case VK_INDEX_TYPE_UINT8_EXT
:
139 case VK_INDEX_TYPE_UINT16
:
141 case VK_INDEX_TYPE_UINT32
:
144 unreachable("invalid index type");
148 void genX(CmdBindIndexBuffer
)(
149 VkCommandBuffer commandBuffer
,
152 VkIndexType indexType
)
154 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
155 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
157 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_INDEX_BUFFER
;
159 cmd_buffer
->state
.restart_index
= restart_index_for_type(indexType
);
160 cmd_buffer
->state
.gfx
.gen7
.index_buffer
= buffer
;
161 cmd_buffer
->state
.gfx
.gen7
.index_type
= vk_to_gen_index_type(indexType
);
162 cmd_buffer
->state
.gfx
.gen7
.index_offset
= offset
;
166 get_depth_format(struct anv_cmd_buffer
*cmd_buffer
)
168 const struct anv_render_pass
*pass
= cmd_buffer
->state
.pass
;
169 const struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
171 if (!subpass
->depth_stencil_attachment
)
174 struct anv_render_pass_attachment
*att
=
175 &pass
->attachments
[subpass
->depth_stencil_attachment
->attachment
];
177 switch (att
->format
) {
178 case VK_FORMAT_D16_UNORM
:
179 case VK_FORMAT_D16_UNORM_S8_UINT
:
182 case VK_FORMAT_X8_D24_UNORM_PACK32
:
183 case VK_FORMAT_D24_UNORM_S8_UINT
:
184 return D24_UNORM_X8_UINT
;
186 case VK_FORMAT_D32_SFLOAT
:
187 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
196 genX(cmd_buffer_flush_dynamic_state
)(struct anv_cmd_buffer
*cmd_buffer
)
198 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
199 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.gfx
.dynamic
;
201 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
202 ANV_CMD_DIRTY_RENDER_TARGETS
|
203 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
|
204 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
|
205 ANV_CMD_DIRTY_DYNAMIC_CULL_MODE
|
206 ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE
)) {
207 uint32_t sf_dw
[GENX(3DSTATE_SF_length
)];
208 struct GENX(3DSTATE_SF
) sf
= {
209 GENX(3DSTATE_SF_header
),
210 .DepthBufferSurfaceFormat
= get_depth_format(cmd_buffer
),
211 .LineWidth
= d
->line_width
,
212 .GlobalDepthOffsetConstant
= d
->depth_bias
.bias
,
213 .GlobalDepthOffsetScale
= d
->depth_bias
.slope
,
214 .GlobalDepthOffsetClamp
= d
->depth_bias
.clamp
,
215 .FrontWinding
= genX(vk_to_gen_front_face
)[d
->front_face
],
216 .CullMode
= genX(vk_to_gen_cullmode
)[d
->cull_mode
],
218 GENX(3DSTATE_SF_pack
)(NULL
, sf_dw
, &sf
);
220 anv_batch_emit_merge(&cmd_buffer
->batch
, sf_dw
, pipeline
->gen7
.sf
);
223 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
|
224 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
225 struct anv_state cc_state
=
226 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
227 GENX(COLOR_CALC_STATE_length
) * 4,
229 struct GENX(COLOR_CALC_STATE
) cc
= {
230 .BlendConstantColorRed
= d
->blend_constants
[0],
231 .BlendConstantColorGreen
= d
->blend_constants
[1],
232 .BlendConstantColorBlue
= d
->blend_constants
[2],
233 .BlendConstantColorAlpha
= d
->blend_constants
[3],
234 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
235 .BackfaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
237 GENX(COLOR_CALC_STATE_pack
)(NULL
, cc_state
.map
, &cc
);
239 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ccp
) {
240 ccp
.ColorCalcStatePointer
= cc_state
.offset
;
244 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
) {
245 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_LINE_STIPPLE
), ls
) {
246 ls
.LineStipplePattern
= d
->line_stipple
.pattern
;
247 ls
.LineStippleInverseRepeatCount
=
248 1.0f
/ MAX2(1, d
->line_stipple
.factor
);
249 ls
.LineStippleRepeatCount
= d
->line_stipple
.factor
;
253 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
254 ANV_CMD_DIRTY_RENDER_TARGETS
|
255 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
256 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
257 ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE
|
258 ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE
|
259 ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP
|
260 ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE
|
261 ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP
)) {
262 uint32_t depth_stencil_dw
[GENX(DEPTH_STENCIL_STATE_length
)];
264 struct GENX(DEPTH_STENCIL_STATE
) depth_stencil
= {
265 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
266 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
268 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
269 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
271 .StencilBufferWriteEnable
=
272 (d
->stencil_write_mask
.front
|| d
->stencil_write_mask
.back
) &&
273 d
->stencil_test_enable
,
275 .DepthTestEnable
= d
->depth_test_enable
,
276 .DepthBufferWriteEnable
= d
->depth_test_enable
&& d
->depth_write_enable
,
277 .DepthTestFunction
= genX(vk_to_gen_compare_op
)[d
->depth_compare_op
],
278 .StencilTestEnable
= d
->stencil_test_enable
,
279 .StencilFailOp
= genX(vk_to_gen_stencil_op
)[d
->stencil_op
.front
.fail_op
],
280 .StencilPassDepthPassOp
= genX(vk_to_gen_stencil_op
)[d
->stencil_op
.front
.pass_op
],
281 .StencilPassDepthFailOp
= genX(vk_to_gen_stencil_op
)[d
->stencil_op
.front
.depth_fail_op
],
282 .StencilTestFunction
= genX(vk_to_gen_compare_op
)[d
->stencil_op
.front
.compare_op
],
283 .BackfaceStencilFailOp
= genX(vk_to_gen_stencil_op
)[d
->stencil_op
.back
.fail_op
],
284 .BackfaceStencilPassDepthPassOp
= genX(vk_to_gen_stencil_op
)[d
->stencil_op
.back
.pass_op
],
285 .BackfaceStencilPassDepthFailOp
= genX(vk_to_gen_stencil_op
)[d
->stencil_op
.back
.depth_fail_op
],
286 .BackfaceStencilTestFunction
= genX(vk_to_gen_compare_op
)[d
->stencil_op
.back
.compare_op
],
288 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
290 struct anv_state ds_state
=
291 anv_cmd_buffer_merge_dynamic(cmd_buffer
, depth_stencil_dw
,
292 pipeline
->gen7
.depth_stencil_state
,
293 GENX(DEPTH_STENCIL_STATE_length
), 64);
295 anv_batch_emit(&cmd_buffer
->batch
,
296 GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), dsp
) {
297 dsp
.PointertoDEPTH_STENCIL_STATE
= ds_state
.offset
;
301 if (cmd_buffer
->state
.gfx
.gen7
.index_buffer
&&
302 cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
303 ANV_CMD_DIRTY_INDEX_BUFFER
)) {
304 struct anv_buffer
*buffer
= cmd_buffer
->state
.gfx
.gen7
.index_buffer
;
305 uint32_t offset
= cmd_buffer
->state
.gfx
.gen7
.index_offset
;
308 anv_batch_emit(&cmd_buffer
->batch
, GEN75_3DSTATE_VF
, vf
) {
309 vf
.IndexedDrawCutIndexEnable
= pipeline
->primitive_restart
;
310 vf
.CutIndex
= cmd_buffer
->state
.restart_index
;
314 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
316 ib
.CutIndexEnable
= pipeline
->primitive_restart
;
318 ib
.IndexFormat
= cmd_buffer
->state
.gfx
.gen7
.index_type
;
319 ib
.MOCS
= anv_mocs_for_bo(cmd_buffer
->device
,
322 ib
.BufferStartingAddress
= anv_address_add(buffer
->address
,
324 ib
.BufferEndingAddress
= anv_address_add(buffer
->address
,
329 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
330 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY
)) {
332 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
333 topology
= d
->primitive_topology
;
335 topology
= genX(vk_to_gen_primitive_type
)[d
->primitive_topology
];
337 cmd_buffer
->state
.gfx
.primitive_topology
= topology
;
340 cmd_buffer
->state
.gfx
.dirty
= 0;
344 genX(cmd_buffer_enable_pma_fix
)(struct anv_cmd_buffer
*cmd_buffer
,
347 /* The NP PMA fix doesn't exist on gen7 */