src/intel/vulkan/gen7_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 static inline int64_t
  36 clamp_int64(int64_t x, int64_t min, int64_t max)
  37 {
  38    if (x < min)
  39       return min;
  40    else if (x < max)
  41       return x;
  42    else
  43       return max;
  44 }
  45
  46 #if GEN_GEN == 7 && !GEN_IS_HASWELL
  47 void
  48 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
  49 {
  50    uint32_t count = cmd_buffer->state.dynamic.scissor.count;
  51    const VkRect2D *scissors =  cmd_buffer->state.dynamic.scissor.scissors;
  52    struct anv_state scissor_state =
  53       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  54
  55    for (uint32_t i = 0; i < count; i++) {
  56       const VkRect2D *s = &scissors[i];
  57
  58       /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
  59        * ymax < ymin for empty clips.  In case clip x, y, width height are all
  60        * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
  61        * what we want. Just special case empty clips and produce a canonical
  62        * empty clip. */
  63       static const struct GEN7_SCISSOR_RECT empty_scissor = {
  64          .ScissorRectangleYMin = 1,
  65          .ScissorRectangleXMin = 1,
  66          .ScissorRectangleYMax = 0,
  67          .ScissorRectangleXMax = 0
  68       };
  69
  70       const int max = 0xffff;
  71       struct GEN7_SCISSOR_RECT scissor = {
  72          /* Do this math using int64_t so overflow gets clamped correctly. */
  73          .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
  74          .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
  75          .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
  76          .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
  77       };
  78
  79       if (s->extent.width <= 0 || s->extent.height <= 0) {
  80          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
  81                                 &empty_scissor);
  82       } else {
  83          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
  84       }
  85    }
  86
  87    anv_batch_emit(&cmd_buffer->batch,
  88                   GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
  89       ssp.ScissorRectPointer = scissor_state.offset;
  90    }
  91
  92    if (!cmd_buffer->device->info.has_llc)
  93       anv_state_clflush(scissor_state);
  94 }
  95 #endif
  96
  97 static const uint32_t vk_to_gen_index_type[] = {
  98    [VK_INDEX_TYPE_UINT16]                       = INDEX_WORD,
  99    [VK_INDEX_TYPE_UINT32]                       = INDEX_DWORD,
 100 };
 101
 102 static const uint32_t restart_index_for_type[] = {
 103    [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 104    [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 105 };
 106
 107 void genX(CmdBindIndexBuffer)(
 108     VkCommandBuffer                             commandBuffer,
 109     VkBuffer                                    _buffer,
 110     VkDeviceSize                                offset,
 111     VkIndexType                                 indexType)
 112 {
 113    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 114    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 115
 116    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 117    if (GEN_IS_HASWELL)
 118       cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 119    cmd_buffer->state.gen7.index_buffer = buffer;
 120    cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
 121    cmd_buffer->state.gen7.index_offset = offset;
 122 }
 123
 124 void
 125 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 126 {
 127    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 128
 129    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 130                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 131                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
 132                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
 133
 134       const struct anv_image_view *iview =
 135          anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 136       const struct anv_image *image = iview ? iview->image : NULL;
 137       const bool has_depth =
 138          image && (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
 139       const uint32_t depth_format = has_depth ?
 140          isl_surf_get_depth_format(&cmd_buffer->device->isl_dev,
 141                                    &image->depth_surface.isl) : D16_UNORM;
 142
 143       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 144       struct GENX(3DSTATE_SF) sf = {
 145          GENX(3DSTATE_SF_header),
 146          .DepthBufferSurfaceFormat = depth_format,
 147          .LineWidth = cmd_buffer->state.dynamic.line_width,
 148          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 149          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 150          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 151       };
 152       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 153
 154       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
 155    }
 156
 157    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 158                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 159       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 160       struct anv_state cc_state =
 161          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 162                                             GENX(COLOR_CALC_STATE_length) * 4,
 163                                             64);
 164       struct GENX(COLOR_CALC_STATE) cc = {
 165          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 166          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 167          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 168          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 169          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 170          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 171       };
 172       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 173       if (!cmd_buffer->device->info.has_llc)
 174          anv_state_clflush(cc_state);
 175
 176       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 177          ccp.ColorCalcStatePointer = cc_state.offset;
 178       }
 179    }
 180
 181    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 182                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 183                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 184                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 185       uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
 186       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 187
 188       struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
 189          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 190          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 191
 192          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 193          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 194       };
 195       GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
 196
 197       struct anv_state ds_state =
 198          anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
 199                                       pipeline->gen7.depth_stencil_state,
 200                                       GENX(DEPTH_STENCIL_STATE_length), 64);
 201
 202       anv_batch_emit(&cmd_buffer->batch,
 203                      GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
 204          dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
 205       }
 206    }
 207
 208    if (cmd_buffer->state.gen7.index_buffer &&
 209        cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 210                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 211       struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
 212       uint32_t offset = cmd_buffer->state.gen7.index_offset;
 213
 214 #if GEN_IS_HASWELL
 215       anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
 216          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 217          vf.CutIndex                   = cmd_buffer->state.restart_index;
 218       }
 219 #endif
 220
 221       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 222 #if !GEN_IS_HASWELL
 223          ib.CutIndexEnable             = pipeline->primitive_restart;
 224 #endif
 225          ib.IndexFormat                = cmd_buffer->state.gen7.index_type;
 226          ib.MemoryObjectControlState   = GENX(MOCS);
 227
 228          ib.BufferStartingAddress =
 229             (struct anv_address) { buffer->bo, buffer->offset + offset };
 230          ib.BufferEndingAddress =
 231             (struct anv_address) { buffer->bo, buffer->offset + buffer->size };
 232       }
 233    }
 234
 235    cmd_buffer->state.dirty = 0;
 236 }
 237
 238 void
 239 genX(cmd_buffer_emit_hz_op)(struct anv_cmd_buffer *cmd_buffer,
 240                           enum blorp_hiz_op op)
 241 {
 242    anv_finishme("Implement Gen7 HZ ops");
 243 }
 244
 245 void genX(CmdSetEvent)(
 246     VkCommandBuffer                             commandBuffer,
 247     VkEvent                                     event,
 248     VkPipelineStageFlags                        stageMask)
 249 {
 250    stub();
 251 }
 252
 253 void genX(CmdResetEvent)(
 254     VkCommandBuffer                             commandBuffer,
 255     VkEvent                                     event,
 256     VkPipelineStageFlags                        stageMask)
 257 {
 258    stub();
 259 }
 260
 261 void genX(CmdWaitEvents)(
 262     VkCommandBuffer                             commandBuffer,
 263     uint32_t                                    eventCount,
 264     const VkEvent*                              pEvents,
 265     VkPipelineStageFlags                        srcStageMask,
 266     VkPipelineStageFlags                        destStageMask,
 267     uint32_t                                    memoryBarrierCount,
 268     const VkMemoryBarrier*                      pMemoryBarriers,
 269     uint32_t                                    bufferMemoryBarrierCount,
 270     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 271     uint32_t                                    imageMemoryBarrierCount,
 272     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 273 {
 274    stub();
 275
 276    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 277                             false, /* byRegion */
 278                             memoryBarrierCount, pMemoryBarriers,
 279                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 280                             imageMemoryBarrierCount, pImageMemoryBarriers);
 281 }