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[mesa.git] / src / intel / vulkan / gen7_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
34
35 static uint32_t
36 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
37 {
38 static const uint32_t push_constant_opcodes[] = {
39 [MESA_SHADER_VERTEX] = 21,
40 [MESA_SHADER_TESS_CTRL] = 25, /* HS */
41 [MESA_SHADER_TESS_EVAL] = 26, /* DS */
42 [MESA_SHADER_GEOMETRY] = 22,
43 [MESA_SHADER_FRAGMENT] = 23,
44 [MESA_SHADER_COMPUTE] = 0,
45 };
46
47 VkShaderStageFlags flushed = 0;
48
49 anv_foreach_stage(stage, cmd_buffer->state.push_constants_dirty) {
50 if (stage == MESA_SHADER_COMPUTE)
51 continue;
52
53 struct anv_state state = anv_cmd_buffer_push_constants(cmd_buffer, stage);
54
55 if (state.offset == 0)
56 continue;
57
58 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS),
59 ._3DCommandSubOpcode = push_constant_opcodes[stage],
60 .ConstantBody = {
61 .PointerToConstantBuffer0 = { .offset = state.offset },
62 .ConstantBuffer0ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
63 });
64
65 flushed |= mesa_to_vk_shader_stage(stage);
66 }
67
68 cmd_buffer->state.push_constants_dirty &= ~flushed;
69
70 return flushed;
71 }
72
73 GENX_FUNC(GEN7, GEN7) void
74 genX(cmd_buffer_emit_descriptor_pointers)(struct anv_cmd_buffer *cmd_buffer,
75 uint32_t stages)
76 {
77 static const uint32_t sampler_state_opcodes[] = {
78 [MESA_SHADER_VERTEX] = 43,
79 [MESA_SHADER_TESS_CTRL] = 44, /* HS */
80 [MESA_SHADER_TESS_EVAL] = 45, /* DS */
81 [MESA_SHADER_GEOMETRY] = 46,
82 [MESA_SHADER_FRAGMENT] = 47,
83 [MESA_SHADER_COMPUTE] = 0,
84 };
85
86 static const uint32_t binding_table_opcodes[] = {
87 [MESA_SHADER_VERTEX] = 38,
88 [MESA_SHADER_TESS_CTRL] = 39,
89 [MESA_SHADER_TESS_EVAL] = 40,
90 [MESA_SHADER_GEOMETRY] = 41,
91 [MESA_SHADER_FRAGMENT] = 42,
92 [MESA_SHADER_COMPUTE] = 0,
93 };
94
95 anv_foreach_stage(s, stages) {
96 if (cmd_buffer->state.samplers[s].alloc_size > 0) {
97 anv_batch_emit(&cmd_buffer->batch,
98 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS),
99 ._3DCommandSubOpcode = sampler_state_opcodes[s],
100 .PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset);
101 }
102
103 /* Always emit binding table pointers if we're asked to, since on SKL
104 * this is what flushes push constants. */
105 anv_batch_emit(&cmd_buffer->batch,
106 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS),
107 ._3DCommandSubOpcode = binding_table_opcodes[s],
108 .PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset);
109 }
110 }
111
112 GENX_FUNC(GEN7, GEN7) uint32_t
113 genX(cmd_buffer_flush_descriptor_sets)(struct anv_cmd_buffer *cmd_buffer)
114 {
115 VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
116 cmd_buffer->state.pipeline->active_stages;
117
118 VkResult result = VK_SUCCESS;
119 anv_foreach_stage(s, dirty) {
120 result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
121 &cmd_buffer->state.samplers[s]);
122 if (result != VK_SUCCESS)
123 break;
124 result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
125 &cmd_buffer->state.binding_tables[s]);
126 if (result != VK_SUCCESS)
127 break;
128 }
129
130 if (result != VK_SUCCESS) {
131 assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
132
133 result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
134 assert(result == VK_SUCCESS);
135
136 /* Re-emit state base addresses so we get the new surface state base
137 * address before we start emitting binding tables etc.
138 */
139 anv_cmd_buffer_emit_state_base_address(cmd_buffer);
140
141 /* Re-emit all active binding tables */
142 dirty |= cmd_buffer->state.pipeline->active_stages;
143 anv_foreach_stage(s, dirty) {
144 result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
145 &cmd_buffer->state.samplers[s]);
146 if (result != VK_SUCCESS)
147 return result;
148 result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
149 &cmd_buffer->state.binding_tables[s]);
150 if (result != VK_SUCCESS)
151 return result;
152 }
153 }
154
155 cmd_buffer->state.descriptors_dirty &= ~dirty;
156
157 return dirty;
158 }
159
160 static inline int64_t
161 clamp_int64(int64_t x, int64_t min, int64_t max)
162 {
163 if (x < min)
164 return min;
165 else if (x < max)
166 return x;
167 else
168 return max;
169 }
170
171 #if GEN_GEN == 7 && !GEN_IS_HASWELL
172 static void
173 emit_scissor_state(struct anv_cmd_buffer *cmd_buffer,
174 uint32_t count, const VkRect2D *scissors)
175 {
176 struct anv_state scissor_state =
177 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
178
179 for (uint32_t i = 0; i < count; i++) {
180 const VkRect2D *s = &scissors[i];
181
182 /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
183 * ymax < ymin for empty clips. In case clip x, y, width height are all
184 * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
185 * what we want. Just special case empty clips and produce a canonical
186 * empty clip. */
187 static const struct GEN7_SCISSOR_RECT empty_scissor = {
188 .ScissorRectangleYMin = 1,
189 .ScissorRectangleXMin = 1,
190 .ScissorRectangleYMax = 0,
191 .ScissorRectangleXMax = 0
192 };
193
194 const int max = 0xffff;
195 struct GEN7_SCISSOR_RECT scissor = {
196 /* Do this math using int64_t so overflow gets clamped correctly. */
197 .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
198 .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
199 .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
200 .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
201 };
202
203 if (s->extent.width <= 0 || s->extent.height <= 0) {
204 GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
205 &empty_scissor);
206 } else {
207 GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
208 }
209 }
210
211 anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_SCISSOR_STATE_POINTERS,
212 .ScissorRectPointer = scissor_state.offset);
213
214 if (!cmd_buffer->device->info.has_llc)
215 anv_state_clflush(scissor_state);
216 }
217
218 void
219 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
220 {
221 if (cmd_buffer->state.dynamic.scissor.count > 0) {
222 emit_scissor_state(cmd_buffer, cmd_buffer->state.dynamic.scissor.count,
223 cmd_buffer->state.dynamic.scissor.scissors);
224 } else {
225 /* Emit a default scissor based on the currently bound framebuffer */
226 emit_scissor_state(cmd_buffer, 1,
227 &(VkRect2D) {
228 .offset = { .x = 0, .y = 0, },
229 .extent = {
230 .width = cmd_buffer->state.framebuffer->width,
231 .height = cmd_buffer->state.framebuffer->height,
232 },
233 });
234 }
235 }
236 #endif
237
238 static const uint32_t vk_to_gen_index_type[] = {
239 [VK_INDEX_TYPE_UINT16] = INDEX_WORD,
240 [VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
241 };
242
243 static const uint32_t restart_index_for_type[] = {
244 [VK_INDEX_TYPE_UINT16] = UINT16_MAX,
245 [VK_INDEX_TYPE_UINT32] = UINT32_MAX,
246 };
247
248 void genX(CmdBindIndexBuffer)(
249 VkCommandBuffer commandBuffer,
250 VkBuffer _buffer,
251 VkDeviceSize offset,
252 VkIndexType indexType)
253 {
254 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
255 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
256
257 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
258 if (GEN_IS_HASWELL)
259 cmd_buffer->state.restart_index = restart_index_for_type[indexType];
260 cmd_buffer->state.gen7.index_buffer = buffer;
261 cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
262 cmd_buffer->state.gen7.index_offset = offset;
263 }
264
265 static VkResult
266 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
267 {
268 struct anv_device *device = cmd_buffer->device;
269 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
270 struct anv_state surfaces = { 0, }, samplers = { 0, };
271 VkResult result;
272
273 result = anv_cmd_buffer_emit_samplers(cmd_buffer,
274 MESA_SHADER_COMPUTE, &samplers);
275 if (result != VK_SUCCESS)
276 return result;
277 result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
278 MESA_SHADER_COMPUTE, &surfaces);
279 if (result != VK_SUCCESS)
280 return result;
281
282 struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
283
284 const struct brw_cs_prog_data *cs_prog_data = &pipeline->cs_prog_data;
285 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
286
287 unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
288 unsigned push_constant_data_size =
289 (prog_data->nr_params + local_id_dwords) * 4;
290 unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
291 unsigned push_constant_regs = reg_aligned_constant_size / 32;
292
293 if (push_state.alloc_size) {
294 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD),
295 .CURBETotalDataLength = push_state.alloc_size,
296 .CURBEDataStartAddress = push_state.offset);
297 }
298
299 assert(prog_data->total_shared <= 64 * 1024);
300 uint32_t slm_size = 0;
301 if (prog_data->total_shared > 0) {
302 /* slm_size is in 4k increments, but must be a power of 2. */
303 slm_size = 4 * 1024;
304 while (slm_size < prog_data->total_shared)
305 slm_size <<= 1;
306 slm_size /= 4 * 1024;
307 }
308
309 struct anv_state state =
310 anv_state_pool_emit(&device->dynamic_state_pool,
311 GENX(INTERFACE_DESCRIPTOR_DATA), 64,
312 .KernelStartPointer = pipeline->cs_simd,
313 .BindingTablePointer = surfaces.offset,
314 .SamplerStatePointer = samplers.offset,
315 .ConstantURBEntryReadLength =
316 push_constant_regs,
317 #if !GEN_IS_HASWELL
318 .ConstantURBEntryReadOffset = 0,
319 #endif
320 .BarrierEnable = cs_prog_data->uses_barrier,
321 .SharedLocalMemorySize = slm_size,
322 .NumberofThreadsinGPGPUThreadGroup =
323 pipeline->cs_thread_width_max);
324
325 const uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
326 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD),
327 .InterfaceDescriptorTotalLength = size,
328 .InterfaceDescriptorDataStartAddress = state.offset);
329
330 return VK_SUCCESS;
331 }
332
333 void
334 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
335 {
336 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
337 VkResult result;
338
339 assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
340
341 if (cmd_buffer->state.current_pipeline != GPGPU) {
342 anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
343 .PipelineSelection = GPGPU);
344 cmd_buffer->state.current_pipeline = GPGPU;
345 }
346
347 if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
348 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
349
350 if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
351 (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
352 /* FIXME: figure out descriptors for gen7 */
353 result = flush_compute_descriptor_set(cmd_buffer);
354 assert(result == VK_SUCCESS);
355 cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
356 }
357
358 cmd_buffer->state.compute_dirty = 0;
359 }
360
361 void
362 genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
363 {
364 struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
365 uint32_t *p;
366
367 uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
368
369 assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
370
371 genX(flush_pipeline_select_3d)(cmd_buffer);
372
373 if (vb_emit) {
374 const uint32_t num_buffers = __builtin_popcount(vb_emit);
375 const uint32_t num_dwords = 1 + num_buffers * 4;
376
377 p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
378 GENX(3DSTATE_VERTEX_BUFFERS));
379 uint32_t vb, i = 0;
380 for_each_bit(vb, vb_emit) {
381 struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
382 uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
383
384 struct GENX(VERTEX_BUFFER_STATE) state = {
385 .VertexBufferIndex = vb,
386 .BufferAccessType = pipeline->instancing_enable[vb] ? INSTANCEDATA : VERTEXDATA,
387 .VertexBufferMemoryObjectControlState = GENX(MOCS),
388 .AddressModifyEnable = true,
389 .BufferPitch = pipeline->binding_stride[vb],
390 .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
391 .EndAddress = { buffer->bo, buffer->offset + buffer->size - 1},
392 .InstanceDataStepRate = 1
393 };
394
395 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, &p[1 + i * 4], &state);
396 i++;
397 }
398 }
399
400 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_PIPELINE) {
401 /* If somebody compiled a pipeline after starting a command buffer the
402 * scratch bo may have grown since we started this cmd buffer (and
403 * emitted STATE_BASE_ADDRESS). If we're binding that pipeline now,
404 * reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
405 if (cmd_buffer->state.scratch_size < pipeline->total_scratch)
406 gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
407
408 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
409 }
410
411 if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT ||
412 cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) {
413 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
414 *
415 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
416 * stall needs to be sent just prior to any 3DSTATE_VS,
417 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
418 * 3DSTATE_BINDING_TABLE_POINTER_VS,
419 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
420 * PIPE_CONTROL needs to be sent before any combination of VS
421 * associated 3DSTATE."
422 */
423 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
424 .DepthStallEnable = true,
425 .PostSyncOperation = WriteImmediateData,
426 .Address = { &cmd_buffer->device->workaround_bo, 0 });
427 }
428
429 uint32_t dirty = 0;
430 if (cmd_buffer->state.descriptors_dirty) {
431 dirty = gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer);
432 gen7_cmd_buffer_emit_descriptor_pointers(cmd_buffer, dirty);
433 }
434
435 if (cmd_buffer->state.push_constants_dirty)
436 cmd_buffer_flush_push_constants(cmd_buffer);
437
438 /* We use the gen8 state here because it only contains the additional
439 * min/max fields and, since they occur at the end of the packet and
440 * don't change the stride, they work on gen7 too.
441 */
442 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
443 gen8_cmd_buffer_emit_viewport(cmd_buffer);
444
445 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
446 gen7_cmd_buffer_emit_scissor(cmd_buffer);
447
448 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
449 ANV_CMD_DIRTY_RENDER_TARGETS |
450 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
451 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
452
453 bool enable_bias = cmd_buffer->state.dynamic.depth_bias.bias != 0.0f ||
454 cmd_buffer->state.dynamic.depth_bias.slope != 0.0f;
455
456 const struct anv_image_view *iview =
457 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
458 const struct anv_image *image = iview ? iview->image : NULL;
459 const uint32_t depth_format = image ?
460 isl_surf_get_depth_format(&cmd_buffer->device->isl_dev,
461 &image->depth_surface.isl) : D16_UNORM;
462
463 uint32_t sf_dw[GENX(3DSTATE_SF_length)];
464 struct GENX(3DSTATE_SF) sf = {
465 GENX(3DSTATE_SF_header),
466 .DepthBufferSurfaceFormat = depth_format,
467 .LineWidth = cmd_buffer->state.dynamic.line_width,
468 .GlobalDepthOffsetEnableSolid = enable_bias,
469 .GlobalDepthOffsetEnableWireframe = enable_bias,
470 .GlobalDepthOffsetEnablePoint = enable_bias,
471 .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
472 .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
473 .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
474 };
475 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
476
477 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
478 }
479
480 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
481 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
482 struct anv_state cc_state =
483 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
484 GENX(COLOR_CALC_STATE_length) * 4,
485 64);
486 struct GENX(COLOR_CALC_STATE) cc = {
487 .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
488 .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
489 .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
490 .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
491 .StencilReferenceValue =
492 cmd_buffer->state.dynamic.stencil_reference.front,
493 .BackFaceStencilReferenceValue =
494 cmd_buffer->state.dynamic.stencil_reference.back,
495 };
496 GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
497 if (!cmd_buffer->device->info.has_llc)
498 anv_state_clflush(cc_state);
499
500 anv_batch_emit(&cmd_buffer->batch,
501 GENX(3DSTATE_CC_STATE_POINTERS),
502 .ColorCalcStatePointer = cc_state.offset);
503 }
504
505 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
506 ANV_CMD_DIRTY_RENDER_TARGETS |
507 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
508 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
509 uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
510
511 const struct anv_image_view *iview =
512 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
513
514 struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
515 .StencilBufferWriteEnable = iview && (iview->aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT),
516
517 .StencilTestMask =
518 cmd_buffer->state.dynamic.stencil_compare_mask.front & 0xff,
519 .StencilWriteMask =
520 cmd_buffer->state.dynamic.stencil_write_mask.front & 0xff,
521
522 .BackfaceStencilTestMask =
523 cmd_buffer->state.dynamic.stencil_compare_mask.back & 0xff,
524 .BackfaceStencilWriteMask =
525 cmd_buffer->state.dynamic.stencil_write_mask.back & 0xff,
526 };
527 GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
528
529 struct anv_state ds_state =
530 anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
531 pipeline->gen7.depth_stencil_state,
532 GENX(DEPTH_STENCIL_STATE_length), 64);
533
534 anv_batch_emit(&cmd_buffer->batch,
535 GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS),
536 .PointertoDEPTH_STENCIL_STATE = ds_state.offset);
537 }
538
539 if (cmd_buffer->state.gen7.index_buffer &&
540 cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
541 ANV_CMD_DIRTY_INDEX_BUFFER)) {
542 struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
543 uint32_t offset = cmd_buffer->state.gen7.index_offset;
544
545 #if GEN_IS_HASWELL
546 anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF,
547 .IndexedDrawCutIndexEnable = pipeline->primitive_restart,
548 .CutIndex = cmd_buffer->state.restart_index);
549 #endif
550
551 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER),
552 #if !GEN_IS_HASWELL
553 .CutIndexEnable = pipeline->primitive_restart,
554 #endif
555 .IndexFormat = cmd_buffer->state.gen7.index_type,
556 .MemoryObjectControlState = GENX(MOCS),
557 .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
558 .BufferEndingAddress = { buffer->bo, buffer->offset + buffer->size });
559 }
560
561 cmd_buffer->state.vb_dirty &= ~vb_emit;
562 cmd_buffer->state.dirty = 0;
563 }
564
565 void genX(CmdSetEvent)(
566 VkCommandBuffer commandBuffer,
567 VkEvent event,
568 VkPipelineStageFlags stageMask)
569 {
570 stub();
571 }
572
573 void genX(CmdResetEvent)(
574 VkCommandBuffer commandBuffer,
575 VkEvent event,
576 VkPipelineStageFlags stageMask)
577 {
578 stub();
579 }
580
581 void genX(CmdWaitEvents)(
582 VkCommandBuffer commandBuffer,
583 uint32_t eventCount,
584 const VkEvent* pEvents,
585 VkPipelineStageFlags srcStageMask,
586 VkPipelineStageFlags destStageMask,
587 uint32_t memoryBarrierCount,
588 const VkMemoryBarrier* pMemoryBarriers,
589 uint32_t bufferMemoryBarrierCount,
590 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
591 uint32_t imageMemoryBarrierCount,
592 const VkImageMemoryBarrier* pImageMemoryBarriers)
593 {
594 stub();
595 }