src/intel/vulkan/gen7_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #if GEN_GEN == 7 && !GEN_IS_HASWELL
  36 void
  37 gen7_cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
  38                                          uint32_t stages)
  39 {
  40    static const uint32_t sampler_state_opcodes[] = {
  41       [MESA_SHADER_VERTEX]                      = 43,
  42       [MESA_SHADER_TESS_CTRL]                   = 44, /* HS */
  43       [MESA_SHADER_TESS_EVAL]                   = 45, /* DS */
  44       [MESA_SHADER_GEOMETRY]                    = 46,
  45       [MESA_SHADER_FRAGMENT]                    = 47,
  46       [MESA_SHADER_COMPUTE]                     = 0,
  47    };
  48
  49    static const uint32_t binding_table_opcodes[] = {
  50       [MESA_SHADER_VERTEX]                      = 38,
  51       [MESA_SHADER_TESS_CTRL]                   = 39,
  52       [MESA_SHADER_TESS_EVAL]                   = 40,
  53       [MESA_SHADER_GEOMETRY]                    = 41,
  54       [MESA_SHADER_FRAGMENT]                    = 42,
  55       [MESA_SHADER_COMPUTE]                     = 0,
  56    };
  57
  58    anv_foreach_stage(s, stages) {
  59       if (cmd_buffer->state.samplers[s].alloc_size > 0) {
  60          anv_batch_emit(&cmd_buffer->batch,
  61                         GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ssp) {
  62             ssp._3DCommandSubOpcode = sampler_state_opcodes[s];
  63             ssp.PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset;
  64          }
  65       }
  66
  67       /* Always emit binding table pointers if we're asked to, since on SKL
  68        * this is what flushes push constants. */
  69       anv_batch_emit(&cmd_buffer->batch,
  70                      GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), btp) {
  71          btp._3DCommandSubOpcode = binding_table_opcodes[s];
  72          btp.PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset;
  73       }
  74    }
  75 }
  76
  77 uint32_t
  78 gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer)
  79 {
  80    VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
  81                               cmd_buffer->state.pipeline->active_stages;
  82
  83    VkResult result = VK_SUCCESS;
  84    anv_foreach_stage(s, dirty) {
  85       result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
  86                                             &cmd_buffer->state.samplers[s]);
  87       if (result != VK_SUCCESS)
  88          break;
  89       result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
  90                                                  &cmd_buffer->state.binding_tables[s]);
  91       if (result != VK_SUCCESS)
  92          break;
  93    }
  94
  95    if (result != VK_SUCCESS) {
  96       assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
  97
  98       result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
  99       assert(result == VK_SUCCESS);
 100
 101       /* Re-emit state base addresses so we get the new surface state base
 102        * address before we start emitting binding tables etc.
 103        */
 104       anv_cmd_buffer_emit_state_base_address(cmd_buffer);
 105
 106       /* Re-emit all active binding tables */
 107       dirty |= cmd_buffer->state.pipeline->active_stages;
 108       anv_foreach_stage(s, dirty) {
 109          result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
 110                                                &cmd_buffer->state.samplers[s]);
 111          if (result != VK_SUCCESS)
 112             return result;
 113          result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
 114                                                     &cmd_buffer->state.binding_tables[s]);
 115          if (result != VK_SUCCESS)
 116             return result;
 117       }
 118    }
 119
 120    cmd_buffer->state.descriptors_dirty &= ~dirty;
 121
 122    return dirty;
 123 }
 124 #endif /* GEN_GEN == 7 && !GEN_IS_HASWELL */
 125
 126 static inline int64_t
 127 clamp_int64(int64_t x, int64_t min, int64_t max)
 128 {
 129    if (x < min)
 130       return min;
 131    else if (x < max)
 132       return x;
 133    else
 134       return max;
 135 }
 136
 137 #if GEN_GEN == 7 && !GEN_IS_HASWELL
 138 void
 139 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
 140 {
 141    uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 142    const VkRect2D *scissors =  cmd_buffer->state.dynamic.scissor.scissors;
 143    struct anv_state scissor_state =
 144       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
 145
 146    for (uint32_t i = 0; i < count; i++) {
 147       const VkRect2D *s = &scissors[i];
 148
 149       /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
 150        * ymax < ymin for empty clips.  In case clip x, y, width height are all
 151        * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
 152        * what we want. Just special case empty clips and produce a canonical
 153        * empty clip. */
 154       static const struct GEN7_SCISSOR_RECT empty_scissor = {
 155          .ScissorRectangleYMin = 1,
 156          .ScissorRectangleXMin = 1,
 157          .ScissorRectangleYMax = 0,
 158          .ScissorRectangleXMax = 0
 159       };
 160
 161       const int max = 0xffff;
 162       struct GEN7_SCISSOR_RECT scissor = {
 163          /* Do this math using int64_t so overflow gets clamped correctly. */
 164          .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
 165          .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
 166          .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
 167          .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
 168       };
 169
 170       if (s->extent.width <= 0 || s->extent.height <= 0) {
 171          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
 172                                 &empty_scissor);
 173       } else {
 174          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
 175       }
 176    }
 177
 178    anv_batch_emit(&cmd_buffer->batch,
 179                   GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
 180       ssp.ScissorRectPointer = scissor_state.offset;
 181    }
 182
 183    if (!cmd_buffer->device->info.has_llc)
 184       anv_state_clflush(scissor_state);
 185 }
 186 #endif
 187
 188 static const uint32_t vk_to_gen_index_type[] = {
 189    [VK_INDEX_TYPE_UINT16]                       = INDEX_WORD,
 190    [VK_INDEX_TYPE_UINT32]                       = INDEX_DWORD,
 191 };
 192
 193 static const uint32_t restart_index_for_type[] = {
 194    [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 195    [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 196 };
 197
 198 void genX(CmdBindIndexBuffer)(
 199     VkCommandBuffer                             commandBuffer,
 200     VkBuffer                                    _buffer,
 201     VkDeviceSize                                offset,
 202     VkIndexType                                 indexType)
 203 {
 204    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 205    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 206
 207    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 208    if (GEN_IS_HASWELL)
 209       cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 210    cmd_buffer->state.gen7.index_buffer = buffer;
 211    cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
 212    cmd_buffer->state.gen7.index_offset = offset;
 213 }
 214
 215 static VkResult
 216 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 217 {
 218    struct anv_device *device = cmd_buffer->device;
 219    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 220    struct anv_state surfaces = { 0, }, samplers = { 0, };
 221    VkResult result;
 222
 223    result = anv_cmd_buffer_emit_samplers(cmd_buffer,
 224                                          MESA_SHADER_COMPUTE, &samplers);
 225    if (result != VK_SUCCESS)
 226       return result;
 227    result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
 228                                               MESA_SHADER_COMPUTE, &surfaces);
 229    if (result != VK_SUCCESS)
 230       return result;
 231
 232    struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
 233
 234    const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
 235    const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
 236
 237    unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
 238    unsigned push_constant_data_size =
 239       (prog_data->nr_params + local_id_dwords) * 4;
 240    unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
 241    unsigned push_constant_regs = reg_aligned_constant_size / 32;
 242
 243    if (push_state.alloc_size) {
 244       anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
 245          curbe.CURBETotalDataLength    = push_state.alloc_size;
 246          curbe.CURBEDataStartAddress   = push_state.offset;
 247       }
 248    }
 249
 250    assert(prog_data->total_shared <= 64 * 1024);
 251    uint32_t slm_size = 0;
 252    if (prog_data->total_shared > 0) {
 253       /* slm_size is in 4k increments, but must be a power of 2. */
 254       slm_size = 4 * 1024;
 255       while (slm_size < prog_data->total_shared)
 256          slm_size <<= 1;
 257       slm_size /= 4 * 1024;
 258    }
 259
 260    struct anv_state state =
 261       anv_state_pool_emit(&device->dynamic_state_pool,
 262                           GENX(INTERFACE_DESCRIPTOR_DATA), 64,
 263                           .KernelStartPointer = pipeline->cs_simd,
 264                           .BindingTablePointer = surfaces.offset,
 265                           .SamplerStatePointer = samplers.offset,
 266                           .ConstantURBEntryReadLength =
 267                              push_constant_regs,
 268 #if !GEN_IS_HASWELL
 269                           .ConstantURBEntryReadOffset = 0,
 270 #endif
 271                           .BarrierEnable = cs_prog_data->uses_barrier,
 272                           .SharedLocalMemorySize = slm_size,
 273                           .NumberofThreadsinGPGPUThreadGroup =
 274                              pipeline->cs_thread_width_max);
 275
 276    const uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
 277    anv_batch_emit(&cmd_buffer->batch,
 278                   GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), idl) {
 279       idl.InterfaceDescriptorTotalLength        = size;
 280       idl.InterfaceDescriptorDataStartAddress = state.offset;
 281    }
 282
 283    return VK_SUCCESS;
 284 }
 285
 286 void
 287 genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm)
 288 {
 289    /* References for GL state:
 290     *
 291     * - commits e307cfa..228d5a3
 292     * - src/mesa/drivers/dri/i965/gen7_l3_state.c
 293     */
 294
 295    uint32_t l3cr2_slm, l3cr2_noslm;
 296    anv_pack_struct(&l3cr2_noslm, GENX(L3CNTLREG2),
 297                    .URBAllocation = 24,
 298                    .ROAllocation = 0,
 299                    .DCAllocation = 16);
 300    anv_pack_struct(&l3cr2_slm, GENX(L3CNTLREG2),
 301                    .SLMEnable = 1,
 302                    .URBAllocation = 16,
 303                    .URBLowBandwidth = 1,
 304                    .ROAllocation = 0,
 305                    .DCAllocation = 8);
 306    const uint32_t l3cr2_val = enable_slm ? l3cr2_slm : l3cr2_noslm;
 307    bool changed = cmd_buffer->state.current_l3_config != l3cr2_val;
 308
 309    if (changed) {
 310       /* According to the hardware docs, the L3 partitioning can only be
 311        * changed while the pipeline is completely drained and the caches are
 312        * flushed, which involves a first PIPE_CONTROL flush which stalls the
 313        * pipeline...
 314        */
 315       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 316          pc.DCFlushEnable              = true;
 317          pc.CommandStreamerStallEnable = true;
 318          pc.PostSyncOperation          = NoWrite;
 319       }
 320
 321       /* ...followed by a second pipelined PIPE_CONTROL that initiates
 322        * invalidation of the relevant caches. Note that because RO
 323        * invalidation happens at the top of the pipeline (i.e. right away as
 324        * the PIPE_CONTROL command is processed by the CS) we cannot combine it
 325        * with the previous stalling flush as the hardware documentation
 326        * suggests, because that would cause the CS to stall on previous
 327        * rendering *after* RO invalidation and wouldn't prevent the RO caches
 328        * from being polluted by concurrent rendering before the stall
 329        * completes. This intentionally doesn't implement the SKL+ hardware
 330        * workaround suggesting to enable CS stall on PIPE_CONTROLs with the
 331        * texture cache invalidation bit set for GPGPU workloads because the
 332        * previous and subsequent PIPE_CONTROLs already guarantee that there is
 333        * no concurrent GPGPU kernel execution (see SKL HSD 2132585).
 334        */
 335       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 336          pc.TextureCacheInvalidationEnable   = true;
 337          pc.ConstantCacheInvalidationEnable  = true;
 338          pc.InstructionCacheInvalidateEnable = true;
 339          pc.StateCacheInvalidationEnable     = true;
 340          pc.PostSyncOperation                = NoWrite;
 341       }
 342
 343       /* Now send a third stalling flush to make sure that invalidation is
 344        * complete when the L3 configuration registers are modified.
 345        */
 346       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 347          pc.DCFlushEnable              = true;
 348          pc.CommandStreamerStallEnable = true;
 349          pc.PostSyncOperation          = NoWrite;
 350       }
 351
 352       anv_finishme("write GEN7_L3SQCREG1");
 353       anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 354          lri.RegisterOffset   = GENX(L3CNTLREG2_num);
 355          lri.DataDWord        = l3cr2_val;
 356       }
 357
 358       uint32_t l3cr3_slm, l3cr3_noslm;
 359       anv_pack_struct(&l3cr3_noslm, GENX(L3CNTLREG3),
 360                       .ISAllocation = 8,
 361                       .CAllocation = 4,
 362                       .TAllocation = 8);
 363       anv_pack_struct(&l3cr3_slm, GENX(L3CNTLREG3),
 364                       .ISAllocation = 8,
 365                       .CAllocation = 8,
 366                       .TAllocation = 8);
 367       const uint32_t l3cr3_val = enable_slm ? l3cr3_slm : l3cr3_noslm;
 368       anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 369          lri.RegisterOffset   = GENX(L3CNTLREG3_num);
 370          lri.DataDWord        = l3cr3_val;
 371       }
 372
 373       cmd_buffer->state.current_l3_config = l3cr2_val;
 374    }
 375 }
 376
 377 void
 378 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
 379 {
 380    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 381    const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
 382    MAYBE_UNUSED VkResult result;
 383
 384    assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
 385
 386    bool needs_slm = cs_prog_data->base.total_shared > 0;
 387    genX(cmd_buffer_config_l3)(cmd_buffer, needs_slm);
 388
 389    genX(flush_pipeline_select_gpgpu)(cmd_buffer);
 390
 391    if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
 392       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 393
 394    if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
 395        (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
 396       /* FIXME: figure out descriptors for gen7 */
 397       result = flush_compute_descriptor_set(cmd_buffer);
 398       assert(result == VK_SUCCESS);
 399       cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
 400    }
 401
 402    cmd_buffer->state.compute_dirty = 0;
 403 }
 404
 405 void
 406 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 407 {
 408    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 409
 410    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 411                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 412                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
 413                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
 414
 415       const struct anv_image_view *iview =
 416          anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 417       const struct anv_image *image = iview ? iview->image : NULL;
 418       const bool has_depth =
 419          image && (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
 420       const uint32_t depth_format = has_depth ?
 421          isl_surf_get_depth_format(&cmd_buffer->device->isl_dev,
 422                                    &image->depth_surface.isl) : D16_UNORM;
 423
 424       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 425       struct GENX(3DSTATE_SF) sf = {
 426          GENX(3DSTATE_SF_header),
 427          .DepthBufferSurfaceFormat = depth_format,
 428          .LineWidth = cmd_buffer->state.dynamic.line_width,
 429          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 430          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 431          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 432       };
 433       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 434
 435       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
 436    }
 437
 438    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 439                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 440       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 441       struct anv_state cc_state =
 442          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 443                                             GENX(COLOR_CALC_STATE_length) * 4,
 444                                             64);
 445       struct GENX(COLOR_CALC_STATE) cc = {
 446          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 447          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 448          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 449          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 450          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 451          .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 452       };
 453       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 454       if (!cmd_buffer->device->info.has_llc)
 455          anv_state_clflush(cc_state);
 456
 457       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 458          ccp.ColorCalcStatePointer = cc_state.offset;
 459       }
 460    }
 461
 462    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 463                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 464                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 465                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 466       uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
 467       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 468
 469       struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
 470          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 471          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 472
 473          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 474          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 475       };
 476       GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
 477
 478       struct anv_state ds_state =
 479          anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
 480                                       pipeline->gen7.depth_stencil_state,
 481                                       GENX(DEPTH_STENCIL_STATE_length), 64);
 482
 483       anv_batch_emit(&cmd_buffer->batch,
 484                      GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
 485          dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
 486       }
 487    }
 488
 489    if (cmd_buffer->state.gen7.index_buffer &&
 490        cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 491                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 492       struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
 493       uint32_t offset = cmd_buffer->state.gen7.index_offset;
 494
 495 #if GEN_IS_HASWELL
 496       anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
 497          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 498          vf.CutIndex                   = cmd_buffer->state.restart_index;
 499       }
 500 #endif
 501
 502       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 503 #if !GEN_IS_HASWELL
 504          ib.CutIndexEnable             = pipeline->primitive_restart;
 505 #endif
 506          ib.IndexFormat                = cmd_buffer->state.gen7.index_type;
 507          ib.MemoryObjectControlState   = GENX(MOCS);
 508
 509          ib.BufferStartingAddress =
 510             (struct anv_address) { buffer->bo, buffer->offset + offset };
 511          ib.BufferEndingAddress =
 512             (struct anv_address) { buffer->bo, buffer->offset + buffer->size };
 513       }
 514    }
 515
 516    cmd_buffer->state.dirty = 0;
 517 }
 518
 519 void genX(CmdSetEvent)(
 520     VkCommandBuffer                             commandBuffer,
 521     VkEvent                                     event,
 522     VkPipelineStageFlags                        stageMask)
 523 {
 524    stub();
 525 }
 526
 527 void genX(CmdResetEvent)(
 528     VkCommandBuffer                             commandBuffer,
 529     VkEvent                                     event,
 530     VkPipelineStageFlags                        stageMask)
 531 {
 532    stub();
 533 }
 534
 535 void genX(CmdWaitEvents)(
 536     VkCommandBuffer                             commandBuffer,
 537     uint32_t                                    eventCount,
 538     const VkEvent*                              pEvents,
 539     VkPipelineStageFlags                        srcStageMask,
 540     VkPipelineStageFlags                        destStageMask,
 541     uint32_t                                    memoryBarrierCount,
 542     const VkMemoryBarrier*                      pMemoryBarriers,
 543     uint32_t                                    bufferMemoryBarrierCount,
 544     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 545     uint32_t                                    imageMemoryBarrierCount,
 546     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 547 {
 548    stub();
 549 }