src/intel/vulkan/gen7_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 static uint32_t
  36 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
  37 {
  38    static const uint32_t push_constant_opcodes[] = {
  39       [MESA_SHADER_VERTEX]                      = 21,
  40       [MESA_SHADER_TESS_CTRL]                   = 25, /* HS */
  41       [MESA_SHADER_TESS_EVAL]                   = 26, /* DS */
  42       [MESA_SHADER_GEOMETRY]                    = 22,
  43       [MESA_SHADER_FRAGMENT]                    = 23,
  44       [MESA_SHADER_COMPUTE]                     = 0,
  45    };
  46
  47    VkShaderStageFlags flushed = 0;
  48
  49    anv_foreach_stage(stage, cmd_buffer->state.push_constants_dirty) {
  50       if (stage == MESA_SHADER_COMPUTE)
  51          continue;
  52
  53       struct anv_state state = anv_cmd_buffer_push_constants(cmd_buffer, stage);
  54
  55       if (state.offset == 0)
  56          continue;
  57
  58       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS),
  59                      ._3DCommandSubOpcode = push_constant_opcodes[stage],
  60                      .ConstantBody = {
  61                         .PointerToConstantBuffer0 = { .offset = state.offset },
  62                         .ConstantBuffer0ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
  63                      });
  64
  65       flushed |= mesa_to_vk_shader_stage(stage);
  66    }
  67
  68    cmd_buffer->state.push_constants_dirty &= ~flushed;
  69
  70    return flushed;
  71 }
  72
  73 #if GEN_GEN == 7 && !GEN_IS_HASWELL
  74 void
  75 gen7_cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
  76                                          uint32_t stages)
  77 {
  78    static const uint32_t sampler_state_opcodes[] = {
  79       [MESA_SHADER_VERTEX]                      = 43,
  80       [MESA_SHADER_TESS_CTRL]                   = 44, /* HS */
  81       [MESA_SHADER_TESS_EVAL]                   = 45, /* DS */
  82       [MESA_SHADER_GEOMETRY]                    = 46,
  83       [MESA_SHADER_FRAGMENT]                    = 47,
  84       [MESA_SHADER_COMPUTE]                     = 0,
  85    };
  86
  87    static const uint32_t binding_table_opcodes[] = {
  88       [MESA_SHADER_VERTEX]                      = 38,
  89       [MESA_SHADER_TESS_CTRL]                   = 39,
  90       [MESA_SHADER_TESS_EVAL]                   = 40,
  91       [MESA_SHADER_GEOMETRY]                    = 41,
  92       [MESA_SHADER_FRAGMENT]                    = 42,
  93       [MESA_SHADER_COMPUTE]                     = 0,
  94    };
  95
  96    anv_foreach_stage(s, stages) {
  97       if (cmd_buffer->state.samplers[s].alloc_size > 0) {
  98          anv_batch_emit(&cmd_buffer->batch,
  99                         GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS),
 100                         ._3DCommandSubOpcode  = sampler_state_opcodes[s],
 101                         .PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset);
 102       }
 103
 104       /* Always emit binding table pointers if we're asked to, since on SKL
 105        * this is what flushes push constants. */
 106       anv_batch_emit(&cmd_buffer->batch,
 107                      GENX(3DSTATE_BINDING_TABLE_POINTERS_VS),
 108                      ._3DCommandSubOpcode  = binding_table_opcodes[s],
 109                      .PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset);
 110    }
 111 }
 112
 113 uint32_t
 114 gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer)
 115 {
 116    VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
 117                               cmd_buffer->state.pipeline->active_stages;
 118
 119    VkResult result = VK_SUCCESS;
 120    anv_foreach_stage(s, dirty) {
 121       result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
 122                                             &cmd_buffer->state.samplers[s]);
 123       if (result != VK_SUCCESS)
 124          break;
 125       result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
 126                                                  &cmd_buffer->state.binding_tables[s]);
 127       if (result != VK_SUCCESS)
 128          break;
 129    }
 130
 131    if (result != VK_SUCCESS) {
 132       assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
 133
 134       result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
 135       assert(result == VK_SUCCESS);
 136
 137       /* Re-emit state base addresses so we get the new surface state base
 138        * address before we start emitting binding tables etc.
 139        */
 140       anv_cmd_buffer_emit_state_base_address(cmd_buffer);
 141
 142       /* Re-emit all active binding tables */
 143       dirty |= cmd_buffer->state.pipeline->active_stages;
 144       anv_foreach_stage(s, dirty) {
 145          result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
 146                                                &cmd_buffer->state.samplers[s]);
 147          if (result != VK_SUCCESS)
 148             return result;
 149          result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
 150                                                     &cmd_buffer->state.binding_tables[s]);
 151          if (result != VK_SUCCESS)
 152             return result;
 153       }
 154    }
 155
 156    cmd_buffer->state.descriptors_dirty &= ~dirty;
 157
 158    return dirty;
 159 }
 160 #endif /* GEN_GEN == 7 && !GEN_IS_HASWELL */
 161
 162 static inline int64_t
 163 clamp_int64(int64_t x, int64_t min, int64_t max)
 164 {
 165    if (x < min)
 166       return min;
 167    else if (x < max)
 168       return x;
 169    else
 170       return max;
 171 }
 172
 173 #if GEN_GEN == 7 && !GEN_IS_HASWELL
 174 static void
 175 emit_scissor_state(struct anv_cmd_buffer *cmd_buffer,
 176                    uint32_t count, const VkRect2D *scissors)
 177 {
 178    struct anv_state scissor_state =
 179       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
 180
 181    for (uint32_t i = 0; i < count; i++) {
 182       const VkRect2D *s = &scissors[i];
 183
 184       /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
 185        * ymax < ymin for empty clips.  In case clip x, y, width height are all
 186        * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
 187        * what we want. Just special case empty clips and produce a canonical
 188        * empty clip. */
 189       static const struct GEN7_SCISSOR_RECT empty_scissor = {
 190          .ScissorRectangleYMin = 1,
 191          .ScissorRectangleXMin = 1,
 192          .ScissorRectangleYMax = 0,
 193          .ScissorRectangleXMax = 0
 194       };
 195
 196       const int max = 0xffff;
 197       struct GEN7_SCISSOR_RECT scissor = {
 198          /* Do this math using int64_t so overflow gets clamped correctly. */
 199          .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
 200          .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
 201          .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
 202          .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
 203       };
 204
 205       if (s->extent.width <= 0 || s->extent.height <= 0) {
 206          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
 207                                 &empty_scissor);
 208       } else {
 209          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
 210       }
 211    }
 212
 213    anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_SCISSOR_STATE_POINTERS,
 214                   .ScissorRectPointer = scissor_state.offset);
 215
 216    if (!cmd_buffer->device->info.has_llc)
 217       anv_state_clflush(scissor_state);
 218 }
 219
 220 void
 221 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
 222 {
 223    if (cmd_buffer->state.dynamic.scissor.count > 0) {
 224       emit_scissor_state(cmd_buffer, cmd_buffer->state.dynamic.scissor.count,
 225                          cmd_buffer->state.dynamic.scissor.scissors);
 226    } else {
 227       /* Emit a default scissor based on the currently bound framebuffer */
 228       emit_scissor_state(cmd_buffer, 1,
 229                          &(VkRect2D) {
 230                             .offset = { .x = 0, .y = 0, },
 231                             .extent = {
 232                                .width = cmd_buffer->state.framebuffer->width,
 233                                .height = cmd_buffer->state.framebuffer->height,
 234                             },
 235                          });
 236    }
 237 }
 238 #endif
 239
 240 static const uint32_t vk_to_gen_index_type[] = {
 241    [VK_INDEX_TYPE_UINT16]                       = INDEX_WORD,
 242    [VK_INDEX_TYPE_UINT32]                       = INDEX_DWORD,
 243 };
 244
 245 static const uint32_t restart_index_for_type[] = {
 246    [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 247    [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 248 };
 249
 250 void genX(CmdBindIndexBuffer)(
 251     VkCommandBuffer                             commandBuffer,
 252     VkBuffer                                    _buffer,
 253     VkDeviceSize                                offset,
 254     VkIndexType                                 indexType)
 255 {
 256    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 257    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 258
 259    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 260    if (GEN_IS_HASWELL)
 261       cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 262    cmd_buffer->state.gen7.index_buffer = buffer;
 263    cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
 264    cmd_buffer->state.gen7.index_offset = offset;
 265 }
 266
 267 static VkResult
 268 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 269 {
 270    struct anv_device *device = cmd_buffer->device;
 271    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 272    struct anv_state surfaces = { 0, }, samplers = { 0, };
 273    VkResult result;
 274
 275    result = anv_cmd_buffer_emit_samplers(cmd_buffer,
 276                                          MESA_SHADER_COMPUTE, &samplers);
 277    if (result != VK_SUCCESS)
 278       return result;
 279    result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
 280                                               MESA_SHADER_COMPUTE, &surfaces);
 281    if (result != VK_SUCCESS)
 282       return result;
 283
 284    struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
 285
 286    const struct brw_cs_prog_data *cs_prog_data = &pipeline->cs_prog_data;
 287    const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
 288
 289    unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
 290    unsigned push_constant_data_size =
 291       (prog_data->nr_params + local_id_dwords) * 4;
 292    unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
 293    unsigned push_constant_regs = reg_aligned_constant_size / 32;
 294
 295    if (push_state.alloc_size) {
 296       anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD),
 297                      .CURBETotalDataLength = push_state.alloc_size,
 298                      .CURBEDataStartAddress = push_state.offset);
 299    }
 300
 301    assert(prog_data->total_shared <= 64 * 1024);
 302    uint32_t slm_size = 0;
 303    if (prog_data->total_shared > 0) {
 304       /* slm_size is in 4k increments, but must be a power of 2. */
 305       slm_size = 4 * 1024;
 306       while (slm_size < prog_data->total_shared)
 307          slm_size <<= 1;
 308       slm_size /= 4 * 1024;
 309    }
 310
 311    struct anv_state state =
 312       anv_state_pool_emit(&device->dynamic_state_pool,
 313                           GENX(INTERFACE_DESCRIPTOR_DATA), 64,
 314                           .KernelStartPointer = pipeline->cs_simd,
 315                           .BindingTablePointer = surfaces.offset,
 316                           .SamplerStatePointer = samplers.offset,
 317                           .ConstantURBEntryReadLength =
 318                              push_constant_regs,
 319 #if !GEN_IS_HASWELL
 320                           .ConstantURBEntryReadOffset = 0,
 321 #endif
 322                           .BarrierEnable = cs_prog_data->uses_barrier,
 323                           .SharedLocalMemorySize = slm_size,
 324                           .NumberofThreadsinGPGPUThreadGroup =
 325                              pipeline->cs_thread_width_max);
 326
 327    const uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
 328    anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD),
 329                   .InterfaceDescriptorTotalLength = size,
 330                   .InterfaceDescriptorDataStartAddress = state.offset);
 331
 332    return VK_SUCCESS;
 333 }
 334
 335 void
 336 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
 337 {
 338    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 339    VkResult result;
 340
 341    assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
 342
 343    if (cmd_buffer->state.current_pipeline != GPGPU) {
 344       anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
 345                      .PipelineSelection = GPGPU);
 346       cmd_buffer->state.current_pipeline = GPGPU;
 347    }
 348
 349    if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
 350       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 351
 352    if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
 353        (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
 354       /* FIXME: figure out descriptors for gen7 */
 355       result = flush_compute_descriptor_set(cmd_buffer);
 356       assert(result == VK_SUCCESS);
 357       cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
 358    }
 359
 360    cmd_buffer->state.compute_dirty = 0;
 361 }
 362
 363 void
 364 genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
 365 {
 366    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 367    uint32_t *p;
 368
 369    uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
 370
 371    assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
 372
 373    genX(flush_pipeline_select_3d)(cmd_buffer);
 374
 375    if (vb_emit) {
 376       const uint32_t num_buffers = __builtin_popcount(vb_emit);
 377       const uint32_t num_dwords = 1 + num_buffers * 4;
 378
 379       p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
 380                           GENX(3DSTATE_VERTEX_BUFFERS));
 381       uint32_t vb, i = 0;
 382       for_each_bit(vb, vb_emit) {
 383          struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
 384          uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
 385
 386          struct GENX(VERTEX_BUFFER_STATE) state = {
 387             .VertexBufferIndex = vb,
 388             .BufferAccessType = pipeline->instancing_enable[vb] ? INSTANCEDATA : VERTEXDATA,
 389             .VertexBufferMemoryObjectControlState = GENX(MOCS),
 390             .AddressModifyEnable = true,
 391             .BufferPitch = pipeline->binding_stride[vb],
 392             .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
 393             .EndAddress = { buffer->bo, buffer->offset + buffer->size - 1},
 394             .InstanceDataStepRate = 1
 395          };
 396
 397          GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, &p[1 + i * 4], &state);
 398          i++;
 399       }
 400    }
 401
 402    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_PIPELINE) {
 403       /* If somebody compiled a pipeline after starting a command buffer the
 404        * scratch bo may have grown since we started this cmd buffer (and
 405        * emitted STATE_BASE_ADDRESS).  If we're binding that pipeline now,
 406        * reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
 407       if (cmd_buffer->state.scratch_size < pipeline->total_scratch)
 408          gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
 409
 410       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 411    }
 412
 413    if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT ||
 414        cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) {
 415       /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
 416        *
 417        *    "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
 418        *    stall needs to be sent just prior to any 3DSTATE_VS,
 419        *    3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
 420        *    3DSTATE_BINDING_TABLE_POINTER_VS,
 421        *    3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one
 422        *    PIPE_CONTROL needs to be sent before any combination of VS
 423        *    associated 3DSTATE."
 424        */
 425       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 426                      .DepthStallEnable = true,
 427                      .PostSyncOperation = WriteImmediateData,
 428                      .Address = { &cmd_buffer->device->workaround_bo, 0 });
 429    }
 430
 431    uint32_t dirty = 0;
 432    if (cmd_buffer->state.descriptors_dirty) {
 433       dirty = gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer);
 434       gen7_cmd_buffer_emit_descriptor_pointers(cmd_buffer, dirty);
 435    }
 436
 437    if (cmd_buffer->state.push_constants_dirty)
 438       cmd_buffer_flush_push_constants(cmd_buffer);
 439
 440    /* We use the gen8 state here because it only contains the additional
 441     * min/max fields and, since they occur at the end of the packet and
 442     * don't change the stride, they work on gen7 too.
 443     */
 444    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
 445       gen8_cmd_buffer_emit_viewport(cmd_buffer);
 446
 447    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
 448       gen7_cmd_buffer_emit_scissor(cmd_buffer);
 449
 450    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 451                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 452                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
 453                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
 454
 455       bool enable_bias = cmd_buffer->state.dynamic.depth_bias.bias != 0.0f ||
 456          cmd_buffer->state.dynamic.depth_bias.slope != 0.0f;
 457
 458       const struct anv_image_view *iview =
 459          anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 460       const struct anv_image *image = iview ? iview->image : NULL;
 461       const uint32_t depth_format = image ?
 462          isl_surf_get_depth_format(&cmd_buffer->device->isl_dev,
 463                                    &image->depth_surface.isl) : D16_UNORM;
 464
 465       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 466       struct GENX(3DSTATE_SF) sf = {
 467          GENX(3DSTATE_SF_header),
 468          .DepthBufferSurfaceFormat = depth_format,
 469          .LineWidth = cmd_buffer->state.dynamic.line_width,
 470          .GlobalDepthOffsetEnableSolid = enable_bias,
 471          .GlobalDepthOffsetEnableWireframe = enable_bias,
 472          .GlobalDepthOffsetEnablePoint = enable_bias,
 473          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 474          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 475          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 476       };
 477       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 478
 479       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
 480    }
 481
 482    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 483                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 484       struct anv_state cc_state =
 485          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 486                                             GENX(COLOR_CALC_STATE_length) * 4,
 487                                             64);
 488       struct GENX(COLOR_CALC_STATE) cc = {
 489          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 490          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 491          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 492          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 493          .StencilReferenceValue =
 494             cmd_buffer->state.dynamic.stencil_reference.front,
 495          .BackFaceStencilReferenceValue =
 496             cmd_buffer->state.dynamic.stencil_reference.back,
 497       };
 498       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 499       if (!cmd_buffer->device->info.has_llc)
 500          anv_state_clflush(cc_state);
 501
 502       anv_batch_emit(&cmd_buffer->batch,
 503                      GENX(3DSTATE_CC_STATE_POINTERS),
 504                      .ColorCalcStatePointer = cc_state.offset);
 505    }
 506
 507    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 508                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 509                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 510                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 511       uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
 512
 513       const struct anv_image_view *iview =
 514          anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 515
 516       struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
 517          .StencilBufferWriteEnable = iview && (iview->aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT),
 518
 519          .StencilTestMask =
 520             cmd_buffer->state.dynamic.stencil_compare_mask.front & 0xff,
 521          .StencilWriteMask =
 522             cmd_buffer->state.dynamic.stencil_write_mask.front & 0xff,
 523
 524          .BackfaceStencilTestMask =
 525             cmd_buffer->state.dynamic.stencil_compare_mask.back & 0xff,
 526          .BackfaceStencilWriteMask =
 527             cmd_buffer->state.dynamic.stencil_write_mask.back & 0xff,
 528       };
 529       GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
 530
 531       struct anv_state ds_state =
 532          anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
 533                                       pipeline->gen7.depth_stencil_state,
 534                                       GENX(DEPTH_STENCIL_STATE_length), 64);
 535
 536       anv_batch_emit(&cmd_buffer->batch,
 537                      GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS),
 538                      .PointertoDEPTH_STENCIL_STATE = ds_state.offset);
 539    }
 540
 541    if (cmd_buffer->state.gen7.index_buffer &&
 542        cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 543                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 544       struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
 545       uint32_t offset = cmd_buffer->state.gen7.index_offset;
 546
 547 #if GEN_IS_HASWELL
 548       anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF,
 549                      .IndexedDrawCutIndexEnable = pipeline->primitive_restart,
 550                      .CutIndex = cmd_buffer->state.restart_index);
 551 #endif
 552
 553       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER),
 554 #if !GEN_IS_HASWELL
 555                      .CutIndexEnable = pipeline->primitive_restart,
 556 #endif
 557                      .IndexFormat = cmd_buffer->state.gen7.index_type,
 558                      .MemoryObjectControlState = GENX(MOCS),
 559                      .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
 560                      .BufferEndingAddress = { buffer->bo, buffer->offset + buffer->size });
 561    }
 562
 563    cmd_buffer->state.vb_dirty &= ~vb_emit;
 564    cmd_buffer->state.dirty = 0;
 565 }
 566
 567 void genX(CmdSetEvent)(
 568     VkCommandBuffer                             commandBuffer,
 569     VkEvent                                     event,
 570     VkPipelineStageFlags                        stageMask)
 571 {
 572    stub();
 573 }
 574
 575 void genX(CmdResetEvent)(
 576     VkCommandBuffer                             commandBuffer,
 577     VkEvent                                     event,
 578     VkPipelineStageFlags                        stageMask)
 579 {
 580    stub();
 581 }
 582
 583 void genX(CmdWaitEvents)(
 584     VkCommandBuffer                             commandBuffer,
 585     uint32_t                                    eventCount,
 586     const VkEvent*                              pEvents,
 587     VkPipelineStageFlags                        srcStageMask,
 588     VkPipelineStageFlags                        destStageMask,
 589     uint32_t                                    memoryBarrierCount,
 590     const VkMemoryBarrier*                      pMemoryBarriers,
 591     uint32_t                                    bufferMemoryBarrierCount,
 592     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 593     uint32_t                                    imageMemoryBarrierCount,
 594     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 595 {
 596    stub();
 597 }