src/intel/vulkan/gen7_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31 #include "vk_format_info.h"
  32
  33 #include "genxml/gen_macros.h"
  34 #include "genxml/genX_pack.h"
  35
  36 #if GEN_GEN == 7 && !GEN_IS_HASWELL
  37 static int64_t
  38 clamp_int64(int64_t x, int64_t min, int64_t max)
  39 {
  40    if (x < min)
  41       return min;
  42    else if (x < max)
  43       return x;
  44    else
  45       return max;
  46 }
  47
  48 void
  49 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
  50 {
  51    struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
  52    uint32_t count = cmd_buffer->state.gfx.dynamic.scissor.count;
  53    const VkRect2D *scissors = cmd_buffer->state.gfx.dynamic.scissor.scissors;
  54    struct anv_state scissor_state =
  55       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  56
  57    for (uint32_t i = 0; i < count; i++) {
  58       const VkRect2D *s = &scissors[i];
  59
  60       /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
  61        * ymax < ymin for empty clips.  In case clip x, y, width height are all
  62        * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
  63        * what we want. Just special case empty clips and produce a canonical
  64        * empty clip. */
  65       static const struct GEN7_SCISSOR_RECT empty_scissor = {
  66          .ScissorRectangleYMin = 1,
  67          .ScissorRectangleXMin = 1,
  68          .ScissorRectangleYMax = 0,
  69          .ScissorRectangleXMax = 0
  70       };
  71
  72       const int max = 0xffff;
  73       struct GEN7_SCISSOR_RECT scissor = {
  74          /* Do this math using int64_t so overflow gets clamped correctly. */
  75          .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
  76          .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
  77          .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, fb->height - 1),
  78          .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, fb->width - 1)
  79       };
  80
  81       if (s->extent.width <= 0 || s->extent.height <= 0) {
  82          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
  83                                 &empty_scissor);
  84       } else {
  85          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
  86       }
  87    }
  88
  89    anv_batch_emit(&cmd_buffer->batch,
  90                   GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
  91       ssp.ScissorRectPointer = scissor_state.offset;
  92    }
  93
  94    anv_state_flush(cmd_buffer->device, scissor_state);
  95 }
  96 #endif
  97
  98 static const uint32_t vk_to_gen_index_type[] = {
  99    [VK_INDEX_TYPE_UINT16]                       = INDEX_WORD,
 100    [VK_INDEX_TYPE_UINT32]                       = INDEX_DWORD,
 101 };
 102
 103 static const uint32_t restart_index_for_type[] = {
 104    [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 105    [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 106 };
 107
 108 void genX(CmdBindIndexBuffer)(
 109     VkCommandBuffer                             commandBuffer,
 110     VkBuffer                                    _buffer,
 111     VkDeviceSize                                offset,
 112     VkIndexType                                 indexType)
 113 {
 114    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 115    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 116
 117    cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 118    if (GEN_IS_HASWELL)
 119       cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 120    cmd_buffer->state.gfx.gen7.index_buffer = buffer;
 121    cmd_buffer->state.gfx.gen7.index_type = vk_to_gen_index_type[indexType];
 122    cmd_buffer->state.gfx.gen7.index_offset = offset;
 123 }
 124
 125 static uint32_t
 126 get_depth_format(struct anv_cmd_buffer *cmd_buffer)
 127 {
 128    const struct anv_render_pass *pass = cmd_buffer->state.pass;
 129    const struct anv_subpass *subpass = cmd_buffer->state.subpass;
 130
 131    if (!subpass->depth_stencil_attachment)
 132       return D16_UNORM;
 133
 134    struct anv_render_pass_attachment *att =
 135       &pass->attachments[subpass->depth_stencil_attachment->attachment];
 136
 137    switch (att->format) {
 138    case VK_FORMAT_D16_UNORM:
 139    case VK_FORMAT_D16_UNORM_S8_UINT:
 140       return D16_UNORM;
 141
 142    case VK_FORMAT_X8_D24_UNORM_PACK32:
 143    case VK_FORMAT_D24_UNORM_S8_UINT:
 144       return D24_UNORM_X8_UINT;
 145
 146    case VK_FORMAT_D32_SFLOAT:
 147    case VK_FORMAT_D32_SFLOAT_S8_UINT:
 148       return D32_FLOAT;
 149
 150    default:
 151       return D16_UNORM;
 152    }
 153 }
 154
 155 void
 156 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 157 {
 158    struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
 159    struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
 160
 161    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 162                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 163                                       ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
 164                                       ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
 165       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 166       struct GENX(3DSTATE_SF) sf = {
 167          GENX(3DSTATE_SF_header),
 168          .DepthBufferSurfaceFormat = get_depth_format(cmd_buffer),
 169          .LineWidth = d->line_width,
 170          .GlobalDepthOffsetConstant = d->depth_bias.bias,
 171          .GlobalDepthOffsetScale = d->depth_bias.slope,
 172          .GlobalDepthOffsetClamp = d->depth_bias.clamp
 173       };
 174       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 175
 176       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
 177    }
 178
 179    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 180                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 181       struct anv_state cc_state =
 182          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 183                                             GENX(COLOR_CALC_STATE_length) * 4,
 184                                             64);
 185       struct GENX(COLOR_CALC_STATE) cc = {
 186          .BlendConstantColorRed = d->blend_constants[0],
 187          .BlendConstantColorGreen = d->blend_constants[1],
 188          .BlendConstantColorBlue = d->blend_constants[2],
 189          .BlendConstantColorAlpha = d->blend_constants[3],
 190          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 191          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 192       };
 193       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 194       anv_state_flush(cmd_buffer->device, cc_state);
 195
 196       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 197          ccp.ColorCalcStatePointer = cc_state.offset;
 198       }
 199    }
 200
 201    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 202                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 203                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 204                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 205       uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
 206
 207       struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
 208          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 209          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 210
 211          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 212          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 213
 214          .StencilBufferWriteEnable =
 215             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 216             pipeline->writes_stencil,
 217       };
 218       GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
 219
 220       struct anv_state ds_state =
 221          anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
 222                                       pipeline->gen7.depth_stencil_state,
 223                                       GENX(DEPTH_STENCIL_STATE_length), 64);
 224
 225       anv_batch_emit(&cmd_buffer->batch,
 226                      GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
 227          dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
 228       }
 229    }
 230
 231    if (cmd_buffer->state.gfx.gen7.index_buffer &&
 232        cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 233                                       ANV_CMD_DIRTY_INDEX_BUFFER)) {
 234       struct anv_buffer *buffer = cmd_buffer->state.gfx.gen7.index_buffer;
 235       uint32_t offset = cmd_buffer->state.gfx.gen7.index_offset;
 236
 237 #if GEN_IS_HASWELL
 238       anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
 239          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 240          vf.CutIndex                   = cmd_buffer->state.restart_index;
 241       }
 242 #endif
 243
 244       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 245 #if !GEN_IS_HASWELL
 246          ib.CutIndexEnable             = pipeline->primitive_restart;
 247 #endif
 248          ib.IndexFormat                = cmd_buffer->state.gfx.gen7.index_type;
 249          ib.IndexBufferMOCS            = anv_mocs_for_bo(cmd_buffer->device,
 250                                                          buffer->address.bo);
 251
 252          ib.BufferStartingAddress      = anv_address_add(buffer->address,
 253                                                          offset);
 254          ib.BufferEndingAddress        = anv_address_add(buffer->address,
 255                                                          buffer->size);
 256       }
 257    }
 258
 259    cmd_buffer->state.gfx.dirty = 0;
 260 }
 261
 262 void
 263 genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer,
 264                                 bool enable)
 265 {
 266    /* The NP PMA fix doesn't exist on gen7 */
 267 }
 268
 269 void genX(CmdSetEvent)(
 270     VkCommandBuffer                             commandBuffer,
 271     VkEvent                                     event,
 272     VkPipelineStageFlags                        stageMask)
 273 {
 274    anv_finishme("Implement events on gen7");
 275 }
 276
 277 void genX(CmdResetEvent)(
 278     VkCommandBuffer                             commandBuffer,
 279     VkEvent                                     event,
 280     VkPipelineStageFlags                        stageMask)
 281 {
 282    anv_finishme("Implement events on gen7");
 283 }
 284
 285 void genX(CmdWaitEvents)(
 286     VkCommandBuffer                             commandBuffer,
 287     uint32_t                                    eventCount,
 288     const VkEvent*                              pEvents,
 289     VkPipelineStageFlags                        srcStageMask,
 290     VkPipelineStageFlags                        destStageMask,
 291     uint32_t                                    memoryBarrierCount,
 292     const VkMemoryBarrier*                      pMemoryBarriers,
 293     uint32_t                                    bufferMemoryBarrierCount,
 294     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 295     uint32_t                                    imageMemoryBarrierCount,
 296     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 297 {
 298    anv_finishme("Implement events on gen7");
 299
 300    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 301                             false, /* byRegion */
 302                             memoryBarrierCount, pMemoryBarriers,
 303                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 304                             imageMemoryBarrierCount, pImageMemoryBarriers);
 305 }